03rd week of 2009 patent applcation highlights part 59 |
Patent application number | Title | Published |
20090019244 | Information Record/Read Apparatus - A plurality of sectors | 2009-01-15 |
20090019245 | METHODS FOR IMPLEMENTATION OF DATA FORMATS ON A REMOVABLE DISK DRIVE STORAGE SYSTEM - An archiving system including one or more removable disk drives embedded in removable disk cartridges, referred to simply as removable disk drives. The removable disk drives allow for expandability and replacement such that the archiving system need not be duplicated to add new or more storage capacity. In embodiments, the removable disk drives store metadata that contain information about the data stored on the removable disk drive. The metadata allows the system to retrieve the correct data from the random access memory and establishes controls on the data stored on the removable disk drive. In embodiments, the metadata is stored in two locations, such that, if the metadata in one location is corrupted, the second copy of the metadata may be retrieved. | 2009-01-15 |
20090019246 | Power efficient storage with data de-duplication - Power consumption in a storage system is reduced by selectively controlling power supplied to the storage devices, while also incorporating a de-duplication function to reduce the amount of required storage capacity. First storage devices are initially in a powered on condition and second storage devices are in a powered off condition. Write data received by the controller is initially stored to a first volume allocated from the first storage devices. While the second storage devices are powered on, content of the write data stored in the first volume is compared with content of any existing data stored in a second volume allocated on the second storage devices. When results of the comparison show that the content of the write data does not match the content of the existing data, the write data is stored to the second volume. | 2009-01-15 |
20090019247 | Bufferless Transactional Memory with Runahead Execution - A method for executing an atomic transaction includes receiving the atomic transaction at a processor for execution, determining a transactional memory location needed in memory for the atomic transaction, reserving the transactional memory location while all computation and store operations of the atomic transaction are deferred, and performing the computation and store operations, wherein the atomic transaction cannot be aborted after the reservation, and further wherein the store operation is directly committed to the memory without being buffered. | 2009-01-15 |
20090019248 | PORTABLE DEVICE AND METHOD FOR CONTROLLING SHARED MEMORY IN PORTABLE DEVICE - A portable terminal and a method of controlling a shared memory, the portable terminal are disclosed. The portable terminal includes a memory unit, being equipped with at least 2 ports and having a storage block partitioned into partitioned blocks in a quantity of n, and a plurality of processors, reading or writing data by accessing a particular partitioned block through each dedicated port. At least one of the partitioned blocks is assigned to a common storage block, accessible by a processor having an access privilege, and the access privilege is transferred between the plurality of processors. The common storage block can be partitioned into k sub partitioned blocks, which the data type and process to be stored are predetermined. With the present invention, in the case of the common storage block for the plurality of processors, by allowing the partitioned storage blocks to be partitioned again into sub partitioned blocks depending on a type of data to be stored, the data processing/transmission speed and efficiency can be optimized. | 2009-01-15 |
20090019249 | Chunk-specific executable code for chunked java object heaps - A mechanism is disclosed for storing one or more chunk-specific sets of executable instructions at one or more predetermined offsets within chunks of a chunked heap. The mechanism provides for storing a chunk-specific set of executable instructions within a portion of a chunk, where the set of executable instructions begins at a predetermined offset within the range of virtual memory addresses allocated to the chunk. The set of executable instructions, when executed, is operable to perform one or more operations that are specific to the chunk. | 2009-01-15 |
20090019250 | WIRELESSLY CONFIGURABLE MEMORY DEVICE ADDRESSING - A memory device includes a plurality of memory modules and a memory management module. A memory module of the plurality of memory modules includes a plurality of memory cells and a memory millimeter wave (MMW) transceiver. The memory management module determines a main memory configuration for at least some of the plurality of memory modules. The memory management module also determines physical addresses for the main memory configuration and determines a MMW communication resource table that includes an allocation mapping of one or more MMW communication resources to one or more of the at least some of the plurality of memory modules. | 2009-01-15 |
20090019251 | DYNAMIC STORAGE POOLS WITH THIN PROVISIONING - A method for data storage, including configuring in a data storage system a volume storage pool as data storage resources available for allocation of volumes in the data storage system. The method also includes defining a threshold value for the volume storage pool. When the allocation of the volumes causes the threshold value to be crossed, the method includes performing an action for managing the volume storage pool. | 2009-01-15 |
20090019252 | System and Method for Cache-Locking Mechanism Using Translation Table Attributes for Replacement Class ID Determination - A system, method, and program product are provided that identifies a cache set using Translation LookAside Buffer (TLB) attributes. When a virtual address is requested, the method, system, and program product identifies a cache set using buffer attributes. When a virtual address is received, an attempt is made to load the received virtual address from a cache. When the attempt results in a cache miss, a page is identified within a Translation LookAside Buffer that includes the virtual address. A class identifier is then retrieved from the identified page, with the class identifier identifying a cache set that is selected from the cache. | 2009-01-15 |
20090019253 | PROCESSING SYSTEM IMPLEMENTING VARIABLE PAGE SIZE MEMORY ORGANIZATION - A processing system includes memory management software responsive to changes in a page table. The memory management software consolidates contiguous page table entries into one or more page table entries that have larger memory page sizes. The memory management software updates the entries of a translation lookaside buffer that correspond to the consolidated contiguous page table entries. | 2009-01-15 |
20090019254 | PROCESSING SYSTEM IMPLEMENTING MULTIPLE PAGE SIZE MEMORY ORGANIZATION WITH MULTIPLE TRANSLATION LOOKASIDE BUFFERS HAVING DIFFERING CHARACTERISTICS - A processing system includes memory management software responsive to a translation lookaside buffer miss. The memory management software updates translation lookaside buffer information based on one or more missed virtual addresses. Entries of a first translation lookaside buffer are updated by the memory management software with information corresponding to the missed virtual addresses if memory page size information for the missed virtual addresses meet a first criterion. Entries of a second translation lookaside buffer are updated by the memory management software with information corresponding to the missed virtual addresses if memory page size information for the missed virtual addresses meet a second criterion. The first and second criterion may correspond to first and second memory page sizes supported by the respective translation lookaside buffers. | 2009-01-15 |
20090019255 | System and Method for Cache-Locking Mechanism Using Segment Table Attributes for Replacement Class ID Determination - A system, method, and program product are provided that identifies a cache set using Segment LookAside Buffer attributes. When an effective address is requested, an attempt is made to load the received effective address from an L2 cache. When this attempt results in a cache miss, the system identifies a segment within the Segment LookAside Buffer that includes the effective address. A class identifier is retrieved from the identified segment within the Segment LookAside Buffer. This class identifier identifies a cache set selected from the cache for replacement. Data is then reloaded into the cache set of the cache by using the retrieved class identifier that corresponds to the effective address. | 2009-01-15 |
20090019256 | Memory transaction handling in a data processing apparatus - A data processing apparatus is provided comprising a memory, memory management unit and identification circuitry for identifying a predetermined type of data access transaction within a plurality of received data access transactions. The memory management unit is responsive to the predetermined type of data access transaction to both permit completion of a data access and to cause an exception to be raised despite completion of the data access having been permitted. | 2009-01-15 |
20090019257 | Method and Apparatus for Length Decoding and Identifying Boundaries of Variable Length Instructions - A mechanism for superscalar decode of variable length instructions. A length decode unit may obtain a plurality of instruction bytes based on a scan window of a predetermined size. The instruction bytes may be associated with a plurality of variable length instructions, which are scheduled to be executed by a processing unit. The length decode unit may, for each instruction byte, estimate the start of a next variable length instruction following a current variable length instruction, and store a first pointer. A pre-pick unit may, for each instruction byte, use the first pointer to estimate the start of a subsequent variable length instruction following the next variable length instruction within the scan window, and store a second pointer. A pick unit may use a start pointer and related first and second pointers to determine the actual start of the variable length instructions within the scan window, and generate instruction pointers. | 2009-01-15 |
20090019258 | FAULT TOLERANT SELF-OPTIMIZING MULTI-PROCESSOR SYSTEM AND METHOD THEREOF - A fault-tolerant self-optimizing multi-processor system is disclosed that includes a plurality of redundant network switching units and a plurality of processors electrically coupled to the network switching units. Each processor comprises a local memory, local storage, multiple network interfaces and a routing agent (RA). The RAs form a unidirectional virtual ring (UVR) network using the redundant network switching units. The UVR network may coordinate all of the processors for data matching, failure detection/recovery and system management functions. Once data is matched via the UVR network, application programs communicate directly via the network switching units, thus fully exploiting the hardware redundancy. Each of the RAs may implement a tuple space daemon responsible for data matching and delivery, forwarding unsatisfied data requests to a downstream processor or dropping expired tuples from UVR circulation. The RAs provide overall system fault tolerance and are responsible for delivering data sources to the matching processors. | 2009-01-15 |
20090019259 | MULTIPROCESSING METHOD AND MULTIPROCESSOR SYSTEM - A multiprocessing method and a multiprocessor system capable of reducing time lost due to sequential waiting when procedures (program units) having dependencies are executed in which an order of execution of a plurality of program units in a sequential execution program and dependencies of the plurality of program units are registered, the execution states of the plurality of program units are managed based on the registered dependencies, executable program units are determined, and are assigned to server processors sequentially and executed are disclosed. | 2009-01-15 |
20090019260 | MASS PREFETCHING METHOD FOR DISK ARRAY - Disclosed herein is a mass prefetching method for disk arrays. In order to improve disk read performance for a non-sequential with having spatial locality as well as a sequential read, when a host requests a block to be read, all the blocks of the strip to which the block belongs are read. This is designated as strip prefetching (SP). Throttled Strip Prefetching (TSP), proposed in the present invention, investigates whether SP is beneficial by an online disk simulation, and does not perform SP if it is determined that SP is not beneficial. Since all prefetching operations of TSP are aligned in the strip of the disk array, the disk independence loss is resolved, and thus the performance of disk arrays is improved for concurrent sequential reads of multiple processes. TSP may however suffer from the loss of disk parallelism due to the disk independence of SP for a single sequential read. In order to solve this problem, this invention proposes Massive Stripe Prefetching (MSP). MSP includes an algorithm that detects a single sequential read at the block level. When a single sequential read is detected, prefetching is aligned in a stripe, and the prefetching size is set to a multiple of stripe size. Accordingly, the parallelism of disks is maximized. | 2009-01-15 |
20090019261 | High-Performance, Superscalar-Based Computer System with Out-of-Order Instruction Execution - A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order. | 2009-01-15 |
20090019262 | PROCESSOR MICRO-ARCHITECTURE FOR COMPUTE, SAVE OR RESTORE MULTIPLE REGISTERS, DEVICES, SYSTEMS, METHODS AND PROCESSES OF MANUFACTURE - An electronic circuit ( | 2009-01-15 |
20090019263 | Method and Apparatus for Length Decoding Variable Length Instructions - A mechanism for superscalar decode of variable length instructions. The decode mechanism may be included within a processing unit, and may comprise a length decode unit. The length decode unit may obtain a plurality of instruction bytes. The instruction bytes may be associated with a plurality of variable length instructions, which are to be executed by the processing unit. The length decode unit may perform a length decode operation for each of the plurality of instruction bytes. For each instruction byte, the length decode unit may estimate the instruction length of a current variable length instruction associated with a current instruction byte. Furthermore, during the length decode operation, for each instruction byte, the length decode unit may estimate the start of a next variable length instruction based on the estimated instruction length of the current variable length instruction, and store a first pointer to the estimated start of the next variable length instruction. | 2009-01-15 |
20090019264 | ADAPTIVE EXECUTION CYCLE CONTROL METHOD FOR ENHANCED INSTRUCTION THROUGHPUT - A method, system and processor for increasing the instruction throughput in a processor executing longer latency instructions within the instruction pipeline. Logic associated with specific stages of the execution pipeline, responsible for executing the particular type of instructions, determines when at least a threshold number of the particular-type instructions is scheduled to be executed. The logic then automatically changes an execution cycle frequency of the specific pipeline stages from a first cycle frequency to a second, pre-established higher cycle frequency, which enables more efficient execution and higher execution throughput of the particular-type instructions. The cycle frequency of only the one or more functional stages are switched to the higher cycle frequency independent of the cycle frequency of the other functional stages in the processor pipeline. The logic also automatically switches the execution cycle frequency of the specific pipeline stages back from the second, higher cycle frequency to the first cycle frequency, when the number of scheduled first-type instructions has completed execution. | 2009-01-15 |
20090019265 | ADAPTIVE EXECUTION FREQUENCY CONTROL METHOD FOR ENHANCED INSTRUCTION THROUGHPUT - A method, system and processor for adaptively and selectively controlling the instruction execution frequency of a data processor. Processing logic or a software compiler determines when a number of first-type instructions, requiring longer execution latency, are scheduled to be executed. The logic/compiler then triggers the CPM unit to automatically switch the execution frequency of the instruction processor from a first frequency that is optimal for processing regular-type instructions to a second, pre-established lower frequency that is optimal for processing the first-type instructions, to enable more efficient execution and higher execution throughput of the number of first-type operations within the processor. When the first-type instructions have completed execution, the processor's instruction execution frequency is returned to the first optimal frequency. | 2009-01-15 |
20090019266 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING SYSTEM - With respect to memory access instructions contained in an internal representation program, an information processing apparatus generates a load cache instruction, a cache hit judgment instruction, and a cache miss instruction that is executed in correspondence with a result of a judgment process performed according to the cache hit judgment instruction. In a case where the internal representation program contains a plurality of memory access instructions having a possibility of causing accesses to mutually the same cache line in a cache memory, the information processing apparatus generates a combine instruction instructing that judgment results of the judgment processes that are performed according to the cache hit judgment instruction should be combined into one judgment result. The information processing apparatus outputs an output program that contains these instructions that have been generated. | 2009-01-15 |
20090019267 | Method, System, and Apparatus for Dynamic Reconfiguration of Resources - A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware. | 2009-01-15 |
20090019268 | PROCESSOR - The processor includes: a plurality of functional bocks that are respectively synchronized and operates to perform a process according to a control signal; a connection unit that is changeable to a smaller bandwidth than a bandwidth of inputs/outputs of the respective functional blocks and is connected between the respective functional blocks; a first data converter that switches a bandwidth of the connection unit; a second data converter that switches a data transmission rate of input/output data of the respective functional blocks; and a controller that controls the first data converter and the second data converter. | 2009-01-15 |
20090019269 | Methods and Apparatus for a Bit Rake Instruction - Techniques for performing a bit rake instruction in a programmable processor. The bit rake instruction extracts an arbitrary pattern of bits from a source register, based on a mask provided in another register, and packs and right justifies the bits into a target register. The bit rake instruction allows any set of bits from the source register to be packed together. | 2009-01-15 |
20090019270 | EMBEDDED DEVICE PROGRAM DEBUG CONTROL - An embedded processor system includes an integrated development environment and an embedded processor system operating system. The operating system is operable to run on the embedded processor system, and a command queue is operable to receive commands from a debugging module external to the embedded processor system. A command queue processing module is operable to change settings in the embedded processor in response to commands in the command queue. | 2009-01-15 |
20090019271 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM - An information processing apparatus having a storage unit configured to execute a workflow with a plurality of processes combined therein and hold history information of the workflow, the information processing apparatus comprising an instructing unit configured to instruct such that a test workflow regarding a workflow selected to be executed is executed; a generating unit configured to generate the test workflow for the workflow selected to be executed; and an executing unit configured to execute the test workflow; wherein the generating unit generates the test workflow at least by adding a process not held in history information to processes of the test workflow, without adding a process held in the history information to the processes of the test workflow. | 2009-01-15 |
20090019272 | STORE QUEUE ARCHITECTURE FOR A PROCESSOR THAT SUPPORTS SPECULATIVE EXECUTION - Embodiments of the present invention provide a system that buffers stores on a processor that supports speculative execution. The system starts by buffering a store into an entry in the store queue during a speculative execution mode. If an entry for the store does not already exist in the store queue, the system writes the store into an available entry in the store queue and updates a byte mask for the entry. Otherwise, if an entry for the store already exists in the store queue, the system merges the store into the existing entry in the store queue and updates the byte mask for the entry to include information about the newly merged store. The system then forwards the data from the store queue to subsequent dependent loads. | 2009-01-15 |
20090019273 | Exception-based error handling in an array-based language - A computer-readable medium stores computer-executable instructions. The medium may hold: one or more instructions for executing a first code block; one or more instructions for generating an exception object based on the executing of the first code block; one or more instructions for receiving the exception object at a second code block; and one or more instructions for storing the exception object in a memory. | 2009-01-15 |
20090019274 | DATA PROCESSING ARRANGEMENT COMPRISING A RESET FACILITY - A data processing arrangement (MPS) comprises a plurality of data processors (SPR, PM | 2009-01-15 |
20090019275 | Secure Boot Method and Semiconductor Memory System Using the Method - A semiconductor memory system includes an external memory, an internal memory, and a one-time programmable (OTP) memory. The external memory includes a kernel, a public key, first boot information used to authenticate the public key and generate a test secret key, and a second boot loader verifying integrity of the kernel. The internal memory includes a first boot loader that verifies integrity of the second boot loader and generates the test secret key. The OTP memory includes second boot information generated using the public key and a secret key. Since the secure boot method and the semiconductor memory system using the method do not need an additional OTP memory to store a secret key unlike conventional technology, the capacity and recording time of the OTP memory can be reduced to about half compared to the conventional technology. | 2009-01-15 |
20090019276 | NETWORK TERMINAL OPERATED BY DOWNLOADABLE OPERATING SYSTEM AND OPERATING METHOD THEREOF - A network terminal operated by a downloadable operating system is provided. In the network terminal, a power supply supplies a power to an element of the network terminal, a nonvolatile storage medium stores a basic input/output system (BIOS) that automatically operates upon the supplying of the power, a controller is initialized by the operation of the BIOS in order to enable a connection between the network terminal and a host computer and to enable a download of a terminal operating system (OS) from the host computer to the network terminal, and a volatile storage medium stores the terminal OS downloaded from the host computer. | 2009-01-15 |
20090019277 | NETWORK TERMINAL OPERATED BY DOWNLOADABLE OPERATING SYSTEM AND OPERATING METHOD THEREOF - A network terminal operated by a downloadable operating system is provided. In the network terminal, a power supply supplies a power to an element of the network terminal, a nonvolatile storage medium stores a basic input/output system (BIOS) that automatically operates upon the supplying of the power, a controller is initialized by the operation of the BIOS in order to enable a connection between the network terminal and a host computer and to enable a download of a terminal operating system (OS) from the host computer to the network terminal, and a volatile storage medium stores the terminal OS downloaded from the host computer. | 2009-01-15 |
20090019278 | Method And System For A Platform Level Data Model And Messages For Transferring SMBIOS Structures And Data - A platform may comprise a management controller (MC) and a BIOS that may store SMBIOS information that may comprise metadata. SMBIOS information may be stored in the SMBIOS structure table. SMBIOS information may be transferred to the MC and may be communicated from the MC to an entity external to the platform. The BIOS may be inaccessible to the external entity. The MC may communicate with the external entity when the platform is powered ON or OFF. SMBIOS information may be transferred between the BIOS and the MC via a communication link. The MC and/or the BIOS may determine whether SMBIOS information from the MC is up-to-date. SMBIOS information may be copied from the BIOS to the MC if not up-to-date. SMBIOS information may be transferred via SMBIOS messages based on structure type, instance ID and/or handle. | 2009-01-15 |
20090019279 | USER APPARATUS AND PROGRAM - A user apparatus cannot acquire as many distribution keys K | 2009-01-15 |
20090019280 | Method of validating a digital certificate and a system therefor - A method of validating a digital certificate comprises retrieving from a first data store a digital certificate, retrieving from a second data store a plurality of certificate revocation lists (CRLs), and selecting one of the plurality of CRLs to validate the digital certificate as of a date which is before the current date. | 2009-01-15 |
20090019281 | SECURE HOST NETWORK ADDRESS CONFIGURATION - A Personal Computer Memory Card International Association (PCMCIA) card may establish, via a non-secure network, a secure communications channel between a computer and a secure network. The non-secure network may define a first address space. The secure network may define a second address space. The PCMCIA card may include a cryptography module, a network adapter, and/or a processor. The cryptography module may provide Type 1 cryptography of data communicated between the computer and the secure network. The network adapter may be in communication with the non-secure network and may be associated with a first network address from the first address space. The processor may be in communication with the secure network via the cryptography module and the network adapter. The processor may identify a second network address for the computer from the second address space and may communicate the second network address to the computer, for example via dynamic host control protocol (DHCP). | 2009-01-15 |
20090019282 | Anonymous authentication method based on an asymmetic cryptographic algorithm - A method for authenticating at least one client entity (A) by means of an authentication entity (B) based on a public key encryption (ASYM(PB,R))/decryption (ASYM(SB,R′)) algorithm, implemented on the client entity side and authentication entity side, respectively, including, on the client entity side:
| 2009-01-15 |
20090019283 | System and method for a secure multi-level network access mechanism using virtual service set identifier broadcast - A method, system, and computer program product for network management, including masking a true service set identifier (SSID) in beacon frame; and broadcasting the beacon frame with the masked true SSID, whereby an authorized device retrieve the true SSID from the broadcast beacon frame. | 2009-01-15 |
20090019284 | AUTHENTICATION METHOD AND KEY GENERATING METHOD IN WIRELESS PORTABLE INTERNET SYSTEM - An authentication method and authorization key generation method in a wireless portable Internet system is provided. In a wireless portable Internet system, the base station and the subscriber station share an authorization key when an authentication process is performed according to a predetermined authentication method negotiated therebetween. Particularly, the subscriber station and the base station perform an additional authentication process including an authorization key-related parameter and a security-related parameter and exchanges a security algorithm and SA (Security Association) information. In addition, an authorization key is derived from one or more basic key obtained through various authentication processes as an input key of an authorization key generation algorithm. Therefore, reliability of a security related parameter received from the receiving node can be enhanced and an authorization key having a hierarchical and secure structure can be provided. | 2009-01-15 |
20090019285 | Establishing a Trust Relationship Between Computing Entities - A first computing entity provides evidence to a second computing entity to demonstrate that the first computing entity has a trusted configuration specification that is one of a set of such specifications agreed between the computing entities. This evidence comprises a computed commitment, made using (but not revealing) the configuration specification of the first computing entity, and a ring signature generated using a plurality of keys where each such key is generated using the commitment and one of the trusted configuration specifications. The second computing entity verifies the ring signature in order to convince itself that the configuration specification of the first computing entity is in the set. | 2009-01-15 |
20090019286 | Watermark Detection - A detector ( | 2009-01-15 |
20090019287 | CONTENTS SERVER, CONTENTS RECEIVING APPARATUS AND NETWORK SYSTEM FOR ADDING INFORMATION TO DIGITAL CONTENTS - Method and system for embedding a unique and different digital watermark in digital contents for each access without increasing the overhear or load at the contents server. The contents server has a digital watermark-embedded contents storage unit for storing a plurality of digital contents where a different digital watermark is embedded, and a fingerprint performing unit for, adding to the digital contents the information specified using a bit row that is formed by a digital watermark being embedded for each part of the digital contents. | 2009-01-15 |
20090019288 | SECURE RECOVERY IN A SERVERLESS DISTRIBUTED FILE SYSTEM - Systems and methods for secure file writes after a catastrophic event are allowed over an unauthenticated channel in a serverless distributed file system if an authenticator accompanies the secure file writes. The authenticator can be a power-of-attorney certificate with time limitations, a vector of message authenticated code, or a single message authenticator with secured with a secret shared among members of the serverless distributed file system. The serverless distributed file system includes at least 3f+1 participating computer members, with f representing a number of faults tolerable by the system. The group requires at least one authenticator for file creation and file uploads. Any changes to files stored among the members can be made over an unauthenticated channel if the file changes are secured by the authenticator and the group is able to verify the authenticator. | 2009-01-15 |
20090019289 | NEGATIVE AUTHENTICATION SYSTEM FOR A NETWORKED COMPUTER SYSTEM - The disclosed invention is a method for screening access to a computer system using a negative authentication system. Input login requests are compared against a set of detectors comprising anti-passwords and only allowed further access if they do not match any of the anti-passwords. A method of generating a set of detectors comprising anti-passwords is also disclosed. | 2009-01-15 |
20090019290 | METHOD AND CENTRAL PROCESSING UNIT FOR PROCESSING ENCRYPTED SOFTWARE - The present invention provides a central processing unit for processing at least one encrypted software. The encrypted software comprises at least one encrypted software section. The encrypted software section is encrypted with a management key MK, and the MK being encrypted with a device key DK as a encrypted MK. The central processing unit comprises processing and cache unit, and cryptographic unit. The cryptographic unit comprises device key storage unit for storing the DK, a plurality of management key storage units for storing MKs, wherein each management key storage unit corresponding to a management key index MKI, and decryption unit. The decryption unit decrypts a encrypted MK with the DK to obtain a MK, stores the MK to a management key storage unit, and output a MKI corresponding to the management key storage unit, thus the MKI is used to correspond to the encrypted software section. Wherein, the decryption unit invokes corresponding MK according to the MKI and decrypts the encrypted software section, and directly transfers the decrypted software code and/or data to the processing and cache unit. | 2009-01-15 |
20090019291 | BACKUP AND RESTORATION OF DRM SECURITY DATA - The present invention provides for a method of security data restoration for a user device for back-up purposes in which the said security data can be restored through the interaction of a first and at least a second portion of data, including the steps of storing the first portion of data on a storage medium remote from the device, writing the at least second portion of data to wireless storage means, and, when restoration is required, communicating the at least second portion of data from the wireless storage means to the said storage medium so as to allow for the interaction of the first and the at least second portion of data. | 2009-01-15 |
20090019292 | Secure management of information - Methods and system are devised to provide security with regard to position data recorded by an electronic pen. The position data originates from a specific area of a position-coding pattern and is destined for a specific Application Service Handler, ASH, which is allocated the specific area of the pattern. The pen stores one or more Pen Application Licenses, PALs, which each includes license data in association with an encryption key, the license data identifying an area of the pattern. The encryption key of a given PAL corresponds to an encryption key of a given ASH. Thus, the PALs enable the pen to encrypt recorded position data, originating from the specific area of the pattern, with the encryption key that is related to the encryption key of the receiving ASH. The license data may further define a group of pens and a validity period, allowing a party generating a PAL to control its use. Generating a PAL may in turn need prior authorization, given by PAL validation data derived from an authorizer. The PAL validation data, which is to be included in the PAL, may set boundaries for the license data that can be included in a PAL, and may also be digitally signed by the authorizer. The pen may be prohibited to install the PAL unless its license data can be properly validated against the PAL validation data. | 2009-01-15 |
20090019293 | AUTOMATIC DATA REVOCATION TO FACILITATE SECURITY FOR A PORTABLE COMPUTING DEVICE - Some embodiments of the present invention provide a system that automatically revokes data on a portable computing device. During operation, the system uses a key K | 2009-01-15 |
20090019294 | Redundant power supply system - A redundant power supply system aims to balance power supply among main power units and stationary power units to achieve optimum output quality for the main power units and stationary power units, and also prevent interruption of power supply resulting from any main power units or stationary power units. It includes a power integration control unit. The power integration control unit and the main power units and stationary power units are bridged respectively by a power balance unit which functions in a load power balance mode such that the power integration control unit outputs a total output power in power ON and standby conditions, and each power supply device delivers actual output power according to the load ratio of the power supply device. | 2009-01-15 |
20090019295 | MOTHERBOARD AND POWER SUPPLY MODULE THEREOF - A motherboard and a power supply module thereof are disclosed. The power supply module provided by the invention can be directly fixed on a motherboard supporting an AM2 CPU and an AM2+ CPU. The power supply module provided by the invention utilizes a switching unit to switch between a group of pulse width modulation (PWM) signals for generating core voltages needed by an AM2 CPU and another PWM signal for generating a core voltage needed by an AM2+ CPU according to a version signal provided by the CPU of the motherboard. Therefore, no matter a CPU socket of the motherboard receives the AM2 CPU or the AM2+ CPU, the power supply module of the invention can obtain the maximum usage efficiency thereof, and the manufacture cost of motherboard with the power supply module decreases. | 2009-01-15 |
20090019296 | Network system port thereof for transmitting various signals and power - The present invention is to provide a network system for transmitting various signals and power, which comprises at least a power sourcing equipment and at least a powered device over a network. Each of the power sourcing equipment and the powered device has at least a port, wherein a first isolated conductor is disposed at one side of the port while a second isolated conductor is disposed at the other side of the port and creates a power circuit for transmitting power in combination with the first isolated conductor. Four differential signal pairs of the port, each with two conductors, are disposed between the first isolated conductor and the second isolated conductor, wherein each of the power sourcing equipment and the powered device transmits Ethernet signals through two of the differential signal pairs of its port and transmits other network signals through the other two differential signal pairs. | 2009-01-15 |
20090019297 | Semiconductor device - Semiconductor device reduces power consumption of total display system. A display memory | 2009-01-15 |
20090019298 | METHOD AND SYSTEM FOR MANAGING ECOSYSTEM SLEEP - A method for managing sleep modes in an ecosystem of components, the method includes: receiving an inactivity signal from at least one component in the ecosystem of components, the inactivity signal indicating that a predefined period of inactivity has been exceeded for that component; sending a sleep command to one or more components in the ecosystem in response to the inactivity signal, thereby establishing a sleep mode in the one or more components; subsequent to establishing the sleep mode, detecting activity in one or more of the one or more components through an awake signal received therefrom; sending an awake message to the one or more components in response to the awake signal, thereby terminating the sleep mode in the one or more components; wherein the sleep mode shuts off defined non-essential features within the one or more components, while maintaining defined essential processing tasks associated with of the one or more components placed into the sleep mode. | 2009-01-15 |
20090019299 | METHOD AND APPARATUS FOR ADJUSTING WAKEUP TIME IN ELECTRICAL POWER CONVERTER SYSTEMS AND TRANSFORMER ISOLATION - An electrical power converter system adjusts a wakeup voltage periodically, to permit earlier connection and/or operation, to increase performance. The electrical power converter system selects between a mathematically adjusted wakeup voltage based on at least one previous period, and a table derived wakeup voltage that takes into account historical information. The electrical power converter system is particularly suited to applications with periodicity such as solar based photovoltaic power generation. | 2009-01-15 |
20090019300 | System and Method for Portable Power Source Management - A system is provided that includes a host system configured with a portable power source and a host power manager. The host power manager is configured to monitor an available power level of the portable power source and at least one power usage by one or more auxiliary devices. The host power manager is further configured to promote less than a full power usage by at least one of the auxiliary devices. | 2009-01-15 |
20090019301 | STORAGE APPARATUS - One aspect of the embodiments utilizes a storage apparatus includes a storage device through which data is input from and output to an external apparatus having an external interface. The storage apparatus includes a power supply control switch provided on a power supply line through which power is supplied to the storage device. A conversion control circuit converts signals mutually between a device interface of the storage device and the external interface, and performs control to turn off the power supply control switch so that supply of power to the storage device is stopped upon the storage device entering an idle state, the idle state being a state where input to and output from the external apparatus are absent. | 2009-01-15 |
20090019302 | Calculating Apparatus Having A Plurality of Stages - A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e., hundreds, of stages arranged in parallel sub-arrays, the clocking conductor is snaked alongside the sub-arrays. In individual stages it is arranged that the shortest of the two calculations taking place in a stage, takes place in the return path. An array can be divided into separate sections for independent processing. | 2009-01-15 |
20090019303 | Clock frequency adjustment for semi-conductor devices - A method and apparatus are provided for clocking data processing modules, which require differing average clock frequencies, and for transferring data between the modules. This comprises a means for providing a common clock signal to modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. Clock pulses are applied to modules between which data is to be transferred at times consistent with the data transfer. | 2009-01-15 |
20090019304 | METHOD AND APPARATUS FOR HARDWARE TIMING OPTIMIZER - A method for optimizing signal operating parameters for a signal sent over a data transmission channel through a programmable logic device (PLD) is provided. A transmit test pattern is generated and is associated with a set of signal operating parameters for the transmission and receiving of the test pattern over a data transmission channel. The data transmission channel loops from a transmit port to a receive port of the PLD. A determination of whether the received test pattern matches the transmit test pattern is performed. The match results and the set of signal operating parameters are recorded. At least one of the signal operating parameters of the set of signal operating parameters is modified through a processor of the PLD. Another transmit pattern is transmitted and received according to the modified set of signal operating parameters and the results are recorded. Methods for optimizing data transfer into a PLD and corresponding apparatuses are included. | 2009-01-15 |
20090019305 | MARKET DATA RECOVERY - Networks, systems and methods for recovering data messages from a market data stream and for building a book for a financial instrument are disclosed. An out-of-band data stream related to an as-of state of the market for one or more financial instruments is distributed parallel to a stream of market data for the financial instrument. The as-of data stream is referenced to the financial according to a unique identifier of the messages of the market data stream. The as-of data for a financial instrument may be provided at periodic rate that may be varied according to one or more factors. | 2009-01-15 |
20090019306 | Protecting tag information in a multi-level cache hierarchy - In one embodiment, the present invention includes a shared cache memory that is inclusive with other cache memories coupled to it. The shared cache memory includes error correction logic to correct an error present in a tag array of one of the other cache memories and to provide corrected tag information to replace a tag entry in the tag array including the error. Other embodiments are described and claimed. | 2009-01-15 |
20090019307 | DIGITAL BROADCAST FILE DATA RECEIVING METHOD AND APPARATUS - A digital broadcast file data receiving method and a digital broadcast file data receiving apparatus are provided. The digital broadcast file data receiving method and the digital broadcast file data receiving apparatus enable reception and display of proper broadcast file data by detecting an error in a specific data block and receiving the specific data block again in a process of receiving digital broadcast file data. | 2009-01-15 |
20090019308 | Method and Apparatus for Data Recovery System Using Storage Based Journaling - A storage system maintains a journal and a snapshot of one or more data volumes. Two journal entry types are maintained, an AFTER journal entry and a BEFORE journal entry. Two modes of data recovery are provided: “fast” recovery and “undo-able” recovery. A combination of both recovery modes allows the user to quickly recover a targeted data state. | 2009-01-15 |
20090019309 | METHOD AND COMPUTER PROGRAM PRODUCT FOR DETERMINING A MINIMALLY DEGRADED CONFIGURATION WHEN FAILURES OCCUR ALONG CONNECTIONS - A minimally degraded configuration is determined when failing connections occur. Associative deconfigurations are determined from deconfiguring hardware items in a server system, associative groups are derived, and failed connections are determined. Failed connections are determined between two hardware items that are in the same associative group, and the two hardware items at both endpoints of the failed connection are deconfigured. Each associative group state is set to unknown, and the failed connections are counted where a single endpoint of the failed connection is within the associative group. The associative group state is set to deconfigured, if a member of the associative group was deconfigured. Counts of the associative groups that remain in the unknown state are analyzed, and the associative group with the smallest failed connection count is selected and set to a configured state. The other associative group at the other end is set to a deconfigured stated, and the hardware item in the other associative group is deconfigured. | 2009-01-15 |
20090019310 | COLLECTING AND REPRESENTING KNOWLEDGE - Problem determination knowledge is provided by an extraction tool that extracts tag information recorded in identified problem tracking tools, where the tags relate to problem knowledge. The extracted tag information is examined to produce a catalog of symptom definitions that can be utilized by tools such as problem submission, logging and/or analysis tools. | 2009-01-15 |
20090019311 | METHOD OF TESTING AN ELECTRONIC SYSTEM - A method of preparing a test for an electronic system including a plurality of pieces of equipment interconnected by at least one communications link, in which method, in order to perform the test, use is made of a test bench appropriate for the electronic system under test, which test bench is connected to the system and controlled in application of a command sequence established from at least one informal functional specification; while preparing the test, the informal functional specification, the command sequence, and a link identifying the informal functional specification from which the command sequence was established are all recorded so that after execution of the command sequence and after the test results have been recorded, it is possible to read the link and identify unambiguously the informal functional specification that corresponds to the test results obtained. | 2009-01-15 |
20090019312 | System and Method for Providing an Instrumentation Service Using Dye Injection and Filtering in a SIP Application Server Environment - An instrumentation service is described that uses dye injection and filtering in a Session Initiation Protocol (SIP) application server environment. The instrumentation service can provide a flexible mechanism for selectively adding diagnostic code to the SIP application server and the various applications running on it. It can allow flexible selection of locations in the server and application code, at which instrumentation code can be added. The process of adding diagnostic code can be deferred to the time of running the server at the deployment site. The instrumentation service further allows flexible selection of diagnostic actions, which can be executed at selected locations. In various embodiments, the execution of diagnostic code can be dynamically enabled or disabled while the server is running. Also, the behavior of diagnostic code executed at such locations can be dynamically changed while the server is running. | 2009-01-15 |
20090019313 | SYSTEM AND METHOD FOR PERFORMING CLIENT-SIDE INPUT VALIDATION - A system and method for performing client-side input validation may include a JavaServer Faces (JSF) environment having parameters indicating whether to enable or disable client-side validation for a given application, and one or more validation functions for validating required fields, minimum and maximum values, regular expressions, input lengths, or other input parameters. | 2009-01-15 |
20090019314 | NETWORK ADVISOR - A system for diagnosing the configuration and use of devices in an interconnected network. The system may be used to analyze a network and/or discrete network devices, and then suggest steps that a user may take to improve the performance or usability of the network and/or device. | 2009-01-15 |
20090019315 | AUTOMATED SOFTWARE TESTING VIA MULTI-CHANNEL REMOTE COMPUTING - Embodiments of the present invention address deficiencies of the art in respect to software functional testing and provide a method, system and computer program product for automated software functional testing via multi-channel remote computing. In one embodiment of the invention, an automated software functional testing data processing system can be provided. The system can include a multi-user operating platform supporting multiple different user sessions configured for communicative coupling to corresponding remote desktops, and a test driver disposed in at least one of the remote desktops. In particular, the test driver can include program code enabled to forward test inputs to an application under test (AUT) executing in one of the user sessions, and to log received test outputs resulting from the test inputs. | 2009-01-15 |
20090019316 | METHOD AND SYSTEM FOR CALCULATING AND DISPLAYING RISK - A system for calculating and rendering a risk level. In response to receiving an input to perform an action within a data processing system, a level of risk to the data processing system to perform the action is calculated based on a set of rules. It is determined whether the calculated level of risk presents an elevated risk. In response to determining that the calculated level of risk does present the elevated risk, a user interface is rendered with an appropriate elevated visual warning based on the calculated level of risk. | 2009-01-15 |
20090019317 | MECHANISM FOR IDENTIFYING THE SOURCE OF PERFORMANCE LOSS IN A MICROPROCESSOR - A system and method of accounting for lost clock cycles in a microprocessor. A method includes detecting a first reason which prevents exit of an entry from an instruction retirement queue, and incrementing a first count corresponding to the first reason, wherein the first count is incremented while the first reason prevents exit of the entry from the queue. A first point in time is determined when said first reason no longer prevents exit of the entry from the queue. A second reason which prevents exit of the entry from the queue is detected, wherein the second reason came into existence prior to said first point in time. A second count corresponding to the second reason is incremented, wherein incrementing the second count begins at the first point in time. | 2009-01-15 |
20090019318 | Approach for monitoring activity in production systems - An approach is provided for monitoring of the activity in production computer systems. During a first period of time, substantially all of a first plurality of dispatches sent to a CPU are recorded. Each dispatch of the first plurality of dispatches indicates an initial instruction of a stream of instructions that is executed without interruption by the CPU. Based on the first plurality of dispatches, a baseline profile that indicates a normal execution flow in the system is generated. During a second period of time, substantially all of a second plurality of dispatches sent to the CPU are monitored. Based on the baseline profile and on at least one of the second plurality of dispatches, a determination is made whether an abnormal execution flow exists in the system during the second period of time. One or more actions are performed in response to determining that the abnormal execution flow exists in the system during the second period of time. | 2009-01-15 |
20090019319 | REMOTE MONITORING DIAGNOSTIC SYSTEM - Disclosed is a remote monitoring diagnostic system in which a center and monitoring diagnostic units of a number of objects to be monitored are connected by a network. The center includes an algorithm forming unit for forming algorithms for monitoring, diagnosing, and operating each object to be monitored, a program group formation unit for forming monitoring, diagnostic, and operational programs from these algorithms, a transmitter for transmitting the programs in response to a request from the monitoring diagnostic unit, and a unit for forming information concerning prevention/maintenance form a diagnostic result and monitoring data from the monitoring diagnostic unit of each object to be monitored. The monitoring diagnostic unit of each object to be monitored includes a mobile program execution processor for executing the corresponding object to be monitored, and a transmitter for transmitting monitoring data to the center. | 2009-01-15 |
20090019320 | METHOD AND APPARATUS FOR TROUBLESHOOTING A COMPUTER SYSTEM - One embodiment of the present invention provides a system for troubleshooting a computer system. During operation, the system receives an identifier for a suspect computer system, which is suspected of operating abnormally. The system also receives an identifier for a normal computer system, which is operating normally. Next, the system automatically sends a command to be executed to both the suspect computer system and to the normal computer system. The system subsequently receives a response to the command from both the suspect computer system and the normal computer system and compares the responses to determine differences in behavior between the suspect computer system and the normal computer system. | 2009-01-15 |
20090019321 | ERROR CORRECTION FOR MEMORY - Methods and devices operate to apply and provide differing levels of error correction within a multi-level, non-volatile memory. In an example, the differing level of error correction is provided within one page of a row of multi-level cells relative to other pages stored within the same row of multi-level cells. | 2009-01-15 |
20090019322 | Production Line Control System - A production line control system ( | 2009-01-15 |
20090019323 | System and method for initializing a memory system, and memory device and processor-based system using same - Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of read data received through the read data lanes. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames. | 2009-01-15 |
20090019324 | METHOD AND APPARATUS FOR ANALYZING SERIAL DATA STREAMS - An apparatus and method for processing a data signal is provided. An acquisition unit of a test instrument acquires a data signal for a predetermined time. The data signal is stored in a memory of the test instrument and a clock recovery unit recovers a clock signal from the stored data signal. The stored data signal is sliced by a processor into a plurality of data segments of a predetermined length in accordance with the recovered clock signal. | 2009-01-15 |
20090019325 | MEMORY DEVICE, SUPPORTING METHOD FOR ERROR CORRECTION THEREOF, SUPPORTING PROGRAM THEREOF, MEMORY CARD, CIRCUIT BOARD AND ELECTRONIC APPARATUS - A memory device (memory module) having one or a plurality of memory chips is disclosed. By including in a memory chip an error generation part to generate an error, an error is generated in a specific area of a memory in accordance with an address specification, thereby confirmation of an ECC function is facilitated. The error generation part includes an error code generation part that generates an error code. The memory chip is configured by one or a plurality of memory matrixes. | 2009-01-15 |
20090019326 | Self-synchronizing bit error analyzer and circuit - A self-synchronizing data bus analyser is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set. | 2009-01-15 |
20090019327 | GENERATING DEVICE, GENERATING METHOD, PROGRAM AND RECORDING MEDIUM - A generation apparatus and the like for generating a test vector set capable of reducing differences in a logic value generated before and after a scan capture for outputs from scan cells included in a full-scan sequential circuit are provided. A generation apparatus | 2009-01-15 |
20090019328 | IC CIRCUIT WITH TEST ACCESS CONTROL CIRCUIT USING A JTAG INTERFACE - An integrated circuit comprises a first circuit portion ( | 2009-01-15 |
20090019329 | Serial scan chain control within an integrated circuit - An integrated circuit | 2009-01-15 |
20090019330 | INTEGRATED CIRCUIT HAVING BUILT-IN SELF-TEST FEATURES - An integrated circuit includes a sensor for providing a sensor output signal and a diagnostic circuit coupled to the sensor for providing a self-diagnostic signal. The self-diagnostic signal comprises the sensor output signal during a first time duration and an inverted sensor output signal during a second different time duration. | 2009-01-15 |
20090019331 | Integrated circuit for a data transmission system and receiving device of a data transmission system - The invention relates to an integrated circuit for a data transmission system comprising a) a plurality of functional units, b) a TAP controller, according to IEEE 1149, having a JTAG interface, and c) a test unit for testing the functionality of the functional units, whereby the test unit has at least two operating modes and at least one gate terminal for switching between the operating modes and is designed to connect circuit points, assigned to a specific operating mode, of the functional units to terminals of the integrated circuit, when the test unit is operated in the specific operating mode. According to the invention, the at least one gate terminal of the test unit is connected to the TAP controller and the integrated circuit is designed to switch between the operating modes depending on the internal states of the TAP controller. The invention relates furthermore to a receiving device of a data transmission system. | 2009-01-15 |
20090019332 | SISO DECODER WITH SUB-BLOCK PROCESSING AND SUB-BLOCK BASED STOPPING CRITERION - The present invention relates to SISO decoder for iteratively decoding a block of received information symbols (r), in particular for use in a turbo decoder, said block being divided into a number of windows of information symbols. In order to achieve a significant reduction of power consumption a SISO decoder is proposed comprising:
| 2009-01-15 |
20090019333 | Generation of parity-check matrices - Circuits perform row-by-row matrix generation for encoding and decoding of data blocks. They perform fast algebraic generation of high performance low density parity check (LDPC) matrices suitable for use in a wide range of error correction coding and decoding (ECC) applications. Circuit operation is based on a mathematical Cyclic Ring method that enables matrices of any size to be generated from a simple set of initial parameters, based on user-defined performance requirements. The main steps for generating a parity check matrix (H) are selection of an RG matrix structure, selection of Group Ring elements, generating the sub matrices for the RG matrix by a row filling scheme, generating the RG matrix by a cyclic arrangement of the sub matrices, and generating the parity-check matrix by deleting suitably chosen columns from the RG matrix to achieve the desired performance and then transposing the matrix. A circuit performs data encoding or decoding by receiving initial vectors calculated from row vectors of a previously-generated parity check matrix H, cyclic shifting the vectors to generate a desired output row of the parity check matrix H, re-arranging the operation order of the vectors depending on the RG matrix structure and the chosen row, operating on the vectors on information to be encoded. | 2009-01-15 |
20090019334 | ERROR CORRECTION SYSTEM USING CONCATENATED CODES - This invention provides an error correction system whereby codes, including codes known to be optimum, may be concatenated together so that a longer code is produced which may be decoded by decoding the individual codes using any type of error correcting decoder including list decoders, Dorsch decoders in particular, and iterative decoders. The concatenated code consists of one or more codes having replicated codewords to which are added codewords from one or more other codes. The code construction is utilised in the receiver with a decoder that firstly decodes one or more individual codewords from a received vector. The detected codewords from this first decoding are used to undo the code concatenation within the received vector to allow the replicated codewords to be decoded. Examples of the performance benefits of the invention in comparison to the well known state of the art coding arrangement of LDPC codes, and turbo codes using iterative decoders are given for (256,128) and (512,256) codes. | 2009-01-15 |
20090019335 | AUXILIARY PATH ITERATIVE DECODING - A parallel iterative decoding system interposed between a network interface and a block memory matrix receives encoded data and both stores the data in a First-In-First-Out (“FIFO”) memory block and processes it through a timing recovery engine. The timing recovery engine delivers to an iterative decoder synchronized data samples and detects cycle slip. The iterative decoder thereafter performs a predetermined number of iterations to decode the data. Responsive to encoded data failing to converge after the predetermined number of iterations, the encoded data is communicated from the FIFO memory to an auxiliary decoder module. The auxiliary iterative error correction code decoder performs a second predetermined number of iterations to decode the data wherein the number of iterations performed by the auxiliary iterative error correction code decoder is greater than the primary iterative error correction code decoder. Converged data from the auxiliary decoder replaces otherwise null data stored in the block matrix memory. | 2009-01-15 |
20090019336 | MEMORY AND 1-BIT ERROR CHECKING METHOD THEREOF - A memory 1-bit error checking method is provided. Firstly, at least one piece of data fragment whose side is 2 | 2009-01-15 |
20090019337 | Methods and apparatus to compute CRC for multiple code blocks - A method and a circuit for generating cyclic redundancy checks. The method calculates a plurality of cyclic redundancy checks for a transport block with a plurality of information bits. At least one cyclic redundancy check among the plurality of cyclic redundancy checks is calculated based on a subset of information bits, and at least one information bit among the plurality of information bits is not within said subset of the information bits. In addition, a transport block cyclic redundancy check may be calculated based on all the information bits. | 2009-01-15 |
20090019338 | Communications device and wireless communications system - Turbo coding and decoding devices provide interleaving in the error correction coding process, which improves error correction capability. A turbo decoding device for decoding data obtained by performing error detection coding on a plurality of data blocks and further subjecting that data to turbo coding that includes interleaving in the coding process, comprises a rearrangement unit to perform interleaving between a first decoding a second decoding, an error detection unit to perform error detection processing for each block based on data after the first decoding, and an adjustment unit to adjust a likelihood indicated by data obtained after decoding in the first decoder but prior to the interleaving and corresponding to blocks evaluated as having no errors by the error detection unit. | 2009-01-15 |
20090019339 | POWER RECEPTION OPTIMIZATION METHOD, AND ASSOCIATED APPARATUS, FOR OPERATING UPON AN ENCODED DATA BLOCK - Apparatus, and an associated method, for recovering the informational content of an encoded data block. Data bursts are delivered to a receiver. A series of data bursts together include all of the informational content of the encoded data block. A detector detects delivery to the receiver of the data bursts. A determiner determines indicia associated with the communicated data. And, responsive thereto, the data is decoded, selectably utilizing fewer than all of the data bursts that form the encoded data block. | 2009-01-15 |
20090019340 | NON-SYSTEMATIC CODED ERROR CORRECTION - Methods are described that facilitate the detection and correction of data in memory systems or devices by encoding the data bits of a memory row or block in a non-systematic ECC code. This allows memory embodiments of the present invention to utilize reduced complexity error detection and correction hardware and/or routines to efficiently detect and correct corrupted user data in a segment of memory, such as a sector, word line row, or erase block. User data is not stored in a plaintext format in the memory array, allowing for an increased level of data security. The ECC code is distributed throughout the stored data in the memory segment, increasing the robustness of the ECC code and its resistance to damage or data corruption. | 2009-01-15 |
20090019341 | DYNAMIC MEMORY ARCHITECTURE EMPLOYING PASSIVE EXPIRATION OF DATA - Apparatus for passively tracking expired data in a dynamic memory includes a time stamp memory configurable for storing information relating to a refresh status of one or more corresponding data entries in the dynamic memory. The apparatus further includes a timer configurable for defining a desired window of time in which a refresh operation of data in the dynamic memory is to occur in order to ensure that the data is valid. Control circuitry is coupled to the time stamp memory and to the timer. The control circuitry is operative to manage the information stored in the time stamp memory relating to the refresh status of the one or more corresponding data entries in the dynamic memory. | 2009-01-15 |
20090019342 | Determining a Message Residue - A technique of determining a message residue includes accessing a message and simultaneously determining a set of modular remainders with respect to a polynomial for different respective segments of the message. The technique also includes determining a modular remainder with respect to the polynomial for the message based on the set of modular remainders and a set of constants determined prior to accessing the message. The modular remainder with respect to the polynomial for the message is stored in a memory. | 2009-01-15 |
20090019343 | Loss Compensation device, loss compensation method and loss compensation program - It is possible to save storage resources. A loss compensation device for compensating a loss in periodical signals when the loss occurs in an arbitrary section of the periodical signals which are divided into predetermined sections and received in time series, includes: a periodical signal storage which stores one or more sections of newly received periodical signals for a predetermined period of time; a loss detector which detects a loss of each section of the periodical signals; and an element periodical signal generator which generates a plurality of element periodical signals for interpolation having different waveforms, in accordance with the periodical signals stored in the periodical signal storage, at time of detection of the loss if the loss is detected by the loss detector. The plurality of element periodical signals generated by the element periodical signal generator are synthesized, and a result of the synthesizing is arranged at the section where the loss in the periodical signals has occurred. | 2009-01-15 |