02nd week of 2021 patent applcation highlights part 56 |
Patent application number | Title | Published |
20210012783 | Apparatus and Method for Encoding or Decoding a Multi-Channel Signal - An apparatus for encoding a multi-channel signal having at least three channels includes an iteration processor, a channel encoder and an output interface. The iteration processor is configured to calculate inter-channel correlation values between each pair of the at least three channels, for selecting a pair including a highest value or including a value above a threshold, and for processing the selected pair using a multi-channel processing operation to derive first multi-channel parameters for the selected pair and to derive first processed channels. The iteration processor is configured to perform the calculating, the selecting and the processing using at least one of the processed channels to derive second multi-channel parameters and second processed channels. The channel encoder is configured to encode channels resulting from an iteration processing to obtain encoded channels. The output interface is configured to generate an encoded multi-channel signal including the encoded channels and the first and second multi-channel parameters. | 2021-01-14 |
20210012784 | Apparatus, Method or Computer Program for estimating an inter-channel time difference - An apparatus for estimating an inter-channel time difference between a first channel signal and a second channel signal, includes a signal analyzer for estimating a signal characteristic of the first channel signal or the second channel signal or both signals or a signal derived from the first channel signal or the second channel signal; a calculator for calculating a cross-correlation spectrum for a time block from the first channel signal in the time block and the second channel signal in the time block; a weighter for weighting a smoothed or non-smoothed cross-correlation spectrum to obtain a weighted cross correlation spectrum using a first weighting procedure or using a second weighting procedure depending on a signal characteristic estimated by the signal analyzer, wherein the first weighting procedure is different from the second weighting procedure; and a processor for processing the weighted cross-correlation spectrum to obtain the inter-channel time difference. | 2021-01-14 |
20210012785 | METHOD FOR MULTI-STAGE COMPRESSION IN SUB-BAND PROCESSING - A sub-band processing system for reducing computational complexity and memory requirements is disclosed. The sub-band processing system includes: a first logic that partitions and stores a frequency spectrum of bins of real and imaginary data into a smaller number of sub-bands; a second logic that executes a first lossy compression for a first set of the sub-bands, wherein the first set includes those sub-bands having indices that are greater than or equal to a first index; and a third logic that executes, subsequent to a frequency spectrum processing of the lossy compressed data rendered by the second logic, a second lossy compression for a second set of the sub-bands, wherein the second set includes those sub-bands having indices that are less than the first index and greater than or equal to a second index. | 2021-01-14 |
20210012786 | SIGNAL PROCESSING METHODS AND APPARATUSES FOR ENHANCING SOUND QUALITY - Provided are a signal processing method and apparatus for enhancing sound quality. The signal processing method performed by a signal transmitting apparatus includes determining, based on a plurality of parameters, a valid bandwidth so as to encode an input signal; performing pre-processing on the input signal, based on the valid bandwidth; and encoding the pre-processed input signal, based on the valid bandwidth, and the signal processing method performed by a signal receiving apparatus includes decoding a bitstream or a packet received via a transmission channel; determining a valid bandwidth, based on a plurality of parameters used in the decoding; and performing post-processing on a decoded signal, based on the valid bandwidth. | 2021-01-14 |
20210012787 | DETECTION AND RESTORATION OF DISTORTED SIGNALS OF BLOCKED MICROPHONES - Methods, systems, and devices for mitigating audio interference are described. The methods, systems, and devices may relate to monitoring a parameter associated with an audio signal received by at least a first microphone of multiple microphones of a device, determining that the monitored parameter associated with the audio signal exceeds a threshold by comparing the monitored parameter to the threshold, determining an acoustic path interference associated with the monitored parameter based on the monitored parameter exceeding the threshold, the acoustic path interference including a physical interference in an acoustic path to at least the first microphone, and implementing a restoration process to mitigate the acoustic path interference based on determining the acoustic path interference associated with the monitored parameter. | 2021-01-14 |
20210012788 | AUDIO ALERT AUDIBILITY ESTIMATION METHOD AND SYSTEM - A method and system of estimating human perception of audibility of audio alerts in the presence of background noise. In the audibility estimation system, a microphone generates an input signal corresponding to an audio alert. A processor receives the input signal and generates an audibility metric representing human perception of audibility of the audio alert based on a comparison between a background noise estimate and an audio alert estimate, and causes an action to be taken based on the audibility metric. | 2021-01-14 |
20210012789 | SYSTEM AND METHOD FOR REDUCING DISTORTION AND ECHO LEAKAGE IN HANDS-FREE COMMUNICATION - A method of echo cancellation in hands-free communication is disclosed. The method includes: receiving, via a receive signal processor, a far-end audio signal; providing the far-end audio signal to: an acoustic echo canceller module as a reference signal, and at least one loudspeaker for playback; determining an external gain value associated with the far-end audio signal, the external gain applied to the far-end audio signal downstream of the receive signal processor and prior to playback from the at least one loudspeaker; adjusting at least one parameter of the acoustic echo canceller module based on the external gain value; receiving playback output of the far-end audio signal from the at least one loudspeaker as an input signal to a microphone; and processing the microphone input signal by the adjusted acoustic echo canceller module to produce an echo-cancelled signal. | 2021-01-14 |
20210012790 | SIGNAL ANALYSIS DEVICE, SIGNAL ANALYSIS METHOD, AND SIGNAL ANALYSIS PROGRAM - A signal analysis device ( | 2021-01-14 |
20210012791 | IMAGE REPRESENTATION OF A CONVERSATION TO SELF-SUPERVISED LEARNING - A system and method for receiving, using one or more processors, a first conversation; identifying, using the one or more processors, a first set of utterances associated with a first conversation participant and a second set of utterances associated with a second conversation participant; and generating, using the one or more processors, a first image representation of the first conversation, the first image representation of the first conversation visually representing the first set of utterances and second set of utterances, wherein an utterance is visually represented by a first parameter associated with timing of the utterance, a second parameter associated with a number of tokens in the utterance, and a third parameter associated with which conversation participant was a source of the utterance. | 2021-01-14 |
20210012792 | METHOD FOR DETECTING VOICE, APPARATUS FOR DETECTING VOICE, AND CHIP FOR PROCESSING VOICE - A method for detecting voice, an apparatus for detecting voice, and a chip for processing voice are disclosed. The apparatus includes: a sub-band generation module and a voice activity detection module; wherein the sub-band generation module is configured to process a current time-domain signal frame to obtain sub-band time-domain signals, and the voice activity detection module is configured to determine, according to amplitudes of the sub-band time-domain signals in the current time-domain signal frame, whether the current time-domain signal frame is an effective voice signal. The apparatus for detecting voice may be practiced in a time domain, such that complexity of algorithms is lowered, and power consumption is reduced. | 2021-01-14 |
20210012793 | Writer with HMTS (High Moment Trailing Shield) Aligned with Spin Layer - A PMR (perpendicular magnetic recording) write head configured for microwave assisted magnetic recording (MAMR) includes a spin-torque oscillator (STO) and trailing shield formed of high moment magnetic material (HMTS). By patterning the STO and the HMTS in a simultaneous process the HMTS and the STO layer are precisely aligned and have very similar cross-track widths. In addition, the write gap at an off-center location has a thickness that is independent from its center-track thickness and the write gap total width can have a flexible range whose minimum value is the same width as the STO width. | 2021-01-14 |
20210012794 | Writer with HMTS (HIgh Moment Trailing Shield) Aligned with Spin Layer - A PMR (perpendicular magnetic recording) write head configured for microwave assisted magnetic recording (MAMR) includes a spin-torque oscillator (STO) and trailing shield formed of high moment magnetic material (HMTS). By patterning the STO and the HMTS in a simultaneous process the HMTS and the STO layer are precisely aligned and have very similar cross-track widths. In addition, the write gap at an off-center location has a thickness that is independent from its center-track thickness and the write gap total width can have a flexible range whose minimum value is the same width as the STO width. | 2021-01-14 |
20210012795 | Multi-Layer Actuator Electrode Configuration For Resonance Improvement - A piezoelectric actuator assembly is described. The piezoelectric actuator assembly includes a first, second and third active piezoelectric layers. The first layer includes a top surface and a bottom surface. The second layer includes a top surface and a bottom surface over the top surface of the first layer. The third layer includes a top surface and a bottom surface over the top surface of the second layer. The first single and second layers can define a first effective electrode length. Similarly, the second and third layers can define a second effective electrode length configured to be longer than the first effective electrode length. | 2021-01-14 |
20210012796 | HARD DISK DRIVE - According to one embodiment, there is provided a hard disk drive including a first recording surface, a second recording surface, a first magnetic head, a first actuator and a second actuator that move the first magnetic head, a second magnetic head, a third actuator and a fourth actuator that move the second magnetic head, a fifth actuator that moves the second actuator and the fourth actuator, a drive circuit that implements at least one of a first mode in which the second actuator and the fourth actuator operate differently from each other or a second mode in which the first and third actuators operate differently from each other, and a controller that controls the drive circuit. | 2021-01-14 |
20210012797 | IN-PIVOT HYBRID STEPPER MOTOR FOR BALL SCREW CAM ELEVATOR MECHANISM FOR REDUCED-HEAD HARD DISK DRIVE - An approach to a reduced-head hard disk drive (HDD) involves an actuator elevator subsystem that includes a ball screw cam assembly with a hybrid permanent magnet (PM)-variable reluctance (VR) stepper motor disposed therein, to rotate the cam screw, which vertically translates an actuator arm assembly so that a corresponding pair of read-write heads can access different magnetic-recording disks of a multiple-disk stack. A suitably configured hybrid stepper motor can provide 200 full steps/rev for a 3.8 mm translation. Thus, to meet or surpass a step resolution of 6 μm/μstep or 0.5625°/μstep, the hybrid stepper motor would only need to be operated at 4 micro-step mode in order to achieve a 0.45°/μstep or 0.00475 mm/μstep, which enables a smoother motion since the available holding torque at the 4 | 2021-01-14 |
20210012798 | MAGNETIC RECORDING MEDIUM - A magnetic recording medium is provided and includes a layer structure including a magnetic layer, a non-magnetic layer, and a base layer in this order, in which an average thickness t | 2021-01-14 |
20210012799 | MAGNETIC RECORDING MEDIUM - A tape-shaped magnetic recording medium includes a substrate; and a magnetic layer that is provided on the substrate and contains a magnetic powder. An average thickness of the magnetic layer is not more than 90 nm, an average aspect ratio of the magnetic powder is not less than 1.0 and not more than 3.0, the coercive force Hc1 in a vertical direction is not more than 3000 Oe, and the coercive force Hc1 in the vertical direction and a coercive force Hc2 in a longitudinal direction satisfy a relationship of Hc2/Hc1≤0.8. | 2021-01-14 |
20210012800 | MAGNETIC RECORDING MEDIUM - A tape-shaped magnetic recording medium is provided with a base, an underlayer provided on the base, and a magnetic layer provided on the underlayer including magnetic powder including hexagonal ferrite. The underlayer and the magnetic layer include lubricant. The magnetic layer includes a surface provided with a large number of holes, and arithmetic average roughness Ra of the surface is 2.5 nm or smaller. A BET specific surface area of a whole of the magnetic recording medium in a state in which the lubricant is removed is 3.5 m | 2021-01-14 |
20210012801 | MAGNETIC DISC, ALUMINUM ALLOY SUBSTRATE FOR MAGNETIC DISC, AND PRODUCTION METHOD FOR ALUMINUM ALLOY SUBSTRATE - Provided are a magnetic disk and a method of fabricating the magnetic disk. The magnetic disk includes an aluminum alloy plate fabricated by a process involving a CC method and a compound removal process, and an electroless Ni—P plating layer disposed on the surface of the plate. The aluminum alloy plate is composed of an aluminum alloy containing 0.4 to 3.0 mass % (hereinafter abbreviated simply as “%”) of Fe, 0.1% to 3.0% of Mn, 0.005% to 1.000% of Cu, 0.005% to 1.000% of Zn, with a balance of Al and unavoidable impurities. In the magnetic disk, the maximum amplitude of waviness in a wavelength range of 0.4 to 5.0 mm is 5 nm or less, and the maximum amplitude of waviness in a wavelength range of 0.08 to 0.45 mm is 1.5 nm or less. | 2021-01-14 |
20210012802 | OPTICAL DISK RECORDING METHOD, OPTICAL DISK DEVICE, AND INTEGRATED CIRCUIT - A mark corresponding to recording data is formed on an optical disk by: encoding the recording data in accordance with a modulation code and generating encoded data; classifying the encoded data by a combination of at least two of a mark length of a mark, a space length of a preceding space, the mark length of a preceding mark, and the space length of a succeeding space; setting a correction amount for adjusting the position of the start edge and the end edge of a recording pulse based on an evaluation index of a decoding result, which is a result of decoding a reproduction signal of the encoded data, for each of the classification; and generating the recording pulse corresponding to the encoded data by using the correction amount corresponding to the classification of the run length of the encoded data. | 2021-01-14 |
20210012803 | MAGNETIC RECORDING APPARATUS AND METHOD OF CONTROLLING MAGNETIC HEAD THEREOF - According to one embodiment, a magnetic recording apparatus measures and stores recording signal quality of a disk at an initial stage, inspects the recording signal quality before data is recorded, determines whether or not the recording signal quality obtained in the inspection satisfies a standard when compared to the stored recording signal quality at the initial stage, adjusts, based on a result of the determination, light irradiation power of a light irradiation element so as to satisfy the standard, determines a read offset amount based on a result of the adjustment, and performs control so that a position of a read head is shifted based on the determined read offset amount. | 2021-01-14 |
20210012804 | CARTRIDGE MEMORY, RECORDING MEDIUM CARTRIDGE, AND METHOD OF PRODUCING THE SAME - [Object] A cartridge memory according to an embodiment of the present technology is a cartridge memory for a recording medium cartridge, including: a memory unit; and a capacity setting unit. The memory unit has a memory capacity capable of storing management information relating to a second information recording medium configured to be capable of recording information with a second data track number larger than a first data track number. The capacity setting unit is configured to be capable of setting a data storage area limited to a first capacity capable of storing management information relating to a first information recording medium configured to be capable of recording information with the first data track number. | 2021-01-14 |
20210012805 | MAGNETIC RECORDING MEDIUM AND CARTRIDGE - [Object] Provided is a technology that is capable of further improving a recording density of data. | 2021-01-14 |
20210012806 | SETTING BIAS CURRENTS AND LIMITING CORROSION IN TMR SENSORS - A method includes determining whether a tunneling magnetoresistance (TMR) sensor is corroded using resistance, amplitude and signal to noise ratio (SNR) measurements of the sensor. A method to determine whether a TMR sensor is corroded includes determining an expected initial resistance value, R | 2021-01-14 |
20210012807 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM - Problem: An information processing device, an information processing method, and a program are to be provided. | 2021-01-14 |
20210012808 | VIDEO CURATION SERVICE FOR PERSONAL STREAMING - Aspects of the subject disclosure may include, for example, a device that includes a processing system with a processor, and a memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations such as receiving user input comprising a keyword identifying an object, monitoring a video recording during a generation of the video recording by a camera, wherein the monitoring includes detecting the object being captured by the camera, creating a video clip from the video recording, wherein the video clip comprises a start point and a stop point in the video recording determined by a machine learning algorithm, and sending a notification of the creating of the video clip. Other embodiments are disclosed. | 2021-01-14 |
20210012809 | DYNAMIC AUDIOVISUAL SEGMENT PADDING FOR MACHINE LEARNING - Techniques for padding audiovisual clips (for example, audiovisual clips of sporting events) for the purpose of causing the clip to have a predetermined duration so that the padded clip can be evaluated for viewer interest by a machine learning (ML) algorithm. The unpadded clip is padded with audiovisual segment(s) that will cause the padded clip to have a level of viewer interest that it would have if the unpadded clip had been longer. In some embodiments the padded segments are synthetic images generated by a generative adversarial network such that the synthetic images would have the same level of viewer interest (as adjudged by an ML algorithm) as if the unpadded clip had been shot to be longer. | 2021-01-14 |
20210012810 | SYSTEMS AND METHODS TO ASSOCIATE MULTIMEDIA TAGS WITH USER COMMENTS AND GENERATE USER MODIFIABLE SNIPPETS AROUND A TAG TIME FOR EFFICIENT STORAGE AND SHARING OF TAGGED ITEMS - Example methods and apparatus to add a tagged snippet of multimedia content to a playlist are disclosed. An example apparatus comprises an automatic content recognition search service to search a fingerprint database to find a match between query fingerprints for a snippet of multimedia content captured from a multimedia program at a timestamp and reference fingerprints of matching reference multimedia content stored in the fingerprint database, a tag service to generate a tag representing the snippet of multimedia content, wherein the tag, the timestamp, meta information associated with the matching reference multimedia content, and a monitored variable for a number of viewers of the snippet of multimedia content are stored in a database storage as a tagged snippet of multimedia content, and to add the tagged snippet of multimedia content to a playlist for an identified multimedia program if the number of viewers of the tagged snippet exceeds a threshold. | 2021-01-14 |
20210012811 | PLAYBACK DEVICE, PLAYBACK METHOD, AND RECORDING MEDIUM - A decoding system decodes a video stream, which is encoded video information. The decoding system includes a decoder that acquires the video steam and generates decoded video information, and a maximum luminance information acquirer that acquires, in a case where a dynamic range of luminance of the video stream is a second dynamic range that is wider than a first dynamic range, maximum luminance information indicating the maximum luminance of the video stream from the video stream. The decoding system also includes an outputter that outputs the decoded video information and the maximum luminance information. Where the dynamic range of luminance of the video stream is expressed by the maximum luminance of all pictures in the video stream as the maximum luminance information, the outputter outputs the decoded video information, along with the maximum luminance information indicating the maximum luminance of all pictures in the video stream. | 2021-01-14 |
20210012812 | PLAYBACK DEVICE, PLAYBACK METHOD, AND RECORDING MEDIUM - A decoding system decodes a video stream, which is encoded video information. The decoding system includes an attribute information acquirer that acquires first attribute information, indicating whether a dynamic range of luminance of the video stream is a first dynamic range or a second dynamic range that is wider than the first dynamic range, and a decoder that acquires the video steam and generates decoded video information. The decoding system also includes an outputter that, in a case where the first attribute information indicates the second dynamic range, outputs the decoded video information and maximum luminance information indicating a maximum luminance of the video stream in accordance with the second dynamic range. Further, in other cases, the outputter outputs the decoded video information and maximum luminance information indicating the maximum luminance of all pictures in the video stream. | 2021-01-14 |
20210012813 | Bi-Level Specificity Content Annotation Using an Artificial Neural Network - A content annotation system includes a computing platform having a hardware processor and a memory storing a tagging software code including an artificial neural network (ANN). The hardware processor executes the tagging software code to receive content having a content interval including an image of a generic content feature, encode the image into a latent vector representation of the image using an encoder of the ANN, and use a first decoder of the ANN to generate a first tag describing the generic content feature based on the latent vector representation. When a specific content feature learned by the ANN corresponds to the generic content feature described by the first tag, the tagging software code uses a second decoder of the ANN to generate a second tag uniquely identifying the specific content feature based on the latent vector representation, and tags the content interval with the first and second tags. | 2021-01-14 |
20210012814 | Regulated Negative Charge Pump Circuitry and Methods - In a particular implementation, a circuit comprises: a first branch comprising a first transistor, where the first branch is configured to generate a first voltage; a second branch comprising a second transistor, where the second branch is configured to generate a second voltage; and a comparator configured to generate an output signal based on a comparison of the first and second voltages. Also, the output signal may be configured to regulate an output voltage of one or more negative charge pump circuits coupled to the circuit. | 2021-01-14 |
20210012815 | MEMORY DEVICES INCLUDING SWITCH CIRCUIT THAT OPERATES REGARDLESS OF POWER SUPPLY VOLTAGE - A memory device includes a memory cell connected to a bit line and a source line, a read and write circuit configured to read data of the memory cell and/or write data in the memory cell, and a switch circuit configured to receive a selection signal based on a power supply voltage. The switch circuit includes a first switch connected between the bit line and the read and write circuit, a second switch connected between the source line and the read and write circuit, and a switch controller configured to turn on or turn off the first and the second switches based on the selection signal using one of a read voltage and a write voltage that are different from the power supply voltage. | 2021-01-14 |
20210012816 | SEMICONDUCTOR DEVICE - A semiconductor device with a high on-state current and high operating speed is provided. The semiconductor device includes a transistor and a first circuit. The transistor includes a first gate and a second gate, and the first gate and the second gate include a region where they overlap each other with a semiconductor layer therebetween. The first circuit includes a temperature sensor and a voltage control circuit. The temperature sensor has a function of obtaining temperature information and outputting the temperature information to the voltage control circuit. The voltage control circuit has a function of converting the temperature information into a control voltage. The first circuit applies the control voltage to the second gate. | 2021-01-14 |
20210012817 | INPUT/OUTPUT LINE SHARING FOR MEMORY ARRAYS - Methods, systems, and devices for input/output line sharing for memory subarrays are described. I/O lines may be shared across subarrays, which may correspond to separate memory tiles. The sharing of I/O lines may allow an I/O line to carry data from one subarray in response to access commands associated with one address range, and to carry data from another subarray in response to access commands associated with another address range. In some cases, sense amplifiers and other components may also be shared across subarrays, including across subarrays in different banks. The sharing of I/O lines may, in some cases, support activating only a subset of subarrays in a bank when accessing data stored in the bank, which may provide power savings. | 2021-01-14 |
20210012818 | APPARATUSES INCLUDING TEMPERATURE-BASED THRESHOLD VOLTAGE COMPENSATED SENSE AMPLIFIERS AND METHODS FOR COMPENSATING SAME - Systems, methods, and apparatuses for temperature-compensated operation of electronic devices are described. For example, an apparatus for performing voltage compensation on a sense amplifier based on temperature may include a sense amplifier control circuit coupled to the sense amplifier to provide a compensation pulse to the sense amplifier, wherein the sense amplifier operates in a voltage compensation phase during the compensation pulse. The apparatus may determine the compensation pulse responsive to a voltage compensation duration signal that is based on the operating temperature of the apparatus. The voltage compensation occurs when there is no activate command immediately before or immediately after so that compensation duration change do not happen during an activate command from the command decoder. | 2021-01-14 |
20210012819 | APPARATUSES AND METHODS FOR CONTROLLING WORD LINE DISCHARGE - Apparatuses and methods for driving word driver lines in a gradual manner are disclosed herein. Word driver lines may be driven to intermediate potentials between high and low potentials. In some examples, the word driver lines may be driven in a step-wise manner. In some examples, the intermediate potential may be a bias voltage. The bias voltage may be provided by a bias voltage generator. One or more enable signals may be used to control the driving of the word driver line. In some examples, an address signal may be used to control the driving of the word driver line. Driving the word driver line in a gradual manner may cause a word line to discharge in a gradual manner in some examples. | 2021-01-14 |
20210012820 | MAGNETIC MEMORY AND METHOD FOR CONTROLLING THE SAME - A magnetic memory includes a storage element including a first ferromagnetic layer, a first conductive layer which faces the first ferromagnetic layer in a first direction and extends in a second direction different from the first direction, and a first conductive part and a second conductive part which are connected to the first conductive layer at positions which sandwich the first ferromagnetic layer in the second direction when seen in the first direction; and a plurality of first switching elements which are electrically connected to the first conductive part of the storage element. | 2021-01-14 |
20210012821 | REFERENCE GENERATION FOR VOLTAGE SENSING IN A RESISTIVE MEMORY - A sense amplifier circuit includes a reference path, a cell path, and a comparator circuit. The reference path includes a first current load device and a reference comparison node in which the reference path is coupled to a cell reference circuit during a read, wherein the first current load device includes a control input for controlling a current of the reference path. The cell path includes a second current load device and a cell comparison node in which the cell path is coupled to a memory cell during a read, wherein the second current load device includes a control input for controlling a current of the cell path. The comparator circuit indicates a data value being stored in the memory cell based on a comparison of voltages at the reference and cell comparison nodes. Different signals are provided to the control inputs of the first and second current load devices. | 2021-01-14 |
20210012822 | SENSING SCHEME FOR STT-MRAM USING LOW-BARRIER NANOMAGNETS - The present disclosure relates to a structure including a non-fixed read-cell circuit configured to switch from a first state to a second state based on a state of a memory cell to generate a sensing margin. | 2021-01-14 |
20210012823 | Bias Generation Circuitry - Various implementations described herein are directed to device having a memory block and a sense amplifier coupled to the memory block. The device may include a bias generator that applies a bias signal to the sense amplifier for regulating read current to the sense amplifier for faster activation of the memory block. | 2021-01-14 |
20210012824 | Memory Cells And Methods Of Forming A Capacitor Including Current Leakage Paths Having Different Total Resistances - A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed. | 2021-01-14 |
20210012825 | CIRCUITRY BORROWING FOR MEMORY ARRAYS - Methods, systems, and devices for circuitry borrowing in memory arrays are described. In one example, a host device may transmit an access command associated with data for a first memory section to a memory device. The first memory section may be located between a second memory section and a third memory section. A first set of circuitry shared by the first memory section and the second memory section may be operated using drivers associated with the first memory section and drivers associated with the second memory section. A second set of circuitry shared by the first memory section and the third memory section may be operated using drivers associated with the first memory section and drivers associated with the third memory section. An access operation may be performed based on operating the first set of circuitry and the second set of circuitry. | 2021-01-14 |
20210012826 | SINGLE PLATE CONFIGURATION AND MEMORY ARRAY OPERATION - Methods, systems, and devices for a single plate configuration and memory array operation are described. A non-volatile memory array may utilize a single plate to cover a subset of the array. One or more memory cells of the subset may be selected by operating the plate and an access line of an unselected memory cell at a fixed voltage. A second voltage may be applied to an access line of the selected cell, and subsequently reduced to perform an access operation. Removing the applied voltage may allow for the memory cell to undergo a recovery period prior to a subsequent access operation. | 2021-01-14 |
20210012827 | POWER DOMAIN SWITCHES FOR SWITCHING POWER REDUCTION - Methods, systems, and devices for power domain switches for switching power reduction are described. A device, such as a memory device, may receive an indication (e.g., a command) for a power domain component of the device to transition between states. The device may float first and second gate drivers. A pass gate may be used to connect (e.g., short) the first switch to the second switch. The pass gate may be deactivated to isolate the gates. The first and second gate drivers may be enabled, and the first and second gate drivers drive the first and second switches to disconnect the power domain component from a power source to deactivate the power domain component, or connect to the power source to activate the power domain component. The energy to switch between active and inactive states may thereby be reduced. | 2021-01-14 |
20210012828 | VERTICAL MEMORY DEVICE - A memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines. | 2021-01-14 |
20210012829 | SORT OPERATION IN MEMORY - Examples of the present disclosure provide apparatuses and methods related to performing a sort operation in a memory. An example apparatus might include a a first group of memory cells coupled to a first sense line, a second group of memory cells coupled to a second sense line, and a controller configured to control sensing circuitry to sort a first element stored in the first group of memory cells and a second element stored in the second group of memory cells by performing an operation without transferring data via an input/output (I/O) line. | 2021-01-14 |
20210012830 | STORAGE DEVICE AND METHOD FOR OPERATING STORAGE DEVICE - A storage device may include a monitoring module which monitors a characteristic degradation rate of a plurality of blocks included in a cell array of a nonvolatile memory; a group management module which designates the plurality of blocks as one or more groups, on the basis of a monitoring result of the monitoring module; a refresh period management module which determines refresh periods for each of the one or more groups; and a processor which performs refresh on the one or more groups in accordance with the determined refresh periods. | 2021-01-14 |
20210012831 | MEMORY DEVICE AND MEMORY SYSTEM COMPRISING THE SAME - A memory device includes a plurality of memory chips for writing and reading data in response to a control command and an address signal, and a control logic circuit for transferring the control command and the address signal to the plurality of the memory chips, and receiving a first command from a memory controller to perform a first operation, different from a refresh operation, on at least one of a plurality of the memory chips. The control logic circuit, in response to a refresh command, transmits the first command to at least one of a plurality of the memory chips and performs the first operation during a pre-determined refresh time interval without carrying out the refresh operation. | 2021-01-14 |
20210012832 | ROW HAMMER CORRECTION LOGIC FOR DRAM WITH INTEGRATED PROCESSOR - A memory device comprises one or more bank(s), each bank comprising a plurality of DRAM memory rows, the memory device further comprising: an external access port configured to allow an external memory controller to activate and then access the memory rows of each bank; one or more internal processor(s) capable of activating and then accessing the memory rows of each bank; a logic for detecting triggering of the Row Hammer configured to monitor, for each bank, the activation commands from the external memory controller and from one or more internal processor(s), the logic for detecting triggering including memory storage and a logic for sending preventive refresh configured to implement a refresh operation for one or more of the adjacent rows of each identified row by emitting refresh requests instead of the periodic refresh requests generated by the external memory controller, delaying one or more of said periodic refresh requests. | 2021-01-14 |
20210012833 | STATIC MEMORY BASED ON COMPONENTS WITH CURRENT-VOLTAGE HYSTERESIS CHARACTERISTICS - The present disclosure discloses an SRAM cell circuit and an SRAM array circuit. The cell circuit includes a data storage module, a write operation module, and a read operation module. The data storage module consists of the component with the current-voltage hysteresis characteristic and is configured to store data with the current-voltage hysteresis characteristic. The data storage module includes a write operation port and a read operation port, and the data information stored in the data storage module may change without external energy input. The write operation module is coupled to the write operation port and is configured to perform write operation on the stored information. The write operation module ensures the stored information unchanged by continuously controlling the write operation port while not changing the stored information. The read operation module is coupled to the read operation port and configured to perform read operation on the stored information. | 2021-01-14 |
20210012834 | METHODS AND APPARATUS FOR READING NAND FLASH MEMORY - Methods and apparatus for reading NAND flash memory are disclosed. In an embodiment, a method is provided for reading a NAND flash memory that includes strings of memory cells that are coupled to bit lines and word lines. The method includes precharging a plurality of bit lines to a precharge voltage level, and applying a sequence of word line voltages to a selected word line. The method also includes initiating discharge of one or more bit lines associated with one or more cells, respectively. The method also includes controlling discharging current of discharging bit lines to achieve identical discharge rates, waiting for a discharging time period for each bit line that is discharging, and latching bit line data at an end of each discharge time period. | 2021-01-14 |
20210012835 | MEMORY DEVICE HAVING AN INCREASED SENSING MARGIN - A memory device includes a memory cell array including memory cells disposed at points at which word lines and bit lines intersect, a first decoder circuit determining a selected bit line and non-selected bit lines among the bit lines, a second decoder circuit determining a selected word line and non-selected word lines among the word lines, a current compensation circuit providing a current path drawing a compensation current from the selected word line to compensate for off currents flowing in the non-selected bit lines, a first sense amplifier comparing a voltage of the selected word line with a reference voltage and outputting an enable signal, and a second sense amplifier outputting a voltage difference between the voltage of the selected word line and the reference voltage during an operating time determined by the enable signal in a readout operation mode of the memory device. | 2021-01-14 |
20210012836 | PHASE CHANGE MEMORY WITH SUPPLY VOLTAGE REGULATION CIRCUIT - A voltage regulator and a phase change memory are disclosed. In an embodiment a phase-change memory includes an array of a plurality of phase-change memory cells, an address decoder configured for receiving an address signal and selecting a sub-area in the array of the plurality of memory cells, the selected sub-area having a given number of bits of a data signal and a writing circuit including a control circuit configured for receiving the data signal and determining, for each memory cell in the selected sub-area, whether a respective bit of the data signal indicates that the memory cell is to be changed from the amorphous state to the polycrystalline state and one or more driving circuits supplied via a regulated voltage and configured for applying the set current for the first interval to the memory cells that are to be changed from the amorphous state to the polycrystalline state. | 2021-01-14 |
20210012837 | MEMORY DEVICE FOR COMPENSATING FOR CURRENT OF OFF CELLS AND OPERATING METHOD THEREOF - A memory device includes a memory cell array including a plurality of memory cells arranged at points where a plurality of word lines and a plurality of bit lines intersect; a sense amplifier configured to amplify, in a read operation mode of the memory device, a voltage difference value between a voltage of a selected word line connected to a selected memory cell of the plurality of memory cells and a reference voltage; and a leakage current compensation circuit connected to a selected word line path between the selected memory cell and the sense amplifier and configured to compensate for a total leakage current generated by unselected memory cells connected to the selected word line in the read operation mode. | 2021-01-14 |
20210012838 | RRAM WRITE - Disclosed is a resistive random access memory (RRAM) circuit and related method to limit current, or ramp voltage, applied to a source line or bitline of an RRAM array. The RRAM array has one or more source lines and one or more bitlines. A control circuit sets an RRAM cell to a low resistance state in a set operation, and resets the RRA.M cell to a high resistance state in a reset operation. A voltage applied to a bitline or source line is ramped during a first time interval, held to a maximmn voltage value during a second interval, and ceased after the second time interval. | 2021-01-14 |
20210012839 | RESISTIVE RANDOM ACCESS MEMORY AND RESETTING METHOD THEREOF - Provided is a resistive random access memory (RRAM) including at least one memory cell. The at least one memory cell includes a top electrode, a bottom electrode, a data storage layer, an oxygen gettering layer, a first barrier layer, and an oxygen supplying layer. The data storage layer is disposed between the top electrode and the bottom electrode. The oxygen gettering layer is disposed between the data storage layer and the top electrode. The first barrier layer is disposed between the oxygen gettering layer and the data storage layer. The oxygen supplying layer is disposed between the oxygen gettering layer and the top electrode and/or between the oxygen gettering layer and the first barrier layer. | 2021-01-14 |
20210012840 | METHOD OF ERASING DATA IN NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY DEVICE PERFORMING THE SAME AND MEMORY SYSTEM INCLUDING THE SAME - A nonvolatile memory device includes a memory cell region, a peripheral circuit region, a memory block in the memory cell region, a row decoder in the peripheral circuit region, and a control circuit in the peripheral circuit region. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes memory cells stacked in a direction intersecting a substrate, and is divided into a plurality of sub-blocks configured to be erased independently. The row decoder selects the memory block by units of a sub-block. The control circuit receives a data erase command for a selected sub-block among the plurality of sub-blocks, performs a data read operation on at least one victim sub-block among the plurality of sub-blocks in response to the data erase command, selectively performs a soft program operation on the at least one victim sub-block based on a result of the data read operation, and performs a data erase operation on the selected sub-block after the data read operation is performed and the soft program operation is selectively performed. | 2021-01-14 |
20210012841 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a controller configured to execute a read operation. In the read operation, the controller is configured to: apply first and second read voltages to a word line, read data at each of first and second times, apply the first voltage to the source line at each of the first and second times, apply a second voltage to the source line during the application of the first read voltage to the word line and before the first time, and apply a third voltage to the source line during the application of the second read voltage to the word line and before the second time. | 2021-01-14 |
20210012842 | METHOD AND CIRCUIT FOR PROVIDING AUXILIARY POWER AND STORAGE DEVICE INCLUDING THE SAME - A method of providing an auxiliary power by an auxiliary power supply. The method may include converting an external power to a plurality of charging voltages; charging a charging circuit with a first charging voltage of the plurality of charging voltages; monitoring a voltage of the charging circuit; when capacitance of the charging circuit is less than a first reference capacitance, charging the charging circuit with a second charging voltage of the plurality of charging voltages, the second charging voltage being higher than the first charging voltage by a first voltage amount; and providing an auxiliary power to outside the auxiliary power supply. The auxiliary power may be generated based on the voltage of the charging circuit. | 2021-01-14 |
20210012843 | VOLTAGE GENERATION CIRCUIT WHICH IS CAPABLE OF EXECUTING HIGH-SPEED BOOST OPERATION - According to one embodiment, a voltage generation circuit includes a first boost circuit, a voltage division circuit, a first detection circuit, a capacitor and a first switch. The first boost circuit outputs a first voltage. The voltage division circuit divides the first voltage. The first detection circuit is configured to detect a first monitor voltage supplied to the first input terminal, based on a reference voltage which is supplied to a second input terminal of the first detection circuit, and to control an operation of the first boost circuit. The capacitor is connected between an output terminal of the first boost circuit and the first input terminal of the first detection circuit. The first switch cuts off a connection between the capacitor and the first detection circuit, based on an output signal of the first detection circuit, until the first voltage is output from the first boost circuit. | 2021-01-14 |
20210012844 | ENDURANCE AND SERVICEABILITY IN SOLID STATE DRIVES - Systems, apparatuses and methods may provide technology for intelligent drive wear management. The technology may include determining a difference between a wear value derived for a first solid state storage drive and a wear value derived for a second solid state storage drive, and if the difference in wear value exceeds a wear skew threshold, swapping content between the first drive and the second drive. The technology may also include sorting an array of solid state storage drives into a plurality of drive groups based on a wear value derived for each drive, and determining, for a first pair of drives in a drive group, a difference in wear value between the drives in the first pair. Respective pairs of drives in a drive group may be selected based on the drive wear value and a drive rotation counter value associated with each drive. The technology may further include determining an average wear value for each drive group based on the wear values of each drive in the drive group and providing for maintenance service for the drives in the drive group if the average wear value for the drive group exceeds a potential drive failure threshold. | 2021-01-14 |
20210012845 | DECISION FOR EXECUTING FULL-MEMORY REFRESH DURING MEMORY SUB-SYSTEM POWER-ON STAGE - A system includes a plurality of memory devices and a processing device (e.g., a controller), operatively coupled to the plurality of memory devices. The processing device is to detect a power-on of the system and determine a read-retry trigger rate (TR) of a subset of codewords of the plurality of memory devices during a time interval after an initialization of the memory component. The processing device is further to determine whether the TR satisfies a threshold criterion. In response to the TR not satisfying the threshold criterion, the processing device is to initialize a full-memory refresh of the plurality of memory devices. | 2021-01-14 |
20210012846 | LAYOUT STRUCTURE OF MEMORY ARRAY - A layout method includes: forming a layout structure of a memory array having a first row and a second row, wherein each of the first row and the second row comprises a plurality of storage cells; disposing a word line between the first row and the second row; disposing a plurality of control electrodes across the word line for connecting the plurality of storage cells of the first row and the plurality of storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the plurality of control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the plurality of control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line. | 2021-01-14 |
20210012847 | SHIFT REGISTER AND DRIVING METHOD, GATE DRIVING CIRCUIT, AND DISPLAY DEVICE - A shift register includes an input circuit, a first output circuit, a second output circuit, a pull-down control circuit, a pull-down circuit, and a reset circuit. The shift register provided by the disclosure can drive two rows of gate lines. | 2021-01-14 |
20210012848 | Track-and-Hold Circuit - A track-and-hold circuit with a high sampling rate and reduced power consumption is provided. A track-and-hold circuit performing switching between a track mode in which a data signal that is equivalent to an input data signal is output and a hold mode in which a data signal which is input at a time of switching from the track mode to the hold mode is held and output, by using a clock signal, such that only the data signal in the hold mode is output, the track-and-hold circuit including: two sampling circuits configured to be connected in parallel to an input of the data signal and receive an in-phase data signal; a clock circuit configured to input a clock signal, which has a phase opposite to a phase of a clock signal input to one of the two sampling circuits, to the other of the two sampling circuits; and a multiplexer circuit configured to select and output a data output of either one of the two sampling circuits that is in the hold mode, by using the clock signal. | 2021-01-14 |
20210012849 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES - A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information. | 2021-01-14 |
20210012850 | RECOVERY MANAGEMENT OF RETIRED SUPER MANAGEMENT UNITS - A system includes a memory component, and a processing device coupled with the memory component. The processing device to identify a group of management units of the memory component, wherein the group of management units is included in a set of retired groups of management units, select a management unit from the group of management units, perform a media integrity check on the management unit to determine a failed bit count of the management unit, and in response to the failed bit count of the management unit failing to satisfy a threshold criterion, remove the group of management units from the set of retired groups of management units. | 2021-01-14 |
20210012851 | UNCORRECTABLE ECC - Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized. | 2021-01-14 |
20210012852 | SEMICONDUCTOR MEMORY DEVICE, MEMORY CONTROLLER, AND ERROR NOTIFICATION METHOD - A semiconductor memory device includes a data bus terminal group for outputting read data to an external device or inputting write data from an external device, a first terminal from or into which 1-bit data is output or input, a DBI circuit that executes a Data Bus Inversion (DBI) function, an error detection circuit that detects an internal error, and an information superimposing circuit that superimposes predetermined output information onto the 1-bit data to be output from the first terminal and the read data to be output from the data bus terminal group. The predetermined output information includes first output information indicating whether or not an output bit pattern of the data bus terminal group is inverted, and second output information indicating whether or not an internal error has been detected by the error detection circuit. | 2021-01-14 |
20210012853 | STORAGE CONTROL CIRCUIT, STORAGE APPARATUS, IMAGING APPARATUS, AND STORAGE CONTROL METHOD - It is aimed to detect an error of an address abnormality in a memory. An address error detection information generating unit generates address error detection information for detecting an error relating to an access address for a memory. A control part stores the address error detection information generated by the address error detection information generating unit in the memory at a time of write access. An error detecting part compares the address error detection information generated by the address error detection information generating unit with the address error detection information stored in the memory to detect an error at a time of read access. | 2021-01-14 |
20210012854 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - The non-volatile semiconductor memory device comprises a non-volatile semiconductor memory, a controller for controlling the non-volatile semiconductor memory, the controller includes a reset terminal capable of receiving a reset signal from a host, an interface circuit capable of receiving a sleep command, and a data storing circuit, when the reset signal is received in a state which the interface circuit is being supplied with power, the data storing circuit is reset, when a sleep command is received in a state which the interface circuit is being supplied with power, the data necessary for communication with the host or the non-volatile semiconductor memory device is stored into the data storing circuit and power to the interface circuit is interrupted and when the reset signal is received in a state which power to the interface circuit is interrupted, the data is read from the data storing circuit. | 2021-01-14 |
20210012855 | Method and Apparatus for enabling Multiple Return Material Authorizations (RMAs) on an Integrated Circuit Device - An integrated circuit (IC) device configured for multiple return material authorizations (RMAs) is provided. The IC device includes an asset and a return material authorization (RMA) counter fuse including a first fuse, a second fuse, and a third fuse. The IC device enters an RMA state in response to blowing the first fuse, a second state in response to blowing the second fuse, and the RMA state in response to blowing the third fuse. | 2021-01-14 |
20210012856 | SELF-ADAPTIVE READ VOLTAGE ADJUSTMENT USING DIRECTIONAL ERROR STATISTICS FOR MEMORIES WITH TIME-VARYING ERROR RATES - A processing device in a memory system identifies a first range of a plurality of write-to-read delay ranges for the memory component, wherein the first range represents a plurality of write-to-read delay times and has an associated read voltage level used to perform a read operation on a segment of the memory component having a write-to-read delay time that falls within the first range. The processing device further identifies a first set of the plurality of write-to-read delay times at a first end of the first range and determines a first directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times. The processing device determines whether a correspondence between the first directional error rate and the second directional error rate satisfies a first threshold criterion and, responsive to the correspondence between the first directional error rate and the second directional error rate not satisfying the first threshold criterion, modifies the read voltage level associated with the first range. | 2021-01-14 |
20210012857 | SELF-ADAPTIVE READ VOLTAGE ADJUSTMENT USING BOUNDARY ERROR STATISTICS FOR MEMORIES WITH TIME-VARYING ERROR RATES - A processing device in a memory system identifies a first range of a plurality of write-to-read delay ranges for the memory component, wherein the first range represents a plurality of write-to-read delay times and has an associated read voltage level used to perform a read operation on a segment of the memory component having a write-to-read delay time that falls within the first range. The processing device further identifies a first set of the plurality of write-to-read delay times at a first end of the first range and a second set of the plurality of write-to-read delay times at a second end of the first range, and determines a first error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second error rate for the memory component corresponding to the second set of the plurality of write-to-read delay times. The processing device determines whether a correspondence between the first error rate and the second error rate satisfies a first threshold criterion, and, responsive to the correspondence between the first error rate and the second error rate not satisfying the first threshold criterion, modifies the read voltage level associated with the first range. | 2021-01-14 |
20210012858 | EFFECTIVE CLUSTERING OF IMMUNOLOGICAL ENTITIES - The present invention provides a method for classifying immunological entities. The inventors assume that there are commonalities among antigen specificities for which, without a function being specified in advance, bound immunological entities (antigens, epitopes, etc.) are normally handled individually as separate “functions (for example, whether antigen A has the specificity),” and the inventors have discovered that it is possible to classify immunological entities by evaluating the similarities thereof. This method has a high degree of precision with respect to immunity-related illnesses, and the present invention is clinically applicable. | 2021-01-14 |
20210012859 | Method For Determining Genotypes in Regions of High Homology - Described herein are methods directed to determining the carrier status or genotype of a subject. Described herein is a method that combines experimental and computational approaches to resolve the structure of genomic loci (i.e., the genotype) whose sequences are highly homologous to other sequences in the genome. In particular, the determination of carrier status and/or copy number of a gene in a subject, wherein the gene has a corresponding highly homologous homolog, e.g., gene or pseudogene, utilizes Next Generation Sequencing. Also described herein is a computer-assisted method for such determinations. | 2021-01-14 |
20210012860 | SIGNAL ENCODING AND DECODING IN MULTIPLEXED BIOCHEMICAL ASSAYS - This disclosure provides methods, systems, compositions, and kits for the multiplexed detection of a plurality of analytes in a sample. In some examples, this disclosure provides methods, systems, compositions, and kits wherein multiple analytes may be detected in a single sample volume by acquiring a cumulative measurement or measurements of at least one quantifiable component of a signal. In some cases, additional components of a signal, or additional signals (or components thereof) are also quantified. Each signal or component of a signal may be used to construct a coding scheme which can then be used to determine the presence or absence of any analyte. | 2021-01-14 |
20210012861 | METHODS AND SYSTEMS FOR DETERMINING DRUG RESISTANCE USING A PRECEDENCE GRAPH - A computer-implemented method is disclosed which includes receiving biological sample information from one or more subjects at a first time period. The method further includes receiving biological sample information from the one or more subjects at a second time period. The method further includes comparing the biological sample information at the second time period with the biological sample information at the first time period. The method further includes generating a precedence graph based on results of the comparison. The method further includes determining one or more actions based on the precedence graph. | 2021-01-14 |
20210012862 | SHORTLIST SELECTION MODEL FOR ACTIVE LEARNING - Method(s) and apparatus are provided for generating a selection model based on a machine learning (ML) technique, the selection model for selecting a shortlist of compounds requiring validation with a particular property. An iterative procedure or feedback loop for generating the selection model may include: receiving a prediction result list output from a property model for predicting whether a plurality of compounds are associated with a particular property and an property model score; retraining the selection model based on the property model score and/or the prediction result list; selecting a shortlist of compounds using the retrained selection model from the plurality of compounds associated with the prediction result list; sending the selected shortlist of compounds for validation with the particular property, where another ML technique is used to update the property model based on the validation; repeating the receiving and retraining of the selection model until determining the selection model has been validly trained. | 2021-01-14 |
20210012863 | ARTIFICIAL INTELLIGENCE BASED TEMPERATURE MEASUREMENT IN MIXED FLUID CHAMBER - Temperature measurement is an important part of many potential applications in process industry. Conventional temperature measurement methods require manual intervention for process monitoring and fail to provide accurate and precise measurement of temperature of an enclosed mixed fluid chamber. The present disclosure provides artificial intelligence based temperature measurement in mixed fluid chamber. A plurality of inputs pertaining to the mixed fluid chamber are received to build a fluid based model. The fluid based model is used to generate one or more fluid parameters. The one or more fluid parameters are used along with a ground truth temperature data and the received plurality of inputs for training an artificial intelligence (AI) based model. However, the AI based model is trained with and without knowledge of fluid flow. The trained AI based model is further used to accurately estimate temperature of the mixed fluid chamber for a plurality of test input data. | 2021-01-14 |
20210012864 | PREDICTING PARTICIPANT DROP-OUT AND COMPLIANCE SCORES FOR CLINICAL TRIALS - An apparatus obtains participant sentiment data including at least one of: a text conversation between a participant and an investigator in a clinical trial; a video conversation between the participant and the investigator; and the participant's social network information; extracts and normalizes a sentiment score from the participant sentiment data; generates a compliance score for the participant by using a trained regressor on at least the sentiment score; compares the compliance score to a lower threshold and to a higher threshold; selects an action from a decision tree in response to the compliance score; and facilitates the action. | 2021-01-14 |
20210012865 | METHODS AND SYSTEMS FOR BIOMARKER ANALYSIS - Method and systems are described comprising receiving a plurality of human subject biomarker concentration values associated with a human subject, wherein the plurality of human subject biomarkers is associated with a condition, determining, based on the plurality of human subject biomarker concentration values, a human subject test statistic, comparing the human subject test statistic to a test statistic threshold, wherein the test statistic threshold is derived based on non-human primate (NHP) subject data, and, determining, based on the human subject test statistic exceeding the test statistic threshold, that the human subject has the condition. | 2021-01-14 |
20210012866 | Client Management Tool System and Method - A client management tool system comprises a gateway module configured to provide access to a data store storing clinical and non-clinical data, a collection of computerized question forms configured to obtain additional data about a client, a predictive model including a plurality of weighted variables and thresholds in consideration of the client data to identify needs of the client and a valuation of services to address the client needs, a knowledgebase of available programs and service providers able to deliver the needed services, a client management toolkit configured to provide recommended a course of action in response to the identified client need, valuation, and available programs and services providers, and a data presentation module operable to present notifications, alerts, and outcome report related to service delivery to the client. | 2021-01-14 |
20210012867 | Collaborative Synthesis-Based Clinical Documentation - A graphical user interface, referred to herein as a virtual whiteboard, that provides both: (1) an automatically prioritized display of information related to a particular patient that is tailored to the current user of the system, and (2) a “scratch pad” area in which multiple users of the system may input free-form text and other data for sharing with other users of the system. When each user of the system accesses the virtual whiteboard, the system: (1) automatically prioritizes the patient information based on characteristics of the user and displays the automatically prioritized patient information to that user, and (2) displays the contents of the scratch pad to the user. As a result, the whiteboard displays both information that is tailored to the current user and information that is common to all users (i.e., not tailored to any particular user). | 2021-01-14 |
20210012868 | INTRAOPERATIVE SURGICAL EVENT SUMMARY - Systems and methods for generating decision support data for surgical videos are disclosed, the system may include at least on processor configured to implement a method. The method may include receiving video footage of a surgical procedure performed by a surgeon on a patient in an operating room and implementing a model on the received video footage to determine an existence of a surgical decision-making junction. The model may be trained to detect decision-making junctions using training data based on historical video footage depicting surgical situations. The method may include accessing, in a data structure, a correlation between an outcome and a specific action taken at the decision-making junction, and, based on the existence of the decision-making junction and the correlation, outputting a recommendation to at least one of a user device or a user interface related to the specific action. | 2021-01-14 |
20210012869 | Systems and Methods for Real-Time Health Certification Using Point-of-Care Data - A health pass system for COVID-19 is provided. The system includes a database including information on a plurality of individuals. The database is configured to receive point-of-care data relating to the plurality of individuals, the point-of-care data including at least one medical test result for COVID-19 antibodies for at least one of the plurality of individuals. The system includes a processing device configured to analyze the point-of-care data and generate a report. The system includes means for transmitting the report to a mobile electronic device of at least one of the plurality of individuals. The system includes means for displaying the report with a user interface of the mobile electronic device in the form of a real-time health certification. | 2021-01-14 |
20210012870 | MEDICAL DOCUMENT DISPLAY CONTROL APPARATUS, MEDICAL DOCUMENT DISPLAY CONTROL METHOD, AND MEDICAL DOCUMENT DISPLAY CONTROL PROGRAM - The medical document display control apparatus includes a reception unit that receives observation information on a subject, an acquisition unit that acquires relation information on an analysis result obtained by immediately analyzing the observation information received by the reception unit, and a display control unit that immediately displays the relation information acquired by the acquisition unit on a display unit. | 2021-01-14 |
20210012871 | SYSTEMS AND METHODS FOR DETERMINING COMPLIANCE AND EFFICACY OF A DOSING REGIMEN FOR A PHARMACEUTICAL AGENT - Embodiments of the present invention relate generally to determining compliance and/or efficacy of a dosing regimen of a pharmaceutical or other monitored agent to a subject. In certain embodiments, the present disclosure provides devices and methods for biometric data acquisition and monitoring before, during, or after administration of a pharmaceutical or other monitored agent to a user. Other embodiments of the present invention improve patient outcomes by giving patients more control over the delivery of their medication and by providing physicians with meaningful and accurate biometric and diagnostic data during treatment. | 2021-01-14 |
20210012872 | SYSTEM AND METHOD FOR PERSONALIZED DOSING OF PHARMACOLOGIC AGENTS - A system and method for personalized dosing of a pharmacologic agent include: executing, using a processing device, a plurality of dosing regimen program modules to determine a respective plurality of dose sets in response to receiving, from an input device, a target response value for a patient; and executing, using the processing device, a dosing selection algorithm module, following executing the plurality of dosing regimen program modules and in response to receiving from the input device a response profile and a monitoring frequency of the patient, to determine a recommended dose set computed as a combination of the plurality of dose sets weighted by degrees of matching computed using fuzzy sets and the response profile. | 2021-01-14 |
20210012873 | Applied Artificial Intelligence Technology for Hormone Therapy Treatment - Disclosed herein are a number of techniques that systematically integrate a person's biochemical, symptomatic, and genetic status to generate recommended hormone therapy treatment prescriptions. | 2021-01-14 |
20210012874 | MEDICAL FLUID DELIVERY DEVICE PROGRAMMING - In some aspects, systems, devices, and techniques for programming a medical fluid delivery device are described. In one example, the disclosure relates to a system including a medical fluid delivery device configured to deliver a therapeutic agent to a patient, and a processor. The processor may be configured to receive a proposed therapy dosing program that defines a fluid therapy for delivery to a patient via a medical fluid delivery device for a first period of time, determine a total dosage over a second period of time, where the second period of time at least partially overlaps the first period of time, and compare the total dosage over the second period of time to a reference dosage. | 2021-01-14 |
20210012875 | DISPLAY FOR PUMP - This document discusses, among other things, an apparatus comprising a pump configured to deliver insulin, a processor, and a user interface including a bistable display. A display element of the bistable display is placed in one of two stable orientations upon application of a biasing voltage and stays in the stable orientation when the biasing voltage is removed. The processor includes a display module configured to display a non-blank reversion display screen on the bistable display when no input is received at the user interface after a specified time duration, and to recurrently change the reversion display screen until input is received at the user interface. | 2021-01-14 |
20210012876 | INSULIN PUMP WITH LOW GLUCOSE NOTIFICATION MESSAGE - Methods of insulin delivery and an insulin pump are disclosed. | 2021-01-14 |
20210012877 | USER INTERFACE FOR REMOTE JOINT WORKOUT SESSION - Example embodiments relate to a system, method, apparatus, and computer readable media configured to generate a multiple renditions of a user interface that is updated based upon athletic movements of two or more users remotely located from each other. The UI may be configured to simultaneously display energy expenditure values in real-time. In further embodiments, a joint energy expenditure values determined from multiple remote users may be simultaneously displayed. | 2021-01-14 |
20210012878 | SYSTEMS AND METHODS FOR RADIATION TREATMENT PLANNER TRAINING BASED ON KNOWLEDGE DATA AND TRAINEE INPUT OF PLANNING ACTIONS - Systems and methods for radiation treatment planner training based on knowledge data and trainee input of planning actions are disclosed. According to an aspect, a method includes receiving case data including anatomical and/or geometric characterization data of a target volume and one or more organs at risk. Further, the method includes presenting, via a user interface, the case data to a trainee. The method also includes receiving input indicating an action to apply to the case. The input indicating parameters for generating a treatment plan that applies radiation dose to the target volume and one or more parameters for constraining radiation to the one or more organs at risk. The method includes applying training models to the action and the case data to generate analysis data of at least one parameter of the action. The method includes presenting the analysis data of the at least one parameter of the action. | 2021-01-14 |
20210012879 | METHOD FOR DETERMINING FIBER INTAKE - The present invention relates to a method for controlling fiber intake in mammals, comprising the steps: a) providing at least one input data; b) based on said input data, generating at least one output data; wherein the input data is based on information selected from the group consisting of host DNA, host metabolism, host colonic microbial composition, gene activity, metabolic activity, host specific parameters, and any combinations thereof wherein the output data is selected from the group consisting of information on fiber consumption, fiber supplementation and, any combinations thereof. The present invention further relates to a system and use of said method. | 2021-01-14 |
20210012880 | FOOD PRODUCT INFORMATION PROVIDING SYSTEM, DEVICE, METHOD, AND PROGRAM - Provided is a food product information providing system that creates indices for health risks based on genetic information such as the results of genetic testing, biological information such as the results of a medical checkup, and lifestyle information such as the results of a lifestyle questionnaire from a user, and then selects one or more functional materials according to each risk index and provides the user with a food product or recipe that includes the selected functional material(s) and matches the preference of the user. | 2021-01-14 |
20210012881 | SYSTEMS, METHODS AND APPARATUS FOR TREATMENT PROTOCOLS - System, method and apparatus for enabling caregivers to predict when people need supports, make better clinical decisions in the moment, provide more supports remotely and/or directly through technology independent of caregivers, and learn the optimal intervention for each individual in order to prevent crises and enhance outcomes. This may be done through capturing autonomic nervous system, biometric, environmental, and clinical data and applying machine learning to determine predictive modeling equations on a per-person basis with prompts for the person, activation of remote monitoring systems, modifications to the environment, or alerts to caregivers the moment that a predictive variable exceeds its individualized statistical control limit. | 2021-01-14 |
20210012882 | DATA-BASED MENTAL DISORDER RESEARCH AND TREATMENT SYSTEMS AND METHODS - A system for personalized depression disorder treatment is disclosed herein. The system includes a server configured to communicate with existing healthcare resources and to receive patient data corresponding to a patient, the server including an analytics module. The system further includes a first database configured to store empirical patient outcomes, and further configured to communicate with the analytics module. Additionally, the system includes a user device having a graphical user interface (GUI) configured to communicate with the server and to display at least one output generated by the analytics module. The analytics module is configured to determine at least one of a personalized depression treatment and a personalized depression state prediction based on the empirical patient outcomes and the patient data. | 2021-01-14 |