02nd week of 2010 patent applcation highlights part 14 |
Patent application number | Title | Published |
20100006858 | Semiconductor-on-diamond devices and associated methods - Semiconductor devices and methods for making such devices are provided. One such method may include forming an epitaxial layer of single crystal SiC on a single crystal Si growth substrate, forming an epitaxial diamond layer on the layer of SiC, forming a Si layer on the diamond layer, bonding a SiO | 2010-01-14 |
20100006859 | Method of Manufacturing Substrates Having Improved Carrier Lifetimes - This invention relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a chlorosilane gas, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000° C. but less than 2000° C.; with the proviso that the pressure within the reaction chamber is maintained in the range of 0.1 to 760 torr. This invention also relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a non-chlorinated silicon-containing gas, hydrogen chloride, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000° C. but less than 2000° C.; with the proviso that the pressure within the reaction chamber is maintained in the range of 0.1 to 760 torr. | 2010-01-14 |
20100006860 | METHOD FOR IMPROVING INVERSION LAYER MOBILITY IN A SILICON CARBIDE MOSFET - A method of manufacturing a semiconductor device based on a SiC substrate ( | 2010-01-14 |
20100006861 | Silicon carbide semiconductor device and manufacturing method of the same - A SiC semiconductor device includes: a substrate; a drift layer on a first side of the substrate; a trench in the drift layer; a base region contacting a sidewall of the trench; a source region in an upper portion of the base region; a gate electrode in the trench via a gate insulation film; a source electrode on the source region; and a drain electrode on a second side of the substrate. The source region has multi-layered structure including a first layer and a second layer. The first layer as an upper layer contacts the source electrode with ohmic contact. The second layer as a lower layer has an impurity concentration, which is lower than an impurity concentration of the first layer. | 2010-01-14 |
20100006862 | Substrate for fabricating light emitting device and light emitting device fabricated therefrom - The invention provides a substrate for fabricating a light emitting device and the light emitting device fabricated therefrom. The substrate includes at least one platform region having a first facet direction for epitaxial growth; and a plurality of continuous protruded portions surrounding the at least one platform region to isolate the at least one platform region from another platform region, wherein the first facet direction is substantially excluded from facet directions of the plurality of continuous protruded portions. Since facet directions of the plurality of continuous protruded portions substantially do not include the first facet direction, during formation of the light emitting device, epitaxial growth is mainly conducted on the at least one platform region, which may prevent epitaxial defects from generating and enhance external quantum efficiency of the light emitting device. | 2010-01-14 |
20100006863 | OPTICAL SEMICONDUCTOR DEVICE - A metal pattern for a high frequency signal is patterned on a flexile substrate, and the flexile substrate is bent in such a way as to form a substantially right angle at a spot corresponding to an end of the metal pattern for the signal. And an end of the metal pattern is fixedly attached to a lead pin for signaling, attached to a stem, for electrical continuity, so as to be in a posture horizontal with each other. Meanwhile, a part of the lead pins attached to the stem, being in such a state as penetrated through respective holes provided in the flexible substrate, is fixedly attached to a part of metal patterns provided on the flexible substrate so as to ensure electrical continuity therebetween. | 2010-01-14 |
20100006864 | IMPLANTED CONNECTORS IN LED SUBMOUNT FOR PEC ETCHING BIAS - A sapphire growth substrate wafer has epitaxially grown over it N-type layers, an active layer, and P-type layers to form GaN LEDs. Each LED is a flip-chip with its cathode contact and anode contact formed on the same side. The wafer is then diced to separate out the LEDs. A P-type silicon submount wafer has N-type doped interconnect regions for interconnecting all the cathode contacts together after the LEDs are mounted on the submount wafer. The sapphire substrate is then removed by a laser lift-off process. A bias voltage is then applied to the cathode contacts via the interconnect regions to bias the N-type layers for a photo-electrochemical etching process that roughens the exposed layer for increased light extraction. The submount wafer is then diced, cutting through the doped interconnect regions. | 2010-01-14 |
20100006865 | SEMICONDUCTOR MODULE FOR POWER GENERATION OR LIGHT EMISSION - In order to collect a plurality of semiconductor elements easily from a semiconductor module where a plurality of rod-like semiconductor elements for power generation or light emission are built in and to reuse or repair them, two split modules | 2010-01-14 |
20100006866 | LIGHT EMITTING DEVICE, DRIVING METHOD FOR THE SAME AND ELECTRONIC APPARATUS - It is a problem to provide a light-emitting device capable of obtaining a constant brightness without being affected by deterioration in an organic light-emitting layer or temperature change, and of making desired color display. The lowering in OLED brightness due to deterioration is reduced by causing the OLED to emit light while keeping constant the current flowing through the OLED instead of causing the OLED to emit light while keeping constant the OLED drive voltage. Namely, OLED brightness is controlled not by voltage but by current thereby preventing against the change in OLED brightness due to deterioration of OLED. Specifically, the drain current Id of a transistor for supplying a current to the OLED is controlled in a signal line drive circuit thereby keeping constant the drain current Id without relying upon the value of a load resistance. | 2010-01-14 |
20100006867 | LIGHT EMITTING DIODE HAVING LIGHT EMITTING CELL WITH DIFFERENT SIZE AND LIGHT EMITTING DEVICE THEREOF - There is provided a light emitting diode operating under AC power comprising a substrate; a buffer layer formed on the substrate; and a plurality of light emitting cells formed on the buffer layer to have different sizes and to be electrically isolated from one another, the plurality of light emitting cells being connected in series through metal wires. | 2010-01-14 |
20100006868 | AC LED device and method for fabricating the same - An AC LED device and method for fabricating the same are disclosed. An exemplary embodiment of the AC LED device includes at least two separate AC LED unit chips, wherein each of the AC LED unit chip includes a substrate having a first light emitting module and a second light emitting module. Each of the first and second light emitting modules includes a plurality of light emitting micro diodes connected between a first conductive electrode and a second conductive electrode, wherein the amount of light emitting micro diodes emitting light during a positive half cycle of an AC charge is equal to that during a negative half cycle of an AC charge. A plurality of conductive wires is respectively and electrically connected to the separate AC LED unit chips without passive devices. | 2010-01-14 |
20100006869 | SEMICONDUCTOR CHIP, WIRING SUBSTRATE OF A SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE HAVING THE SEMICONDUCTOR CHIP AND DISPLAY DEVICE HAVING THE SEMICONDUCTOR PACKAGE - A semiconductor chip can include a semiconductor substrate, an input portion and an output portion. A circuit element can be formed in the semiconductor substrate. The input portion can be formed on the semiconductor substrate. The input portion can include a first input pad to receive an input signal from the outside and a second input pad spaced apart from the first input pad, the second input pad being electrically connected to the first input pad through an external connection line such that the second input pad inputs the input signal to the circuit element. The output portion can be formed on the semiconductor substrate. The output pad can include an output pad to output an output signal from the circuit element. | 2010-01-14 |
20100006870 | LIGHT EMITTING DEVICE - The present invention relates to a light emitting device. According to the present invention, the light emitting device comprises a substrate, a plurality of light emitting cells disposed on the substrate, a first insulation layer disposed on each light emitting cell, an electrically conductive material disposed on the first insulation layer to couple two of the light emitting cells, and a second insulation layer disposed on the electrically conductive material. Each light emitting cell comprises a first semiconductor layer, a second semiconductor layer, and an inclined surface. The second insulation layer corresponds to a contour of each light emitting cell. | 2010-01-14 |
20100006871 | LIGHT EMITTING DEVICE AND METHOD FOR PRODUCING THE LIGHT EMITTING DEVICE - A light emitting device that has a radiant efficiency that does not decline in use, enables luminous flux to be increased by a high electric current, and produces white light with good color rendering and a method for producing a light emitting device capable of smoothly transmitting heat generated by LED elements to a carrier substrate. The radiation emitting device has first LED elements for emitting UV radiation, second LED elements for emitting visible light, a substrate made of an inorganic material and which carries the first LED elements and the second LED elements, a body made of inorganic material containing the first LED elements, the second LED elements and the substrate, and an SiC fluorescent screen that is doped with at least one of B and Al as well as N and emits visible light when excited by radiation emitted from the first LED elements. | 2010-01-14 |
20100006872 | LIGHT EMITTING DEVICE - Light-emitting elements have a problem that their light-extraction efficiency is low due to scattered light or reflected light inside the light-emitting elements. The light-extraction efficiency of the light-emitting elements needs to be enhanced by a new method. According to the present invention, a light-emitting element includes a first layer generating holes, a second layer including a light-emitting layer for each emission color and a third layer generating electrons between an anode and a cathode, and the thickness of the first layer is different depending on each layer including the light-emitting layer for each emission color. A layer in which an organic compound and a metal oxide are mixed is used as the first layer, and thus, the driving voltage is not increased even when the thickness is increased, which is preferable. | 2010-01-14 |
20100006873 | HIGHLY POLARIZED WHITE LIGHT SOURCE BY COMBINING BLUE LED ON SEMIPOLAR OR NONPOLAR GaN WITH YELLOW LED ON SEMIPOLAR OR NONPOLAR GaN - A packaged light emitting device. The device has a substrate member comprising a surface region. The device also has two or more light emitting diode devices overlying the surface region. Each of the light emitting diode device is fabricated on a semipolar or nonpolar GaN containing substrate. The two or more light emitting diode devices are fabricated on the semipolar or nonpolar GaN containing substrate emits substantially polarized emission. | 2010-01-14 |
20100006874 | PROCESS FOR PRODUCTION OF GALLIUM NITRIDE-BASED COMPOUND SEMICONDUCTOR LIGHT EMITTING DEVICE - In the process for production of a gallium nitride-based compound semiconductor light emitting device, when an n-type semiconductor layer, a light emitting layer obtained by alternately stacking an n-type dopant-containing barrier layer and a well layer, and a p-type semiconductor layer, composed of gallium nitride-based compound semiconductors, are grown in that order on a substrate, the ratio of the supply rates of n-type dopant and Group III element during growth of the barrier layer (M/III) is controlled to a range of 4.5×10 | 2010-01-14 |
20100006875 | WHITE LIGHT-EMITTING DIODE AND ITS LIGHT CONVERSION LAYER - The present invention discloses a white light-emitting diode based on In—Ga—N nitride heterojunction is characterized by that the light-emitting diode has primary blue light emission of a specific wavelength and a light conversion layer so as to generate white light. Further, the present invention also discloses a light conversion layer and its fluorine oxygen garnet phosphor powder. | 2010-01-14 |
20100006876 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE WITH SURFACE TEXTURE AND ITS MANUFACTURE - A nitride semiconductor light emitting device includes: a substrate for growing nitride semiconductor of a hexagonal crystal structure; a first nitride semiconductor layer of a first conductivity type formed above the substrate; an active layer formed on the first nitride semiconductor layer for emitting light when current flows; a second nitride semiconductor layer of a second conductivity type opposite to the first conductivity type formed on the active layer; texture formed above at least a partial area of the second nitride semiconductor layer and having a plurality of protrusions of a pyramid shape, each of the protrusions including a lower layer made of nitride semiconductor doped with impurities of the second conductivity type and an upper layer made of nitride semiconductor not intentionally doped with impurities; and a transparent electrode covering surfaces of the second nitride semiconductor layer and the texture. | 2010-01-14 |
20100006877 | LIGHT-EMITTING DIODE PACKAGE - An LED package including a carrier, a LED chip, and a lens is provided. The LED chip is disposed on the carrier. The lens is disposed on the carrier and above the LED chip. A gap is formed between the LED chip and the lens. The lens has a first surface, a second surface, a protrusion, and at least one protruding ring. The first surface faces the LED chip. The second surface is opposite to the first surface. The protrusion is located at the first surface. The protruding ring is located at the first surface and surrounds the protrusion. | 2010-01-14 |
20100006878 | SEMICONDUCTOR LIGHT EMITTING DEVICE HAVING PATTERNED SUBSTRATE AND MANUFACTURING METHOD OF THE SAME - There is provided a semiconductor light emitting device having a patterned substrate and a manufacturing method of the same. The semiconductor light emitting device includes a substrate; a first conductivity type nitride semiconductor layer, an active layer and a second conductivity type nitride semiconductor layer sequentially formed on the substrate, wherein the substrate is provided on a surface thereof with a pattern having a plurality of convex portions, wherein out of the plurality of convex portions of the pattern, a distance between a first convex portion and an adjacent one of the convex portions is different from a distance between a second convex portion and an adjacent one of the convex portions. | 2010-01-14 |
20100006879 | Radiation Emitting Device - A radiation emitting device includes a radiation emitting functional layer that emits a primary radiation, and a radiation conversion material that is arranged in the radiation path of the radiation emitting functional layer and converts the primary radiation at least partially into a radiation of greater wavelength. | 2010-01-14 |
20100006880 | Led chip package structure using sedimentation and method for making the same - An LED chip package structure using sedimentation includes a package body, at least two conductive substrates, at least one light-emitting element, and a package unit. The package body has a receiving space. The two conductive substrates are received in the receiving space. The light-emitting element is received in the receiving space and electrically connected to the two conductive substrates. The package unit has a package colloid layer and a powder mixed into the package colloid layer, and the package unit is filled into the receiving space. The powder is uniformly deposited in the receiving space by maintaining the package unit at room temperature firstly and the powder is solidified in the receiving space by heating to a predetermined temperature. | 2010-01-14 |
20100006881 | LIGHT EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - There is provided a light emitting device, which comprises compound semiconductor layers including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer; a metal reflection layer formed on a region of the second conductive semiconductor layer; an insulating structure formed at least in a boundary region of the second conductive semiconductor layer; a metal material structure formed to cover the second conductive semiconductor layer having the metal reflection layer and the insulating structure formed; and a substrate bonded to the metal material structure, wherein the boundary region of the second conductive semiconductor layer includes an outer region of the second conductive semiconductor layer along an outer circumference of the second conductive semiconductor layer. | 2010-01-14 |
20100006882 | LIGHTING DEVICE - An object of the invention is to provide a lighting device which can suppress luminance nonuniformity in a light emitting region when the lighting device has large area. A layer including a light emitting material is formed between a first electrode and a second electrode, and a third electrode is formed to connect to the first electrode through an opening formed in the second electrode and the layer including a light emitting material. An effect of voltage drop due to relatively high resistivity of the first electrode can be reduced by electrically connecting the third electrode to the first electrode through the opening. | 2010-01-14 |
20100006883 | LIGHT EMITTING DIODES INCLUDING BARRIER LAYERS/SUBLAYERS AND MANUFACTURING METHODS THEREFOR - Semiconductor light emitting devices, such as light emitting diodes, include a substrate, an epitaxial region on the substrate that includes a light emitting region such as a light emitting diode region, and a multilayer conductive stack including a reflector layer, on the epitaxial region. A barrier layer is provided on the reflector layer and extending on a sidewall of the reflector layer. The multilayer conductive stack can also include an ohmic layer between the reflector and the epitaxial region. The barrier layer further extends on a sidewall of the ohmic layer. The barrier layer can also extend onto the epitaxial region outside the multilayer conductive stack. The barrier layer can be fabricated as a series of alternating first and second sublayers. | 2010-01-14 |
20100006884 | Light Emitting Device and Manufacturing Method Therof - The application relates to a structure of a light emitting device and the manufacturing method thereof. The application discloses a method of forming a bonding pad of the light emitting device by chemical deposition method. The light emitting device includes a substrate, a semiconductor stack deposited on the substrate wherein the semiconductor stack includes at least a p-type semiconductor layer, an n-type semiconductor layer, and an active layer disposed between the p-type semiconductor layer and the n-type semiconductor layer. A bonding pad is formed on at least one of the p-type semiconductor layer and the n-type semiconductor layer wherein the bonding pad includes a seed layer formed by physical deposition method, and a chemically-deposited layer formed by chemical deposition method. The thickness of the seed layer is smaller than that of the chemically-deposited layer. | 2010-01-14 |
20100006885 | ARRANGEMENT OF ELECTRODES FOR LIGHT EMITTING DEVICE - A light emitting diode includes an n-GaN layer on a substrate, an active layer exposing a part of the n-GaN layer, a p-GaN layer on the active layer, a cathode contacting the exposed n-GaN layer and extending from one side of the active layer toward the other side, and an anode formed on the p-GaN layer and including a plurality of sub-electrodes spaced apart from both sides of the cathode and an edge of the active layer at the same distance. | 2010-01-14 |
20100006886 | HIGH POWER LIGHT EMITTING DIODE CHIP PACKAGE CARRIER STRUCTURE - A high power LED (light-emitting diode) chip package carrier structure is disclosed and comprises a circuit board, a metal plate and a lid. The circuit board has a perforate groove for positioning a chip, and an electrode contact area formed at two sides or border of the perforate groove. The metal plate is positioned beneath the circuit board. The lid is positioned above the circuit board, and has a through groove with a width larger than the width of the perforate groove of the circuit board such that the electrode contact area can be exposed out in the through groove of the lid. Thus, the manufacturing process can be simplified and helpful to the mass production. | 2010-01-14 |
20100006887 | RESIN COMPOSITION FOR SEALING LIGHT-EMITTING DEVICE AND LAMP - A resin composition for sealing a light-emitting device of the present invention includes a silsesquioxane resin including two or more oxetanyl groups, an aliphatic hydrocarbon including one or more epoxy groups and a cationic polymerization initiator. Furthermore, a lamp of the present invention includes a package equipped with a cup-shaped sealing member, an electrode exposed in the bottom portion of the sealing member, and a light-emitting device arranged on the bottom portion and electrically connected with the electrode, wherein the light-emitting device is sealed with the above-described resin composition for sealing a light-emitting device filled in the sealing member. | 2010-01-14 |
20100006888 | METHOD OF MANUFACTURING OPTICAL SEMICONDUCTOR DEVICE, OPTICAL SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING OPTICAL SEMICONDUCTOR APPARATUS - Provided is a method of manufacturing an optical semiconductor device, the method including: providing a resin layer on a light-emitting substrate to cover a principle surface of the light-emitting substrate, the light-emitting substrate including a pair of electrodes in each section of the principle surface, the resin layer including multiple holes each exposing two of the electrodes located adjacent to each other but in the different sections; providing post electrodes respectively on all the paired electrodes formed in all the sections by filling a conductive material in the holes of the resin layer on the principal surface; and forming multiple optical semiconductor devices by cutting the light-emitting substrate into sections, the light-emitting substrate provided with the post electrodes respectively on all the paired electrodes formed in all the sections. | 2010-01-14 |
20100006889 | LOW CLAMP VOLTAGE ESD DEVICE AND METHOD THEREFOR - In one embodiment, an ESD device is configured to include a zener diode and a P-N diode and to have a conductor that provides a current path between the zener diode and the P-N diode. | 2010-01-14 |
20100006890 | ESD Protection Device with Increased Holding Voltage During Normal Operation - An ESD protection circuit including an SCR having at least one PNP transistor and at least one NPN transistor such that at least one of the PNP transistor and the NPN transistor having an additional second collector. The circuit further including at least one control circuit coupled to the at least one second collector to control holding voltage of the SCR. | 2010-01-14 |
20100006891 | SEMICONDUCTOR THYRISTOR DEVICE - A semiconductor thyristor device includes a semiconductor substrate, two transistors each of which is different junction type from the other and which are provided adjacent to each other in the semiconductor substrate to constitute one thyristor element, a first wiring layer that is formed on the semiconductor substrate and provides a ground potential to one of the transistors, and a second wiring layer that is formed on the semiconductor substrate and provides a power source potential to the other of the transistors. The first wiring layer covers a region in the semiconductor substrate in which the two transistors adjoin each other. This avoids a leakage current that might be generated due to any potential of a wiring layer for another circuit in a chip layout. | 2010-01-14 |
20100006892 | NEAR-FIELD TERAHERTZ WAVE DETECTOR - A near-field terahertz wave detector comprises a semiconductor chip ( | 2010-01-14 |
20100006893 | STRAINED LAYERS WITHIN SEMICONDUCTOR BUFFER STRUCTURES - A semiconductor workpiece including a substrate, a relaxed buffer layer including a graded portion formed on the substrate, and at least one strained transitional layer within the graded portion of the relaxed buffer layer and method of manufacturing the same. The at least one strained transitional layer reduces an amount of workpiece bow due to differential coefficient of thermal expansion (CTE) contraction of the relaxed buffer layer relative to CTE contraction of the substrate | 2010-01-14 |
20100006894 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The semiconductor device includes a P-type group III-V nitride semiconductor layer, an N-type group III-V nitride semiconductor layer, and an electrode in contact with both of the P-type group III-V nitride semiconductor layer and the N-type group III-V nitride semiconductor layer. The electrode includes a first electrode portion made of a first conductive material, and a second electrode portion, made of a second conductive material different from the first conductive material, bonded to the first electrode portion. The first electrode portion is in contact with the P-type group III-V nitride semiconductor layer, and the second electrode portion is in contact with the N-type group III-V nitride semiconductor layer. | 2010-01-14 |
20100006895 | III-NITRIDE SEMICONDUCTOR DEVICE - A III-nitride power switch that includes a III-nitride heterojunction, field dielectric bodies disposed over the heterojunction, and a gate electrode that does not overlap the top surface of the field dielectric bodies and is disposed over a well in the III-nitride heterojunction. | 2010-01-14 |
20100006896 | Semiconductor integrated circuit - A semiconductor integrated circuit has: a substrate; a basic logic cell placed on the substrate and configured to function as a part of a logic circuit; and a dummy cell placed on the substrate and not configured to function as a part of a logic circuit. The basic logic cell includes a diffusion layer formed in the substrate, and a distance from the diffusion layer to a boundary between the basic logic cell and another cell adjacent to the basic logic cell is equal to a first distance. The dummy cell includes a dummy diffusion layer that is a diffusion layer formed in the substrate, and a distance from the dummy diffusion layer to a boundary between the dummy cell and another cell adjacent to the dummy cell is equal to the first distance. | 2010-01-14 |
20100006897 | Semiconductor Device Layout Having Restricted Layout Region Including Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors - A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. The restricted layout region includes a gate electrode level layout defined to pattern conductive features within a gate electrode level above the portion of the substrate. The gate electrode level layout includes rectangular-shaped layout features placed to extend in only a first parallel direction. Some of the rectangular-shaped layout features form gate electrodes of respective PMOS transistor devices, and some of the rectangular-shaped layout features form gate electrodes of respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the restricted layout region of the semiconductor device. | 2010-01-14 |
20100006898 | Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors - A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. The restricted layout region includes a gate electrode level layout defined to include rectangular-shaped layout features placed to extend in only a first parallel direction. Some of the rectangular-shaped layout features form gate electrodes of respective PMOS transistor devices, and some of the rectangular-shaped layout features form gate electrodes of respective NMOS transistor devices. A total number of the PMOS transistor devices and the NMOS transistor devices in the restricted layout region of the semiconductor device is greater than or equal to eight. Additionally, the restricted layout region corresponds to an entire gate electrode level of a cell layout. | 2010-01-14 |
20100006899 | Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having Equal Number of PMOS and NMOS Transistors - A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features within the gate electrode level region extend over the p-type diffusion regions to form respective PMOS transistor devices. Also, some of the conductive features within the gate electrode level region extend over the n-type diffusion regions to form respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region. | 2010-01-14 |
20100006900 | Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having Equal Number of PMOS and NMOS Transistors - A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Each of the conductive features within the gate electrode level region has a width less than a wavelength of light used in a photolithography process to fabricate the conductive features. Conductive features within the gate electrode level region form respective PMOS transistor devices and respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region. | 2010-01-14 |
20100006901 | Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks and Having Corresponding Non-Symmetric Diffusion Regions - A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. The plurality of diffusion regions are separated from each other by one or more non-active regions of the substrate portion. The plurality of diffusion regions are defined in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. The semiconductor device includes a gate electrode level region formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the number of conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. The number of conductive features within the gate electrode level region includes conductive features defined along at least four different virtual lines of extent in the first parallel direction across the gate electrode level region. | 2010-01-14 |
20100006902 | Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks and Having Corresponding Non-Symmetric Diffusion Regions - A substrate portion of a semiconductor device is formed to include a plurality of diffusion regions that are defined in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the number of conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. The conductive features within the gate electrode level region are defined along at least four different virtual lines of extent in the first parallel direction. A width size of the conductive features within the gate electrode level region is measured perpendicular to the first parallel direction and is less than a wavelength of light used in a photolithography process to fabricate the conductive features. | 2010-01-14 |
20100006903 | Semiconductor Device Portion Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks and Having Corresponding Non-Symmetric Diffusion Regions - A semiconductor device includes a substrate portion having a plurality of diffusion regions defined in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction and fabricated from a respective originating rectangular-shaped layout feature. The gate electrode level region includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width size of the conductive features within the gate electrode level region is measured perpendicular to the first parallel direction. Within a five wavelength photolithographic interaction radius within the gate electrode level region, the width size of the conductive features is less than 193 nanometers, which is the wavelength of light used in a photolithography process to fabricate the conductive features. | 2010-01-14 |
20100006904 | Apparatus and Method for Input/Output Module That Optimizes Frequency Performance in a Circuit - A circuit can include a module having signal pads that are configurable to route signals between the circuit and at least one external device. The module can also have unused pads that are interleaved between the signal pads. A circuit can include a module having signal pads that are configurable to route varying signals between the circuit and at least one external device. The module can also have voltage pads that are configurable to route substantially constant voltages between at least one external device and the circuit. The signal pads can be interleaved between the voltage pads. A module with one or more of these features can achieve ideal performance in both wire bond and flip chip packages with the flexibility of setting a different input/output utilization percentage within the module. | 2010-01-14 |
20100006905 | SEMICONDUCTOR MEMORY DEVICE - To facilitate counting of memory cells in failure analysis, without limiting the arrangement of memory cells or increasing the number of processes. A memory cell array region | 2010-01-14 |
20100006906 | Semiconductor device, single crystalline silicon wafer, and single crystalline silicon ingot - A semiconductor device includes a single crystalline substrate and an active region defined in the single crystalline substrate, wherein a major axis direction of the active region is aligned with a <0,1,1> family direction. | 2010-01-14 |
20100006907 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a FET using a SiGe film as a channel region, dispersion of the Ge concentration in the SiGe film and dispersion of the film thickness of the SiGe film are suppressed. | 2010-01-14 |
20100006908 | BACKSIDE ILLUMINATED IMAGE SENSOR WITH SHALLOW BACKSIDE TRENCH FOR PHOTODIODE ISOLATION - A backside illuminated image sensor comprises a sensor layer implementing a plurality of photosensitive elements of a pixel array, an oxide layer adjacent a backside surface of the sensor layer, and at least one dielectric layer adjacent a frontside surface of the sensor layer. The sensor layer further comprises a plurality of backside trenches formed in the backside surface of the sensor layer and arranged to provide isolation between respective pairs of the photosensitive elements. The backside trenches have corresponding backside field isolation implant regions formed in the sensor layer, and the resulting structure provides reductions in carrier recombination and crosstalk between adjacent photosensitive elements. The image sensor may be implemented in a digital camera or other type of digital imaging device. | 2010-01-14 |
20100006909 | COLOR FILTER ARRAY ALIGNMENT MARK FORMATION IN BACKSIDE ILLUMINATED IMAGE SENSORS - A backside illuminated image sensor includes a sensor layer comprising photosensitive elements of the pixel array, an epitaxial layer formed on a frontside surface of the sensor layer, and a color filter array formed on a backside surface of the sensor layer. The epitaxial layer comprises polysilicon color filter array alignment marks formed in locations corresponding to respective color filter array alignment mark openings in the frontside surface of the sensor layer. The color filter array is aligned to the color filter array alignment marks of the epitaxial layer. The image sensor may be implemented in a digital camera or other type of digital imaging device. | 2010-01-14 |
20100006910 | IMAGE SENSOR - An image sensor includes a photoelectric conversion portion generating signal charges, a voltage conversion portion for converting the signal charges to a voltage, a charge increasing portion for increasing the number of the signal charges stored in the photoelectric conversion portion, a first light shielding film formed to cover at least one part of the charge increasing portion and a second light shielding film provided separately from the first light shielding film and formed to cover the voltage conversion portion. | 2010-01-14 |
20100006911 | CMOS Image Sensor and Manufacturing Method Thereof - Disclosed are a CMOS image sensor and a manufacturing method thereof. The method includes forming an isolation layer in a semiconductor substrate, defining an active region including a photo diode region and a transistor region; forming a gate insulating layer and a gate electrode on the transistor region; forming a first low-concentration diffusion region in the photo diode region; forming a second low-concentration diffusion region in the transistor region; forming an insulating layer over an entire surface of the substrate; implanting fluorine ions in an upper surface of the photo diode region; etching the insulating layer to form insulating sidewalls on sides of the gate electrode; forming a high-concentration diffusion region in the transistor region partially overlapping with the second low-concentration diffusion region; and forming a third low-concentration diffusion region on the upper surface of the photo diode region, the third low-concentration diffusion region having a conductivity type opposite to the first low-concentration diffusion region. | 2010-01-14 |
20100006912 | Planar Metal-Insulator-Metal Circuit Element and Method for Planar Integration of Same - A complementary metal-oxide-semiconductor (CMOS) static random-access-memory (SRAM) element comprising a planar metal-insulator-metal (MIM) capacitor is disclosed, and the planar MIM capacitor is electrically connected to the transistors in the CMOS memory element to reduce the effects of charged particle radiation on the CMOS memory element. Methods for immunizing a CMOS SRAM element to the effects of charged particle radiation are also disclosed, along with methods for manufacturing CMOS SRAM including planar MIM capacitors as integrated circuits. | 2010-01-14 |
20100006913 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate including a trench; a capacitor electrode formed in the trench; a first insulation film formed on a bottom of the trench and between the semiconductor substrate and the capacitor electrode; a second insulation film formed on a side wall of the trench and between the semiconductor substrate and the capacitor electrode; and a first metal oxide film formed at the bottom of the trench and between the capacitor electrode and the first insulation film. | 2010-01-14 |
20100006914 | Nonvolatile semiconductor memory device, and method for manufacturing nonvolatile semiconductor memory device - A nonvolatile semiconductor memory device includes a semiconductor substrate that includes a trench, a charge storage layer that is formed inside of the trench, a first gate that is formed above a side surface and a bottom surface of the trench, a second gate that is formed beside the first gate, and that is formed above the charge storage layer, a first diffusion region that is formed on the semiconductor substrate inside of the trench, and a second diffusion region that is formed on the semiconductor substrate outside of the trench. | 2010-01-14 |
20100006915 | DIELECTRIC LAYER ABOVE FLOATING GATE FOR REDUCING LEAKAGE CURRENT - A memory system is disclosed that includes a set of non-volatile storage elements. A given memory cell has a dielectric cap above the floating gate. In one embodiment, the dielectric cap resides between the floating gate and a conformal IPD layer. The dielectric cap reduces the leakage current between the floating gate and a control gate. The dielectric cap achieves this reduction by reducing the strength of the electric field at the top of the floating gate, which is where the electric field would be strongest without the dielectric cap for a floating gate having a narrow stem. | 2010-01-14 |
20100006916 | NON-VOLATILE MEMORY - Non-volatile memory is described. The non-volatile memory includes a substrate having a source region, a drain region and a channel region. The channel region separates the source region and the drain region. An electrically insulating layer is adjacent to the source region, drain region and channel region. A floating gate electrode is adjacent to the electrically insulating layer. The electrically insulating layer separates the floating gate electrode from the channel region. The floating gate electrode has a floating gate major surface. A control gate electrode has a control gate major surface and the control gate major surface opposes the floating gate major surface. A vacuum layer or gas layer at least partially separates the control gate major surface from the floating gate major surface. | 2010-01-14 |
20100006917 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - This semiconductor device comprises a semiconductor substrate, a gate insulating film formed thereon, and a gate electrode formed through the gate insulating film on the semiconductor substrate. The first silicon nitride film is formed on the upper surface of the gate electrode, and a protection insulating film is formed on the side thereof. The second silicon nitride film is formed on the side of the protection insulating film. The third silicon nitride film is formed on the upper surface of the protection insulating film, and the bottom thereof is formed on a higher position than the bottom of the first silicon nitride film. | 2010-01-14 |
20100006918 | HAFNIUM TANTALUM TITANIUM OXIDE FILMS - Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of methods of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. An embodiment may include forming hafnium tantalum titanium oxide film using atomic layer deposition. | 2010-01-14 |
20100006919 | NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATION - A nonvolatile memory device is provided that includes; a first semiconductor layer extending in a first direction, a second semiconductor layer extending in parallel with and separated from the first semiconductor layer, an isolation layer between the first semiconductor layer and second semiconductor layer, a first control gate electrode between the first semiconductor layer and the isolation layer, a second control gate electrode between the second semiconductor layer and the isolation layer, wherein the second control gate electrode and first control gate electrode are respectively disposed at opposite sides of the isolation layer, a first charge storing layer between the first control gate electrode and the first semiconductor layer, and a second charge storing layer between the second control gate electrode and the second semiconductor layer. | 2010-01-14 |
20100006920 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device according to an embodiment may include a plurality of memory cells arranged on a semiconductor substrate includes a tunneling dielectric film on the semiconductor substrate; a floating gate formed on the tunneling dielectric film and corresponding to each of the memory cells; an inter-gate dielectric film on the floating gate; and a control gate on the inter-gate dielectric film, wherein the floating gate corresponding to a single memory cell has a first gate part, a second gate part, and the floating gate has a part that the tunneling dielectric film contacts the inter-gate dielectric film is provided between the first gate part and the second gate part within the memory cell. | 2010-01-14 |
20100006921 | SEMICONDUCTOR MEMORY, SEMICONDUCTOR MEMORY SYSTEM USING THE SAME, AND METHOD FOR PRODUCING QUANTUM DOTS APPLIED TO SEMICONDUCTOR MEMORY - A semiconductor memory includes a composite floating structure where an insulation film is formed on a semiconductor substrate, Si-based quantum dots covered with an extremely thin Si oxide film is formed on the insulation film, silicide quantum dots covered with a high dielectric insulation film are formed on the extremely thin Si oxide film, and Si-based quantum dots covered with a high dielectric insulation film are formed on the high dielectric insulation film. Multivalued memory operations can be conducted at a high speed and with stability by applying a certain positive voltage to a gate electrode to accumulate electrons in the silicide quantum dots and by applying a certain negative voltage and weak light to the gate electrode to emit the electrons from the silicide quantum dots. | 2010-01-14 |
20100006922 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - The invention provides a nonvolatile semiconductor memory device comprising a plurality of memory strings each including a plurality of electrically programmable memory cells connected in series. The memory string includes a semiconductor pillar, an insulator formed around the circumference of the semiconductor pillar, and first through nth electrodes to be turned into gate electrodes (n denotes a natural number equal to 2 or more) formed around the circumference of the insulator. It also includes interlayer electrodes formed in regions between the first through nth electrodes around the circumference of the insulator. | 2010-01-14 |
20100006923 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a tunnel insulating film formed on a surface of a semiconductor region, a charge storage insulating film formed on a surface of the tunnel insulating film, a block insulating film formed on a surface of the charge storage insulating film, and a control gate electrode formed on a surface of the block insulating film, wherein the block insulating film includes a first insulating film containing a metal element and oxygen as main components, a second insulating film containing silicon and oxygen as main components, and an interface layer formed between the first insulating film and the second insulating film and containing the metal element, silicon, and oxygen as main components. | 2010-01-14 |
20100006924 | ONE-TIME PROGRAMMABLE READ-ONLY MEMORY - A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a third doped region, a first dielectric layer, a select gate, a second dielectric layer, a first channel, a second channel and a silicide layer is provided. The first doped region, the second doped region and the third doped region are disposed apart in a substrate. The first dielectric layer is disposed on the substrate between the first doped region and the second doped region. The select gate is disposed on the first dielectric layer. The second dielectric layer is disposed on the substrate between the second doped region and the third doped region. The silicide layer is disposed on the first doped region, the second doped region and the third doped region. The OTP-ROM stores data by a punch-through effect occurring between the second doped region and the third doped region. | 2010-01-14 |
20100006925 | NON-VOLATILE TWO TRANSISTOR MEMORY CELL AND METHOD FOR PRODUCING THE SAME - The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions ( | 2010-01-14 |
20100006926 | METHODS FOR FORMING HIGH PERFORMANCE GATES AND STRUCTURES THEREOF - Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different. | 2010-01-14 |
20100006927 | Charge Balance Techniques for Power Devices - A vertically-conducting charge balance semiconductor power device includes an active area comprising a plurality of cells capable of conducting current along a vertical dimension when biased in a conducting state, and a non-active perimeter region surrounding the active area. No current flows along the vertical dimension through the non-active perimeter region when the plurality of cells is biased in the conducting state. Strips of p pillars and strips of n pillars are arranged in an alternating manner. The strips of p pillars have a depth extending along the vertical dimension, a width, and a length. The strips of p and n pillars extend through both the active area and the non-active perimeter region along a length of a die that contains the semiconductor power device. The length of the die extends parallel to the length of the strips of p pillars. Each of the strips of p pillars includes a plurality of discontinuities forming portions of a plurality of strips of n regions. The plurality of strips of n regions extends in the non-active perimeter region perpendicular to the length of the die. | 2010-01-14 |
20100006928 | Structure and Method for Forming a Shielded Gate Trench FET with an Inter-electrode Dielectric Having a Low-k Dielectric Therein - A shielded gate trench field effect transistor (FET) comprises trenches extending into a semiconductor region. A shield electrode is disposed in a bottom portion of each trench. The shield electrode is insulated from the semiconductor region by a shield dielectric. A gate electrode is disposed in each trench over the shield electrode, and an inter-electrode dielectric (IED) comprising a low-k dielectric extends between the shield electrode and the gate electrode. | 2010-01-14 |
20100006929 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device contains a semiconductor substrate having a p-type semiconductor layer and an n-type channel layer formed thereon; gate trenches extended through the channel layer so as to reach the p-type semiconductor layer; oxide films formed over the bottom and inner wall of the gate trenches, the oxide films being formed thicker over the bottom of the gate trenches than over the inner wall; gate electrodes formed so as to fill the gate trenches; n-type regions formed at the bottom of the gate trenches, and containing arsenic as a major n-type impurity component; low concentration p-type regions formed under the n-type regions, and having a low p-type impurity concentration; and a drain electrode formed on the back surface of the substrate. | 2010-01-14 |
20100006930 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND DATA PROCESSING SYSTEM - A semiconductor device manufacturing method includes steps of: etching a semiconductor substrate | 2010-01-14 |
20100006931 | VERTICAL DRAIN EXTENDED MOSFET TRANSISTOR WITH VERTICAL TRENCH FIELD PLATE - A vertical drain extended metal-oxide semiconductor field effect (MOSFET) transistor or a vertical double diffused metal-oxide semiconductor (VDMOS) transistor includes: a buried layer having a first conductivity type in a semiconductor backgate having a second conductivity type; an epitaxial (EPI) layer having the first conductivity type and formed above the buried layer; a deep well having the first conductivity type in the EPI layer extending down to the buried layer; at least one shallow well having the second conductivity type in the EPI layer; a shallow implant region having the first conductivity type and formed in the shallow well; a gate electrode having a lateral component extending over an edge of the shallow well and stopping at some spacing from an edge of the shallow implant and having a vertical trench field plate extending vertically into the EPI layer. | 2010-01-14 |
20100006932 | Semiconductor device and method of manufacturing the same - A semiconductor device, including: a first transistor formed on a substrate and including an Hf contained film as its gate insulating film; and a second transistor formed on said substrate and having the same conductive type as that of said first transistor, said second transistor including a silicon oxide film and not including an Hf contained film as its gate insulating film is provided. | 2010-01-14 |
20100006933 | Stabilizing Breakdown Voltages by Forming Tunnels for Ultra-High Voltage Devices - A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW; and a tunnel of the first conductivity type in the pre-HVW and the HVW, and electrically connecting the field ring and the semiconductor substrate. | 2010-01-14 |
20100006934 | Gate Electrodes of HVMOS Devices Having Non-Uniform Doping Concentrations - A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion. | 2010-01-14 |
20100006935 | Breakdown Voltages of Ultra-High Voltage Devices By Forming Tunnels - A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW, wherein at least one of the pre-HVW, the HVW, and the field ring comprises at least two tunnels; an insulation region over the field ring and a portion of the HVW; a drain region in the HVW and adjacent the insulation region; a gate electrode over a portion the insulation region; and a source region on an opposite side of the gate electrode than the drain region. | 2010-01-14 |
20100006936 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer. | 2010-01-14 |
20100006937 | Lateral Double Diffused Metal Oxide Semiconductor (LDMOS) Device and Method of Manufacturing LDMOS Device - A method for manufacturing a lateral double diffused metal oxide semiconductor (LDMOS) device includes forming an oxide layer on a semiconductor substrate, forming first and second trenches by partially etching the oxide layer and the semiconductor substrate, forming a small trench overlapping with the second trench so that the second trench has a stepped structure, and depositing one or more dielectric layers so that the first trench forms a device isolation layer defining a semiconductor device region and the second trench having a stepped structure forms a drain extension device isolation layer. The breakdown voltage of the LDMOS device may be improved while reducing the on-resistance, thereby improving the operational reliability of the device. | 2010-01-14 |
20100006938 | High Integrated Semiconductor Memory Device - Disclosed herein is a semiconductor memory device including plural unit cells, each constituted with a floating body transistor without any capacitor, to prevent data distortion and data crash in the unit cell. A semiconductor memory device comprises plural active regions and a device isolation layer for separating each active region from each others, wherein the plural active regions stand in row and column lines. | 2010-01-14 |
20100006939 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises including a insulating pattern and a silicon film over a SOI substrate, thereby increasing a reduced volume of a floating body after forming a floating body fin transistor so as to secure a data storage space. The method comprises: forming a insulating pattern and a first silicon film over an upper silicon film of a SOI substrate; and forming a fin structure in the first silicon film. | 2010-01-14 |
20100006940 | SOI SUBSTRATE AND MANUFACTURING METHOD THEREOF - An object is to provide an SOI substrate provided with a semiconductor layer which can be used practically even when a glass substrate is used as a base substrate. Another object is to provide a semiconductor device having high reliability using such an SOI substrate. An altered layer is formed on at least one surface of a glass substrate used as a base substrate of an SOI substrate to form the SOI substrate. The altered layer is formed on at least the one surface of the glass substrate by cleaning the glass substrate with solution including hydrochloric acid, sulfuric acid or nitric acid. The altered layer has a higher proportion of silicon oxide in its composition and a lower density than the glass substrate. | 2010-01-14 |
20100006941 | Intergration of a floating body memory on soi with logic transistors on bulk substrate - A method and the resultant memory is described for forming an array of floating body memory cells and logic transistors on an SOI substrate. The floating bodies for the cells are formed over the buried oxide, the transistors in the logic section are formed in the bulk silicon. | 2010-01-14 |
20100006942 | Interconnection structure and electronic device employing the same - An interconnection structure and an electronic device employing the same are provided. The interconnection structure for an integrated structure includes first and second contact plugs disposed on a substrate, and a connection pattern interposed between sidewalls of the first and second contact plugs and configured to electrically connect the first and second contact plugs. | 2010-01-14 |
20100006943 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge (ESD) protection device for providing an ESD path between two circuitries is provided. Each circuitry has a power supply terminal and a ground terminal. The protection device comprises an equivalent MOS, a first terminal, and a second terminal. The equivalent MOS comprises a source, a drain and a gate, wherein the drain is connected to the gate. The first terminal is connected to the gate, while the second terminal is connected to the source. The first terminal is connected to one power supply terminal and ground terminal, whereas the second terminal is connected to the other the power supply terminal and ground terminal. | 2010-01-14 |
20100006944 | MIXED VOLTAGE TOLERANT INPUT/OUTPUT ELECTROSTATIC DISCHARGE DEVICES - An input/output (I/O) mixed-voltage drive circuit and electrostatic discharge protection device for coupling to an I/O pad. The device includes an NFET device having a gate, a drain, a source and body, the gate adapted for coupling to a pre-drive circuit, the source and the body being coupled to one another and to ground. The device also includes a bipolar junction transistor having a collector, an emitter and a base, the emitter being coupled to the drain of the NFET and the collector being coupled to the I/O pad. | 2010-01-14 |
20100006945 | FINFET DRIVE STRENGTH MODIFICATION - A method and circuit in which the drive strength of a FinFET transistor can be selectively modified, and in particular can be selectively reduced, by omitting the LDD extension formation in the source and/or in the drain of the FinFET. | 2010-01-14 |
20100006946 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device includes a plurality of first MOS transistors has a first gate electrode formed on a first gate insulating film provided in a first transistor region on a semiconductor substrate, a plurality of second MOS transistors has a second gate electrode formed on a second gate insulating film which is provided in a second transistor region on the semiconductor substrate and which is smaller in thickness than the first gate insulating film, a first element isolation region in the first transistor region, the first element isolation region provided between the plurality of first MOS transistors, and a second element isolation region in the second transistor region, the second element isolation region provided between the plurality of second MOS transistors. The upper surface of the second element isolation region is lower than the upper surface of the first element isolation region. | 2010-01-14 |
20100006947 | Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having At Least Eight Transistors - A semiconductor device includes a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Each of the conductive features within the gate electrode level region has a width less than a wavelength of light used in a photolithography process to fabricate the conductive features. Conductive features within the gate electrode level region form respective PMOS transistor devices and respective NMOS transistor devices. A total number of the PMOS transistor devices and the NMOS transistor devices in the gate electrode level region is greater than or equal to eight. | 2010-01-14 |
20100006948 | Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having At Least Eight Transistors - A semiconductor device includes a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Within a five wavelength photolithographic interaction radius within the gate electrode level region, a width size of the conductive features is less than 193 nanometers, which is the wavelength of light used in a photolithography process to fabricate the conductive features. A total number of the PMOS transistor devices and the NMOS transistor devices in the gate electrode level region is greater than or equal to eight. | 2010-01-14 |
20100006949 | SCHOTTKY BARRIER CMOS DEVICE AND METHOD - A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions to control short channel effects, well implant steps, and complex device isolation steps. Additionally, the present invention eliminates the parasitic bipolar gain associated with CMOS device operation, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art. The present invention, in one embodiment, uses a silicide exclusion mask process to form the dual silicide Schottky barrier source and/or drain contact for the complimentary PMOS and NMOS devices forming the CMOS device. | 2010-01-14 |
20100006950 | Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having At Least Eight Transistors - A semiconductor device includes a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features within the gate electrode level region extend over the p-type diffusion regions to form respective PMOS transistor devices. Also, some of the conductive features within the gate electrode level region extend over the n-type diffusion regions to form respective NMOS transistor devices. A total number of the PMOS transistor devices and the NMOS transistor devices in the gate electrode level region is greater than or equal to eight. | 2010-01-14 |
20100006951 | Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having Equal Number of PMOS and NMOS Transistors - A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Within a five wavelength photolithographic interaction radius within the gate electrode level region, a width size of the conductive features is less than 193 nanometers, which is the wavelength of light used in a photolithography process to fabricate the conductive features. The conductive features within the gate electrode level region form an equal number of PMOS and NMOS transistor devices. | 2010-01-14 |
20100006952 | FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING SAME - An FET and method of fabricating an FET. The method includes forming a gate dielectric layer on a top surface of a silicon region of a substrate and forming a gate electrode on a top surface of the gate dielectric layer; forming a source and a drain in the silicon region of and separated by a channel region under the gate electrode, the source having a source extension extending under the gate electrode and the drain having a drain extension extending under the gate electrode, the source, source extension, drain and drain extension doped a first type; and forming a source delta region contained entirely within the source and forming a drain delta region contained entirely within the drain, the delta source region and the delta drain region doped a second dopant type, the second dopant type opposite from the first dopant type. | 2010-01-14 |
20100006953 | INTEGRATED CIRCUIT INCLUDING A DIELECTRIC LAYER - An integrated circuit including a dielectric layer and a method for manufacturing. One embodiment provides a substrate having a first side and a second side and at least one dielectric layer. The dielectric layer includes a zirconium oxide and at least one dopant selected from the group consisting of hafnium and titanium and having a first side and a second side. The first side of the dielectric layer is arranged at least on a subarea of the first side of the semiconductor substrate. | 2010-01-14 |
20100006954 | TRANSISTOR DEVICE - A transistor device includes a semiconductor substrate, a source doping region and a drain doping region in the semiconductor, a channel region between the source doping region and the drain doping region, a gate stack on the channel region, wherein the gate stack includes an amorphous interfacial layer, a crystalline metal oxide gate dielectric layer and a gate conductor. | 2010-01-14 |
20100006955 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method includes the steps of: successively forming, on a semiconductor substrate, a gate insulating film and first and second dummy sections stacked in this order; forming a notch section by processing the gate insulating film and the first and second dummy gate sections into a previously set pattern and making the first dummy gate section move back in the gate length direction relative to the second dummy gate section; forming a side wall of an insulating material in a side part of each of the gate insulating film and the first and second dummy gate sections and embedding the notch section therewith; removing the first and second dummy gate sections to leave the gate insulating film and the notch section in the bottom of a removed portion; and forming a gate electrode made of a conductive material by embedding the removed portion with the conductive material. | 2010-01-14 |
20100006956 | Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, And Process To Fabricate Same - A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer. | 2010-01-14 |
20100006957 | MICROSCOPIC STRUCTURE PACKAGING METHOD AND DEVICE WITH PACKAGED MICROSCOPIC STRUCTURE - A method of packaging a micro electromechanical structure is disclosed. The method comprises the steps of forming the structure on a substrate, depositing a sacrificial layer over the structure, patterning the sacrificial layer, depositing a porous layer over the patterned sacrificial layer, removing the patterned sacrificial layer through the porous layer, treating the porous layer with a plasma and depositing a capping layer over the plasma-treated porous layer. The plasma treatment step ensures that the capping layer material cannot enter the cavity formed by the removal of the sacrificial layer through the porous layer. A device formed by this method is also disclosed. | 2010-01-14 |