02nd week of 2012 patent applcation highlights part 19 |
Patent application number | Title | Published |
20120007597 | MICROMACHINED OFFSET REDUCTION STRUCTURES FOR MAGNETIC FIELD SENSING - A micromachined magnetic field sensor integrated with electronics is disclosed. The magnetic field sensors utilize Hall-effect sensing mechanisms to achieve 3-axis sensing. A Z axis sensor can be fabricated either on a device layer or on a conventional IC substrate with the design of conventional horizontal Hall plates. An X and Y axis sensor are constructed on the device layer. In some embodiments, a magnetic flux concentrator is applied to enhance the performance of the magnetic field sensor. In some embodiments, the magnetic field sensors are placed on slope sidewalls to achieve 3-axis magnetic sensing system. In some embodiments, a stress isolation structure is incorporated to lower the sensor offset. The conventional IC substrate and device layer are connected electrically to form a 3-axis magnetic sensing system. The magnetic field sensor can also be integrated with motion sensors that are constructed in the similar technology. | 2012-01-12 |
20120007598 | MICROMACHINED MAGNETIC FIELD SENSORS - A micromachined magnetic field sensor integrated with electronics is disclosed. The magnetic field sensors utilize Hall-effect sensing mechanisms to achieve 3-axis sensing. A Z axis sensor can be fabricated either on a device layer or on a conventional IC substrate with the design of conventional horizontal Hall plates. An X and Y axis sensor are constructed on the device layer. In some embodiments, a magnetic flux concentrator is applied to enhance the performance of the magnetic field sensor. In some embodiments, the magnetic field sensors are placed on slope sidewalls to achieve 3-axis magnetic sensing system. In some embodiments, a stress isolation structure is incorporated to lower the sensor offset. The conventional IC substrate and device layer are connected electrically to form a 3-axis magnetic sensing system. The magnetic field sensor can also be integrated with motion sensors that are constructed in the similar technology. | 2012-01-12 |
20120007599 | UPPER STACK FOR A NUCLEAR MAGNETIC RESONANCE SPECTROMETER APPARATUS AND ASSOCIATED METHOD OF OPERATING A NUCLEAR MAGNETIC RESONANCE SPECTROMETER APPARATUS - An upper stack for a nuclear magnetic resonance spectrometer apparatus includes a cryostat having one or more chambers for holding samples in a frozen state. A sample loading tube that also allows He delivery extends to the cryostat, and a sample changer mechanism is disposable at least in part proximate to the cryostat for moving specimens from the cryostat to an NMR probe where they can be heated and melted using inductive heating. A sample ejection tube extends from the sample changer mechanism allowing a clear path for heating a sample in an NMR probe using a laser beam. | 2012-01-12 |
20120007600 | ACCELERATED B1 MAPPING - A method comprises: performing a number of B i field mapping sequences ( | 2012-01-12 |
20120007601 | INDUCTOR ASSEMBLY FOR A MAGNETIC RESONANCE IMAGING SYSTEM - An inductor assembly includes an electrical conductor having a first end and an opposite second end, and a plurality of turns, each turn having a first lobe and a second lobe, the electrical conductor being formed into a lemniscate shape. A Radio Frequency (RF) coil including the lemniscate shaped inductor and a Magnetic Resonance Imaging (MRI) system including the lemniscate shaped inductor are also described herein. | 2012-01-12 |
20120007602 | LIGHTING TESTER - A combination lighting tester tool. The combination lighting tester tool includes at least three independent testing tools for identifying and diagnosing a problem in a lighting system. For example, the tester includes a lamp testing function in which a high voltage test signal is generated and transmitted using an antenna. When the test signal is in proximity to a gas filled lamp, the voltage is of sufficient magnitude to ionize the gas inside the lamp, causing the lamp to illuminate. The tester also includes a ballast testing function in which the power lines or wires connecting a ballast to a lamp or lighting fixture are tested, and a filament tester for testing the filaments in a lamp for continuity or resistance. The tester also includes a worklight for illuminating an area under test and one or more display devices (e.g., LEDs, an LCD display, or the like) which provide an indication of, for example, a test being performed or a result of a test. | 2012-01-12 |
20120007603 | CIRCUITS AND METHODS FOR CELL NUMBER DETECTION - A circuit used for determining a cell number of several battery cells. The circuit includes a detection block and a controller, and operates in a first detection mode and a second detection mode. The detection block is coupled to each of the battery cells. In the first detection mode, the detection block provides a terminal voltage signal indicative of a terminal voltage of a battery cell. In the second detection mode, the detection block provides a cell voltage signal indicative of a cell voltage of the battery cell. The controller compares the terminal voltage signal with a first threshold in the first detection mode and compares the cell voltage signal with a second threshold in the second detection mode, and provides a cell count signal indicative of the cell number based on the terminal voltage signal and the cell voltage signal. | 2012-01-12 |
20120007604 | TRL Calibration Method for a Microwave Package And a Set of Standard Packages - A method of calibrating a test platform for microwave packages is provided. According to the invention, the conventional Thru, Reflect and Line standard patterns are replaced by microwave standard packages fulfilling similar functions, the test platform being adapted accordingly. The use of standard packages makes it possible to retain the same electrical interface between each of the packages and the test platform. The invention also relates to a method of determining an electrical length L | 2012-01-12 |
20120007605 | HIGH FREQUENCY MEASUREMENT SYSTEM - The invention concerns a high frequency non-linear measurement system for analysing the behaviour of a high frequency device, for example a device for use in a high power, high frequency amplifier, such as an amplifier for use in a mobile telephone network or other telecommunications-related base-station. An embodiment of the invention provides a high frequency non-linear measurement system including one or more multiplexer circuits. Each multiplexer circuit comprises a first signal-combining circuit and a second signal-combining circuit. Each signal-combining circuit comprises a pair of directional couplers connected via a pair of signal filters arranged in parallel. | 2012-01-12 |
20120007606 | System and method for providing scanning polarized reference sources - A method of determining an angular orientation of a sensor relative to a source including the steps of amplitude modulating at least two synchronized polarized Radio Frequency (RF) carrier signals with a predetermined relationship between their amplitude modulation of their electric field components and their polarization states to provide a scanning polarized RF reference source with a desired scanning range, pattern and frequency; detecting the scanning polarized RF reference source at the sensor; and determining the orientation of the sensor based on the detected scanning polarized RF reference source. Similar methods are also provided for determining an angular orientation and/or position of a sensor relative to two or more sources, aligning a mobile sensor relative to a source and homing a sensor relative to a predetermined plane and/or point. | 2012-01-12 |
20120007607 | SENSING SYSTEM AND METHOD - A sensing system comprises a material having a matrix structure in which a plurality of sensing elements are embedded, the sensing elements having electron distribution and/or transport properties that change in response to a change in a physical or chemical property of the material. The sensing system further comprises a receiver, including an antenna, the receiver arranged to receive a source RF signal and a returned RF signal, the returned RF signal being received from the material. A change in the electron distribution and/or transport properties of the sensing elements cause the source RF signal to change, such that a change in a property of the material can be determined from the returned RF signal. A corresponding method of sensing a change in a property of a material is also provided. | 2012-01-12 |
20120007608 | ARRAY ELEMENT CIRCUIT AND ACTIVE MATRIX DEVICE - An active-matrix device is provided which includes a plurality of array element circuits arranged in rows and columns; a plurality of source addressing lines each shared between the array element circuits in corresponding same columns; a plurality of gate addressing lines each shared between the array element circuits in corresponding same rows; a plurality of sensor row select lines each shared between the array element circuits in corresponding same rows, wherein each of the plurality of array element circuits includes: an array element which is controlled by application of a drive voltage by a drive element; writing circuitry for writing the drive voltage to the drive element, the writing circuitry being coupled to a corresponding source addressing line and gate addressing line among the plurality of source addressing lines and gate addressing lines; and sense circuitry for sensing an impedance presented at the drive element, the sense circuitry being coupled to a corresponding sensor row select line; and a row driver and a column driver. | 2012-01-12 |
20120007609 | Method and Device for Position Detection - A method and the device for position detection are disclosed. The device comprises a plurality of strips intersecting each other to form a plurality of intersecting regions. A pair of depressed strips intersecting on an intersecting region contact to each other to form a depressed intersecting region. According to the depressed intersecting regions, each depression can be determined. The total contact impedance of a depressing crossover a plurality of intersecting regions is the parallel contact impedance of the contact impedances of all intersecting regions corresponding to the same depression. | 2012-01-12 |
20120007610 | Method and Device for Determining Impedance of Depression - A method and the device for position detection are disclosed. The device comprises a plurality of strips intersecting each other to form a plurality of intersecting regions. A pair of depressed strips intersecting on an intersecting region contact to each other on a contact point to form a depressed intersecting region, wherein the contact impedance of the contact point is determined according to the position of the contact point and the voltages on the contact point of one and the other of the pair depressed strips. | 2012-01-12 |
20120007611 | Method and Device for Correcting Position Error - A method and the device for position detection are disclosed. The device comprises a plurality of strips intersecting each other to form a plurality of intersecting regions. A pair of depressed strips intersecting on an intersecting region contact to each other on a contact point to form a depressed intersecting region. According to the voltages of each strip before and after the strip is depressed, an error ratio can be determined. Based on the error ration, the position error caused by the contact impedance crossover strips can be corrected. | 2012-01-12 |
20120007612 | Method and Device for Position Detection - A device comprises a plurality of strips intersecting each other to form a plurality of intersecting regions. A pair of strips intersecting on an intersecting region contact to each other on a contact point to form a depressed intersecting region. The erroneously determined intersecting regions can be detected by comparing the contact points with the corresponding intersecting regions so as to provide the only correct contact points. | 2012-01-12 |
20120007613 | CURRENT SENSING ON A MOSFET - A device having a switch with a voltage applied across the switch. A current sensing circuit is connected to one terminal of the switch. The current sensing circuit receives power independently of the voltage applied across the switch. The power supply shares the other terminal of the switch with the current sensing circuit. The switch is adapted for opening and closing. When the switch closes, the current sensing circuit senses current through the switch and upon opening the switch the high voltage of the switch is blocked from the current sensing circuit. The sense current is caused to flow from the current sensing circuit to the other terminal when the switch is closed. The flow of the sense current produces a voltage which is compared differentially to another voltage referenced by the other terminal. | 2012-01-12 |
20120007614 | Method and Device for Position Detection with Palm Rejection - The method and the device for position detection with palm rejection are disclosed. The invention provides a sensor and a controller for controlling the sensor. The sensor includes a plurality of strips. The controller execute a first kind of position detection and a second kind of position detection on the sensor. The first kind of position detection identifies an ignored zone, and the second kind of position detection executes the position detection outside the ignored zone. | 2012-01-12 |
20120007615 | Analysis of a Dielectric Medium - A method of dealing with the electrode polarization error when analyzing a dielectric test medium is achieved by firstly applying an excitation current to the test medium at a test frequency, by means of a first electric couple ( | 2012-01-12 |
20120007616 | Method and Device for Determining Impedance of Depression - A method and the device for position detection are disclosed. The device comprises a plurality of strips intersecting each other to form a plurality of intersecting regions. A pair of depressed strips intersecting on an intersecting region contact to each other on a contact point to form a depressed intersecting region, wherein the contact impedance of the contact point is determined according to the position of the depressed intersecting region and the voltages on the contact point of one and the other of the pair depressed strips. | 2012-01-12 |
20120007617 | DOWNHOLE CORROSION MONITORING - Apparatus and methods for measuring an effect of corrosion with a corrosion sensor. The apparatus includes at least a portion of a metal material configured to be disposed within a borehole and exposed to a fluid. The apparatus includes a sensor configured to measure an effect of corrosion of the at least portion of the metal material within the fluid. | 2012-01-12 |
20120007618 | Method and Device for Position Detection with Palm Rejection - A method and the device for palm ignoring disclosed. The device comprises a plurality of strips intersecting each other to form a plurality of intersecting regions. A pair of strips intersecting on an intersecting region contact to each other on a contact point to form a depressed intersecting region. The depression depressed by the palm can be determined by comparing the total impedance of the depression with a threshold so as to be ignored. | 2012-01-12 |
20120007619 | Multi-functional precious stone testing apparatus and method thereof - A multi-functional precious stone testing apparatus includes a portable housing, a testing unit, and an indication unit. The portable housing includes a hand-held casing and a probe casing extended from a front end of the hand-held casing. The testing unit includes a conductive probe having a testing end portion extended out of a tip end of the probe casing for contacting a testing object to determine a conductivity of the testing object. The indication unit includes a LED light unit received in the hand-held casing for illuminating the testing end portion of the conductive probe during testing, wherein the LED light unit is positioned away from the tip end of the probe casing for preventing heat generated from the LED light unit being transmitted toward the conductive probe to affect an accurate measurement for the conductivity of the testing object. | 2012-01-12 |
20120007620 | GROUNDING ASSEMBLY WITH INSULATED CONDUCTOR - An electrical grounding device can have a grounding plate and an insulated connecting wire. Having an insulated connecting wire reduces or prevents corrosion of the connecting wire by the surrounding underground soil. A grounding assembly is also provided and can have such a grounding device. The grounding assembly can include additional grounding devices which can also have an insulated connecting wire. A method of measuring resistance to ground of a grounding device of a grounding assembly having a multiple grounding devices and one or more bonding wires routed through a conduit is also disclosed. Having all but one of the connecting wires and bonding wires insulated or insulating all the connecting wires of the grounding devices of the grounding assembly allows measurement of resistance to ground by electrically disconnecting all but the connecting wire of the grounding device to be tested, contacting one terminal of an ohm meter to the connecting wire of the grounding device to be tested and contacting the other terminal of the ohm meter to the earth or ground, and reading the ohm meter. | 2012-01-12 |
20120007621 | CIRCUIT INTERRUPTER DEVICE WITH SELF-TEST FUNCTION - A ground fault circuit interrupter (GFCI) device with self-test function includes: hot and neutral conducting circuits; an fault detection circuit responsive to a fault in the hot and neutral conducting circuits to generate a fault detection signal; a signal driving circuit responsive to the fault detection signal to generate a drive signal; a disconnecting mechanism for disconnecting electrical connections in the hot and the neutral conducting circuits when the drive signal exceeds a predetermined level; a self-test circuit for generating a self-test signal according to a predetermined time period and when an alternating current of the power source passes zero points, generating an evaluation result based on the self-test signal and a feedback signal of a fault detection signal corresponding to the self-test signal, and generating error signals if the evaluation result indicates a circuit error; and a device-state indicator circuit for generating alarms based on the error signals. | 2012-01-12 |
20120007622 | IP CORE DESIGN SUPPORTING USER-ADDED SCAN REGISTER OPTION - An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port | 2012-01-12 |
20120007623 | SPRAY COOLING THERMAL MANAGEMENT SYSTEM AND METHOD FOR SEMICONDUCTOR PROBING, DIAGNOSTICS, AND FAILURE ANALYSIS - A micro-spray cooling system beneficial for use in testers of electrically stimulated integrated circuit chips is disclosed. The system includes micro-spray heads disposed about a probe head. The spray heads and probe head are disposed in a sealed manner inside a spray chamber that, during operation, is urged in a sealing manner onto a sealing plate holding the integrated circuit under test. The atomized mist cools the integrated circuit and then condenses on the spray chamber wall. The condensed fluid is pumped out of the chamber and is circulated in a chiller, so as to be re-circulated and injected again into the micro-spray heads. The pressure inside the spray chamber may be controlled to provide a desired boiling point. | 2012-01-12 |
20120007624 | SEMICONDUCTOR SYSTEM AND DEVICE FOR IDENTIFYING STACKED CHIPS AND METHOD THEREOF - A semiconductor system for identifying stacked chips includes a first semiconductor chip and a plurality of second semiconductor chips. The first semiconductor chip generates a plurality of counter codes by using an internal clock or an external input clock and transmits slave address signals and the counter codes through a through-chip via. The second semiconductor chips are given corresponding identifications (IDs) by latching the counter codes for a predetermined delay time, compare the latched counter codes with the slave address signals, and communicate data with the first semiconductor chip through the through-chip via according to the comparison result. | 2012-01-12 |
20120007625 | Test Socket for Testing Electrical Characteristics of a Memory Module - A test socket may include a socket frame, a plate, a socket pin and a link. The socket frame may have a slot configured to accept an object. The plate may be free to move in the slot along an inserting direction of the object to support a lower surface of the object. The socket pin may be movably arranged in a direction substantially perpendicular to the inserting direction of the object. The socket pin may selectively make contact with a tab of the object. A link may be pivotally connected to the socket pin and the plate. Thus, the socket pin of the test socket may avoid dragging along the tab of the object during insertion, and accordingly, the tab of the object may avoid damage. | 2012-01-12 |
20120007626 | TESTING TECHNIQUES FOR THROUGH-DEVICE VIAS - Techniques for testing an electronic device with through-device vias can include using a probe card assembly with probes for contacting connection structures of the electronic device including ends of through-device vias of the electronic device. A pair of the probes can be electrically connected in the probe card assembly and can thus contact and form a direct return loop from one through-device via to another through-device via of a pair of the through-device vias with which the pair of probes is in contact. The electronic device can include test circuitry for driving a test signal onto the one of the through-device vias and a receiver for detecting the test signal on the other of the through-device vias. | 2012-01-12 |
20120007627 | PROBE HEAD OF PROBE CARD AND MANUFACTURING METHOD OF COMPOSITE BOARD OF PROBE HEAD - A probe head of vertical probe card and a manufacturing method of a composite board thereof are provided. The probe head includes guide plate, composite board, and probe pin. The composite board includes first board layer and second board layer which are laminated together by joining operation. The composite board further includes through hole which is made by drilling and passed all the way through the first board layer and the second board layer. The friction coefficient of the first board layer is less than that of the second board layer, and the thermal expansion coefficient of the second board layer is less than that of the first board layer. The probe pin is penetrated all the way through the through hole of the composite board. By this, friction between the probe pin and composite board is reduced so as to stabilize the position of the probe pin. | 2012-01-12 |
20120007628 | METHOD FOR CHECKING ALIGNMENT ACCURACY OF A THIN FILM TRANSISTOR - A method for checking alignment accuracy of a thin film transistor includes providing a substrate, forming a first conductive layer on the substrate, performing a first patterning process to form a gate electrode of a thin film transistor and a first terminal and a second terminal of a testing device, forming a first insulating layer covering the first terminal, the second terminal and the gate electrode on the substrate, forming a contact hole substantially corresponding to the first terminal and the second terminal in the first insulating layer, forming a pixel electrode and a connecting electrode of the testing device in the first contact hole, and performing a close/open circuit test. When the first terminal, the connecting electrode and the second terminal construct a close circuit, alignment accuracy is confirmed. When the first terminal, the connecting electrode and the second terminal construct an open circuit, alignment inaccuracy is confirmed. | 2012-01-12 |
20120007629 | Method For Detecting A Short-Circuit, And Power Supply Module Implementing Said Method - The present invention relates to a power supply module ( | 2012-01-12 |
20120007630 | IMPEDANCE CALIBRATION MODE CONTROL CIRCUIT - An impedance calibration mode control circuit includes: a first signal generating unit configured to generate a first calibration control signal in response to a ZQ calibration command received after a power-up operation; and a second signal generating unit configured to generate a second calibration control signal during a refresh operation of a semiconductor device. | 2012-01-12 |
20120007631 | INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING DATA OUTPUT IMPEDANCE - An integrated circuit for controlling data output impedance includes an address decoder, a selection signal decoder, and a transfer control unit. The address decoder is configured to decode an address signal and generate a selection mode signal and a first adjustment mode signal. The selection signal decoder is configured to decode a selection signal and generate an enable signal and a disable signal. The transfer control unit is configured to transfer a pull-up signal and a pull-down signal as a selection pull-up signal and a selection pull-down signal. | 2012-01-12 |
20120007632 | CALIBRATING RESISTANCE FOR INTEGRATED CIRCUIT - An integrated circuit includes a first ODT unit and an input buffer. The first ODT unit is configured to receive at least one pull-up code and at least one pull-down code for impedance matching of a first line through which data is transferred, and adjust a resistance value. The input buffer is configured to drive input data by buffering the data in response to a level of a reference voltage, wherein the driving of the input data is adjusted in response to the pull-up code and the pull-down code. | 2012-01-12 |
20120007633 | RECONFIGURABLE LOGICAL CIRCUIT - Provided is a reconfigurable logic circuit that can effectively use a preposition logic that composes a logic block. The reconfigurable logic block according to the present invention includes a plurality of logic blocks ( | 2012-01-12 |
20120007634 | DIGITAL PROCESSING MONITORING DEVICE - According to an embodiment, a digital process type monitor device includes a plurality of modules and a mother board connected to each of the modules. Each module includes: a base board connected to a connector and having an FPGA for main control and an IPGA for sub board control mounted thereon; and a sub board for a main-machine I/F process, having an FPGA for an I/F process mounted hereon. Each sub board has storage devices for storing man-machine I/F information on the sub board. Each of the FPGA writes transmission data into a predetermined region of a transmission area and has a common transmission protocol to share the transmission data between the respective modules. | 2012-01-12 |
20120007635 | SEMICONDUCTOR DEVICE - FPGAs and MPLDs, which are conventional programmable semiconductor devices, have had poor cost performance and did not suitably take long signal lines into account. To solve this, a flip-flop is built into each MLUT block comprised of a plurality of MLUTs, each MLUT comprising a memory and an address-data pair. With respect to the adjacent line between adjacent MLUTs, alternated adjacent line are introduced, while in the case of interconnects between non-adjacent MLUTs, dedicated distant line and, furthermore, a torus interconnect network are provided. | 2012-01-12 |
20120007636 | ANALOG SWITCH FOR SIGNAL SWINGING BETWEEN POSITIVE AND NEGATIVE VOLTAGES - An analog signal is input to an input terminal. An analog signal is output via an output terminal. A first transistor is an N-channel MOSFET, and is provided between the input terminal and the output terminal. A first resistor is provided between the gate of the first transistor and a first fixed voltage terminal (power supply terminal), which sets the gate of the first transistor to a high-impedance state. | 2012-01-12 |
20120007637 | LOAD DRIVER SYSTEM - A first driver device and a first diode are connected in parallel between an output node and a first voltage node. A second driver device and a second diode are connected in parallel between the output node and a second voltage node. When a first switching time comes, a first drive control section switches the first driver device from the off state to the on state after detecting that an output voltage at the output node reaches a predetermined first reference voltage. When a second switching time comes, the first drive control section switches the first driver device from the on state to the off state. A second drive control section switches the second driver device from the on state to the off state when the first switching time comes, and switches the second driver device from the off state to the on state when the second switching time comes. | 2012-01-12 |
20120007638 | SYSTEM AND METHOD FOR MULTIPLE-PHASE CLOCK GENERATION - A system and method of clock generation to provide divided-by-2 clocks with prescribed phase shifts are disclosed. In a communication system with high-order harmonic mixing, the system requires LO signals with a set of prescribed phase shifts, such as 0°, 45°, 90°, and 135°, or 0°, 60° and 120°. Often, the clock generation system involves a divide-by-2 divider to derive the clock signals with the prescribed phase shifts. In a conventional implementation of the divide-by-2 divider, the system is subject to phase uncertainty in the output signal. Accordingly, a system comprises multiple latch pairs and respective differential clocks are used to generate the clocks with the set of correct prescribed phase shifts. | 2012-01-12 |
20120007639 | SEMICONDUCTOR DEVICE - A semiconductor device includes a reset signal generator configured to change the number of activated signals among a plurality of reset signals according to a frequency of an external clock, a plurality of mixing control signal generators configured to generate a plurality of first and second mixing control signals, and a clock mixer configured to generate a mixing clock by mixing a first driving clock and a second driving clock, wherein the first driving clock is generated by driving a positive clock of the external clock according to the plurality of first mixing control signals, and the second driving clock is generated by driving a negative clock of the external clock according to the plurality of second mixing control signals. | 2012-01-12 |
20120007640 | Multi-Channel Multi-Protocol Transceiver With Independent Channel Configuration Using Single Frequency Reference Clock Source - A circuit for producing one of a plurality of output clock frequencies from a single, constant input reference clock frequency. The circuit comprises a reference clock system and a phase lock loop. The reference clock system includes a bypass path, a divider path including a first integer divider, and a multiplexer. A divisor of the first integer divider is based on a selected communications protocol of a group of possible communications protocols. The multiplexer is configured to route the bypass path or the divider path based on the selected communications protocol. The phase lock loop includes a voltage controlled oscillator and a feedback path. The feedback path includes a second integer divider. A divisor of the second integer divider is based on the selected communications protocol. The reference clock system is configured to receive a constant reference clock frequency. The voltage controlled oscillator is configured to produce one of a plurality of output clock frequencies corresponding to the selected communications protocol. The selected output clock frequency is produced based on at least one of the routing of the multiplexer, the divisor of the first integer divider, and the divisor of the second integer divider. | 2012-01-12 |
20120007641 | ELECTRONIC PART AND METHOD OF DETECTING FAULTS THEREIN - An electronic component includes an oscillator element, a driving circuit outputting a driving signal to the oscillator element, a clock frequency generator outputting a clock signal to the driving circuit, a clock frequency controller controlling a frequency of the clock signal, a consumption-current detection unit detecting a consumption current of the driving circuit, and a fault detection unit electrically connected to the consumption-current detection unit and the clock frequency controller. When the clock frequency controller changes the frequency of the clock signal, the detected consumption current changes, and allows the consumption-current detection unit to detect the change of the consumption current. The fault detection unit detects a fault based on the change of the frequency of the clock signal and the change of the consumption current. This electronic component can have a fault detection function and a small size. | 2012-01-12 |
20120007642 | REFERENCE FREQUENCY GENERATING DEVICE - The disclosed is a reference frequency generating device ( | 2012-01-12 |
20120007643 | Binary-Weighted Delta-Sigma Fractional-N Frequency Synthesizer With Digital-To-Analog Differentiators Canceling Quantization Noise - A phase lock loop includes a quantization circuit that generators an out of phase noise cancellation signal from an error in a delta-sigma modulator and applies the noise cancellation signal to the charge pump. The quantization circuit includes a digital-to-analog differentiator. The digital-to-analog differentiator may be, for example, a single-bit first-order digital-to-analog differentiator, a single-bit second-order digital-to-analog differentiator, or a full M-bit binary-weighted digital to analog differentiator. | 2012-01-12 |
20120007644 | COMPARATOR-BASED BUFFER WITH RESISTIVE ERROR CORRECTION - A comparator-based buffer method and system enhance the driving capability of high-gain amplifiers with switched-capacitor loads. It includes a current source, a comparator, switches, sampling capacitor and overshoot correction resistor. A correction solution using a resistor in the charging path and a correction phase reduces the overshoot of the output voltage while constraining power consumption and minimizing components. Spectre® simulations verify the effectiveness of the invention. | 2012-01-12 |
20120007645 | DELAY LOCKED LOOP CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - A delay locked loop (DLL) circuit includes a timing pulse generating unit configured to generate a plurality of timing pulses, which are sequentially pulsed during delay shifting update periods, in response to a source clock, wherein the number of the generated timing pulses changes according to a frequency of the source clock; a clock delay unit configured to compare a phase of the source clock with a phase of a feedback clock at a time point defined by each of the timing pulses, and delay a phase of an internal clock, corresponding to a rising or falling edge of the source clock, according to the comparison result; and a delay replica modeling unit configured to reflect actual delay conditions of the internal clock path on an output clock of the clock delay unit, and to output the feedback clock. | 2012-01-12 |
20120007646 | DLL CIRCUIT HAVING ACTIVATION POINTS - A delay locked loop (DLL) circuit includes a delay line configured to generate a delay clock signal by delaying a reference clock signal in response to a delay control signal, the delay line having two or more initial activation points, wherein the initial activation points are selected according to an initial value of the delay control signal; a delay compensating unit configured to generate a feedback clock signal by delaying the delay clock signal for a predetermined time; a phase detecting unit configured to generate a phase detection signal by comparing a phase of the reference clock signal to a phase of the feedback clock signal; and a delay control unit configured to generate the delay control signal in response to the phase detection signal. | 2012-01-12 |
20120007647 | DUTY CYCLE CORRECTION CIRCUIT - A duty cycle correction (DCC) circuit includes a duty signal generating unit configured to compare a high duration of an output clock with a low duration of the output clock in a clock cycle to generate a duty signal, a counting unit configured to count and output a preliminary code after a duty cycle correction (DCC) operation starts, a duty code generating unit configured to generate a duty code by selectively inverting or transferring without inversion the preliminary code in response to an initial value of the duty signal, and a duty cycle correcting unit configured to output the output clock by driving an input clock to a pull-up driving capacity and a pull-down driving capacity which are determined in response to the initial value of the duty signal and the duty code. | 2012-01-12 |
20120007648 | High voltage tolerant, small footprint BJT-CMOS active clamp - In an active clamp implemented in a 5V complementary BiCMOS process, the footprint of the active clamp, which includes at least one NMOS clamp stack, is reduced by introducing a BJT into the circuit to allow the number of NMOS clamp stacks to be reduced. | 2012-01-12 |
20120007649 | METHOD FOR CLAMPING A SEMICONDUCTOR REGION AT OR NEAR GROUND - A clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. The clamping circuit includes a current mirror as well as first and second bipolar transistors. The current mirror receives a first current and supplies a second current in response. The first current is received by the first bipolar transistor, and the second current is received by the second bipolar transistor. The difference between the base-emitter junction voltages of the first and second bipolar transistors, in part, defines the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base/gate terminals of the transistors disposed in the current mirror. The circuit optionally includes a pair of cross-coupled transistors to reduce the output impedance and improve the power supply rejection ratio. | 2012-01-12 |
20120007650 | MULTIPLE E-PROBE WAVEGUIDE POWER COMBINER/DIVIDER - A power combiner/divider having a waveguide, a plurality of amplifiers disposed on a supporting structure, a plurality of probes, each one having a first end electrically coupled to an output of a corresponding one of the plurality of amplifiers and a second end projecting outwardly from the supporting structure and into the waveguide. The probes are disposed in a common region of the waveguide. The region has a common electric field maximum within the waveguide. A first portion of the probes proximate the sidewalls have lengths different from a second portion of the probes disposed in a region distal from the sidewalls of the waveguide. The waveguide is supported by the support structure. The power combiner is a monolithic microwave integrated circuit structure. | 2012-01-12 |
20120007651 | SYSTEM AND METHOD FOR SIGNAL MIXING BASED ON HIGH ORDER HARMONICS - A system and method for signal mixing using high-order harmonics of a local oscillation (LO) signal. In a radio frequency (RF) system, the input RF signal is converted to a lower frequency signal such as an intermediate frequency (IF) signal or a baseband signal for further processing. A voltage controlled oscillator (VCO) is often used to generate a VCO signal which is then divided down to provide the needed LO signals for down conversion. The present invention discloses a system and method for generating a composite harmonic signal based on a linear combination of divided down LO signals with specific phase shifts. Consequently a VCO signal with lower frequency can be used to conserve power. The composite harmonic signal is mixed with the input RF signal to generate a series of mixed signal including one associated with a high-order harmonic of the divided down LO signal. Systems to implement the high order harmonic mixing is also disclosed which comprises a plurality of mixer sections with configurable weighting factors. A combination circuit is used to combine the weighted mixed signals which contains a term corresponding the mixing of the input RF signal with a high order LO harmonic. | 2012-01-12 |
20120007652 | SIGNAL MONITORING SYSTEMS - A signal monitoring system includes a conversion circuit and a controller coupled to the conversion circuit. The conversion circuit converts a reference input to a reference output based on a real-time level of a trim reference and converts a monitored signal to an output signal. The controller calibrates the output signal according to the reference output and according to a predefined reference. The predefined reference is determined by the reference input and by a pre-trimmed level of the trim reference. | 2012-01-12 |
20120007653 | DATA TRANSMISSION DEVICE AND IMAGE SENSOR SYSTEM USING THE SAME - A data transmission device includes a control unit and a delay chain unit. The control unit outputs a first control signal through an nth control signal, where n is a natural number. The delay chain unit includes a first switching element through an nth switching element. The switching elements receive a first data signal through an nth data signal and perform pipelining operations on the first through nth data signals based upon the first through nth control signals, respectively, to output the pipelined data signals as at least one data stream. The switching elements are connected to each other to form at least one data delay chain. | 2012-01-12 |
20120007654 | SYSTEM AND METHOD OF TRANSISTOR SWITCH BIASING IN A HIGH POWER SEMICONDUCTOR SWITCH - A circuit and method are provided for switching in a semiconductor based high power switch. Complementary p-type based transistors are utilized along insertion loss insensitive paths allowing biasing voltages to alternate between supply and ground, allowing for negative voltage supplies and blocking capacitors to be dispensed with, while improving performance. | 2012-01-12 |
20120007655 | INPUT/OUTPUT CIRCUIT - In some embodiments, an input/output (I/O) circuit sends and receives a high-level signal and a low-level signal via a coupling capacitance provided on a communication line. The I/O circuit includes a receiving portion including a first detection circuit arranged to detect one of the signals and a second detection circuit arranged to detect the other signal, a transmitting portion including a three-value output circuit configured to output one of signals consisting of a high-level signal, a low-level signal, and a high impedance signal, and a control circuit configured to control the receiving portion and the transmitting portion. The control circuit judges a level of an inputted signal depending on detection results of the first detection circuit and the second detection circuit in a receiving state and controls an output value of the three-value output circuit in a transmitting state. | 2012-01-12 |
20120007656 | Radiation Tolerant Complementary Cascode Switch Using Non-Radiation Hardened Transistors - A power switching circuit designed for operating in a radiation environment using non-radiation hardened components is provided. The power switching circuit provides a high-voltage rated, non-radiation hardened N-channel FET (N-FET) controlled by a relatively small, low-voltage, non-radiation hardened P-channel FET (P-FET), while both devices are operating in a radiation environment. The P-FET device is drive by a sufficiently high drive voltage in order to overcome gate threshold shifts resulting from accumulated radiation damage. | 2012-01-12 |
20120007657 | DISCONNECTOR SWITCH FOR GALVANIC DIRECT CURRENT INTERRUPTION - A disconnecting apparatus for direct current interruption between a direct current source and an electrical device, in particular between a photovoltaic generator and an inverter, has a current-conducting mechanical switching contact and semiconductor electronics connected in parallel with the switching contact. The semiconductor electronics are non-conducting when the switching contact is closed, wherein a control input of the semiconductor electronics is wired with the switching contact in such a way that, when the switching contact opens, an arc voltage generated as a result of an arc via the switching contact switches the semiconductor electronics to become conducting. | 2012-01-12 |
20120007658 | BALANCED SWITCH - Embodiments of circuits, devices, and methods related to a radio frequency switch are disclosed. In various embodiments, a circuit may comprise a series path including a series transistor to be switched on during a first mode of operation; a shunt path including a shunt transistor to be switched off during the first mode of operation; and a return path including a return transistor to be switched on during the first mode of operation. Other embodiments may also be described and claimed. | 2012-01-12 |
20120007659 | Temperature Compensated Current Source - A temperature compensated current source forms an uncompensated source current that is proportional to a reference voltage applied to an impedance, wherein the impedance varies with temperature. A temperature compensation current is formed that is proportional to absolute temperature (IPTAT). The uncompensated source current and the temperature compensation current is combined to form a temperature compensated source current and provided as an output of the current source. | 2012-01-12 |
20120007660 | Bias Current Generator - A bias current generator comprising at least one field effect transistor operating as a current source or sink, a capacitive store for storing a first control voltage, and a first switch for selectively connecting the capacitive store to a gate of the at least one field effect transistor. | 2012-01-12 |
20120007661 | APPARATUS AND METHOD FOR DETERMINING DYNAMIC VOLTAGE SCALING MODE, AND APPARATUS AND METHOD FOR DETECTING PUMPING VOLTAGE USING THE SAME - A mode determination apparatus in a semiconductor apparatus includes a first condition detection block configured to generate a first condition signal in response to a clock enable signal activated when the semiconductor apparatus enters a dynamic voltage scaling mode, a second condition detection block configured to generate a second condition signal in response to an external high voltage in the dynamic voltage scaling mode, the external high voltage having a voltage level in the dynamic voltage scaling mode different from a voltage level in a normal mode, and a signal processing block configured to generate a dynamic voltage scaling mode signal in response to the first condition signal and the second condition signal. | 2012-01-12 |
20120007662 | HIGH VOLTAGE CONTROL CIRCUIT OF SEMICONDUCTOR DEVICE - A high voltage control circuit of a semiconductor device includes an output node control circuit configured to set an initial potential of an output terminal or to discharge the potential of the output terminal, in response to an input signal and a high voltage supply circuit comprising an acceleration unit and a potential control unit coupled in series between the output terminal and a supply terminal for supplying a high voltage. The acceleration unit is operated in response to the potential of the output terminal, and the potential control unit is operated in response to the input signal. | 2012-01-12 |
20120007663 | INTEGRATED CIRCUIT WITH DEVICE FOR ADJUSTMENT OF THE OPERATING PARAMETER VALUE OF AN ELECTRONIC CIRCUIT AND WITH THE SAME ELECTRONIC CIRCUIT - An integrated circuit includes an electronic circuit and a device for adjustment of the operating parameter value of the electronic circuit. The electronic circuit comprises a resistive stage. The device comprises a first circuit portion adapted to adjust said operating parameter when the device is active and the electronic circuit is inactive, and adapted to be inactive when the electronic circuit is active, and a second circuit portion adapted to determine the active or inactive state of the device in response to the value of an external control signal. The integrated circuit comprises a first external terminal for the connection to ground, a second external terminal for inputting said control signal, a further external terminal for inputting a further external signal and a deactivation circuit driven by said further external signal to deactivate the electronic circuit when the device is active. | 2012-01-12 |
20120007664 | APPARATUS AND METHOD FOR RECOVERY OF WASTED POWER FROM DIFFERENTIAL DRIVERS - An apparatus and method for supplying power to circuits of an integrated circuit (IC) from the wasted power in low-swing high-speed differential line drivers used in the IC, is disclosed. In a high speed line driver the load resistors of the driver are connected to a power supply, either the local power supply or the receiver power supply. DC power for the driver is supplied through these resistors. A large portion of this power, supplied from the power supply is wasted in the DC set-up circuit of the differential line driver. It is proposed to use this wasted power to power selected circuits of an IC. The use of this wasted power from the drivers for powering the circuits reduces the overall power dissipation of the system. | 2012-01-12 |
20120007665 | CMOS IMAGE SENSOR - A CMOS image sensor includes a photodiode, a plurality of transistors for transferring charges accumulated at the photodiode to one column line, and a voltage dropping element connected to a gate electrode of at least one transistor among the plurality of transistors for expanding a saturation region of the transistor by dropping down a gate voltage inputted to the gate electrode of the at least one transistor. | 2012-01-12 |
20120007666 | DEVICE FOR IMPEDANCE MATCHING A COMPONENT, COMPRISING A FILTER HAVING MATCHABLE IMPEDANCE, BASED ON A PEROVSKITE TYPE MATERIAL - A device comprises at the input a first component (PA) having a first output impedance (Z | 2012-01-12 |
20120007667 | AUTOMATIC CUTOFF FREQUENCY ADJUSTING CIRCUIT AND PORTABLE DIGITAL ASSISTANT - The disclosed invention enables the cutoff frequency of a filter to be automatically adjusted to an arbitrary setting value within the adjustment range. An automatic cutoff frequency adjusting circuit includes a voltage/current converter circuit, a charge circuit, a discharge circuit, a digital capacitance having a plurality of electrostatic capacitances, a comparator for comparing a voltage inputted to the digital capacitance with a reference voltage, and a capacitance control circuit for controlling the digital capacitance. The time until the comparator detects that the voltage inputted to the digital capacitance is higher than the reference voltage after a reset signal has become a predetermined logic level is measured, and the digital capacitance is controlled by repeating, under a predetermined condition, processing for obtaining a next setting value of the digital capacitance, based on a measurement result, a target value of the digital capacitance, and the current value of the digital capacitance. | 2012-01-12 |
20120007668 | FILTER CIRCUIT, TRANSMISSION FILTER CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, COMMUNICATION APPARATUS, AND TIMING ADJUSTMENT METHOD FOR FILTER CIRCUIT - A filter circuit includes two parallel digital filters, a DAC, and an LPF. The DAC includes two parallel decoders, a parallel-to-serial converter, a switch driver, and a switch. A PLL circuit supplies a reference clock to the DAC. A frequency divider provided in the DAC divides the frequency of the reference clock by two, and supplies the half frequency clock to a parallel processing section (the two decoders and the parallel-to-serial converter) of the DAC and the two digital filters. This makes it easy to secure a timing margin, permitting use in high-speed communication on the order of several GHz. | 2012-01-12 |
20120007669 | ON-DIE ANTI-RESONANCE STRUCTURE FOR INTEGRATED CIRCUIT - A structure and method for reducing the effects of chip-package resonance in an integrated circuit assembly is described. A series RLC circuit is employed to reduce the output impedance of the power delivery system at the resonance frequency. | 2012-01-12 |
20120007670 | SYSTEM AND METHOD FOR CONTROLLING RADIO FREQUENCY TRANSMISSIONS FROM AN ELECTRONIC DEVICE - The disclosure relates to a system and method for attenuating harmonics in a power amplifier. An electronic circuit for reducing leakage of radio frequency signals from a power amplifier of a wireless communication device is provided. The circuit comprises: a printed circuit board (PCB) having the power amplifier mounted on the PCB; a first electrical track in the PCB connecting to a power input terminal of the power amplifier; and a first capacitor connected to the first electrical track and a ground reference in the PCB, the first capacitor reducing transmission of radio frequency signals from the input terminal of the power amplifier. | 2012-01-12 |
20120007671 | APPARATUS FOR AUTOMATICALLY SEPARATING AND DETECTING NOISE RADIO WAVES - An output signal SHS is secondarily amplified by a high-frequency amplifier AMP | 2012-01-12 |
20120007672 | Linearization Device for a Power Amplifier - A linearization device for a power amplifier using adaptive digital baseband predistortion includes a pre-inverse block receiving a complex discretized input signal {tilde over (x)} | 2012-01-12 |
20120007673 | AMPLIFIER WITH WIDE GAIN RANGE - An amplifier with wide gain range includes a signal converting unit, a channel unit, and multiple amplifiers. The signal converting unit receives a gain modulation signal and accordingly outputs multiple modulation signals and multiple selection signals. Based on a level of the gain modulation signal, one of the selection signals is set at a first logic state and the other selection signals are at a second logic state. The channel unit has multiple channels, respectively controlled by the selection signals, so as to conduct the channel with at the first logic state. The amplifiers are connected in series. Output terminals of the amplifiers are also respectively output to the channels of the channel unit. The amplifiers are also controlled by the modulation signals of the signal converting unit. | 2012-01-12 |
20120007674 | POWER AMPLIFIER REDUCING GAIN MISMATCH - There is provided a power amplifier reducing a gain mismatch in order to reduce a gain mismatch between an N MOS amplifier and a P MOS amplifier by cross-connecting outputs from a two-stage amplification unit in a power amplifier having amplification units with a stacked structure in which the N MOS amplifier and the P MOS amplifier are connected in series with each other. | 2012-01-12 |
20120007675 | POWER AMPLIFIER - A power amplifier is provided. The power amplifier includes a loading circuit, a first stage amplifying circuit, an analog pre-distorter, a loading circuit and a second stage amplifying circuit. The first stage amplifying circuit is coupled to the loading circuit to receive a first signal and output a second signal accordingly. The analog pre-distorter is coupled to the first stage amplifying circuit to detect the envelope of the second signal and generates a third signal according to the envelope. The second stage amplifying circuit is coupled to the first stage amplifying circuit to receive the second signal. The loading circuit is biased on the third signal. The gain of the first stage amplifying circuit is related to the third signal. | 2012-01-12 |
20120007676 | DRIVE AMPLIFIER - A drive amplifier having improved linearity while being characterized by low current consumption. The drive amplifier includes first and second transistors having a gate to which first and second differential Radio Frequency (RF) voltages are respectively input; a third transistor which has a drain connected to a drain of the second transistor and a source connected to the gate of the first transistor, and a drain-source current which increases with an increase in the second differential RF voltage; and a fourth transistor which has a drain connected to a drain of the first transistor and a source connected to the gate of the second transistor, and a drain-source current which increases with an increase in the first differential RF voltage. | 2012-01-12 |
20120007677 | Class AB Operational Amplifier and Output Stage Quiescent Current Control Method - A class AB operational amplifier includes: a first transistor, for generating a first current; a second transistor, where a second source voltage of the second transistor is equal to a first source voltage of the first transistor, for generating an output stage quiescent current; and an output stage quiescent current controller, coupled to a gate and a source of the first transistor, for controlling a first drain-to-source voltage of the first transistor to be equal to a second drain-to-source voltage of the second transistor. A ratio of the output stage quiescent current to the first current is equal to a ratio of a second W/L ratio of the second transistor to a first W/L ratio of the first transistor. | 2012-01-12 |
20120007678 | Broadband Transistor Bias Network - An amplifying circuit for use in, for example, broadband transceivers is described. A bias filter is connected between an amplifying transistor and a power supply to block a wide range of frequencies associated with amplified RF input signals from reaching the power supply, while permitting DC power to reach the transistor. | 2012-01-12 |
20120007679 | Integrated RF Front End with Stacked Transistor Switch - A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal. A preferred embodiment of the RF transceiver IC includes two distinct PA circuits, two distinct receive signal amplifier circuits, and a four-way antenna switch to selectably couple a single antenna connection to any one of the four circuits. | 2012-01-12 |
20120007680 | VARIABLE GAIN AMPLIFIER - A variable gain amplifier includes a direct current (DC) blocking capacitor which receives an input signal at a first terminal, a variable amplifier unit, having a variable transistor size, which amplifies an output of a second terminal of the DC blocking capacitor, a load impedance unit coupled to an output of the variable amplifier unit, a bias resistor having a first terminal coupled to the second terminal of the DC blocking capacitor, a variable bias voltage generator which applies a variable bias voltage to a second terminal of the bias resistor, and a gain controller which provides control to decrease the variable bias voltage when an effective transistor size of the variable amplifier unit is controlled so as to increase, and provides control to increase the variable bias voltage when the effective transistor size of the variable amplifier unit control is controlled so as to decrease. | 2012-01-12 |
20120007681 | METHOD AND SYSTEM FOR A FEEDBACK TRANSIMPEDANCE AMPLIFIER WITH SUB-40KHZ LOW-FREQUENCY CUTOFF - A system for a feedback transimpedance amplifier with sub-40 khz low-frequency cutoff is disclosed and may include amplifying electrical signals received via coupling capacitors utilizing a transimpedance amplifier (TIA) having feedback paths comprising source followers and feedback resistors. The feedback paths may be coupled prior to the coupling capacitors at inputs of the TIA. Voltages may be level shifted prior to the coupling capacitors to ensure stable bias conditions for the TIA. The TIA may be integrated in a CMOS chip and the source followers may comprise CMOS transistors. The TIA may receive current-mode logic or voltage signals. The electrical signals may be received from a photodetector, which may comprise a silicon germanium photodiode and may be differentially coupled to the TIA. The chip may comprise a CMOS photonics chip where optical signals for the photodetector in the CMOS photonics chip may be received via one or more optical fibers. | 2012-01-12 |
20120007682 | CHARGE PUMP CONTROL SCHEME - An integrated circuit includes a charge pump having a voltage output. A voltage level detector is arranged to receive the voltage output, wherein the voltage level detector provides a first enable signal for the charge pump. A ring oscillator has multiple inverters. The ring oscillator is coupled to the charge pump. A counter control circuit is configured to provide a control signal for adjusting a frequency of the ring oscillator based on the first enable signal of the voltage level detector. | 2012-01-12 |
20120007683 | OSCILLATOR TUNING SYSTEM AND OSCILLATOR TUNING METHOD - An oscillator tuning system and an oscillator tuning method are provided. The system includes a determination unit which determines whether a power which is used in an RFID tag having an RFID oscillator is greater than a reference value; and a frequency tuner which tunes a driving frequency of the RFID oscillator according to a result of the determination. The method includes determining whether a power which is used in an RFID tag having an RFID oscillator is greater than a reference value; and tuning a driving frequency of the RFID oscillator according to a result of the determination. | 2012-01-12 |
20120007684 | FLEXURAL RESONATOR ELEMENT, RESONATOR, OSCILLATOR, AND ELECTRONIC DEVICE - A crystal resonator element include a pair of resonating arms extending from a base, the resonating arms includes a groove, a slope portion is formed in a connection portion of the resonating arms to the base so that a distance between the groove and the outer edge of each of the resonating arms increases as it approaches the base from the resonating arms, and a non-electrode region which extends over a range of areas from a connection portion connected to a first side surface formed along the longitudinal direction of the groove and a connection portion connected to a second side surface facing the first side surface with a bottom portion disposed there between and in which excitation electrodes are not formed is provided in the groove in at least a part of the bottom portion positioned in the slope portion. | 2012-01-12 |
20120007685 | RESONATOR ELEMENT, RESONATOR, AND OSCILLATOR - A resonator element includes: at least one resonating arm extending, wherein the resonating arm has a mechanical resonance frequency which is higher than a thermal relaxation frequency thereof, the resonating arm has a groove portion, the groove portion includes a bottom portion, a first side surface that extends along the longitudinal direction of the resonating arm and comes into contact with the opened principal surface and the bottom portion, and a second side surface that faces the first side surface with the bottom portion disposed therebetween and comes into contact with the opened principal surface and the bottom portion, and the groove portion has a non-electrode region which extends from a part of the first side surface close to the bottom portion to a part of the second side surface close to the bottom portion and in which no electrode is provided. | 2012-01-12 |
20120007686 | MULTIBAND VOLTAGE CONTROLLED OSCILLATOR WITHOUT SWITCHED CAPACITOR - A controlled oscillator includes, connected in parallel, a capacitor configured to be tuneable based upon a first signal, an inductor, and an active impedance. The active impedance is formed by a pair of cross-coupled transistors connected so as to produce a negative resistive component at the terminals of the active impedance. Circuitry produces a degeneracy tuneable by a second signal in the cross-coupled pair, such that the cross-coupled pair produces a capacitive component tuneable based upon the second signal at the terminals of the active impedance. | 2012-01-12 |
20120007687 | Digital Amplitude Modulation - A transmitter using quadrature modulation includes a rectangular to polar converter for converting data symbols into a polar form, where each polar symbol has a magnitude signal and an angle signal. Digital phase modulation circuitry includes an all digital PLL circuit for generating a phase modulated RF carrier signal responsive to the angle signal frequency control word (FCW) and a carrier frequency FCW. A digitally controlled amplifier for amplifying the phase modulated signal is controlled by a digital amplitude control circuitry for controlling the gain of the digitally controlled amplifier responsive to the magnitude signal. | 2012-01-12 |
20120007688 | PRINTED CIRCUIT BOARD - A printed circuit board includes an insulation layer and a signal layer attached to the insulation layer. The signal layer includes a pair of differential transmission lines. Width W of each of the differential transmission lines is changed according to change of space S between the differential transmission lines, based on the following formula: | 2012-01-12 |
20120007689 | EMI TRAP USING MICROWAVE CIRCUIT - In one example embodiment, a transmitter comprises a first component coupled to receive a signal for transmission and a second component communicatively coupled to the first component to transmit the signal over a transmission medium. The transmitter further comprises a planar transmission line formed on a substrate and disposed between the first and second components to couple the signal from the first component to the second component. The planar transmission line includes a first transmission line element formed on the substrate and configured to suppress radiation of EMI at a predetermined frequency. | 2012-01-12 |
20120007690 | Adaptive Impedance Matching Network - An adjustable impedance matching network for providing an adjustable matching impedance (Rm) is presented. The matching network includes first and second impedance adjusting circuits. The first impedance adjusting circuit is adapted to adjust the value of an imaginary part of the matching impedance whilst substantially maintaining the value of a real part of the matching impedance based on frequency information frequency and a target reference value. The second impedance adjusting circuit is adapted to adjust the value of an imaginary part of the matching impedance to be substantially equal to zero based on the frequency information, so as to adjust the real part of the matching impedance to be substantially equal to the target reference value. | 2012-01-12 |
20120007691 | IMPEDANCE MATCHING APPARATUS AND METHOD OF ANTENNA CIRCUIT - An impedance matching apparatus is provided. The impedance matching apparatus includes a signal separation unit, an impedance detection unit, and an impedance matching unit. The signal separation unit separates a transmission and reception signal, and selectively passes a desired frequency corresponding to the transmission and reception signal. The impedance detection unit receives a signal outputted from the signal separation unit to detect first and second electric potentials between a plurality of impedances. The impedance matching unit compares the first and second electric potentials detected by the impedance detection unit to match the impedances. | 2012-01-12 |
20120007692 | IMPEDANCE MATCHING APPARATUS AND METHOD OF ANTENNA CIRCUIT - An impedance matching apparatus is provided. The impedance matching apparatus includes a signal separation unit, an impedance detection unit, and an impedance matching unit. The signal separation unit separates a transmission and reception signal, and selectively passes a desired frequency corresponding to the transmission and reception signal. The impedance detection unit includes a plurality of impedances, and detects first and second electric potentials between the impedances. The impedance matching unit compares the first and second electric potentials detected by the impedance detection unit, and changes a matching factor for one of the impedances included in the impedance detection unit to match the impedances according to the compared result. | 2012-01-12 |
20120007693 | DUAL IN-SITU MIXING FOR EXTENDED TUNING RANGE OF RESONATORS - A dual in-situ mixing approach for extended tuning range of resonators is described. In one embodiment, a dual in-situ mixing device tunes an input radio-frequency (RF) signal using a first mixer, a resonator body, and a second mixer. In one embodiment, the first mixer is coupled to receive the input RF signal and a local oscillator signal. The resonator body receives the output of the first mixer, and the second mixer is coupled to receive the output of the resonator body and the local oscillator signal to provide a tuned output RF signal as a function of the frequency of local oscillator signal. | 2012-01-12 |
20120007694 | ELECTROMAGNETIC FIELD STRENGTH REDUCING DEVICE, ELECTROMAGNETIC FIELD STRENGTH REDUCING METHOD, AND RADIO COMMUNICATION DEVICE - An electromagnetic field strength reducing device includes a high-frequency wave eliminator that eliminates a high frequency component from an electrical signal input from a signal source. An electrical signal line is disposed between the high-frequency wave eliminator and the electrical member so as to convey the electrical signal with the high frequency component eliminated to an electrical member. The device also includes a resonant-frequency regulator connected between the electrical signal line and ground to cause the electrical signal line to be resonant at a frequency used for radio communication. The electromagnetic field strength reducing device may be employed in a portable electronic device with a HAC standard radio frequency communication compliance requirement, and use a corresponding method to eliminate the high frequency component. | 2012-01-12 |
20120007695 | High-Frequency Swinging Choke - A high-frequency swinging choke has at least two rod cores arranged next to one another in the longitudinal direction. The rod cores each have at least one winding. The windings are connected in series. | 2012-01-12 |
20120007696 | COUPLED ACOUSTIC DEVICES - In one aspect of the invention, an acoustic device has a first coupled resonator filter (CRF) and a second CRF electrically coupled to one another in series. Each CRF has an input port, an output port, a bottom film bulk acoustic resonator (FBAR), an acoustic decoupler formed on the bottom FBAR, and a top FBAR formed on the acoustic decoupler. Each FBAR has a bottom electrode, a piezoelectric layer formed on the bottom electrode, and a top electrode formed on the piezoelectric layer. The decoupling layer capacitance arising between the two electrodes enclosing the acoustic decoupler in a CRF is configured to achieve targeted filter response. A compensating capacitance is introduced to improve the amplitude and phase imbalance performance of an unbalanced to balanced CRF by eliminating the existence of asymmetric port-to-ground or feedback capacitance at the balanced output port produced by the decoupling layer capacitance. | 2012-01-12 |