02nd week of 2013 patent applcation highlights part 14 |
Patent application number | Title | Published |
20130009235 | NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device includes first and second vertical channel layers generally protruding upwardly from a semiconductor substrate substantially in parallel; a first gate group configured to include a plurality of memory cell gates which are stacked substantially along the first vertical channel layer and are isolated from each other with an interlayer insulating layer interposed substantially between the memory cell gates; a second gate group configured to include a plurality of memory cell gates which are stacked substantially along the second vertical channel layer and are isolated from each other with the interlayer insulating layer interposed substantially between the memory cell gates; a pipe channel layer configured to couple the first and the second vertical channel layers; and a channel layer extension part generally extended from the pipe channel layer to the semiconductor substrate and configured to couple the pipe channel layer and the semiconductor substrate. | 2013-01-10 |
20130009236 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES USING DIRECT STRAPPING LINE CONNECTIONS - Memory devices include a plurality of elongate gate stacks extending in parallel on a substrate and at least one insulation region disposed in a trench between adjacent ones of the gate stacks. The at least one insulation region has linear first portions having a first width and widened second portions having a second width greater than the first width. A common source region is disposed in the substrate underlying the at least one insulation region. The devices further include respective conductive plugs passing through respective ones of the widened second portions of the at least one insulation region and electrically connected to the common source region and at least one strapping line disposed on the conductive plugs between the adjacent ones of the gate stacks and in direct contact with the conductive plugs. | 2013-01-10 |
20130009237 | CHARGE BALANCE SEMICONDUCTOR DEVICES WITH INCREASED MOBILITY STRUCTURES - Charge balanced semiconductor devices with increased mobility structures and methods for making and using such devices are described. The semiconductor devices contain a substrate heavily doped with a dopant of a first conductivity type, a strained region containing a strain dopant in an upper portion of the substrate, an epitaxial layer being lightly doped with a dopant of a first or second conductivity type on the strained region, a trench formed in the epitaxial layer with the trench containing a MOSFET structure having a drift region overlapping the strained region, a source layer contacting an upper surface of the epitaxial layer and an upper surface of the MOSFET structure, and a drain contacting a bottom portion of the substrate. Since the drift region of the MOSFET structure is formed from the strained region in the substrate, the mobility of the drift region is improved and allows higher current capacity for the trench MOSFET devices. Other embodiments are described. | 2013-01-10 |
20130009238 | ENHANCING SCHOTTKY BREAKDOWN VOLTAGE (BV) WITHOUT AFFECTING AN INTEGRATED MOSFET-SCHOTTKY DEVICE LAYOUT - This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region. | 2013-01-10 |
20130009239 | 3-D NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A 3-D non-volatile memory device includes a pipe gate having a first trench formed therein, word lines stacked in multiple layers over the pipe gate, second trenches coupled to the first trench and formed to penetrate the word lines, a first channel layer formed within the first trench, and second channel layers formed within the second trenches, respectively, and coupled to the first channel layer, wherein the width or depth of the first trench is smaller than the diameter of each of the second trenches. | 2013-01-10 |
20130009240 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a drain region of a first conductivity type formed on a semiconductor substrate; an element forming region that is provided on the drain region and that has a concave portion reaching the drain region; a gate electrode disposed in the concave portion; a superjunction structure portion that is disposed in the element forming region and that is formed by alternately arranging a drift layer of the first conductivity type penetrated by the concave portion and a resurf layer of a second conductivity type being in contact with the drift layer on the semiconductor substrate; and a base region of the second conductivity type that is disposed on the superjunction structure portion so as to be in contact with the drift layer in the element forming region, that is penetrated by the concave portion, and that faces the gate electrode with the gate insulating film therebetween. | 2013-01-10 |
20130009241 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a drain layer, a drift, a base, a source region, a plurality of gates provided on the drift region, the base, and the source region, and arranged in a manner spaced apart from each other, a first interlayer insulating film arranged between the plurality of gates on the source region, a gate interconnection film provided on the first interlayer insulating film and the gate, a second interlayer insulating film provided on the gate interconnection film, an inetconnection film provided on the second interlayer insulating film and connected in common to the source region, the interconnection film filling the contact hole provided between each of the gates in the second interlayer insulating film, the gate interconnection film and the first interlayer insulating film and an insulating film arranged between the gate interconnection film and the interconnection film in the contact hole. | 2013-01-10 |
20130009242 | MOS DEVICE WITH LOW INJECTION DIODE - A semiconductor device is formed on a semiconductor substrate. The device includes: a drain; an epitaxial layer overlaying the drain, wherein a drain region extends into the epitaxial layer; and an active region. The active region includes: a body disposed in the epitaxial layer, having a body top surface; a source embedded in the body, extending from the body top surface into the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and into the body; and an active region contact electrode disposed within the active region contact trench. A layer of body region separates the active region contact electrode from the epitaxial layer, and a low injection diode is formed below a body/drain junction. | 2013-01-10 |
20130009243 | LDMOS WITH ENHANCED SAFE OPERATING AREA (SOA) AND METHOD THEREFOR - A laterally double diffused metal oxide semiconductor device includes a well region having a first conductivity, a first carrier redistribution region having the first conductivity type, wherein the second well region is under the well region, and a highly doped buried layer under the second well region. The highly doped buried layer has the first conductivity type and has a dopant concentration less than that of the well region and less than that of the first carrier redistribution region, and the buried layer is tied to the first well region. In addition, a method for forming the laterally double diffused metal oxide semiconductor device, which may use epitaxial growth, is disclosed. | 2013-01-10 |
20130009244 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present application discloses an MOSFET and a method for manufacturing the same. The MOSFET comprises: a semiconductor substrate; a first insulation buried layer disposed on the semiconductor substrate; a back gate formed in a first semiconductor layer which is disposed on the first insulation buried layer; a second insulation buried layer disposed on the first semiconductor layer; source/drain regions formed in a second semiconductor layer which is disposed on the second insulation buried layer; a gate disposed on the second semiconductor layer; and electric connections to the source/drain regions, the gate and the back gate, wherein the back gate comprises first back gate regions of a first conductivity type which are disposed under the source/drain regions and a second back gate region of a second conductivity type which is disposed under a channel region, the first back gate regions adjoins the second back gate region, the first conductivity type is opposite to the second conductivity type, and the electric connection to the back gate comprise a conductive via contacted with one of the first back gate regions. The MOSFET, of any conductivity type, can have adjustable threshold voltage and reduced leakage current via the back gate between the source/drain regions by using the back gate in the form of a PNP junction or an NPN junction. | 2013-01-10 |
20130009245 | Semiconductor Devices with Low Junction Capacitances and Methods of Fabrication Thereof - Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric. | 2013-01-10 |
20130009246 | BULK FINFET WITH UNIFORM HEIGHT AND BOTTOM ISOLATION - A fin Field Effect Transistor (finFET), an array of finFETs, and methods of production thereof. The finFETs are provided on an insulating region, which may optionally contain dopants. Further, the finFETs are optionally capped with a pad. The finFETs provided in an array are of uniform height. | 2013-01-10 |
20130009247 | Method for Manufacturing Semiconductor Device - It is an object to form a conductive region in an insulating film without forming contact holes in the insulating film. A method is provided, in which an insulating film is formed over a first electrode over a substrate, a first region having many defects is formed at a first depth in the insulating film by adding first ions into the insulating film at a first accelerating voltage; a second region having many defects is formed at a second depth which is different from the first depth in the insulating film by adding second ions into the insulating film at a second accelerating voltage, a conductive material containing a metal element is formed over the first and second regions; and a conductive region which electrically connects the first electrode and the conductive material is formed in the insulating film by diffusing the metal element into the first and second regions. | 2013-01-10 |
20130009248 | INDEPENDENTLY ACCESSED DOUBLE-GATE AND TRI-GATE TRANSISTORS IN SAME PROCESS FLOW - A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member portions are removed from above the semiconductor body of the tri-gate device but not the I-gate device. This facilitates the formation of metallization on three sides of the tri-gate device, and the formation of independent gates for the I-gate device. | 2013-01-10 |
20130009249 | FINFET DEVICES AND METHODS OF MANUFACTURE - A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures. | 2013-01-10 |
20130009250 | DUMMY PATTERNS FOR IMPROVING WIDTH DEPENDENT DEVICE MISMATCH IN HIGH-K METAL GATE PROCESS - A semiconductor integrated circuit device including: a diffusion area defined by an isolation region in a substrate; a PMOS transistor comprising a metal gate and a high-k dielectric over the diffusion area and source/drain regions sandwiching the metal gate in a first direction; a plurality of dummy diffusion areas surrounding and spaced apart from the diffusion area; and a plurality of first dummy patterns at the two sides of the PMOS transistor in a second direction perpendicular to the first direction and between the dummy diffusion areas and the diffusion area. | 2013-01-10 |
20130009251 | OFFSET SCREEN FOR SHALLOW SOURCE/DRAIN EXTENSION IMPLANTS, AND PROCESSES AND INTEGRATED CIRCUITS - A process of integrated circuit manufacturing includes providing ( | 2013-01-10 |
20130009252 | High Voltage Bipolar Transistor with Trench Field Plate - A bipolar transistor structure includes an epitaxial layer on a semiconductor substrate, a bipolar transistor device formed in the epitaxial layer and a trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor device. The trench structure includes a field plate spaced apart from the epitaxial layer by an insulating material. The bipolar transistor structure further includes a base contact connected to a base of the bipolar transistor device, an emitter contact connected to an emitter of the bipolar transistor device and isolated from the base contact and an electrical connection between the emitter contact and the field plate. | 2013-01-10 |
20130009253 | POWER MOSFET WITH INTEGRATED GATE RESISTOR AND DIODE-CONNECTED MOSFET - A power MOSFET is formed in a semiconductor device with a parallel combination of a shunt resistor and a diode-connected MOSFET between a gate input node of the semiconductor device and a gate of the power MOSFET. A gate of the diode-connected MOSFET is connected to the gate of the power MOSFET. Source and drain nodes of the diode-connected MOSFET are connected to a source node of the power MOSFET through diodes. The drain node of the diode-connected MOSFET is connected to the gate input node of the semiconductor device. The source node of the diode-connected MOSFET is connected to the gate of the power MOSFET. The power MOSFET and the diode-connected MOSFET are integrated into the substrate of the semiconductor device so that the diode-connected MOSFET source and drain nodes are electrically isolated from the power MOSFET source node through a pn junction. | 2013-01-10 |
20130009254 | Electrical Device and Fabrication Method - An electrical device with a fin structure, a first section of the fin structure having a first width and a first height, a second section of the fin structure having a second width and a second height, wherein the first width is smaller than the second width and the first height is lower than the second height. | 2013-01-10 |
20130009255 | FIELD EFFECT TRANSISTOR WITH SUPPRESSED CORNER LEAKAGE THROUGH CHANNEL MATERIAL BAND-EDGE MODULATION, DESIGN STRUCTURE AND METHOD - Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs. | 2013-01-10 |
20130009256 | SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes a semiconductor layer of a first conductivity type, body regions of a second conductivity type plurally formed on a surface layer portion of the semiconductor layer at an interval, a source region of the first conductivity type formed on a surface layer portion of each body region, a gate insulating film provided on the semiconductor layer to extend between the body regions adjacent to each other, a gate electrode provided on the gate insulating film and opposed to the body regions, and a field relaxation portion provided between the body regions adjacent to each other for relaxing an electric field generated in the gate insulating film. | 2013-01-10 |
20130009257 | REPLACEMENT METAL GATE WITH A CONDUCTIVE METAL OXYNITRIDE LAYER - A disposable gate structure and a gate spacer are formed on a semiconductor substrate. A disposable gate material portion is removed and a high dielectric constant (high-k) gate dielectric layer and a metal nitride layer are formed in a gate cavity and over a planarization dielectric layer. The exposed surface portion of the metal nitride layer is converted into a metal oxynitride by a surface oxidation process that employs exposure to ozonated water or an oxidant-including solution. A conductive gate fill material is deposited in the gate cavity and planarized to provide a metal gate structure. Oxygen in the metal oxynitride diffuses, during a subsequent anneal process, into a high-k gate dielectric underneath to lower and stabilize the work function of the metal gate without significant change in the effective oxide thickness (EOT) of the high-k gate dielectric. | 2013-01-10 |
20130009258 | TUNNELING MAGNETORESISTANCE SENSOR - A tunneling magnetoresistance sensor including a substrate, an insulating layer, a tunneling magnetoresistance component and an electrode array is provided. The insulating layer is disposed on the substrate. The tunneling magnetoresistance component is embedded in the insulating layer. The electrode array is formed in a single metal layer and disposed in the insulating layer either below or above the TMR component. The electrode array includes a number of separate electrodes. The electrodes are electrically connected to the tunneling magnetoresistance component to form a current-in-plane tunneling conduction mode. The tunneling magnetoresistance sensor in this configuration can be manufactured with a reduced cost and maintain the high performance at the same time. | 2013-01-10 |
20130009259 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY USING THE SAME - According to one embodiment, a magnetoresistive element includes the following configuration. A first magnetic layer has an invariable magnetization. A second magnetic layer has a variable magnetization. A nonmagnetic layer is provided between the first and the second magnetic layers. The first magnetic layer has a structure in which first, second and third magnetic material films and a nonmagnetic material film are stacked. The first magnetic material film is provided in contact with the nonmagnetic layer, the nonmagnetic material film is provided in contact with the first magnetic material film, the second magnetic material film is provided in contact with the nonmagnetic material film, and the third magnetic material film is provided in contact with the second magnetic material film. The second magnetic material film has a Co concentration higher than that of the first magnetic material film. | 2013-01-10 |
20130009260 | Method And System For Providing A Magnetic Junction Using Half Metallic Ferromagnets - A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. At least one of the free layer and the pinned layer include at least one half-metal. | 2013-01-10 |
20130009261 | SPIN-CURRENT SWITCHABLE MAGNETIC MEMORY ELEMENT AND METHOD OF FABRICATING THE MEMORY ELEMENT - A spin-current switchable magnetic memory element includes a plurality of magnetic layers including a perpendicular magnetic anisotropy component, at least one of the plurality of magnetic layers including an alloy of a rare-earth metal and a transition metal, and at least one barrier layer formed adjacent to at least one of the plurality of magnetic layers. | 2013-01-10 |
20130009262 | NEUTRON DETECTION USING GD-LOADED OXIDE AND NITRIDE HETEROJUNCTION DIODES - Solid state neutron detection utilizing gadolinium as a neutron absorber is described. The new class of narrow-gap neutron-absorbing semiconducting materials, including Gd-doped HfO | 2013-01-10 |
20130009263 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - A solid-state imaging device includes a plurality of photoelectric conversion regions stacked at different depths within a semiconductor substrate of each pixel to photoelectrically convert light of different wavelength bands, and a discharge region formed between the photoelectric conversion regions adjacent to each other in a depth direction of the semiconductor substrate to discharge charges generated by photoelectric conversion in regions between the photoelectric conversion regions. | 2013-01-10 |
20130009264 | MOISTURE BARRIER - A moisture barrier, device or product having a moisture barrier or a method of fabricating a moisture barrier having at least a polymer layer, and interfacial layer, and a barrier layer. The polymer layer may be fabricated from any suitable polymer including, but not limited to, fluoropolymers such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), or ethylene-tetrafluoroethylene (ETFE). The interfacial layer may be formed by atomic layer deposition (ALD). In embodiments featuring an ALD interfacial layer, the deposited interfacial substance may be, but is not limited to, Al | 2013-01-10 |
20130009265 | PHOTON COUNTING UV-APD - An avalanche photodiode (APD) has a first semiconductor substrate having a first doping type. A first semiconductor layer is on top of the first semiconductor substrate. The first semiconductor layer is doped with the first doping type. A second epitaxial layer is on top of the first semiconductor layer. The second epitaxial layer is in-situ doped with the first doping type at a concentration higher than a concentration of the first doping type in the first semiconductor layer. A third epitaxial layer is on top of the second epitaxial layer. The third epitaxial layer is in-situ doped with a second doping type. The doping of the third epitaxial region forms a first p-n junction with the doping of the second epitaxial layer, wherein a carrier multiplication region includes the first p-n junction, and wherein the third epitaxial layer forms an absorption region for photons. A first implanted region is within the third epitaxial layer. The implanted region is doped with the second doping type. | 2013-01-10 |
20130009266 | PHOTODIODE ARRAY, METHOD FOR DETERMINING REFERENCE VOLTAGE, AND METHOD FOR DETERMINING RECOMMENDED OPERATING VOLTAGE - A reverse bias voltage is applied to a photodiode array provided with a plurality of avalanche photodiodes operated in Geiger mode and with quenching resistors connected in series to the respective avalanche photodiodes. Electric current is measured with change of the reverse bias voltage applied, and the reverse bias voltage at an inflection point in change of electric current measured is determined as a reference voltage. A voltage obtained by adding a predetermined value to the determined reference voltage is determined as a recommended operating voltage. | 2013-01-10 |
20130009267 | Providing Variable Cell Density and Sizes in a Radiation Detector - An apparatus and method to decrease light saturation in a photosensor array and increase detection efficiency uses a light distribution profile from a scintillator-photodetector geometry to configure the photosensor array to have a non-uniform sensor cell pattern, with varying cell density and/or varying cell size and shape. A solid-state photosensor such as a SiPM sensor having such a non-uniform cell structure realizes improved energy resolution, higher efficiency and increased signal linearity. In addition the non-uniform sensor cell array can have improved timing resolution due to improvements in statistical fluctuations. A particular embodiment for such photosensors is in PET medical imaging. | 2013-01-10 |
20130009268 | ALIGNMENT MARKS AND ALIGNMENT METHODS FOR ALIGNING BACKSIDE COMPONENTS TO FRONTSIDE COMPONENTS IN INTEGRATED CIRCUITS - An imaging system may include an imager integrated circuit with frontside components such as imaging pixels and backside components such as color filters and microlenses. The imager integrated circuit may be mounted to a carrier wafer with alignment marks. Bonding marks on the carrier wafer and the imager integrated circuit may be used to align the carrier wafer accurately to the imager integrated circuit. The alignment marks on the carrier wafer may be read, by fabrication equipment, to align backside components of the imager integrated circuit, such as color filters and microlenses, with backside components of the imager integrated circuit, such as photodiodes. | 2013-01-10 |
20130009269 | ALIGNMENT MARKS AND ALIGNMENT METHODS FOR ALIGNING BACKSIDE COMPONENTS TO FRONTSIDE COMPONENTS IN INTEGRATED CIRCUITS - An imaging system may include an imager integrated circuit with frontside components such as imaging pixels and backside components. The imager integrated circuit may also include mirrored alignment marks formed with the frontside components. As part of forming the backside components, the integrated circuit may be flipped over such that the mirrored alignment marks are no longer mirrored and are readable by alignment systems. The formerly mirrored alignment marks may be used by the alignment systems in aligning the backside components with the frontside components in the imager integrated circuit (e.g., in forming the backside components in alignment with the frontside components). | 2013-01-10 |
20130009270 | BACKSIDE ILLUMINATION SENSOR HAVING A BONDING PAD STRUCTURE AND METHOD OF MAKING THE SAME - The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure comprises a device substrate having a front side and a back side; an interconnect structure disposed on the front side of the device substrate; and a bonding pad connected to the interconnect structure. The bonding pad comprises a recessed region in a dielectric material layer; a dielectric mesa of the dielectric material layer interposed between the recessed region; and a metal layer disposed in the recessed region and on the dielectric mesa. | 2013-01-10 |
20130009271 | Schottky-Clamped Bipolar Transistor with Reduced Self Heating - The self heating of a high-performance bipolar transistor that is formed on a fully-isolated single-crystal silicon region of a silicon-on-insulator (SOI) structure is substantially reduced by forming a Schottky structure in the same fully-isolated single-crystal silicon region as the bipolar transistor is formed. | 2013-01-10 |
20130009272 | Semiconductor device - A semiconductor device includes a semiconductor substrate, a semiconductor element disposed in the semiconductor substrate, a guard ring surrounding at least a part of a periphery of the semiconductor element, a guard ring terminal coupled with the guard ring, a power supply line divided from a line coupled with a power source and applying a first constant voltage to the semiconductor element based on a voltage generated by the power source, a guard ring terminal fixation line divided from the line coupled with the power source and applying a second constant voltage to the guard ring terminal, a bypass capacitor disposed on the guard ring terminal fixation line so as to be coupled in parallel with the guard ring, and a resistor disposed on the guard ring terminal fixation line between the power source and the bypass capacitor. | 2013-01-10 |
20130009273 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating a semiconductor device are provided. The method for fabricating a semiconductor device includes forming an isolation layer over a semiconductor substrate defining first and second regions, etching the isolation layer at an edge of the first region to form a guard ring pattern, forming a buried guard ring filling the guard ring pattern, selectively etching the isolation layer of the first region to form a plurality of patterns, forming a plurality of conductive patterns in the respective patterns, and completely removing the isolation layer of the first region through a dip-out process. | 2013-01-10 |
20130009274 | MEMORY HAVING THREE-DIMENSIONAL STRUCTURE AND MANUFACTURING METHOD THEREOF - Provided are a memory having a 3-dimensional structure and a method of fabricating the same, by which high integration density can be obtained. A contact region connected to a word line is formed to extend from a cell region in a first direction. A plurality of step difference layers constituting the contact region are formed to have step differences in a second direction different from the first direction. Also, provided is a method of fabricating a nonvolatile memory by which step differences are formed in a direction substantially perpendicular to a direction in which active regions are aligned. An insulating layer and etching layers are sequentially formed. By performing a selective etching process and pattern transfer, step differences are formed in a direction perpendicular to a direction in which multilayered active layers are disposed. Furthermore, the etching layers are removed using a wet etching process, and an oxide-nitride-oxide (ONO) layer and conductive layers are provided on the multilayered active layers having exposed side surfaces to form cell transistors. Thus, a memory having a high integration density is fabricated. | 2013-01-10 |
20130009275 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND TERMINAL STRUCTURE OF STANDARD CELL - A semiconductor integrated circuit device includes a first standard cell and a second standard cell adjacent to the first standard cell in a first direction. An interconnect is provided to extend in the first direction to electrically connect input and output terminal portions, which extend in a second direction orthogonal to the first direction. The output terminal portion extends in a first sub-direction of the second direction from a region connected to the interconnect, but not in a second sub-direction opposite to the first sub-direction. The input terminal portion extends in a second sub-direction of the second direction from a region connected to the interconnect, but not in the first sub-direction. | 2013-01-10 |
20130009276 | METHODS OF FILLING ISOLATION TRENCHES FOR SEMICONDUCTOR DEVICES AND RESULTING STRUCTURES - The invention relates to a method and resulting structure that can substantially minimize and/or eliminate void formation during an isolation trench isolation fill process for typical trench shaped and goal-post shaped isolation regions. First, a thin thermal oxidation layer is grown on the sidewall of each trench and then a layer of polysilicon is deposited above the oxidation layer and oxidized. In one embodiment, a repeating series of polysilicon deposition and polysilicon oxidation steps are performed until each trench has been completely filled. In another embodiment, within a goal-post shaped trench having a wider upper portion and a narrower lower portion, the remainder of the upper wider trench portion is filled using a conventional high density plasma technique. | 2013-01-10 |
20130009277 | STRUCTURE AND METHOD FOR FORMING ISOLATION AND BURIED PLATE FOR TRENCH CAPACITOR - A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant. | 2013-01-10 |
20130009278 | STACKED SEMICONDUCTOR DEVICE INCLUDING ESD PROTECTION CIRCUITS AND METHOD OF FABRICATING THE STACKED SEMICONDUCTOR DEVICE - A stacked semiconductor device includes a first semiconductor die that has a front side electrically coupled to a substrate pad, the substrate pad is connected to an exterior, a backside of the first semiconductor die, a first integrated circuit, first ESDs, and TSVs, and the TSVs are coupled to the first integrated circuit and the first ESDs. A second semiconductor die is stacked above the backside of the first semiconductor die, the second semiconductor die includes a second integrated circuit that is electrically connected to the TSVs and second ESDs, and the second ESDs is electrically disconnected from the TSVs. The TSVs penetrate the first semiconductor die and extend to the backside of the first semiconductor die. | 2013-01-10 |
20130009279 | INTEGRATED CIRCUITS WITH CONFIGURABLE INDUCTORS - Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits. | 2013-01-10 |
20130009280 | BIPOLAR JUNCTION TRANSISTORS WITH A LINK REGION CONNECTING THE INTRINSIC AND EXTRINSIC BASES - Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together. | 2013-01-10 |
20130009281 | MULTILAYER SELECT DEVICES AND METHODS RELATED THERETO - Methods of forming and tuning a multilayer select device are provided, along with apparatus and systems which include them. As is broadly disclosed in the specification, one such method can include forming a first region having a first conductivity type; forming a second region having a second conductivity type and located adjacent to the first region; and forming a third region having the first conductivity type and located adjacent to the second region and, such that the first, second and third regions form a structure located between a first electrode and a second electrode, wherein each of the regions have a thickness configured to achieve a current density in a range from about 1×e | 2013-01-10 |
20130009282 | MICROELECTRONIC STRUCTURE INCLUDING AIR GAP - A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure. | 2013-01-10 |
20130009283 | METHODS TO REDUCE THE CRITICAL DIMENSION OF SEMICONDUCTOR DEVICES AND RELATED SEMICONDUCTOR DEVICES - A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of portions of a resist layer used as a mask. An intermediate layer is deposited over a target layer and the resist layer is formed over the intermediate layer. After patterning the resist layer, first spacers are formed on sidewalls of remaining portions of the resist layer, masking portions of the intermediate layer. Second spacers are formed on sidewalls of the portions of the intermediate layer. After removing the portions of the intermediate layer, the second spacers are used as a mask to form the features on the target layer. Integrated circuit devices are also disclosed. | 2013-01-10 |
20130009284 | SUBSTRATE DIVIDING METHOD - A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate | 2013-01-10 |
20130009285 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR WAFER - A semiconductor wafer includes at least one chip formed on a substrate, and a scribe line region surrounding the chip. The chip includes a device formation region, and a chip boundary region surrounding the device formation region and formed between the device formation region and the scribe line region. The chip boundary region includes a guard ring structure which physically separates the device formation region from the scribe line region. The guard ring structure includes a signal transfer element which transfers an electric signal between the device formation region and the scribe line region. | 2013-01-10 |
20130009286 | SEMICONDUCTOR CHIP AND FLIP-CHIP PACKAGE COMPRISING THE SAME - A semiconductor chip includes stress-relief to mitigate the effects of differences in coefficients of thermal expansion (CTE) between a printed circuit board (PCB) and a semiconductor chip and a flip-chip package including the semiconductor chip. The semiconductor chip includes a stress-relief buffer coupling a bump and a semiconductor chip pad. | 2013-01-10 |
20130009287 | ACCURATE DEPOSITION OF NANO-OBJECTS ON A SURFACE - The invention notably concerns a method for depositing nano-objects on a surface. The method includes: providing a substrate with surface patterns on one face thereof; providing a transfer layer on said face of the substrate; functionalizing areas on a surface of the transfer layer parallel to said face of the substrate, at locations defined with respect to said surface patterns, such as to exhibit enhanced binding interactions with nano-objects; depositing nano-objects and letting them get captured at the functionalized areas; and thinning down the transfer layer by energetic stimulation to decompose the polymer into evaporating units, until the nano-objects reach the surface of the substrate. The invention also provides a semiconductor device which includes a substrate and nano-objects accurately disposed on the substrate. | 2013-01-10 |
20130009288 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer comprises metal interconnects therein; forming a top metal layer on the dielectric layer; and forming a passivation layer on the top metal layer through high-density plasma chemical vapor deposition (HDPCVD) process. | 2013-01-10 |
20130009289 | SEMICONDUCTOR DEVICE - An object of the present invention is providing a semiconductor device that is capable of improving the reliability of a semiconductor element and enhancing the mechanical strength without suppressing the scale of a circuit. The semiconductor device includes an integrated circuit sandwiched between first and second sealing films, an antenna electrically connected to the integrated circuit, the first sealing film sandwiched between a substrate and the integrated circuit, which includes a plurality of first insulating films and at least one second insulating film sandwiched therebetween, the second sealing film including a plurality of third insulating films and at least one fourth insulating film sandwiched therebetween. The second insulating film has lower stress than the first insulting film and the fourth insulating film has lower stress than the third insulating film. The first and third insulating films are inorganic insulating films. | 2013-01-10 |
20130009290 | POWER MODULE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is a power module package including: a first substrate; a second substrate having a pad for connection to the first substrate formed on one side or both sides of one surface thereof and having external connection terminals for connection to the outside formed on the other surface thereof; and a lead frame having one end bonded to the first substrate and the other end bonded to the pad of the second substrate to thereby vertically connect the first and second substrates to each other. | 2013-01-10 |
20130009291 | POWER MODULE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a power module package and a method for manufacturing the same. The power module package includes: a base substrate having grooves formed between a plurality of semiconductor device mounting areas; semiconductor devices mounted on the semiconductor device mounting areas of the base substrate; and a molding formed on the base substrate and in inner portions of the grooves. | 2013-01-10 |
20130009292 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a first frame, a semiconductor element fixed to the first frame, a second frame, a third frame and a resin package. The second frame faces the first frame and is away from the first frame, the second frame being electrically connected to the semiconductor element via a metal wire. The resin package covers the semiconductor element, the first frame, and the second frame. The first frame and the second frame are exposed in one major surface of the resin package. The third frame juxtaposed to one of the first frame and the second frame, the third frame being continuously exposed from the major surface of the resin package to a side surface in contact with the major surface. | 2013-01-10 |
20130009293 | PACKAGING SUBSTRATE AND METHOD OF FABRICATING THE SAME - A packaging substrate includes a first dielectric layer; a plurality of first conductive pads embedded in and exposed from a first surface of the first dielectric layer; a first circuit layer embedded in and exposed from a second surface of the first dielectric layer; a plurality of first metal bumps disposed in the first dielectric layer, each of the first metal bumps having a first end embedded in the first circuit layer and a second end opposing the first end and disposed on one of the first conductive pads, a conductive seedlayer being disposed between the first circuit layer and the first dielectric layer and between the first circuit layer and the first metal bump; a built-up structure disposed on the first circuit layer and the first dielectric layer; and a plurality of second conductive pads disposed on the built-up structure. The packaging substrate has an over-warpage problem improved. | 2013-01-10 |
20130009294 | MULTI-CHIP PACKAGE HAVING LEADERFRAME-TYPE CONTACT FINGERS - Disclosed is a multi-chip package having leadframe-type contact fingers, primarily comprising a leadframe, a non-conductive tape, a first chip and a second chip disposed on the first chip. The leadframe includes a die paddle on which the first chip is disposed and a plurality of first contact fingers, moreover, at least a second contact finger is integrally extended from the die paddle and is located among the first contact fingers so that the first and second contact fingers are arranged in a row. The non-conductive tape is attached onto the first and second contact fingers conforming to the arranging row of the first contact fingers so that the second contact finger is mechanically fastened with the first contact fingers. An encapsulant encapsulates the first chip, the second chip and the non-conductive tape with a plated metal layer formed on the bottom surfaces of the first and second contact fingers and exposed from the encapsulant. Accordingly, delamination of the conventional substrate or a die paddle can be avoided and the amount of tie bars used can be decreased. | 2013-01-10 |
20130009295 | Semiconductor Device Including a Contact Clip Having Protrusions and Manufacturing Thereof - A semiconductor device includes a leadframe with a die pad and a first lead, a semiconductor chip with a first electrode, and a contact clip with a first contact area and a second contact area. The semiconductor chip is placed over the die pad. The first contact area is placed over the first lead and the second contact area is placed over the first electrode of the semiconductor chip. A plurality of protrusions extends from each of the first and second contact areas and each of the protrusions has a height of at least 5 μm. | 2013-01-10 |
20130009296 | SEMICONDUCTOR DEVICE PACKAGE HAVING FEATURES FORMED BY STAMPING - Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. The lead frame can include a plurality of terminals with stamped features at edges of the terminals. The stamped features can include flattened portions that are thinner than other portions of the terminals and extend laterally beyond the edges of the terminals. Such stamped features can help mechanically interlock the terminals with the plastic molding of the package body. The stamped features can include patterns and/or other features that may further increase interlocking between the terminals and the package body. | 2013-01-10 |
20130009297 | SEMICONDUCTOR DEVICE PACKAGE HAVING CONFIGURABLE LEAD FRAME FINGERS - Embodiments of the present invention relate to the use of configurable lead frame fingers in a semiconductor device package. More specifically, the lead frame of a device package can include a plurality of fingers used to support and provide electrical contact to the die. The die can include a plurality of contacts that comprise a series of parallel columns located a certain distance from one another, and the fingers of the lead frame can be configured to align with the contacts. The lead frame can have multiple terminals, each with one or more fingers and pins. As such, each lead frame configuration may be utilized with different configurations of die. | 2013-01-10 |
20130009298 | SEMICONDUCTOR MODULE - A semiconductor module includes: an insulating plate; a plurality of metal patterns formed on the insulating plate and spaced apart from each other; a power device chip solder-joined on one the metal pattern; a lead frame solder-joined on the metal pattern to which the power device chip is not solder-joined, and on the power device chip; an external main electrode provided to an outer casing, and joined by wire bonding to the lead frame above the metal pattern to which the power device chip is not joined; and a sealing resin formed by potting to seal the power device chip, the lead frame, and the metal patterns. | 2013-01-10 |
20130009299 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion. | 2013-01-10 |
20130009300 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A dug portion ( | 2013-01-10 |
20130009301 | MAGNESIUM-BASED COMPOSITE MEMBER, HEAT RADIATION MEMBER, AND SEMICONDUCTOR DEVICE - A magnesium-based composite member is provided with a through hole through which a fastening member for attachment to a fixing target is to be inserted. A substrate is provided with a substrate hole through which the fastening member is to be inserted, and made of a composite material which is a composite of SiC and a matrix metal which is any of magnesium and a magnesium alloy. A receiving portion is attached to the substrate and made of a metal material different from the matrix metal. The receiving portion is provided with a receiving portion hole through which the fastening member is to be inserted, and at least a part of an inner circumferential surface of the through hole is formed from an inner circumferential surface of the receiving portion hole. | 2013-01-10 |
20130009302 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device ( | 2013-01-10 |
20130009303 | Connecting Function Chips To A Package To Form Package-On-Package - A package-on-package (PoP) comprises a substrate with a plurality of substrate traces, a first function chip on top of the substrate connected to the substrate by a plurality of bond-on-trace connections, and a second function chip on top of the first function chip, directly connected to the substrate. Another package-on-package (PoP) comprises: a substrate with a plurality of substrate traces, a first function chip on top of the substrate connected to the substrate by a plurality of solder mask defined (SMD) connections formed on SMD bonding pads connected to solder bumps, and a second function chip on top of the first function chip, directly connected to the substrate by a plurality of bond-on-trace connections. | 2013-01-10 |
20130009304 | CHIP-STACKED SEMICONDUCTOR PACKAGE - A chip-stacked semiconductor package including a stacked chip structure including a plurality of separate chips stacked on each other; a flexible circuit substrate having the stacked chip structure mounted on a first side of the flexible circuit substrate in a first region of the flexible circuit substrate, and being electrically connected to at least one of the plurality of separate chips of the stacked chip structure by folding a second region of the flexible circuit substrate; a sealing portion sealing the stacked chip structure and the flexible circuit substrate; and an external connecting terminal on a second side of the flexible circuit substrate. | 2013-01-10 |
20130009305 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a first via and a first interconnect supplying a high current is provided in which a first surface having the first via and the first interconnect is planar. The semiconductor device has a first via penetrating a first substrate from a first surface of the first substrate and a first interconnect buried in the first surface of the first substrate and connected with one end of at least one first via. The first via has an inclined portion where an angle formed between a lateral side of the first via and the bottom of the first via is larger than an angle formed between a lateral side of the first interconnect and the bottom of the first interconnect. | 2013-01-10 |
20130009306 | PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF - A packaging substrate includes a first dielectric layer, a first circuit layer, a first metal bump, and a built-up structure. The first metal bump and the first circuit layer are embedded in and exposed from two surfaces of the first dielectric layer. The end of the first metal bump is embedded in the first circuit layer and between the first circuit layer and the first dielectric layer. In addition, a conductive seedlayer is disposed between the first circuit layer and the first metal bump. The built-up structure is disposed on the first circuit layer and the first dielectric layer. The outmost layer of the built-up structure has a plurality of conductive pads. Compared to the prior art, the present invention can effectively improve the warpage problem of the conventional packaging substrate. | 2013-01-10 |
20130009307 | Forming Wafer-Level Chip Scale Package Structures with Reduced number of Seed Layers - A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed. | 2013-01-10 |
20130009308 | SEMICONDUCTOR STACK PACKAGE APPARATUS - A semiconductor stack package apparatus includes an upper semiconductor package and a lower semiconductor package. The upper semiconductor chip includes a chip pad, an upper substrate including a substrate pad formed on a top surface of the upper substrate and an upper ball land formed on a bottom surface of the upper substrate and attached to an intermediate solder ball, and a wire connecting the chip pad and the substrate pad. The lower semiconductor package includes a lower semiconductor chip including a bump, and a lower substrate including a bump land formed on a top surface of the lower substrate in an area corresponding to the bump, an intermediate ball land formed on the top surface of the lower substrate in an area corresponding to the intermediate solder ball, and a lower ball land formed on a bottom surface of the lower substrate and attached to a lower solder ball. | 2013-01-10 |
20130009309 | CONDUCTIVE CHIP DISPOSED ON LEAD SEMICONDUCTOR PACKAGE AND METHODS OF MAKING THE SAME - In one implementation, an apparatus includes a semiconductor die, a lead, a non-conductive epoxy, and a conductive epoxy. The semiconductor die includes an upper surface and a lower surface opposite the upper surface. The lead is electrically coupled to the upper surface of the semiconductor die. The non-conductive epoxy is disposed on a first portion of the lower surface of the semiconductor die. The conductive epoxy is disposed on a second portion of the lower surface of the semiconductor die. In some implementations, a conductive wire extends from the lead to the upper surface of the semiconductor die to electrically couple the lead to the upper surface of the semiconductor die. | 2013-01-10 |
20130009310 | SEMICONDUCTOR DEVICE STRUCTURES AND COMPOSITIONS FOR FORMING SAME - A method of removing a metal nitride material is disclosed. The method comprises forming a semiconductor device structure comprising an exposed metal material and an exposed metal nitride material. The semiconductor device structure is subjected to a solution comprising water, ozone, and at least one additive to remove the exposed metal nitride material at a substantially greater rate than the exposed metal material. Resulting semiconductor device structures are also disclosed, as are compositions used to form the semiconductor device structures. | 2013-01-10 |
20130009311 | SEMICONDUCTOR CARRIER, PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes: a first encapsulant having tapered through holes each having a wide top and a narrow bottom; tapered electrical contacts disposed in the tapered through holes; circuits disposed on a top surface of the first encapsulant and each having one end connecting one of the electrical contacts and the other end having a bonding pad disposed thereon such that the bonding pads are circumferentially arranged to define a die attach area on the top surface of the first encapsulant. As such, a semiconductor chip can be disposed on the top surface of the first encapsulant in the die attach area and electrically connected to the bonding pads through conductive elements, and further a second encapsulant encapsulates the semiconductor chip, the conductive elements, the circuits and the first encapsulant so as to prevent falling off of the electrical contacts and reduce the length of the conductive elements. | 2013-01-10 |
20130009312 | INTERCONNECT STRUCTURE FABRICATED WITHOUT DRY PLASMA ETCH PROCESSING - An interconnect structure within a microelectronic structure and a method for fabricating the interconnect structure within the microelectronic structure use a developable bottom anti-reflective coating layer and at least one imageable inter-level dielectric layer located thereupon over a substrate that includes a base dielectric layer and a first conductor layer located and formed embedded within the base dielectric layer. Incident to use of the developable bottom anti-reflective coating layer and the at least one imageable inter-level dielectric layer, an aperture, such as but not limited to a dual damascene aperture, may be formed through the at least one imageable inter-level dielectric layer and the developable anti-reflective coating layer to expose a capping layer located and formed upon the first conductor layer, absent use of a dry plasma etch method when forming the interconnect structure within the microelectronic structure. | 2013-01-10 |
20130009313 | SEMICONDUCTOR DEVICE PACKAGES WITH SOLDER JOINT ENHANCEMENT ELEMENT AND RELATED METHODS - A semiconductor device package including a substrate, first and second solder joints, a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements. | 2013-01-10 |
20130009314 | TEST CIRCUIT, INTEGRATED CIRCUIT, AND TEST CIRCUIT LAYOUT METHOD - A test circuit includes a substrate, a wiring section having a plurality of pieces of wiring, and a device-under-test section formed on the substrate, and having a device-under-test main body and a plurality of connecting electrodes for establishing connection between the main body and the plurality of pieces of wiring, an extending direction of a straight line connecting a position of a center of rotation in a plane of pattern formation of the main body and each electrodes being inclined at a predetermined angle to an extending direction of the pieces of wiring, and the connecting electrodes being arranged at positions such that connection relation between the electrodes and the plurality of pieces of wiring is maintained even when the main body and the electrodes are rotated about the position of the center of rotation by 90 degrees relative to the wiring section in the plane of the pattern formation. | 2013-01-10 |
20130009315 | INTERCONNECT STRUCTURES WITH ENGINEERED DIELECTRICS WITH NANOCOLUMNAR POROSITY - A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described. | 2013-01-10 |
20130009316 | Apparatus and Methods for Dicing Interposer Assembly - Methods and apparatus for performing dicing of die on wafer interposers. Methods are disclosed that include receiving an interposer assembly including one or more integrated circuit dies mounted on a die side of an interposer substrate and having scribe areas defined in spaces between the integrated circuit dies, the interposer having an opposite side for receiving external connectors; mounting the die side of the interposer assembly to a tape assembly, the tape assembly comprising an adhesive tape and preformed spacers disposed between and filling gaps between the integrated circuit dies; and sawing the interposer assembly by cutting the opposite side of the interposer in the scribe areas to make cuts through the interposer, the cuts separating the interposer into one or more die on wafer assemblies. Apparatuses are disclosed for use with the methods. | 2013-01-10 |
20130009317 | FORMING GROUNDED THROUGH-SILICON VIAS IN A SEMICONDUCTOR SUBSTRATE - A method of forming an interposer includes providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface; forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate; forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and forming an interconnect structure in the ILI) layer, the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate. | 2013-01-10 |
20130009318 | STACKED MEMORY LAYERS HAVING MULTIPLE ORIENTATIONS AND THROUGH-LAYER INTERCONNECTS - In one embodiment, an apparatus includes a first memory layer oriented in a first planar orientation, a second memory layer oriented in a second planar orientation, a third memory layer oriented in the first planar orientation; and a connector that is connected to the first memory layer at an electrical contact of the first memory layer and to the third memory layer at an electrical contact of the third memory layer, where the connector is unconnected to the second memory layer. At least one of the electrical contact of the first memory layer and the electrical contact of the third memory layer comprises a through-layer via. The second planar orientation is angularly offset a predetermined number of degrees from the first planar orientation. | 2013-01-10 |
20130009319 | Apparatus and Methods for Forming Through Vias - Methods and apparatus for forming through vias in an integrated circuit package are disclosed. An apparatus is disclosed, having a substrate having one or more bond pad terminals for receiving electrical connections on at least one surface; an encapsulation layer covering the at least one surface of the substrate and having a first thickness; a plurality of through vias extending through the encapsulation layer and positioned in correspondence with at least one of the one or more bond pad terminals; conductor material disposed within the plurality of through vias to form electrical connectors within the plurality of through vias; and at least one external terminal disposed on a surface of the encapsulation layer, electrically coupled to one of the one or more bond pad terminals by an electrical connector in at least one of the plurality of through vias. Package arrangements and methods for the through vias are disclosed. | 2013-01-10 |
20130009320 | Semiconductor package and method of manufacturing the same - There are provided a semiconductor package including an antenna formed integrally therewith, and a method of manufacturing the same. The semiconductor package includes: a semiconductor chip; a sealing part sealing the semiconductor chip; a substrate part formed on at least one surface of the sealing part; and an antenna part formed on the sealing part or the substrate part and electrically connected to the semiconductor chip. | 2013-01-10 |
20130009321 | SEMICONDUCTOR DEVICE, FABRICATION METHOD FOR A SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS - Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate. | 2013-01-10 |
20130009322 | Through-Substrate Via Having a Strip-Shaped Through-Hole Signal Conductor - A TSV structure suitable for high speed signal transmission includes a metal strip portion that extends through a long and small diameter hole in a substrate. In one example, the metal strip portion is formed by laser ablating away portions of a metal sheath that lines a cylindrical sidewall of the hole, thereby leaving a longitudinal section of metal that is the metal strip portion. A second metal strip portion, that extends in a direction perpendicular to the hole axis, is contiguous with the metal strip portion that extends through the hole such that the two metal strip portions together form a single metal strip. Throughout its length, the single metal strip has a uniform width and thickness and therefore can have a controlled and uniform impedance. In some embodiments, multiple metal strips pass through the same TSV hole. In some embodiments, the structure is a coaxial TSV. | 2013-01-10 |
20130009323 | INTERCONNECT STRUCTURE AND METHOD OF FABRICATING - An interconnect structure is provided which comprises a semiconductor substrate; a patterned and cured photoresist wherein the photoresist contains a low k dielectric substitutent and contains a fortification layer on its top and sidewall surfaces forming vias or trenches; and a conductive fill material in the vias or trenches. Also provided is a method for fabricating an interconnect structure which comprises depositing a photoresist onto a semiconductor substrate, wherein the photoresist contains a low k dielectric constituent; imagewise exposing the photoresist to actinic radiation; then forming a pattern of vias or trenches in the photoresist; surface fortifying the pattern of vias or trenches proving a fortification layer on the top and sidewalls of the vias or trenches; curing the pattern of vias or trenches thereby converting the photoresist into a dielectric; and filling the vias and trenches with a conductive fill material. | 2013-01-10 |
20130009324 | UNIVERSAL INTER-LAYER INTERCONNECT FOR MULTI-LAYER SEMICONDUCTOR STACKS - An apparatus, program product and method facilitate the design of a multi-layer circuit arrangement incorporating a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers. | 2013-01-10 |
20130009325 | SEMICONDUCTOR ELEMENT-EMBEDDED SUBSTRATE, AND METHOD OF MANUFACTURING THE SUBSTRATE - A semiconductor element-embedded substrate includes a semiconductor element; a chip component; a peripheral insulating layer covering at least the outer circumferential side surfaces thereof; an upper surface-side wiring line provided on the upper surface side of the substrate; and a lower surface-side wiring line provided on the lower surface side of the substrate. The built-in semiconductor element includes a terminal on the upper surface side thereof, and this terminal is electrically connected to the upper surface-side wiring line. The built-in chip component includes an upper surface-side terminal electrically connected to the upper surface-side wiring line; a lower surface-side terminal electrically connected to the lower surface-side wiring line; | 2013-01-10 |
20130009326 | MANUFACTURING METHOD OF CHIP PACKAGE WITH COPLANARITY CONTROLLING FEATURE - A chip package includes a substrate, an integrated circuit proximate a top surface of the substrate, and a cap comprising encapsulant that encapsulates the integrated circuit on at least a portion of the top surface of the substrate. The chip package further includes at least one extension feature positioned on at least a portion of the top surface of the substrate. The at least one extension feature also comprises the encapsulant and extends from the cap to a perimeter of the substrate. | 2013-01-10 |
20130009327 | RESIN COMPOSITION FOR SEMICONDUCTOR ENCAPSULATION, AND SEMICONDUCTOR DEVICE USING SAME - Disclosed is a resin composition for semiconductor encapsulation, containing an epoxy resin (A), a curing agent (B), and an inorganic filler material (C), the epoxy resin (A) including an epoxy resin (A-1) represented by formula (1), and the epoxy resin (A-1) containing a component represented by the formula (1) in which n≧1, and a component (a1) represented by the formula (1) in which n=0 (wherein in the formula (1), R1 represents a hydrocarbon group having 1 to 6 carbon atoms; R2 represents a hydrocarbon group having 1 to 6 carbon atoms, or an aromatic hydrocarbon group having 6 to 14 carbon atoms, while R1s and R2s may be respectively identical with or different from each other; a represents an integer from 0 to 4; b represents an integer from 0 to 4; and n represents an integer of 0 or larger). | 2013-01-10 |
20130009328 | ALIGNMENT MARK, SEMICONDUCTOR HAVING THE ALIGNMENT MARK, AND FABRICATING METHOD OF THE ALIGNMENT MARK - An alignment mark with a sheet or a layer of copper, which is compatible with a copper process, is provided herein. In one embodiment, a whole sheet of copper (Cu) is used as a background of the alignment mark, by which the color of the background of the alignment mark is stable and reliable. By such arrangement, the contrast between colors of a main pattern and the background of the alignment mark can be significantly improved, without considering a problem the homogeneity of manufacturing process. If the alignment mark is applied for manufacturing of a display, a recognition successful rate of alignment to attach an integrated circuit (IC) to a panel of the display is increased. | 2013-01-10 |
20130009329 | Precision Control of Web Material having Micro-replicated Lens Array - A manufacturing system includes a sensing system that provides high-resolution feedback for web guiding and tension control. The system may be especially useful for web material that is manufactured to include micro-replicated structures with micron size scale. A micro-replication station forms a pattern of micro-replicated lenses on a web material. The sensing system illuminates a measurement area on the web material and detects an angular distribution of light exiting a set of the micro-replicated lenses within the first measurement area. A control system that adjusts at least one process control parameter of the transport system based on the detected angular distribution. | 2013-01-10 |
20130009330 | Spray Drying Vancomycin - A method and formulation for preparing spray dried vancomycin. In various embodiment, the formulation includes vancomycin HCl (10-20%) and one or more of the following PEG (0-5%), mannitol (0-5%), ethanol (0-10%), and a citrate buffer. Spray dried vancomycin has favorable reconstitution times and water content. | 2013-01-10 |
20130009331 | PROCESS FOR PRODUCTION OF COMPOSITE FINE PARTICLES WITH HETEROGENEOUS SURFACES - Provided is a process for production of composite fine particles with heterogeneous surfaces. The process ensures a high productivity and enables a voluntary control of particle diameters. Further, the process imposes no restrictions on heterogeneous substances added for functional expression, and allows a heterogeneous substance to be encapsulated in central portions of composite fine particle spheres. A composite film obtained by laminating two or more kinds of films is cut into minute pieces, followed by melting the same to obtain spherical minute pieces. Particularly, liquid films are separately formed with two or more kinds of liquids containing polymerizable monomers. Further, two or more kinds of films can thereby be obtained through polymerization. The two or more kinds of films thus obtained are then laminated to further allow polymerization to take place, thus obtaining the composite film. | 2013-01-10 |
20130009332 | METHOD FOR PRODUCING AN SMC MULTI-LAYER COMPONENT - Method for producing an SMC multi-layer component in a production process. The component has a sandwich structure. At least one foam material layer ( | 2013-01-10 |
20130009333 | PROCESS FOR MAKING NONWOVEN WEBS - A nonwoven web comprising bicomponent fibers. The fibers have continuous phases each of a first polyarylene sulfide (PAS) component and a polymer component. The polymer component may also be a second polyarylene sulfide. The first polyarylene sulfide component contains a tin or a zinc additive or both, and the first polyarylene sulfide component of any given fiber is at least partially exposed to the external surface of that fiber. | 2013-01-10 |
20130009334 | SEMICONDUCTIVE RUBBER BELT, AND PROCESS FOR PRODUCING THE SAME - An object of the present invention is to provide a semiconductive rubber belt wherein a variation in the electric resistance is decreased, in particular, in the belt circumferential direction so that high-quality images can be formed, and a process for producing the same. In order to achieve the object, in a case where on any single straight line extended in the belt circumferential direction, the maximum value of the molecular orientation ratio correction value MOR-C of the semiconductive rubber belt, the minimum value thereof, and the average thereof are set to satisfy a specified relationship. | 2013-01-10 |