02nd week of 2015 patent applcation highlights part 12 |
Patent application number | Title | Published |
20150008473 | LED LIGHT - Provided is an LED light which may include a base plate, an LED module disposed under the base plate, a plurality of heat pipes provided over the base plate, and a plurality of heat dissipation fins provided over the base plate. The plurality of heat pipes may include a first portion thermally coupled to the base plate and a second portion that extends from the first portion. The plurality of heat dissipation fins may be spaced apart from each other and thermally coupled to the second portion of the heat pipes to dissipate heat from the LED module. The LED light may include an upper bracket provided over the plurality of heat dissipation fins and fastened to a hanger, and a plurality of studs that connect the base plate to the upper bracket. | 2015-01-08 |
20150008474 | OPTO-ELECTRIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - An opto-electric device includes an opto-electric layer structure having an anode and a cathode layer and an opto-electric layer arranged between the anode and cathode layers, and having a light-transmission side. A dual electrically conductive layer structure is arranged at a side of the opto-electric layer structure opposite the light-transmission side, the dual electrically conductive layer structure having a first and a second electrically conductive layer mutually insulated by a first electrically insulating layer. A second electrically insulating layer is arranged between the light emitting layer structure and the dual electrically conductive layer structure, wherein the first electrically conductive layer is electrically connected by at least a first transverse electrical conductor with the anode layer and the second electrically conductive layer is electrically connected by at least a second transverse electrical conductor with the cathode layer. | 2015-01-08 |
20150008475 | LIGHT EMMITING DIODE CHIP - A light emitting diode (LED) chip including a first type semiconductor layer, an light-emitting layer, a second type semiconductor layer, a current blocking layer, a transparent conductive layer and an electrode is provided. The light-emitting layer is disposed on the first type semiconductor layer. The second type semiconductor layer is disposed on the light-emitting layer. The current blocking layer is disposed on the second type semiconductor layer. The transparent conductive layer is disposed on the second type semiconductor layer and covered the current blocking layer. The electrode is disposed on the transparent conductive layer corresponding to the current blocking layer. The current blocking layer and the electrode respectively have a first width and a second width in a cross section view, and the first width of the current blocking layer is larger than the second width of the electrode. | 2015-01-08 |
20150008476 | SEMICONDUCTOR DEVICES AND ARRANGEMENTS - A semiconductor device including: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type adjacent to the first region; third and fourth semiconductor regions of the second conductivity type over or at least partially within the first semiconductor region; a fifth semiconductor region of the first conductivity type between the third and fourth semiconductor regions; a first gate over the fifth semiconductor region; sixth and seventh semiconductor regions of the first conductivity type over or at least partially within the second semiconductor region; an eighth semiconductor region of the second conductivity type between the sixth and seventh semiconductor regions; a second gate over the eighth semiconductor region; the third and seventh semiconductor regions coupled to first and second regions of the first gate, respectively, and the fourth and sixth semiconductor regions coupled to first and second regions of the second gate, respectively. | 2015-01-08 |
20150008477 | IGBT Having an Emitter Region with First and Second Doping Regions - An IGBT includes a semiconductor substrate, a source metallization and an emitter metallization. The semiconductor substrate includes a source region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, and an emitter region of the second conductivity type. The source metallization is in contact with the source region. The emitter metallization is in contact with the emitter region. The emitter region includes a first doping region of the second conductivity type forming an ohmic contact with the emitter metallization and a second doping region of the second conductivity type forming a non-ohmic contact with the emitter metallization. | 2015-01-08 |
20150008478 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A manufacturing method of a semiconductor device includes applying at least one of a particle ray and a radial ray to a surface of a semiconductor substrate on which a transistor including a gate insulation film and a gate electrode has been formed adjacent to the surface, and annealing the semiconductor substrate for recovering a crystal defect contained in the gate insulation film and the gate electrode, after the applying. Further, the manufacturing method includes pre-annealing for reducing a content of a hydrogen molecule and a water molecule contained in the gate insulation film and the gate electrode to a predetermined concentration, before the applying. In the semiconductor device manufactured by this method, a concentration of thermally stable defect existing in the gate insulation film is reduced to a predetermined concentration. | 2015-01-08 |
20150008479 | IGBT AND IGBT MANUFACTURING METHOD - An IGBT manufacturing method is provided. The IGBT has an n-type emitter region, a p-type top body region, an n-type intermediate region, a p-type bottom body region, an n-type drift region, a p-type collector region, trenches penetrating the emitter region, the top body region, the intermediate region and the bottom body region from an upper surface of a semiconductor substrate and reaching the drift region, and gate electrodes formed in the trenches. The method includes forming the trenches on the upper surface of the semiconductor substrate, forming the insulating film in the trenches, forming an electrode layer on the semiconductor substrate and in the trenches after forming the insulating film, planarizing an upper surface of the electrode layer, and implanting n-type impurities to a depth of the intermediate region from the upper surface side of the semiconductor substrate after planarizing the upper surface of the electrode layer. | 2015-01-08 |
20150008480 | SEMICONDUCTOR COMPONENT - A semiconductor component is disclosed. One embodiment provides a semiconductor body having a cell region with at least one zone of a first conduction type and at least one zone of a second conduction type in a rear side. A drift zone of the first conduction type in the cell region is provided. The drift zone contains at least one region through which charge carriers flow in an operating mode of the semiconductor component in one polarity and charge carriers do not flow in an operating mode of the semiconductor component in an opposite polarity. | 2015-01-08 |
20150008481 | LATERAL POWER SEMICONDUCTOR TRANSISTORS - The invention generally relates to a lateral power semiconductor transistor for example in integrated circuits. In particular the invention relates to Lateral Insulated Gate Bipolar Transistors or other lateral bipolar devices such as PIN diodes. The invention also generally relates to a method of increasing switching speed of a lateral bipolar power semiconductor transistor. There is provided a lateral bipolar power semiconductor transistor comprising a first floating semiconductor region of the first conductivity type located laterally spaced to an anode/drain region and a second floating semiconductor region of the second conductivity type located laterally adjacent the first floating semiconductor region, and a floating electrode placed above and in direct contact to the first and second floating semiconductor regions. | 2015-01-08 |
20150008482 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to the embodiments, a semiconductor device having a CMOS image sensor is provided. The CMOS image sensor includes a plurality of photoelectric conversion units adapted to photoelectrically convert an incident light into signal charges; and a transfer unit adapted to transfer the signal charges generated by the photoelectric conversion unit to a floating diffusion unit from the photoelectric conversion unit. A channel portion of a transfer gate transistor of the transfer unit has at least one SiGe layer. | 2015-01-08 |
20150008483 | Fin Structure of Semiconductor Device - The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material having the first lattice constant; a middle portion between the lower portion and upper portion, wherein the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; and a pair of notches extending into opposite sides of the middle portion; and an isolation structure surrounding the fin structure, wherein a top surface of the isolation structure is higher than a top surface of the pair of notches. | 2015-01-08 |
20150008484 | HIGH MOBILITY STRAINED CHANNELS FOR FIN-BASED TRANSISTORS - Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface. | 2015-01-08 |
20150008485 | HIGH ELECTRON MOBILITY TRANSISTORS AND METHODS OF FABRICATING THE SAME - A High electron mobility transistor (HEMT) includes a source electrode, a gate electrode, a drain electrode, a channel forming layer in which a two-dimensional electron gas (2DEG) channel is induced, and a channel supplying layer for inducing the 2DEG channel in the channel forming layer. The source electrode and the drain electrode are located on the channel supplying layer. A channel increase layer is between the channel supplying layer and the source and drain electrodes. A thickness of the channel supplying layer is less than about 15 nm. | 2015-01-08 |
20150008486 | SENSOR HAVING A THIN-FILM INHIBITION LAYER - Sensors and detection systems suitable for measuring analytes, such as biomolecule, organic and inorganic species, including environmentally and medically relevant volatiles and gases, such as NO, NO2, CO2, NH3, H2, CO and the like, are provided. Certain embodiments of nanostructured sensor systems are configured for measurement of medically important gases in breath. Applications include the measurement of endogenous nitric oxide (NO) in breath, such as for the monitoring or diagnosis of asthma and other pulmonary conditions. | 2015-01-08 |
20150008487 | JUNCTION FIELD-EFFECT TRANSISTOR WITH RAISED SOURCE AND DRAIN REGIONS FORMED BY SELECTIVE EPITAXY - Junction field-effect transistors and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate. | 2015-01-08 |
20150008488 | UNIFORM HEIGHT REPLACEMENT METAL GATE - A method of manufacturing a semiconductor structure includes forming a raised source-drain region in a semiconductor substrate adjacent to a dummy gate and forming a chemical mechanical polish (CMP) stop layer over the gate structure and above a top surface of the semiconductor substrate. A first ILD layer is formed above the CMP stop layer. The first ILD layer is removed to a portion of the CMP stop layer located above the gate structure and a portion of the CMP stop layer located above the gate structure is also removed to expose the dummy gate. The dummy gate is replaced with a metal gate and the metal gate is polished until the CMP stop layer located above the raised source-drain region is reached. | 2015-01-08 |
20150008489 | FIN-TYPE FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME - A fin-type field effect transistor includes a first fin including a first source, a first drain, and a first channel. The fin-type field effect transistor includes a second fin including a second source, a second drain, and a second channel. The fin-type field effect transistor includes a first semiconductor region under the first fin and a second semiconductor region under the second fin. A first reacted region is adjacent the first semiconductor region while a second reacted region is adjacent the second semiconductor region. The first reacted region has a first dimension causing a first strain in the first channel. The second reacted region has a second dimension causing a second strain in the second channel. The first strain and second strain are substantially equal to one another. A method of fabricating an example fin-type field effect transistor is provided. | 2015-01-08 |
20150008490 | Fluctuation Resistant FinFET - This improved, fluctuation resistant FinFET, with a doped core and lightly doped epitaxial channel region between that core and the gate structure, is confined to the active-gate span because it is based on a channel structure having a limited extent. The improved structure is capable of reducing FinFET random doping fluctuations when doping is used to control threshold voltage, and the channel structure reduces fluctuations attributable to doping-related variations in effective channel length. Further, the transistor design affords better source and drain conductance when compared to prior art FinFETs. Two representative embodiments of the key structure are described in detail. | 2015-01-08 |
20150008491 | Metal Gate Structure - A device comprises a metal gate structure in a trench and over a substrate, wherein the gate structure comprises a first metal sidewall in the trench, wherein the first metal sidewall becomes progressively thinner towards an upper portion of the first metal sidewall, a second metal sidewall in the trench, wherein the second metal sidewall becomes progressively thinner towards an upper portion of the second metal sidewall and a metal bottom layer on a bottom of the trench and between the first metal sidewall and the second metal sidewall. | 2015-01-08 |
20150008492 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - According to one embodiment, a semiconductor device of a junctionless structure includes a semiconductor layer of a first conductivity type. A pair of source/drain electrodes at a distance is on the semiconductor layer. A gate insulating film is on the semiconductor layer between the source/drain electrodes. A gate electrode is on the gate insulating film. The semiconductor layer has two or more kinds of impurities. One kind of the two or more kinds of impurities is an element selected from a group of chalcogens, and another kind of the two or more kinds of impurities is a first conductivity type impurity. | 2015-01-08 |
20150008493 | ACTIVE PIXEL STRUCTURE WITH IMPROVED CHARGE TRANSFER - The invention relates to an active CMOS pixel structure comprising: at least one photoelectric conversion zone (NPD) defined by n-doping of the substrate, said zone accumulating an amount of charge during an exposure to light and comprising a p-doped surface zone (PIN); and at least one MOS transfer transistor (TX), the gate of said transfer transistor (TX) being electrically insulated from the substrate and being used to control transfer of said charge from said photoelectric conversion zone (NPD) to said floating diffusion node (FD), in which the gate of said transfer transistor (TX) partially covers said p-doped surface zone (PIN), and said photoelectric conversion zone (NPD) extends under said gate of said transfer transistor (TX) at least as far as the end of the p-doped surface zone (PIN). | 2015-01-08 |
20150008494 | SOLID-STATE IMAGE SENSOR AND IMAGING SYSTEM - At least one exemplary embodiment is directed to a solid state image sensor including at least one antireflective layer and/or non rectangular shaped wiring layer cross section to reduce dark currents and 1/f noise. | 2015-01-08 |
20150008495 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same are provided to prevent a floating body effect and reduce coupling capacitance between buried bit lines. The semiconductor device comprises a first pillar disposed over a semiconductor substrate and including a vertical channel region, a bit line located in the lower portion of the vertical channel region inside the first pillar and a semiconductor layer extended from the semiconductor substrate to one sidewall of the first pillar. | 2015-01-08 |
20150008496 | TEMPERATURE COMPENSATION METHOD FOR HIGH-DENSITY FLOATING-GATE MEMORY - A temperature compensation technique is provided for a non-volatile memory arrangement. The memory arrangement includes: a memory circuit ( | 2015-01-08 |
20150008497 | CAPACITOR - A capacitor includes an active layer, a gate insulation layer on the active layer, a gate electrode on the gate insulation layer, an interlayer insulating layer on the gate electrode, and a first electrode on the interlayer insulating layer and connected to the active layer through at least one contact hole. | 2015-01-08 |
20150008498 | Semiconductor Component Arrangement Comprising a Trench Transistor - A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench. The method also includes producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode. The gate electrode and the at least one electrode of the electrode structure are produced by common process steps. | 2015-01-08 |
20150008499 | VERTICAL SEMICONDUCTOR DEVICE - A vertical semiconductor device includes a channel structure extending from a substrate in a first direction perpendicular to an upper surface of the substrate, and a ground selection line, word lines, and a string selection line sequentially formed on a side surface of the channel structure in the first direction to be separated from one another. The channel structure includes a protruding region formed in a side wall portion of the channel structure between the ground selection line and the upper surface of the substrate, the protruding region protruding in a horizontal direction perpendicular to the first direction. | 2015-01-08 |
20150008500 | NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR PRODUCING NON-VOLATILE SEMICONDUCTOR MEMORY - A non-volatile semiconductor memory free from adverse effects due to process charge is provided. The non-volatile semiconductor memory includes: a silicon substrate; a first silicon oxide film; a second silicon oxide film; a first silicon nitride film; and a second silicon nitride film, wherein the first silicon oxide film is layered on the silicon substrate, the first silicon nitride film is layered on the first silicon oxide film, the second silicon oxide film is layered on the first silicon nitride film, and the second silicon nitride film is layered to have a first part that is in contact with the first silicon nitride film and a second part that is in contact with the silicon substrate. | 2015-01-08 |
20150008501 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a stacked layer structure including first to n-th semiconductor layers (n is a natural number equal to or larger than 2) stacked in a first direction which is perpendicular to a surface of a semiconductor substrate, and an upper insulating layer stacked on the n-th semiconductor layer, the stacked layer structure extending in a second direction which is parallel to the surface of the semiconductor substrate, and first to n-th NAND strings provided on surfaces of the first to n-th semiconductor layers in a third direction which is perpendicular to the first and second directions respectively. | 2015-01-08 |
20150008502 | THREE DIMENSIONAL NAND DEVICE WITH BIRDS BEAK CONTAINING FLOATING GATES AND METHOD OF MAKING THEREOF - A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer. | 2015-01-08 |
20150008503 | Method Of Making A Three-Dimensional Memory Array With Etch Stop - A method of making a semiconductor device including forming a sacrificial feature over a substrate, forming a plurality of etch through regions having an etch through material and an etch stop region having an etch stop material over the sacrificial feature, forming a stack of alternating layers of a first material and a second material over the plurality of the etch through regions and the plurality of the etch stop regions, etching the stack to form a plurality of openings through the stack and through the etch through regions to expose the sacrificial feature, such that the etch through material is etched preferentially compared to the first and the second materials of the stack, removing the sacrificial feature through the plurality of openings and etching the stack to form a slit trench up to or only partially through the etch stop region, such that the first and the second materials of the stack are etched preferentially compared to the etch stop material. | 2015-01-08 |
20150008504 | NON-VOLATILE MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF - A non-volatile memory structure includes a substrate, a gate electrode formed on the substrate, conductive spacers respectively formed on two sides of the gate electrode, and an oxide-nitride-oxide (ONO) structure having an inverted T shape formed on the substrate. The gate electrode includes a gate conductive layer and a gate dielectric layer. The ONO structure includes a base portion and a body portion. The base portion of the ONO structure is sandwiched between the gate electrode and the substrate, and between the conductive spacer and the substrate. The body portion of the T-shaped ONO structure is upwardly extended from the base portion and sandwiched between the gate electrode and the conductive spacer. | 2015-01-08 |
20150008505 | THREE DIMENSIONAL NAND DEVICE WITH BIRDS BEAK CONTAINING FLOATING GATES AND METHOD OF MAKING THEREOF - A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer. | 2015-01-08 |
20150008506 | SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - A semiconductor memory device includes a substrate having a cell region and a peripheral region, a gate stack including a plurality of insulating layers and a plurality of gates alternately stacked on the cell region of the substrate, a stress buffer layer on the gate stack, a vertical channel that extends vertically through the gate stack and is electrically connected to the substrate, a memory layer wrapped around the vertical channel. A bit line electrically connected to the vertical channel may be provided on the gate stack. In a method of fabricating a semiconductor device, the buffer stress layer is formed directly on an upper insulating layer of a stack whose shape is altered to form the gate stack to inhibit warping of the substrate during fabrication of the device. | 2015-01-08 |
20150008507 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor device in which a data re-write operation can be performed a larger number of times and a data re-write operation is performed at a higher speed and a manufacturing method thereof. The semiconductor device includes a substrate, a first gate electrode, a second gate electrode, an insulating film, and a pair of source/drain regions. The first gate electrode is formed of a semiconductor layer containing an impurity of a first conductivity type. The second gate electrode is formed of a semiconductor layer containing an impurity of a second conductivity type. Each of the source/drain regions contains an impurity of the first conductivity type. The source region includes a first source region and a second source region having a concentration of the impurity of the first conductivity type higher than that of the first source region. | 2015-01-08 |
20150008508 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided. The device includes insulating patterns and conductive patterns stacked alternately, a channel layer formed through the insulating patterns and the conductive patterns, a tunnel insulating layer formed to surround sidewalls of the channel layer, and a charge storage layer formed to surround the tunnel insulating layer. An interfacial surface of the tunnel insulating layer in contact with the charge storage layer includes a thermal oxide layer. | 2015-01-08 |
20150008509 | METHOD FOR MANUFACTURING A DOUBLE-GATE ELECTRONIC MEMORY CELL AND ASSOCIATED MEMORY CELL - A method of manufacturing a double-gate electronic memory cell is presented. The cell includes a substrate; a first gate structure, with the first gate structure having a lateral flank; a stack including several layers and of which a layer is able to store electrical charges, the stack covering the lateral flank of the first gate structure and a portion of the substrate; and a second gate structure. The second gate structure includes a first portion formed from a first gate material; a second portion formed from a second gate material, with the first gate material able to be etched selectively in relation to the second gate material and with the second gate material able to be etched selectively in relation to the first gate material; a first zone of silicidation extending over the first portion of the second gate structure; and a second zone of silicidation extending over the second portion of the second gate structure. | 2015-01-08 |
20150008510 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes: a first region including: a first semiconductor layer; a first semiconductor region; a second semiconductor region; a third semiconductor region having higher impurity concentration than the first semiconductor region; a first electrode; a second electrode; an insulating film; a third electrode; a fourth electrode, a second region including a pad electrode, and the third region including: the first semiconductor layer; the first semiconductor region; a third semiconductor region; the first electrode; the second electrode; and a first insulating layer. | 2015-01-08 |
20150008511 | BOND PAD STACK FOR TRANSISTORS - A method for forming bond pads on a semiconductor die includes forming a dielectric stack including a bottom and top dielectric layer having a contact hole therethrough over a bond pad. An outer edge of the bottom dielectric layer within the contact hole extends beyond an outer edge of the top dielectric layer to define a bond pad edge. A second metal layer on a first metal layer is deposited. A first photoresist layer is formed exclusively within the contact hole. The second metal layer is wet etched to recess the second metal layer from sidewalls of the bottom dielectric layer in the contact hole. A second photoresist layer is formed exclusively within the contact hole. The first metal layer is wet etched to recess the first metal layer from the top dielectric layer. The first metal layer extends over the bond pad edge onto the bottom dielectric layer. | 2015-01-08 |
20150008512 | Method of Manufacturing a Semiconductor Device with Device Separation Structures and Semiconductor Device - A method of manufacturing a semiconductor device includes introducing at least a first and a second trench pattern including array trenches from a first surface into a semiconductor substrate, wherein an array isolation portion of the semiconductor substrate separates the first and second trench patterns. A buried gate electrode structure is provided in the first and second trench patterns at a distance to the first surface. In a single etch process, both a device separation trench having a first width is introduced into the array isolation portion and cell separation trenches having at most a second width that is smaller than the first width are introduced into semiconductor fins between the array trenches. Switching devices integrated in the same semiconductor die may be formed in a cost effective way. | 2015-01-08 |
20150008513 | TRENCH TYPE POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A trench type semiconductor power device is disclosed. An epitaxial layer is formed on a semiconductor substrate. A gate trench is formed in the epitaxial layer. A gate oxide layer and a trench gate are formed in the gate trench. A spacer is provided on the gate. A metal top structure on the gate is separated from a contact structure by the spacer. The contact structure extends into the epitaxial layer. A source doping region is provided in the epitaxial layer at least between the contact structure and the gate trench. | 2015-01-08 |
20150008514 | TRENCH GATE MOSFET - A trench gate MOSFET is provided. An epitaxial layer is disposed on a substrate. A body layer is disposed in the epitaxial layer. The epitaxial layer has a first trench therein, the body layer has a second trench therein, and the first trench is disposed below the second trench. A first insulating layer is disposed on a surface of the first trench. A second insulating layer is disposed in the first trench. A first conductive layer is disposed between the first and second insulating layers. A second conductive layer is disposed in the second trench. A third insulating layer is disposed between the second conductive layer and the body layer and between the second conductive layer and the first conductive layer. A dielectric layer is disposed on the epitaxial layer and covers the second conductive layer. Two doped regions are disposed in the body layer respectively beside the second trench. | 2015-01-08 |
20150008515 | TRENCH GATE MOSFET - A trench gate MOSFET is provided. An epitaxial layer is disposed on a substrate. A body layer is disposed in the epitaxial layer. The epitaxial layer has a first trench therein, the body layer has a second trench therein, the first trench is disposed below the second trench, and first trench is narrower than the second trench. | 2015-01-08 |
20150008516 | SEMICONDUCTOR DEVICE WITH BURIED GATE ELECTRODE STRUCTURES - A method of manufacturing a semiconductor device includes introducing at least a first and a second trench pattern from a first surface into a semiconductor substrate. An array isolation region including a portion of the semiconductor substrate separates the first and second trench patterns. At least the first trench pattern includes array trenches and a contact trench which is structurally connected with the array trenches. A buried gate electrode structure is provided in a lower section of the first and second trench patterns in a distance to the first surface. A connection plug is provided between the first surface and the gate electrode structure in the contact trench. Gate electrodes of semiconductor switching devices integrated in the same semiconductor portion can be reliably separated and internal gate electrodes can be effectively connected in a cost-effective manner. | 2015-01-08 |
20150008517 | Semiconductor Device with Vertical Transistor Channels and a Compensation Structure - A semiconductor device includes transistor cells with vertical channels perpendicular to a first surface of a semiconductor portion. A buried compensation structure in the semiconductor portion between the transistor cells and a second surface of the semiconductor portion parallel to the first surface includes first areas and second areas. The first and second areas are alternatingly arranged along a lateral direction parallel to the first surface. A contiguous impurity layer of a first conductivity type separates the transistor cells from the buried compensation structure. | 2015-01-08 |
20150008518 | FLATBAND SHIFT FOR IMPROVED TRANSISTOR PERFORMANCE - An integrated circuit includes MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. An integrated circuit includes MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel. | 2015-01-08 |
20150008519 | POWER INTEGRATED DEVICE HAVING SURFACE CORRUGATIONS - According to a process for manufacturing an integrated power device, projections and depressions are formed in a semiconductor body that extend in a first direction and are arranged alternated in succession in a second direction, transversely to the first direction. Further provided are a first conduction region and a second conduction region. The first conduction region and the second conduction region define a current flow direction parallel to the first direction, along the projections and the depressions. To form the projections and the depressions, portions of the semiconductor body that extend in the first direction and correspond to the depressions, are selectively oxidized. | 2015-01-08 |
20150008520 | DUAL CHANNEL HYBRID SEMICONDUCTOR-ON-INSULATOR SEMICONDUCTOR DEVICES - Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal. Within each of the SOI region and the bulk region, two types of semiconductor material portions are formed depending on whether a semiconductor material intermixes with the semiconductor alloy material. | 2015-01-08 |
20150008521 | TRANSISTOR HAVING A STRESSED BODY - A transistor includes a body and a semiconductor region configured to stress a portion of the body. For example, stressing a channel of the transistor may increase the mobility of carriers in the channel, and thus may reduce the “on” resistance of the transistor. For example, the substrate, source/drain regions, or both the substrate and source/drain regions of a PFET may be doped to compressively stress the channel so as to increase the mobility of holes in the channel. Or, the substrate, source/drain regions, or both the substrate and source/drain regions of an NFET may be doped to tensile stress the channel so as to increase the mobility of electrons in the channel. | 2015-01-08 |
20150008522 | SEMICONDUCTOR DEVICE - Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor. | 2015-01-08 |
20150008523 | COMPENSATED WELL ESD DIODES WITH REDUCED CAPACITANCE - An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode. | 2015-01-08 |
20150008524 | Integrated circuit device structure and fabrication method thereof - An integrated circuit device structure, in which, a diffusion region is formed in a substrate, an extension conductor structure is contacted with the diffusion region and extended externally to a position along a surface of the substrate, the position is outside the diffusion region, another extension conductor structure is contacted with the diffusion region, a jumper conductor structure is disposed over the substrate and on these two extension conductor structures for electrically connecting these two extension conductor structures, the jumper conductor structure may be over one or more gate structures, a contact structure penetrates through a dielectric layer to be contacted with the jumper conductor structure, and a metal conductor line is contacted with the contact structure. | 2015-01-08 |
20150008525 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate; an insulator layer provided on the substrate; a first transistor provided on the insulator layer; a semiconductor layer including a plurality of impurity regions of a first conduction type, the impurity regions forming a part of the first transistor; a heat dissipation layer; a thermal conductive layer linking the semiconductor layer and the heat dissipation layer; and an interruption structure configured to interrupt a flow of a current between the first transistor and the thermal conductive layer. | 2015-01-08 |
20150008526 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate; a first active region formed in the substrate and that includes a first region that has a first width and a second region including a second width larger than the first width and extended in a first direction; a second active region formed in the substrate and extended in parallel to the second region of the first active region; and an element isolation insulating film formed in the substrate and that partitions the first active region and the second active region, respectively, wherein the second region of the first active region or the second active region includes a depressed part depressed in a second direction that is perpendicular to the first direction in a plan view. | 2015-01-08 |
20150008527 | INTEGRATED CIRCUIT STRUCTURE HAVING SELECTIVELY FORMED METAL CAP - An integrated circuit structure with a selectively formed and at least partially oxidized metal cap over a gate. In one embodiment, an integrated circuit structure has: a substrate; a metal gate located over the substrate; at least one liner layer over the substrate and substantially surrounding the metal gate; and an at least partially oxidized etch stop layer located directly over the metal gate, the etch stop layer including at least one of cobalt (Co), manganese (Mn), tungsten (W), iridium (Ir), rhodium (Rh) or ruthenium (Ru). | 2015-01-08 |
20150008528 | DIFFUSION BARRIER AND METHOD OF FORMATION THEREOF - A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions. | 2015-01-08 |
20150008529 | ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE - Provided is an electrostatic discharge (ESD) protection structure including a substrate, a pick-up region, a first MOS device, a second MOS device, a first doped region and a second doped region. The pick-up region is located in the substrate. The first MOS device has a first drain region of a first conductivity type located in the substrate. The second MOS device has a second drain region of the first conductivity type located in the substrate. The first drain region is closer to the pick up region than the second drain region is. The first doped region of a second conductivity type is located under the first doped region. The second doped region of the second conductivity type is located under the second doped region. The area and/or doping concentration of the first doped region is greater than that of the second doped region. | 2015-01-08 |
20150008530 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device is provided. A cell region is disposed in a substrate. The cell region includes a memory cell. A peripheral region is disposed in the substrate. The peripheral region is adjacent to the cell region. The peripheral region has a trench isolation, a first active region and a second active region. The trench isolation is interposed between the first active region and the second active region. A common gate pattern is disposed on the peripheral region. The common gate pattern extends in a first direction and partially overlaps the first active region, the second active region and the trench isolation. A buried conductive pattern is enclosed by the trench isolation. The buried conductive pattern extends in a second direction crossing the first direction. A top surface of the buried conductive pattern is lower than a bottom surface of the common gate pattern. | 2015-01-08 |
20150008531 | EMBEDDED POLYSILICON RESISTOR IN INTEGRATED CIRCUITS FORMED BY A REPLACEMENT GATE PROCESS - An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode. | 2015-01-08 |
20150008532 | TRANSISTOR STRUCTURE WITH SILICIDED SOURCE AND DRAIN EXTENSIONS AND PROCESS FOR FABRICATION - A transistor is formed in a semiconductor substrate with a gate over a channel region, source/drain extension regions in the substrate adjacent the channel region, and source/drain regions in the substrate adjacent the source/drain extension regions. Silicide is formed on the source/drain extension regions and the source/drain regions so that the silicide has a first thickness over the source/drain extension regions and a second thickness over source/drain regions, with the second thickness being greater than the first thickness. Silicide on the source/drain extension regions lowers transistor series resistance which boosts transistor performance and also protects the source/drain extension regions from silicon loss and silicon damage during contact etch. | 2015-01-08 |
20150008533 | MULTI-PORT SRAM MANUFACTURING - Some embodiments relate to an integrated circuit including fin field effect transistors (FinFETs) thereon. The integrated circuit includes first and second active fin regions having a first conductivity type and spaced apart from one another. A gate dielectric layer is disposed over the first and second active fin regions. First and second gate electrodes are disposed over the first and second active fin regions, respectively. The first and second gate electrodes are also disposed over the gate dielectric layer. The first and second gate electrodes are electrically coupled together and are electrically separated from the first and second active fin regions by the gate dielectric layer. The first gate electrode is made of a first metal having a first workfunction, and the second gate electrode is made of a second metal having a second workfunction that differs from the first workfunction. | 2015-01-08 |
20150008534 | SEMICONDUCTOR DEVICE - In a semiconductor device, each of a first connection metal member, a second connection metal member, a third connection metal member, and a fourth connection metal member electrically connects a corresponding line to a corresponding one of main electrodes formed on lower surfaces and upper surfaces of first and second semiconductor elements. A cross-sectional area of each of the first connection metal member, the second connection metal member, the third connection metal member, and the fourth connection metal member is larger than a cross-sectional area of a fifth connection metal member that is disposed at a region located outside regions of the first and second semiconductor elements in a plan view. | 2015-01-08 |
20150008535 | DEVICES INCLUDING FIN TRANSISTORS ROBUST TO GATE SHORTS AND METHODS OF MAKING THE SAME - Disclosed are methods, systems and devices, including a method that includes the acts of etching an inter-row trench in a substrate, substantially or entirely filling the inter-row trench with a dielectric material, and forming a fin and a insulating projection at least in part by etching a gate trench in the substrate. In some embodiments, the insulating projection includes at least some of the dielectric material in the inter-row trench. | 2015-01-08 |
20150008536 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING A SEMICONDUCTOR DEVICE STRUCTURE - The present disclosure provides for semiconductor device structures and methods for forming semiconductor device structures, wherein a field-inducing structure is provided lower than an active portion of a fin along a height dimension of that fin, the height dimension extending in parallel to a normal direction of a semiconductor substrate surface in which the fin is formed. The field-inducing structure hereby implements a permanent field effect below the active portion. The active portion of the fin is to be understood as a portion of the fin covered by a gate dielectric. | 2015-01-08 |
20150008537 | N-TYPE MOSFET AND METHOD FOR MANUFACTURING THE SAME - An N-type MOSFET and a method for manufacturing the same are disclosed. In one aspect, the method comprises forming source/drain regions in a semiconductor substrate. The method also includes forming an interfacial oxide layer on the semiconductor substrate. The method also includes forming a high-k gate dielectric layer on the interfacial oxide layer. The method also includes forming a first metal gate layer on the high-k gate dielectric layer. The method also includes implanting dopants into the first metal gate layer through conformal doping. The method also includes annealing a gate stack to change an effective work function of the gate stack which includes the first metal gate layer, the high-k gate dielectric, and the interfacial oxide layer. | 2015-01-08 |
20150008538 | PARTIALLY RECESSED CHANNEL CORE TRANSISTORS IN REPLACEMENT GATE FLOW - An integrated circuit containing MOS transistors with replacement gates may be formed with elevated LDD regions and/or recessed replacement gates on a portion of the transistors. Elevating the LDD regions is accomplished by a selective epitaxial process prior to LDD implant. Recessing the replacement gates is accomplished by etching substrate material after removal of sacrificial gate material and before formation of a replacement gate dielectric layer. Elevating the LDD regions and recessing the replacement gates may increase a channel length of the MOS transistors and thereby desirably increase threshold uniformity of the transistors. | 2015-01-08 |
20150008539 | SEMICONDUCTOR DEVICE - A field plate electrode is repetitively disposed in a folded manner or a spiral shape in a direction along an edge of a first circuit region. A coupling transistor couples a first circuit to a second circuit lower in supply voltage than the first circuit. A second conductivity type region is disposed around the coupling transistor. A part of the field plate electrode partially overlaps with the second conductivity type region. The field plate electrode is electrically coupled to a drain electrode of the coupling transistor at a portion located on the first circuit region side from a center thereof in a width direction of the separation region. A ground potential or a power potential of the second circuit is applied to the field plate electrode at a portion located on the second conductivity type region side from the center. | 2015-01-08 |
20150008540 | MEMS-CMOS INTEGRATED DEVICES, AND METHODS OF INTEGRATION AT WAFER LEVEL - A method for forming an integrated semiconductor device includes providing a first wafer, providing a second wafer, and bonding the first wafer over the second wafer. The first wafer includes a first substrate having a microelectromechanical system (MEMS) device layer. The second wafer includes a second substrate having at least one active device, and at least one interconnect layer over the second substrate. The MEMS device layer is connected with the at least one interconnect layer. The method further includes forming at least one conductive plug through the first substrate and the MEMS device layer and inside the at least one interconnect layer, etching the second substrate and the at least one interconnect layer to form a cavity extending from a surface of the second substrate to the MEMS device layer, and etching the first substrate and the MEMS device layer to form a MEMS device interfacing with the cavity. | 2015-01-08 |
20150008541 | MEMS PRESSURE SENSORS AND FABRICATION METHOD THEREOF - A MEMS capacitive pressure sensor is provided. The pressure sensor includes a substrate having a first region and a second region, and a first dielectric layer formed on the substrate. The pressure sensor also includes a first electrode layer formed on the first dielectric layer, and a second dielectric layer having first openings formed on the first electrode layer. Further, the pressure sensor includes conductive sidewalls connecting with the first electrode layer formed on sidewalls of the first openings, and a second electrode layer with a portion formed on the second dielectric layer in the second region and the rest suspended over the conductive sidewalls in the first region. Further, the pressure sensor also includes a chamber between the conductive sidewalls and the second electrode layer; and a third dielectric layer formed on the second electrode layer exposing a portion of the second electrode layer in the first region. | 2015-01-08 |
20150008542 | Micromechanical component and manufacturing method for a micromechanical component - A micromechanical component includes a substrate having a cavern structured into the same, an at least partially conductive diaphragm, which at least partially spans the cavern, and a counter electrode, which is situated on an outer side of the diaphragm oriented away from the substrate so that a clearance is present between the counter electrode and the at least partially conductive diaphragm, the at least partially conductive diaphragm being spanned onto or over at least one electrically insulating material which at least partially covers the functional top side of the substrate, and at least one pressure access being formed on the cavern so that the at least partially conductive diaphragm is bendable into the clearance when a gaseous medium flows from an outer surroundings of the micromechanical component into the cavern. Also described is a manufacturing method for a micromechanical component. | 2015-01-08 |
20150008543 | MEMS CAPACITIVE PRESSURE SENSORS AND FABRICATION METHOD THEREOF - A MEMS capacitive pressure sensor is provided. The MEMS capacitive pressure sensor includes a substrate having a first region and a second region, and a first dielectric layer formed on the substrate. The capacitive pressure sensor also includes a second dielectric layer having a step surface profile formed on the first dielectric layer, and a first electrode layer having a step surface profile formed on the second dielectric layer. Further, the MEMS capacitive pressure sensor includes an insulation layer formed on the first electrode layer, and a second electrode layer having a step surface profile with a portion formed on the insulation layer in the peripheral region and the rest suspended over the first electrode layer in the device region. Further, the MEMS capacitive pressure sensor also includes a chamber having a step surface profile formed between the first electrode layer and the second electrode layer. | 2015-01-08 |
20150008544 | PHYSICAL QUANTITY SENSOR - A physical quantity sensor detects a physical quantity using a piezoresistive effect and includes a first-conductivity-type well layer disposed on a first insulating layer, a plurality of second-conductivity-type piezoresistive layers disposed on a surface side of the first-conductivity-type well layer, and a second-conductivity-type isolation layer disposed between the plurality of second-conductivity-type piezoresistive layers so as to pass through the first-conductivity-type well layer from a surface of the first-conductivity-type well layer to a surface of the first insulating layer. | 2015-01-08 |
20150008545 | TECHNIQUE FOR FORMING A MEMS DEVICE - An apparatus is formed on a substrate including at least one semiconductor device. The apparatus includes a microelectromechanical system (MEMS) device comprising at least one of a portion of a first structural layer and a portion of a second structural layer formed above the first structural layer. The second structural layer has a thickness substantially greater than a thickness of the first structural layer. In at least one embodiment, the MEMS device includes a first portion of the second structural layer and a second portion of the second structural layer. In at least one embodiment, the MEMS device further comprises a gap between the first portion of the second structural layer and the second portion of the second structural layer. In at least one embodiment, the gap has a width at least one order of magnitude less than the thickness of the second structural layer. | 2015-01-08 |
20150008546 | MRAM Device and Fabrication Method Thereof - A method of forming and a magnetoresistive random access memory (MRAM) device. In an embodiment, the MRAM device includes a magnetic tunnel junction (MTJ) disposed over a bottom electrode, the magnetic tunnel junction having a first sidewall, a top electrode disposed over the magnetic tunnel junction, and a dielectric spacer supported by the magnetic tunnel junction and extending along sidewalls of the top electrode, the dielectric spacer having a second sidewall substantially co-planar with the first sidewall of the magnetic tunnel junction. | 2015-01-08 |
20150008547 | Hybridized Oxide Capping Layer for Perpendicular Magnetic Anisotropy - A hybrid oxide capping layer (HOCL) is disclosed and used in a magnetic tunnel junction to enhance thermal stability and perpendicular magnetic anisotropy in an adjoining free layer. The HOCL has a lower interface oxide layer and one or more transition metal oxide layers wherein each of the metal layers selected to form a transition metal oxide has an absolute value of free energy of oxide formation less than that of the metal used to make the interface oxide layer. One or more of the HOCL layers is under oxidized. Oxygen from one or more transition metal oxide layers preferably migrates into the interface oxide layer during an anneal to further oxidize the interface oxide. As a result, a less strenuous oxidation step is required to initially oxidize the lower HOCL layer and minimizes oxidative damage to the free layer. | 2015-01-08 |
20150008548 | MAGNETIC MEMORY DEVICE - According to one embodiment, a magnetic memory device includes a semiconductor substrate, a magnetoresistive element provided on the semiconductor substrate and includes a storage layer, a tunnel barrier layer, and a reference layer which are stacked, the reference layer having a magnetization direction perpendicular to a principal surface of the semiconductor substrate, and a magnetic field generation section provided away from the magnetoresistive element and configured to generate a magnetic field perpendicular to the principal surface of the semiconductor substrate to reduce a magnetic field from the reference layer which is applied to the storage layer. | 2015-01-08 |
20150008549 | MAGNETIC MEMORY DEVICES HAVING JUNCTION MAGNETIC LAYERS AND BUFFER LAYERS AND RELATED METHODS - A magnetic memory device may include a free magnetic structure, a tunnel barrier layer, and a pinned magnetic structure wherein the tunnel barrier layer is between the free magnetic structure and the pinned magnetic structure. The pinned magnetic structure may include first and second pinned layers and an exchange coupling layer between the first and second pinned layers. The second pinned layer may be between the first pinned layer and the tunnel barrier layer, and the second pinned layer may include a junction magnetic layer and a buffer layer between the junction magnetic layer and the exchange coupling layer. The buffer layer may include a layer of a material including a non-magnetic metallic element. Related devices, structures, and methods are also discussed. | 2015-01-08 |
20150008550 | MAGNETIC MEMORY ELEMENT - The disclosed technology generally relates to semiconductor devices, and more particularly spin transfer torque magnetic random access memory (STTMRAM) elements having perpendicular magnetic anisotropy (PMA). In one aspect, a magnetic element comprises a metal underlayer and a seed layer on the underlayer, the seed layer comprising alternating layers of a first metal and a second metal. The alternating layers of a first metal and a second metal are repeated n times with, 2<=n<=20. Also a spin transfer torque magnetic random access memory element is disclosed having a perpendicular magnetic orientation comprising a metal underlayer on a substrate, a seed layer on the metal underlayer; the seed layer comprising alternating layers of a first metal and a second metal, a magnetic tunnel junction (MTJ) element with a perpendicular orientation including: a reference layer formed on the seed layer, a tunnel barrier layer formed on the reference layer, a storage layer formed on the tunnel barrier layer and a top electrode and a bottom electrode. | 2015-01-08 |
20150008551 | SEMICONDUCTOR STRUCTURE, DEVICE COMPRISING SUCH A STRUCTURE, AND METHOD FOR PRODUCING A SEMICONDUCTOR STRUCTURE - A semi-conducting structure, configured to receive an electromagnetic radiation and to transform the electromagnetic radiation into an electric signal, including: a first zone and a second zone of a same conductivity type and of same elements; a barrier zone, provided between the first and second zones, for acting as a barrier to majority carriers of the first and second zones on a barrier thickness, the barrier zone having its lowest bandgap energy defining a barrier proportion; and a first interface zone configured to interface the first zone and the barrier zone on a first interface thickness, the first interface zone including a composition of elements which is varied from a proportion corresponding to that of the first material to the barrier proportion, the first interface thickness being at least equal to half the barrier thickness. | 2015-01-08 |
20150008552 | SEMICONDUCTOR PACKAGE - A wiring is located on a multilayer ceramic substrate. A ceramic block is located on the multilayer ceramic substrate. Electronic parts, including a semiconductor laser, are located on a surface of the ceramic block. A wiring located on the surface of the ceramic block connects some of the electronic parts to the wiring. A metallic cap with a glass window is located on the multilayer ceramic substrate. This metallic cap covers the ceramic block and the electronic parts, including the semiconductor laser. | 2015-01-08 |
20150008553 | IMAGE SENSOR HAVING 3D PHOTOELECTRIC CONVERSION DEVICE - An image sensor includes a transfer gate formed over a substrate including front and back sides, a photoelectric conversion area formed in the substrate on one side of the transfer gate, a trench formed in the photoelectric conversion area and having a trench entrance located on the back side of the substrate, and a color filter formed over the backside of the substrate. | 2015-01-08 |
20150008554 | SOLID-STATE IMAGING APPARATUS AND ELECTRONIC APPARATUS - A solid-state imaging apparatus includes a phase difference detection pixel including a photoelectric conversion section that is formed on a semiconductor substrate and configured to photoelectrically convert incident light, a waveguide configured to guide the incident light to the photoelectric conversion section, and a light-shielding section that is formed in vicinity of an opening of the waveguide and configured to shield a part of the incident light that enters the waveguide. | 2015-01-08 |
20150008555 | SOLID STATE IMAGING APPARATUS, PRODUCTION METHOD THEREOF AND ELECTRONIC DEVICE - A solid state imaging apparatus includes an insulation structure formed of an insulation substance penetrating through at least a silicon layer at a light receiving surface side, the insulation structure having a forward tapered shape where a top diameter at an upper portion of the light receiving surface side of the silicon layer is greater than a bottom diameter at a bottom portion of the silicon layer. Also, there are provided a method of producing the solid state imaging apparatus and an electronic device including the solid state imaging apparatus. | 2015-01-08 |
20150008556 | ISOLATION TRENCH THROUGH BACKSIDE OF SUBSTRATE - Among other things, one or more semiconductor arrangements comprising isolation trenches, and techniques for forming such isolation trenches are provided. A substrate comprises a front side surface and a backside surface. One or more devices are formed over the front side surface. A wet etch is performed to form a tapered portion of an isolation trench. A dry etch is performed to form a non-tapered portion of the isolation trench. Because both the wet etch and the dry etch are performed, etching time is reduced compared to merely using the dry etch due to the wet etch having a relatively faster etch rate than the dry etch. In an embodiment, the isolation trench provides isolation for a current leakage path associated with a device or other material formed over the front side surface. In an embodiment, metal is formed within the isolation trench for backside metallization. | 2015-01-08 |
20150008557 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a buried insulating film formed on the substrate, an SOI layer formed on the buried insulating film, an insulating film formed to extend from a top surface of the SOI layer to the buried insulating film and to divide the SOI layer into a first SOI layer and a second SOI layer isolated from the first SOI layer, an element formed in the first SOI layer, and an electrode having at one end thereof a pad located directly above the second SOI layer, the other end of the electrode being connected to the first SOI layer. A cavity region is formed between the buried insulating film and the substrate directly below the first SOI layer. The portion of the buried insulating film directly below the second SOI layer is at least partially in direct contact with the substrate. | 2015-01-08 |
20150008558 | SELF-ALIGNED BIPOLAR JUNCTION TRANSISTORS - Device structures and design structures for a bipolar junction transistor. An intrinsic base is formed on the substrate, a terminal is formed on the intrinsic base, and an extrinsic base is formed that is arranged in juxtaposition with the intrinsic base on the substrate. The intrinsic base and terminal are respectively comprised of first and second semiconductor materials. | 2015-01-08 |
20150008559 | BIPOLAR JUNCTION TRANSISTOR WITH MULTIPLE EMITTER FINGERS - Bipolar junction transistors and design structures for a bipolar junction transistor. The bipolar junction transistor may include a plurality of emitters that are arranged in distinct emitter fingers. A silicide layer is formed that covers an extrinsic base layer of the bipolar junction transistor and that fills the gaps between adjacent emitters. Non-conductive spacers on the emitter sidewalls electrically insulate the emitters from the silicide layer. The emitters extend through the extrinsic base layer and the silicide layer to contact the intrinsic base layer. The emitters may be formed using sacrificial emitter pedestals in a replacement-type process. | 2015-01-08 |
20150008560 | SEMICONDUCTOR DEVICE AND METHOD FOR LOW RESISTIVE THIN FILM RESISTOR INTERCONNECT - The invention relates to a semiconductor device and a method of manufacturing an electronic device. A first conductive layer (first metal interconnect layer) is deposited. There is an insulating layer (first intermetal dielectric) layer deposited. A resistive layer is deposited on top of the insulating layer and structured in order to serve as a thin film resistor. A second insulating layer (second intermetal dielectric) is then deposited on top of the resistive layer. A first opening is etched into the insulating layers (first and second intermetal dielectric) down to the first conductive layer. A second opening is etched into the insulating layers (first and second intermetal dielectrics) down to the first conductive layer. A cross-sectional plane of the second opening is arranged such that it at least partially overlaps the resistive layer of the thin film resistor in a first direction. | 2015-01-08 |
20150008561 | BIPOLAR TRANSISTOR HAVING SINKER DIFFUSION UNDER A TRENCH - A bipolar transistor includes a substrate having a semiconductor surface, a first trench enclosure and a second trench enclosure outside the first trench enclosure both at least lined with a dielectric extending downward from the semiconductor surface to a trench depth, where the first trench enclosure defines an inner enclosed area. A base and an emitter formed in the base are within the inner enclosed area. A buried layer is below the trench depth including under the base. A sinker diffusion includes a first portion between the first and second trench enclosures extending from a topside of the semiconductor surface to the buried layer and a second portion within the inner enclosed area, wherein the second portion does not extend to the topside of the semiconductor surface. | 2015-01-08 |
20150008562 | PNP BIPOLAR JUNCTION TRANSISTOR FABRICATION USING SELECTIVE EPITAXY - Lateral PNP bipolar junction transistors and design structures for a lateral PNP bipolar junction transistor. An emitter and a collector of the lateral PNP bipolar junction transistor are comprised of p-type semiconductor material that is formed by a selective epitaxial growth process. The source and drain each directly contact a top surface of a device region used to form the emitter and collector. A base contact may be formed on the top surface and overlies an n-type base defined within the device region. The emitter is laterally separated from the collector by the base contact. Another base contact may be formed in the device region that is separated from the other base contact by the base. | 2015-01-08 |
20150008563 | Composite of III-Nitride Crystal on Laterally Stacked Substrates - Group-III nitride crystal composites made up of especially processed crystal slices, cut from III-nitride bulk crystal, whose major surfaces are of {1-10±2}, {11-2±2}, {20-2±1} or {22-4±1} orientation, disposed adjoining each other sideways with the major-surface side of each slice facing up, and III-nitride crystal epitaxially present on the major surfaces of the adjoining slices, with the III-nitride crystal containing, as principal impurities, either silicon atoms or oxygen atoms. With x-ray diffraction FWHMs being measured along an axis defined by a <0001> direction of the substrate projected onto either of the major surfaces, FWHM peak regions are present at intervals of 3 to 5 mm width. Also, with threading dislocation density being measured along a <0001> direction of the III-nitride crystal substrate, threading-dislocation-density peak regions are present at the 3 to 5 mm intervals. | 2015-01-08 |
20150008564 | BRIDGE RECTIFIER AND METHOD FOR SAME - A bridge rectifier including a common P-type diode, a common N-type diode, two first metal layers, two pairs of second metal layers, two AC inputs and two DC outputs. The P-type diode includes a common P-type doping region, a pair of first N-type substrate regions and a pair of P-type doping regions. The N-type diode includes a common N-type doping region, a pair of second N-type substrate regions and a pair of N-type doping regions. The first metal layers connect to the common N-type doping region and the common P-type doping region. The second metal layers connect to the P-type doping region and the N-type doping region. Two AC inputs connect to one of the second metal layers of the P-type diode and one of the second metal layers of the N-type diode respectively. Two DC inputs connect to the first metal layers respectively. | 2015-01-08 |
20150008565 | HIGH-FREQUENCY PACKAGE - A high-frequency package includes an MMIC including a signal source and a conductor pattern that is connected to the signal source, a substrate having a signal line and a GND formed thereon and the MMIC mounted thereon, a metal bump for signaling that is formed between the MMIC and the substrate, and connects the conductor pattern of the MMIC and the signal line of the substrate, and a plurality of metal bumps for shielding that are formed between the MMIC and the substrate so as to surround the signal source and the conductor pattern with the metal bump for signaling, where a space between a pair of adjacent metal bumps among the metal bump for signaling and the plurality of metal bumps for shielding is equal to or less than half of a wavelength of an electromagnetic wave generated from the signal source. | 2015-01-08 |
20150008566 | METHOD AND STRUCTURE OF PANELIZED PACKAGING OF SEMICONDUCTOR DEVICES - A method for fabricating packaged semiconductor devices in panel format; placing a panel-sized metallic grid with openings on an adhesive tape ( | 2015-01-08 |
20150008567 | USING AN INTEGRATED CIRCUIT DIE CONFIGURATION FOR PACKAGE HEIGHT REDUCTION - A semiconductor device includes a semiconductor die having a first major surface and a second major surface opposite the first major surface, a first minor surface and a second minor surface opposite the first minor surface, a plurality of contact pads on the first major surface, and a notch which extends from the first minor surface and the second major surface into the semiconductor die. The notch has a notch depth measured from the second major surface into the semiconductor die, wherein the notch depth is less than a thickness of the semiconductor die, and a notch length measured from the first minor surface into the semiconductor die, wherein the notch length is less than a length of the semiconductor die measured between the first and second minor surfaces. The device includes a lead having a first end in the notch, and an encapsulant over the first major surface. | 2015-01-08 |
20150008568 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a package having a hollow portion, which can meet the need of reduction in size and thickness. The semiconductor device includes: a resin molded member ( | 2015-01-08 |
20150008569 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor device includes a die pad, which includes an upper surface and a lower surface, the upper surface forming a rectangular shape in plan view; a plurality of support pins that support the die pad; a plurality of inner leads arranged around the die pad; a plurality of outer leads connected to each of the inner leads; a semiconductor chip which includes a main surface and a back surface and in which a plurality of electrode pads is formed in the main surface; a plurality of wires which electrically couple the electrode pads of the semiconductor chip to the inner leads respectively; and a sealing body that seals the support pins, the inner leads, the semiconductor chip, and the wires. A first support pin of the plurality of support pins is integrally formed together with the die pad. The first support pin is terminated inside the sealing body. | 2015-01-08 |
20150008570 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes a base plate, an insulating layer provided on an upper surface of the base plate, a metal pattern provided on an upper surface of the insulating layer, a semiconductor element bonded to the metal pattern, and an insulating substrate disposed to be in contact with an upper surface of the semiconductor element. An end of the insulating substrate is located outside the semiconductor element in plan view. The end of the insulating substrate and the metal pattern are directly or indirectly bonded. The semiconductor element includes an electrode on the upper surface. A portion of the insulating substrate, in which the electrode on the upper surface of the semiconductor element overlaps in plan view, is provided with a through-hole. | 2015-01-08 |
20150008571 | SUBSTRATE WARPAGE CONTROL USING EXTERNAL FRAME STIFFENER - A chip package and methods of manufacturing the same are disclosed. In particular, a chip package comprising a ball grid array is disclosed in which the chip package includes a package substrate supporting the ball grid array and in which the chip package further includes a warpage control frame that helps to minimize or mitigate warpage of the chip package. | 2015-01-08 |
20150008572 | Power Semiconductor Package with Multiple Dies - A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive. | 2015-01-08 |