01st week of 2010 patent applcation highlights part 26 |
Patent application number | Title | Published |
20100002504 | Mulitple-bit per cell (MBC) non-volatile memory apparatus and system having polarity control and method of programming same - A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M−1) virtual pages and selectively inverts data words to minimize a number of bits to be programmed in an M | 2010-01-07 |
20100002505 | READING METHOD FOR MLC MEMORY AND READING CIRCUIT USING THE SAME - A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the word line voltages is higher than another one of the word line voltages, and one of the bit line voltages corresponding to the one of the word line voltages is lower than another one of the bit line voltages corresponding to the another one of the word line voltages. | 2010-01-07 |
20100002506 | Memory device and memory programming method - Provided are memory devices and memory programming methods. A memory device may include: a multi-level cell array that includes a plurality of multi-level cells; a programming unit that programs a first data page in the plurality of multi-level cells and programs a second data page in a multi-level cell from among the plurality of multi-level cells in which the first data page is programmed; an error analysis unit that analyzes read error information corresponding to the first data page based on a read voltage level to determine whether to correct a read error based on the analyzed read error information; and a controller that adjusts the read voltage level of the first data page depending on the determination result. Through this, it is possible to reduce an error occurrence when reading and/or programming a data page. | 2010-01-07 |
20100002507 | FLASH MEMORY DEVICE REDUCING NOISE OF COMMON SOURCE LINE, PROGRAM VERIFY METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME - A flash memory device controls a common source line voltage and performs a program verify method. A plurality of memory cells is connected between a bit line and the common source line. A data input/output circuit is connected to the bit line and is configured to store data to be programmed in a selected memory cell of the plurality of memory cells. The data input/output circuit maintains data to be programmed within the data input/output circuit during a program verify operation, and decreases noise in the common source line by selectively precharging the bit line based on the data to be programmed. | 2010-01-07 |
20100002508 | FLASH MEMORY DEVICE CONTROLLING COMMON SOURCE LINE VOLTAGE, PROGRAM-VERIFY METHOD, AND MEMORY SYSTEM - Disclosed is a flash memory device and a program-verify method. The flash memory device includes; a plurality of memory cells connected between a bit line and a common source line, and a data input/output circuit connected to the bit line and configured to store program data for a selected one of the plurality memory cells. The data input/output circuit maintains the program data during a program-verify operation and controls a voltage level on the bit line in accordance with the program data. | 2010-01-07 |
20100002509 | INTEGRATED FLASH MEMORY SYSTEMS AND METHODS FOR LOAD COMPENSATION - Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the load can be tuned to dynamically compensate for variations in supply voltage. In certain aspects, a compensation circuit may employ an operational amplifier configured as a voltage follower. The voltage follower compensates for any variations in supply voltage, forcing a constant voltage drop across the load element(s), thus maintaining a constant load. Other circuits may also be included, such as precharge circuits, clamp circuits, buffer circuits, trimming circuit, and sense amplifier circuits with sensed body effect. System-On-Chip integrated system aspects may include a microcontroller, a mixed IP, and a flash memory system having functionality and blocks that interface and interoperate with each other for load compensation. | 2010-01-07 |
20100002510 | NAND TYPE FLASH MEMORY AND WRITE METHOD OF THE SAME - A NAND type flash memory includes first to third memory cell transistors having current paths connected in series between one end of a current path of each of first and second selection transistors, and each having a control gate and a charge storage layer, the first and second memory cell transistors being adjacent to the first and second selection transistors, the third memory cell transistor being positioned between the first and second memory cell transistors, the third memory cell transistor holding data having not less than three bits, the first memory cell transistor holding 2-bit data in which middle and upper pages is written by skipping a lower page, and a lower page verify voltage being set when writing the middle page, and a middle page verify voltage is set when writing the upper page, changing a position of a threshold distribution of the first memory cell transistor. | 2010-01-07 |
20100002511 | SECURE NON-VOLATILE MEMORY DEVICE AND METHOD OF PROTECTING DATA THEREIN - The invention relates to a non-volatile memory device comprising: an input for providing external data (D | 2010-01-07 |
20100002512 | DISABLING FAULTY FLASH MEMORY DIES - Articles and associated methods and systems relate to disabling defective flash memory dies in a device containing multiple flash memory dies. Packages containing multiple flash memory dies may be labeled to indicate a flash memory data storage capacity based on the flash memory dies that are not disabled. Various disabling methods may be applied at the die level, package level, and/or board level. | 2010-01-07 |
20100002513 | Selective Erase Operation For Non-Volatile Storage - A non-volatile storage system can selectively perform one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control line) without intentionally erasing other non-volatile storage elements that are connected to the common word line (or other type of control line) but not in the subset. | 2010-01-07 |
20100002514 | Correcting For Over Programming Non-Volatile Storage - A non-volatile storage system corrects over programmed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control line). | 2010-01-07 |
20100002515 | Programming And Selectively Erasing Non-Volatile Storage - A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements that were supposed to remain erased, without intentionally erasing programmed data. | 2010-01-07 |
20100002516 | Integrated Circuit Memory Devices Having Vertically Arranged Strings of Memory Cells Therein and Methods of Operating Same - Nonvolatile memory devices include a first NAND-type string of EEPROM cells having a first plurality of string selection transistors therein electrically connected in series within the string. This first plurality of string selection transistors includes a first plurality of depletion-mode transistors and a first enhancement-mode transistor. A second NAND-type string of EEPROM cells is also provided with a second plurality of string selection transistors therein that are electrically connected in series. The second plurality of string selection transistors includes a second plurality of depletion-mode transistors and a second enhancement-mode transistor. According to these embodiments of the invention, the first enhancement-mode transistor is stacked vertically relative to one of the second plurality of depletion-mode transistors and the second enhancement-mode transistor is stacked vertically relative to one of the first plurality of depletion-mode transistors. A first string selection plug is configured to electrically connect a gate electrode of the first enhancement-mode transistor to a gate electrode of one of the second plurality of depletion-mode transistors. Similarly, a second string selection plug is configured to electrically connect a gate electrode of the second enhancement-mode transistor to a gate electrode of one of the first plurality of depletion-mode transistors. | 2010-01-07 |
20100002517 | SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING - A semiconductor device is disclosed. The semiconductor device includes a plurality of memory cells that are provided in a matrix and that have a charge storage layer made of an insulating film that is provided on a semiconductor substrate and a plurality of word lines that are provided on the charge storage layer. A plurality of memory cells that are arranged in a single line among the plurality of memory cells arranged in the matrix are coupled to the same word line. The semiconductor device further includes an application section that when reading data from a selected memory cell selected from the plurality of memory cells, applies a voltage to a selected word line to be coupled to the selected memory cell among the plurality of word lines. The application section applies a voltage that has a polarity that is opposite to the voltage applied to the selected word line to non-selected word lines arranged on both adjacent sides of the selected word line. | 2010-01-07 |
20100002518 | Flash memory device and programming method thereof - The flash memory device includes a memory cell array having a plurality of memory cells, a high voltage generator configured to generate a plurality of pass voltages, with a first pass voltage of the plurality of pass voltages supplied to the memory cell array during a programming operation; and a main controller including a voltage controller configured to shift the first pass voltage at a plurality of time intervals during the programming operation. | 2010-01-07 |
20100002519 | Flash memory device and programming method thereof - A flash memory device including a controller to determine higher, M, and lower, N, word-line address bits based on an input word-line address, to determine a selected area of a memory array based on the higher and lower word-line address bits, and an unselected area of the memory array based on the selected area; and a high voltage generator to provide a first pass voltage to a word line of the selected area, and to provide a second pass voltage to a word line of the unselected area. The pass voltages are discriminately applied to the programmed and non-programmed memory cells, enlarging the pass voltage window. The memory array is divided into pluralities of zones to which local voltages are each applied in different levels. | 2010-01-07 |
20100002520 | METHOD FOR PROGRAMMING A FLASH MEMORY DEVICE - A method for programming a flash memory device includes applying a program bias to a memory cell of a plurality of memory cells within a memory cell string. Each memory cell string comprises a source select line, a plurality of memory cells and a drain select line. A first pass bias is applied to at least one of the memory cells in a source select line direction relative to the memory cell to which the program bias has been applied. A second pass bias is applied to the memory cells in a drain select line direction relative the memory cell(s) to which the first pass bias has been applied. | 2010-01-07 |
20100002521 | Method for Programming of Memory Cells, in Particular of the Flash Type, and Corresponding Programming Architecture - A method is described for programming memory cells, in particular of the Flash type. In accordance with the method, a verification is performed with a first parallelism (M) in which a reading is carried out for determining the state of a group of memory cells, a determination is performed of a programming parallelism (np), based on the results of the verification, and a real programming of the memory cells carried out with the programming parallelism (np). An architecture is also described for programming memory cells in particular of the Flash type. | 2010-01-07 |
20100002522 | Nonvolatile Memory Device for Preventing Program Disturbance and Method of Programming the Nonvolatile Memory Device - A nonvolatile memory device for preventing program disturbances includes a memory cell array block, a word line driver, and a well bias control unit. The memory cell array block includes at least one cell string having a plurality of memory cells serially connected to a bit line and alternately connected to even word lines and odd word lines. After a program verification, the word line driver drives the even word lines with a first voltage and then the odd word lines with the first voltage to drop the even word line to a voltage lower than the first voltage. The well bias control unit floats a bias of a p-well formed by high voltage NMOS transistors that apply corresponding driving voltages to the even word lines and the odd word lines according to an operation mode of a program operation, a read operation, and an erase operation. | 2010-01-07 |
20100002523 | Flash Memory Devices that Utilize Age-Based Verify Voltages to Increase Data Reliability and Methods of Operating Same - Disclosed is a method of verifying a programmed condition of a flash memory device, being comprised of: determining a level of an additional verifying voltage in response to the number of programming/erasing cycles of memory cells; conducting a verifying operation to programmed memory cells with an initial verifying voltage lower than the additional verifying voltage; and selectively conducting an additional verifying operation with the additional verifying voltage to the program-verified memory cells in response to the number of programming/erasing cycles. | 2010-01-07 |
20100002524 | FLOTOX-TYPE EEPROM - In designing a FLOTOX EEPROM of a dual cell type, a consideration should be given to the layout of cells for microminiaturization of the FLOTOX EEPROM. The FLOTOX EEPROM of the dual cell type includes two paired floating gates ( | 2010-01-07 |
20100002525 | Array Data Input Latch and Data Clocking Scheme - A data input latch and clocking method and apparatus for high performance SRAM in which an L1 data input latch is controlled by a logical combination of the normal local clock buffer clock signal and the local array clock buffer clock signal. This logical combination of clock signals minimizes the hold time of the L1 latch provides a fast cycle time in which the SRAM macro can process successive write instructions while avoiding early mode issues. | 2010-01-07 |
20100002526 | Latch-based Random Access Memory - A latch-based integrated circuit random access memory having selectable bit write capability that is less susceptible to disturbing data stored in unselected bits during write operations by utilizing an inhibit signal to block writing of the unselected bits. | 2010-01-07 |
20100002527 | POWER UP DETECTION SYSTEM FOR A MEMORY DEVICE - A power up detection system for a memory device. Two rows of memory cells are mask programmed to include a word of data having an arbitrary size. The word in the second row is a single-bit shifted version of the word in the first row, such that each bit is shifted one bit position in a predetermined direction. The bits of the first word are read from the first row into slave latches of the register stages of a data register, and then shifted into the master latches of the next register stage of the data register. The bits of the second word are read from the second row into the slave latches of the register stages. Data comparison logic compares data stored in the master and slave latches of each register stage, and provides a signal indicating matching data between the first latches and the second latches, thereby indicating successful power up of the memory device. | 2010-01-07 |
20100002528 | SEMICONDUCTOR DEVICE - A sense amplifier section comprises two stages of latch-type sense amplifier circuits, i.e., a primary-stage latch-type sense amplifier and a secondary-stage latch-type sense amplifier, wherein stress exerted on the primary-stage latch-type sense amplifier is reduced significantly to ensure high accuracy in amplification. In the above configuration including the secondary-stage latch-type sense amplifier, when an amplified output from the primary-stage latch-type sense amplifier reaches a predetermined voltage level (e.g., 50 mV), a transition to amplifying operation of the secondary-stage latch-type sense amplifier is enabled so that a time duration of operation of the primary-stage latch-type sense amplifier (corresponding to a time duration of stress exertion on the primary-stage latch-type sense amplifier) can be shortened significantly. Further, by providing a clamp circuit in the primary-stage latch-type sense amplifier, it is possible to decrease a stress voltage itself to be applied to the primary-stage latch-type sense amplifier. | 2010-01-07 |
20100002529 | CIRCUIT AND METHOD FOR CONTROLLING SLEW RATE OF DATA OUTPUT CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE - A data output circuit of a semiconductor memory device includes at least two data output pads disposed adjacent to each other, a driver unit configured to output a first data by driving a first pad among the data output pads, and a control unit configured to determine whether a phase of the first data is equal to a phase of adjacent data outputted through second pad adjacent to the first pad, and control a slew rate of the driver unit according to the determination result. | 2010-01-07 |
20100002530 | Memory Address Repair Without Enable Fuses - A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding the need for a separate enable fuse. A reduction in the number of fuses results in space savings on the memory chip real estate and also savings in power consumption because of fewer fuses to be blown and read. With reduced fuse count, the yield of the memory chip's die may also be improved because of less number of defective fuses or failed fuse blows. The use of effective default state inversion for address fuses may further reduce the average number of fuses that need to be blown to repair a given non-redundant memory address. Because of the rules governing abstracts, this abstract should not be used to construe the claims. | 2010-01-07 |
20100002531 | Multi-Port Memory Devices Having Clipping Circuits Therein that Inhibit Data Errors During Overlapping Write and Read Operations - An integrated circuit device includes a memory array having a multi-port memory cell (e.g., dual-port SRAM cell) therein. This multi-port memory cell includes at least first and second read/write ports, which may be provided by respective access transistors (e.g., N-type MOS transistors) that are responsive to word line signals. The first and second read/write ports are electrically coupled to the first and second bit lines, respectively. A first clipping circuit is also provided. The first clipping circuit is responsive to a first write control signal. The first clipping circuit is configured to bias the first bit line with a read blocking voltage during a first “overlapping” operation to write data from the second bit line into the multi-port memory cell concurrently with reading data from the multi-port memory cell onto the first bit line. | 2010-01-07 |
20100002532 | ULTRA-LOW POWER HYBRID SUB-THRESHOLD CIRCUITS - The present invention provides a solution to avoid the robustness problems of sub-threshold circuits by switching small parts of circuits to nominal-voltage only when they are being used, and switching them back to sub-threshold levels when the operation finishes. Such “hybrid sub-threshold” approach is capable of supporting ultra-low power operation without the disadvantages of sub-threshold circuits. | 2010-01-07 |
20100002533 | STIRRING ASSEMBLY WITH A STIRRING ELEMENT AND A GASSING DEVICE - The invention relates to a stirring assembly comprising a stirring element ( | 2010-01-07 |
20100002534 | BUBBLE GENERATION FOR AERATION AND OTHER PURPOSES - A method of producing small bubbles ( | 2010-01-07 |
20100002535 | Method and Apparatus for Mixing Fluids - Provided are a method and apparatus for mixing fluids, whereby small amounts of fluids are effectively mixed. An apparatus for mixing fluids includes: a chamber comprising a first region and a second region; a fluid influx channel connected to the first region through which a plurality of fluids flow into the chamber; a turbulent flow generation film interposed between the first region and the second region that includes through-holes through which the fluids are passed to generate turbulent flow in the fluids in the second region to mix the fluids; and a first fluid discharge channel connected to the second region through which the mixed fluids are discharged. Fluids are mixed without additional external devices. Thus, an apparatus for mixing fluids may be miniaturized while effectively mixing fluids. | 2010-01-07 |
20100002536 | MARINE SEISMIC ACQUISITION WITH CONTROLLED STREAMER FLARING - Marine seismic data is acquired with a system of steerable seismic streamers that are intentionally maintained in a flared configuration while the streamers are towed through a body of water. | 2010-01-07 |
20100002537 | PERFORMING QUALITY CONTROL WITH RESPECT TO POSITIONING OF SURVEY HARDWARE - To perform quality control with respect to positioning of survey hardware, survey navigation data is acquired regarding components of the survey hardware used to perform a survey operation with respect to a subterranean structure. Error statistics according to the survey navigation data are determined in real time. An action is effected in response to the error statistics. | 2010-01-07 |
20100002538 | DETERMINING THE STRUCTURE OF A TOWED SEISMIC SPREAD ELEMENT - A technique includes obtaining a plurality of sets of measurements of distances between nodes located on a seismic spread element while the element is in tow. Each set is acquired in response to the operation of a different set of sources. The technique includes determining a three-dimensional structure of the seismic spread element while in tow based at least in part on the sets of measurements. | 2010-01-07 |
20100002539 | ZERO-OFFSET SEISMIC TRACE CONSTRUCTION - Described are methods for obtaining seismic signals representative of properties of the earth's interior, including the steps of obtaining near-field acoustic signals recorded in the vicinity of a seismic source ( | 2010-01-07 |
20100002540 | DEVICE AND METHOD FOR GENERATING A BEAM OF ACOUSTIC ENERGY FROM ABOREHOLE, AND APPLICATION THEREOF - In some aspects of the invention, a device, positioned within a well bore, configured to generate and direct an acoustic beam into a rock formation around a borehole is disclosed. The device comprises a source configured to generate a first signal at a first frequency and a second signal at a second frequency; a transducer configured to receive the generated first and the second signals and produce acoustic waves at the first frequency and the second frequency; and a non-linear material, coupled to the transducer, configured to generate a collimated beam with a frequency equal to the difference between the first frequency and the second frequency by a non-linear mixing process, wherein the non-linear material includes one or more of a mixture of liquids, a solid, a granular material, embedded microspheres, or an emulsion. | 2010-01-07 |
20100002541 | INTERPOLATING SEISMIC DATA - A technique includes modeling interpolated seismic measurements as a random process characterized by seismic measurements acquired at a set of sensor locations and an interpolation error. The technique includes determining the interpolated seismic measurements based at least in part on a minimization of the interpolation error. | 2010-01-07 |
20100002542 | ULTRASONIC DISTANCE-MEASURING SENSOR ASSEMBLY AND ULTRASONIC DISTANCE-MEASURING SENSOR THEREOF - An ultrasonic distance-measuring sensor assembly and an ultrasonic distance-measuring sensor thereof are disclosed. The ultrasonic distance-measuring sensor includes at least two piezoelectric actuators and a member. The member includes a side wall, at least two vibration generating/receiving surfaces and a partition. The vibration generating/receiving surfaces accommodate the piezoelectric actuators as sources. The side wall surrounds the vibration generating/receiving surfaces. The partition is disposed between the vibration generating/receiving surfaces and includes a gap. The gap is disposed between the vibration sending/receiving surfaces. | 2010-01-07 |
20100002543 | Micromechanical Structure for Receiving and/or Generating Acoustic Signals, Method for Producing a Micromechnical Structure, and Use of a Micromechanical Structure - A micromechanical structure and a method for producing a micromechanical structure are provided, the micromechanical structure being configured for receiving and/or generating acoustic signals in a medium at least partially surrounding the structure. The structure includes a first counterelement that has first openings and essentially forms a first side of the structure, a second counterelement that has second openings and essentially forms a second side of the structure, and an essentially closed diaphragm disposed between the first counterelement and the second counterelement. | 2010-01-07 |
20100002544 | DATE MECHANISM FOR A TIMEPIECE - Date mechanism ( | 2010-01-07 |
20100002545 | Timepiece - A timepiece includes a dial having a tens date display window for displaying the tens digit of the date, and a ones date display window for displaying the ones digit of the date; and a calendar mechanism having a tens indicator wheel to which a plurality of tens digit markers are disposed and a ones indicator wheel to which a plurality of ones digit markers are disposed, and which displays one of the plural tens digit markers disposed to the tens indicator wheel from the tens date display window, and displays one of the plural ones digit markers disposed to the ones indicator wheel from the ones date display window. The ones indicator wheel has a ones indicator plate on which the ones digit markers are disposed, and a ones indicator pinion affixed to the ones indicator plate. The tens indicator wheel has a tens indicator plate on which the tens digit markers are disposed, and a tens indicator pinion affixed to the tens indicator plate. The ones indicator pinion is a ring-shaped external tooth wheel having external teeth formed on the outside circumference surface. The tens indicator pinion and a tens intermediate wheel that meshes with and transfers drive power to the tens indicator pinion are disposed in the space on the inside circumference side of the ones indicator pinion. | 2010-01-07 |
20100002546 | TIMEPIECE INCLUDING A STRIKING MECHANISM - In a timepiece with a striking mechanism, for example a minute repeater watch, in order to prevent the control stem ( | 2010-01-07 |
20100002547 | WATCH FITTED WITH AN ELECTRIC MOTOR CONTROL CASE - The invention concerns an electronic watch ( | 2010-01-07 |
20100002548 | COUPLED RESONATORS FOR A TIMEPIECE - The resonator ( | 2010-01-07 |
20100002549 | Near Field Light Assisted Magnetic Recording Head and Recording Apparatus Using The Same - A head using near field light is formed, which is characterized by including a near field light assisted magnetic recording head characterized by including a pyramid tip | 2010-01-07 |
20100002550 | NEAR FIELD LIGHT ASSIGNED MAGNETIC RECORDING HEAD AND RECORDING APPARATUS USING THE SAME - A near field light assisted magnetic recording head | 2010-01-07 |
20100002551 | Reconfiguration controlling apparatus for optically reconfigurable gate array and method thereof - To provide a reconfiguration controller of an optically reconfigurable gate array for correctly and reliably writing various types of logical operation circuits of an optically reconfigurable gate array and performing high-speed logical operation by quickly starting up the circuits. [MEANS FOR SOLVING PROBLEMS] A reconfiguration controller comprises a laser array ( | 2010-01-07 |
20100002552 | OPTICAL DISK APPARATUS AND TILT CONTROL METHOD THEREOF - An optical disk apparatus which can carry out tilt control using a signal of a focus control system so as to improve the recording/reproducing performance of an optical disk. The optical disk apparatus includes a motor which rotates the optical disk, an optical pickup which reads at least information from the optical disk being rotated by the motor, a first memory which uses information of a rotation angle of the optical disk from the optical pickup as an address, a second memory which stores an offset by which information stored in the first memory should be shifted and then read, and a control portion which reads the information stored in the first memory after shifting the information by the offset stored in the second memory and which carries out tilt control using the read information. | 2010-01-07 |
20100002553 | DRIVING DEVICE AND METHOD, PROGRAM, AND RECORDING MEDIUM - A driving device includes an optical pickup unit that irradiates a disc having a plurality of recording surfaces with a laser beam used for recording or reproducing information, and a generating unit that generates a focus control signal used for controlling a focus state of the laser beam emitted from the optical pickup unit on the basis of a focus error signal. The generating unit includes level detector that detects a level of the focus error signal, an offset generator that generates an offset signal used for performing focus jumping from one of the plurality of recording surfaces to another one of the plurality of recording surfaces in accordance with the focus error signal, and a switcher that switches a polarity of the focus control signal by comparing the level of the focus error signal of the level detector with a threshold value. | 2010-01-07 |
20100002554 | OPTICAL DISK DEVICE AND OPTICAL DISK TYPE DETERMINATION METHOD - An optical disk device includes an optical head unit, a drive means and a recording surface state determination means, and determines the type of an optical disk based on a state of the information recording surface. The information recording surface includes a management region on which management information is recorded and formed by a guiding groove or a prepit sequence and a data recording region on which a user data is recorded and on which a track formed by a guiding groove or a prepit sequence. The optical head unit irradiates a focused beam onto the information recording surface of an optical disk which rotates. The drive means drives to move the focused beam along a radial direction of the optical disk by driving the optical head unit. The recording surface state determination means determines a state of the information recording surface based on a reflected light of the focused beam. The optical disk device determines the type of the optical disk based on a state of the information recording surface in a determination region being set to straddle between a management region and the data recording region. | 2010-01-07 |
20100002555 | CONTROL SIGNAL FOR THREE DIMENSIONAL OPTICAL DATA STORAGE - A method is presented for use in determining a degree of quality of a multi-layer optical data carrier in its at least partially recorded state. Predetermined first data is provided being indicative of a qualified, at least partially recorded multi-layer optical data carrier. This data corresponds to an optical response obtainable from a specific data carrier under predetermined conditions of an optical scan of the rotating data carrier. A data carrier being qualified is scanned by at least one optical beam under said predetermined conditions of the scan, and a first control signal from the data carrier is detected and data indicative of the detected control signal is generated. The so generated data is processed to determine a relation with said predetermined data. The determined relation is used for determining a degree of quality of said scanned data carrier. | 2010-01-07 |
20100002556 | REPRODUCTION SIGNAL EVALUATION METHOD, REPRODUCTION SIGNAL EVALUATION UNIT, AND OPTICAL DISK DEVICE ADOPTING THE SAME - A reproduction signal evaluation method for evaluating quality of a reproduction signal reproduced from an information recording medium based on a binary signal generated from the reproduction signal using a PRML signal processing system, includes: a pattern extraction step of extracting, from the binary signal, a specific state transition pattern which has the possibility of causing a bit error; a step of computing a differential metric based on the binary signal; an extraction step of extracting the differential metric which is not greater than a predetermined signal processing threshold; a step of determining a mean value of the differential metrics which are not greater than the signal processing threshold and extracted in the extraction step; a standard deviation computing step of determining a standard deviation which corresponds to an error rate predicted from the mean value; and an evaluation step of evaluating a quality of the reproduction signal using the standard deviation. | 2010-01-07 |
20100002557 | REMOVABLE STORAGE DEVICE WITH VIBRATION REDUCTION STRUCTURE - A removable storage device includes a base including a first frame and a second frame connected to a first frame. A containing space is formed on the second frame. A first connector is disposed on an end of the second frame. A height difference is formed between the first frame and the second frame. The removable storage device further includes a storage module installed on the first frame. A second connector is disposed on an end of the storage module. The removable storage device further includes a cable. One end of the cable is connected to the first connector, and the other end of the cable is connected to the second connector. A part of the cable is contained in the containing space of the second frame. | 2010-01-07 |
20100002558 | OPTICAL DISK DEVICE AND OPTICAL RECEIVER IC - A first optical receiver circuit in an optical receiver IC, which composes an optical disk device, generates a first voltage signal VS | 2010-01-07 |
20100002559 | Compatible optical recording medium - The optical recording medium has a recording layer sensitive for recording at a first wavelength and sensitive for reading at a second wavelength, the recording layer having a groove structure, wherein at the first wavelength the groove structure has a diffraction efficiency into a first diffraction order sufficiently large to generate a push-pull signal, and at the second wavelength it has a diffraction efficiency into a first diffraciton order close to zero. The optical pickup for recording on an optical recording medium intended to be read with a second wavelength and a second numerical aperture is characterized in that it has a light source for generating a light beam at a first wavelength and a numerical aperture given by the second numerical aperture multiplied with a ration of the first wavelength and the second wavelength. | 2010-01-07 |
20100002560 | COUPLING LENS, OPTICAL HEAD AND OPTICAL DISC DEVICE - Provides a coupling lens which, when used in combination with an objective lens for a plurality of types of optical discs such as a high density disc, DVD, CD or the like, is capable of compensating for various types of aberrations including those caused by wavelength changes and thus providing good recording or reproduction characteristics with a good wavelength dispersion compensation ability; and an optical head and an optical disc apparatus (drive). | 2010-01-07 |
20100002561 | OPTICAL PICKUP DEVICE AND OPTICAL DISK DRIVE APPARATUS - An optical pickup device includes an optical part module having a light emitting device and an optical pickup case to which the optical part module is fixed by way of an adhesive, in which the optical part module is adhesively fixed by disposing a bonding surface of the optical part module to the optical pickup case at least at two positions on lateral surfaces of the optical part module putting an optical axis therebetween, and a bonding distance L in the lateral surface between the optical part module and the optical pickup is defined as: 40 μm2010-01-07 | |
20100002562 | OPTICAL PICKUP AND OPTICAL DISC APPARATUS USING THE SAME - An optical pickup includes a light source emitting a light beam, an objective lens condensing the light beam emitted from the light source onto an optical disc, at least one divergent angle conversion lens (collimator lens) disposed between the light source and the objective lens and changing a divergent angle of the incident light beam, a driving unit (collimator lens driving mechanism) configured to drive the divergent angle conversion lens in a direction of an optical axis, an optical detection device (optical detector) detecting a return light beam reflected at the optical disc, and an environmental change detecting unit (temperature sensor) configured to detect change in environmental temperature, wherein the objective lens is made of a refractive element having, on one surface thereof, a diffraction structure in a stepped shape or a blazed sectional shape, which generates diffraction light providing a spot adapted to perform satisfactory recording and/or reproducing, the objective lens satisfying certain relationships among an amount of wavefront aberration thereof corresponding to change in environmental temperature, an amount of the change in environmental temperature, and a focal length. | 2010-01-07 |
20100002563 | MEDIA WITH TETRAGONALLY-STRAINED RECORDING LAYER HAVING IMPROVED SURFACE ROUGHNESS - A media for storing information comprises a substrate, a conductive layer formed over the substrate, and a ferroelectric layer epitaxially formed on the conductive layer. The ferroelectric layer includes an a-lattice constant that is substantially matched to an a-lattice constant of the conductive layer and an average c-lattice constant that is longer than an average c-lattice constant of a bulk-grown ferroelectric layer. | 2010-01-07 |
20100002564 | Method and device for hard drive shock event detection - A method and system for sensing the current applied to the motor of a data storage device and determining whether a shock event has occurred by processing the sensed current levels. | 2010-01-07 |
20100002565 | SERVO MASTER MAGNETICALLY TRANSFERRING SERVO PATTERNS TO MAGNETIC RECORDING MEDIUM, AND MAGNETIC TRANSFER METHOD USING THE SERVO MASTER - The servo master includes a membrane having a first surface and a second surface; a plurality of stamp areas which are disposed on the first surface, each of the plurality of stamp areas including a magnetic layer patterned with servo patterns to be magnetically transferred to a magnetic recording medium; and a pressing members which are disposed on the second surface, each of the plurality of pressing members being operable to apply pressure to a corresponding stamp area of the plurality of stamp areas. | 2010-01-07 |
20100002566 | INFORMATION RECORDING MEDIUM, AND METHOD OF MANUFACTURING INFORMATION RECORDING MEDIUM - An information recording medium ( | 2010-01-07 |
20100002567 | COMPATIBLE OPTICAL RECORDING MEDIUM - The present invention relates to a format of a recordable optical recording medium, which is designed in such a way that it can be read by any standard player and recorder. The optical recording medium has a recording layer with a structure of lands and grooves, which generates a strong push-pull signal in an area of the recording layer without recorded marks and a small push-pull signal in an area of the recording layer with recorded marks. | 2010-01-07 |
20100002568 | High-density information storage apparatus - A system is provided. The system includes an information storage medium including a substrate and a plurality of pit trains formed on the substrate at a track pitch between 0.64 and 0.67 micrometers. The system further includes a pickup head having a numerical aperture of around 0.6 and a wavelength of around 650 nanometers. The system has a tangential tilt margin between 0.54 and 0.68 degrees, and a radial tilt margin between 0.68 and 0.83 degrees when a jitter of the system is about 10%. | 2010-01-07 |
20100002569 | OPTICAL INFORMATION RECORDING MEDIUM, METHOD OF RECORDING AND REPRODUCING INFORMATION, AND AZO METAL COMPLEX DYE - An aspect of the present invention relates to an optical information recording medium comprising a recording layer on a surface of a support, wherein the surface of the support has pregrooves with a track pitch ranging from 50 to 500 nm, the recording layer comprises an azo metal complex dye in the form of a complex of at least one azo dye denoted by general formula (1) and at least one metal ion: | 2010-01-07 |
20100002570 | Transmit diversity and spatial spreading for an OFDM-based multi-antenna communication system - A multi-antenna transmitting entity transmits data to a single- or multi-antenna receiving entity using (1) a steered mode to direct the data transmission toward the receiving entity or (2) a pseudo-random transmit steering (PRTS) mode to randomize the effective channels observed by the data transmission across the subbands. The PRTS mode may be used to achieve transmit diversity or spatial spreading. For transmit diversity, the transmitting entity uses different pseudo-random steering vectors across the subbands but the same steering vector across a packet for each subband. The receiving entity does not need to have knowledge of the pseudo-random steering vectors or perform any special processing. For spatial spreading, the transmitting entity uses different pseudo-random steering vectors across the subbands and different steering vectors across the packet for each subband. Only the transmitting and receiving entities know the steering vectors used for data transmission. | 2010-01-07 |
20100002571 | METHODS FOR TRANSCEIVING DATA IN MULTI-BAND ORTHOGONAL FREQUENCY DIVISION MULTIPLE ACCESS COMMUNICATIONS SYSTEM AND COMMUNICATIONS APPARATUSES UTILIZING THE SAME - A communications apparatus is provided. A receiving module receives a signal with a predetermined signal bandwidth. A low pass filter filters the signal to obtain a filtered signal. A filter bandwidth of the low pass filter is wide enough to pass the regular sub-carrier frequency components and at least half of the guard sub-carrier frequency components of the signal. An analog to digital converter samples the filtered signal with a sampling rate exceeding a standard sampling rate defined in accordance with the predetermined signal bandwidth of the signal to obtain a plurality of digital samples. A Fast Fourier Transform module performs a fast Fourier transform on a predetermined number of points of the digital samples to obtain a plurality of transformed samples. The predetermined number exceeds a standard number defined in accordance with the predetermined carrier bandwidth. A sub-carrier collector collects the data from the transformed samples. | 2010-01-07 |
20100002572 | Dynamic precision for datapath modules - A system and method for dynamically reducing the precision of datapath modules within an FFT unit without adversely affecting the demodulation of an orthogonal frequency division multiplexing (OFDM) signal. An FFT unit is typically implemented in an OFDM receiver to separate sub-carriers within a received OFDM signal. In general, an FFT unit implemented within an OFDM receiver must be designed to operate with a precision high enough such that quantization noise, introduced within the FFT unit, does not dominate the overall maximum SNR requirement of the system. However, the SNR requirement for many OFDM receivers is dynamic and, as a result, OFDM receivers often have an instantaneous SNR requirement far below the required maximum. In these situations, it would be advantageous to reduce the precision of datapath modules within the FFT to conserve power, which is often limited in wireless devices. | 2010-01-07 |
20100002573 | Detection of Access Bursts in a Random Access Channel - A technique for detecting one or more access bursts ( | 2010-01-07 |
20100002574 | APPARATUS AND METHOD FOR CHANNEL ESTIMATION IN A MOBILE COMMUNICATION SYSTEM - An apparatus and a method for estimating a Channel Impulse Response (CIR) with respect to a location where a power of a channel exists are provided to enhance a channel estimator in a mobile communication system. The apparatus includes a CIR searcher for selecting a CIR group that is a region where a channel power exists, a CIR estimation part for estimating a CIR of the selected CIR group, and a Discrete Fourier Transform (DFT) for performing a DFT on the estimated CIR. | 2010-01-07 |
20100002575 | ADAPTIVE MODULATION AND CODING IN A SC-FDMA SYSTEM - A method and a system for transmitting data by a transmitter over a channel having a predetermined channel quality estimate, comprises the steps of splitting (S | 2010-01-07 |
20100002576 | SYSTEM AND METHOD IN AN INTER-CARRIER NETWORK INTERFACE - A system that incorporates teachings of the present disclosure may include, for example, a PE-ASBR (Provider Edge-Autonomous System Boundary Routers) having a controller to receive new routing information without an attribute of origin, insert a site of origin of the PE-ASBR into the new routing information if the PE-ASBR is dual-homed to another MPLS-VPN cluster, and broadcast to other network elements the new routing information with the site of origin of the PE-ASBR. Additional embodiments are disclosed. | 2010-01-07 |
20100002577 | GRACEFUL REMOVAL AND/OR INSERTION OF A NETWORK ELEMENT - In one embodiment, when a network element is to be removed from or inserted into a network a Graceful Operations Manager schedules graceful shut-down and/or start-up routines for different protocols and/or components on the network element in an optimal order based on dependencies between the different protocols and components. The Graceful Operations Manager communicates with the different components at different stages of their shut-down or start-up process and communicates information on the standby topology across components and/or protocols to enable the synchronization of the standby topology computation on all components and/or protocols that are affected by the removal or insertion. | 2010-01-07 |
20100002578 | Resiliency Schemes in Communications Networks - A connection oriented communications network | 2010-01-07 |
20100002579 | METHODS AND SYSTEMS FOR PRIORITY-BASED SERVICE REQUESTS, GRANTS FOR SERVICE ADMISSION AND NETWORK CONGESTION CONTROL - A method for priority-based network congestion control may be implemented by a network entity. The method may include determining one or more priorities associated with a service request that is being processed by the network entity. The method may also include determining resource availability. The method may also include determining whether to grant the service request based on the one or more priorities associated with the service request and the resource availability. | 2010-01-07 |
20100002580 | METHOD AND SYSTEM FOR PROVIDING AUTO-BANDWIDTH ADJUSTMENT - An approach is provided for auto-bandwidth adjustment of allocated bandwidth for a traffic tunnel over a network. A determination is made regarding a traffic load over the tunnel, where the tunnel meters traffic in accordance with the bandwidth allocation. A determination is made regarding whether the traffic load triggers an adjustment threshold, where the adjustment threshold is set to provide a desired headroom below the bandwidth allocation. And the bandwidth allocation is adjusted when the adjustment threshold is triggered to provide the desired headroom between the adjusted bandwidth allocation and the traffic load. | 2010-01-07 |
20100002581 | Method for Inter-Router Dual-Function Energy- and Area-Efficient Links for Network-on-Chips - The present invention provides methods for connecting routers and transmitting data along inter-router links within Nework-on-Chip (NoC) architectures. | 2010-01-07 |
20100002582 | Apparatus and methods for managing access and update requests in a wireless network - Methods and apparatus that enable a wireless network to detect and manage impending congestion events caused by a plurality of mobile devices attempting to access the network in a brief space of time. In one embodiment, the network comprises a 3g (UMTS) cellular network, and includes a congestion management and avoidance entity that preemptively triggers a collision mode upon detecting an impending congestion event. This mode advantageously reduces processing burden on the base station by causing the mobile devices (UEs) to halt current access attempts, and invoke a multiple access scheme (e.g., wait a random amount of time before attempting further access attempts). The comparatively early detection and avoidance of collisions reduces the mobile device's power consumption, while addressing congestion events early in the wireless communication process so as to maintain optimal network conditions. | 2010-01-07 |
20100002583 | Systems And Methods For Modeling A Mobile Ad Hoc Wireless Network - Systems and methods for modeling a mobile ad hoc wireless network are disclosed herein. In some embodiments of the disclosed subject matter, methods for modeling a mobile ad hoc wireless network for a predetermined geographical area. An exemplary method includes dividing the geographic area into a network grid including a plurality of network grid elements, locating obstacles, if any, to communication between transmission nodes located in at least two different grid elements from the plurality of network grid elements, locating bottlenecks within the plurality of network grid elements, locating network grid elements from the plurality of network grid elements where wireless transmission is unconstricted, determining a transmission flow rate across the bottlenecks, and comparing the transmission flow rate across the bottlenecks to determine if any of the bottlenecks are not real bottlenecks. | 2010-01-07 |
20100002584 | MANAGING TRAFFIC IN COMMUNICATIONS SYSTEM HAVING DISSIMILAR CDMA CHANNELS - In a code division multiple access (CDMA) communications system including one or more terminals (such as customer premise equipments, CPEs) that communicate with a node (such as an Internet gateway) via at least a random access channel and a reservation-oriented channel, various schemes of managing communications traffic among the channels are provided. Decisions as to the channel on which a given terminal may transmit may be based on: traffic statistics (such as packet size or average data rate over a time period), traffic content (such as packet type), the terminal's output buffer loading (queue state, or “Q-state”), a history of the terminal's output buffer loading (one or more Q-states), and so forth. In one application, decisions in managing traffic in a live user's web browsing sessions may involve intelligent ascertainment of whether a given terminal is busy based on traffic analysis or output buffer loading. | 2010-01-07 |
20100002585 | SYSTEM AND METHOD FOR AVOIDING STALL USING TIMER FOR HIGH-SPEED DOWNLINK PACKET ACCESS SYSTEM - At least one timer is used to prevent a stall condition. If a timer is not active, the timer is started for a data block that is correctly received. The data block has a sequence number higher than a sequence number of another data block that was first expected to be received. When the timer is stopped or expires, all correctly received data blocks among data blocks up to and including a data block having a sequence number that is immediately before the sequence number of the data block for which the timer was started is delivered to a higher layer. Further, all correctly received data blocks up to a first missing data block, including the data block for which the timer was started, is delivered to the higher layer. | 2010-01-07 |
20100002586 | Method for Tracking Network Parameters - A method for tracking network parameters in a communication network formed by nodes and links between them, particularly in a packet-based IP network, with access controls for the purpose of limiting the traffic load, where the network parameters include a link/cost metric with link weights for the links, a) a traffic matrix for the network is regularly ascertained, b) a blocking probability for traffic which is subject to an access control is determined from a current traffic matrix, c) a check is performed to determine whether the ascertained blocking probability satisfies a criterion for scheduled network operation, d) if the blocking probability does not satisfy the criterion and/or redetermination for limits used as part of the access controls using the current traffic matrix does not result in a blocking probability which satisfies the criterion then the current traffic matrix is used to determine a new link/cost metric for optimizing the transport of traffic through the network, e) new values for limits used as part of the access controls are determined on the basis of the new link/cost metric and, following determination of the new values for the limits, a check is performed to determine whether the criterion is satisfied when the limits are fixed at these values again, f) if the criterion is satisfied then the link weights are configured with the new link/cost metric in the network and the limits are stipulated at the new values, wherein in step d) the link/cost metric is first of all optimized for the transport of traffic through the network without taking account of error situations, and if it is established in the subsequent step e) that the criterion is not satisfied when the limits are fixed again on the basis of the new link/cost metric, optimized without taking account of error situations, then the process returns to step d) and the link/cost metric for transporting traffic through the network is optimized taking account of error situations. | 2010-01-07 |
20100002587 | Diagnostics for Serial Communication Busses - The serial communication bus includes a first module coupled to a second module via a serial cable. Each of the first and second modules comprise one or more of: a power interface, a controller, memory, a first interface, and a second interface. The power interface is configured to receive operating power for the respective module from an external power source. The controller is configured to obtain digital diagnostic data representative of operational characteristics of at least the respective module. The memory is configured to store the digital diagnostic data. The first interface is configured to allow an external host to read the digital diagnostic data from the memory. The second interface, which is distinct and separate from the first interface, is configured to serially communicate data to the second module via the serial cable. | 2010-01-07 |
20100002588 | Network Switch With Onboard Diagnostics and Statistics Collection - The network switch is configured to enable monitoring of switched data. The network switch includes a housing and one or more port cards. Each port card has one or more physical ports and includes switching circuitry to selectively create a communication path between two physical ports. The network switch also includes packet analyzer circuitry, situated within the housing, to monitor data packets switched via a communication path between two physical ports without substantially degrading signal integrity of the data packets. | 2010-01-07 |
20100002589 | ELECTRONIC DEVICE, SYTEM ON CHIP AND METHOD FOR MONITORING A DATA FLOW - An electronic device is provided which comprises a plurality of processing units (IP | 2010-01-07 |
20100002590 | METHOD OF PERFORMING RANDOM ACCESS PROCEDURE IN WIRELESS COMMUNICATION SYSTEM - A method of performing a random access procedure in a wireless communication system is provided. The method includes transmitting a random access preamble, and monitoring a downlink control channel in a transmission time interval (TTI) window for a random access response, the TTI window comprising a plurality of TTIs, wherein a TTI is an interval to search a random access-radio network temporary identity (RA-RNTI) transmitted on the downlink control channel and monitoring the downlink control channel for the random access response is stopped when the random access response including an random access preamble identifier corresponding to the transmitted random access preamble is received. | 2010-01-07 |
20100002591 | Communication System and Communication Apparatus - Communication time period measuring frames are simultaneously sent from an OAM adaptive device on a transmission side, to both a working path and a protection path. In an OAM adaptive device on a reception side, reception times of the frames having arrived from both the paths are checked so as to measure a time period difference between both the paths. The time period difference is fed back to a logic distance adjustment function of each PON section to determine required communication time periods of the PON sections respectively included in a working system and a protection system. Communication time periods of the working system and the protection system in a packet communication network are arbitrated in order to decrease a packet loss at line switching in a packet relaying network. | 2010-01-07 |
20100002592 | Ethernet Media Access Control Organization Specific Extension - An apparatus comprising a data framer configured to frame a Media Access Control (MAC) control message for transmission, the MAC control message comprising an organization specific identifier (OUI) and at least one type-length-value (TLV) comprising a type field, a length field, and a value field, wherein a format of the TLV is specified by the OUI, and wherein the value field comprises information related to operation, administration, and maintenance (OAM) features of a network. Also included is an apparatus comprising at least one component configured to implement a method comprising compiling an OAM message comprising a plurality of organization-specific TLVs and an organization unique identifier (OUI) that indicates an organization responsible for the format of the TLV, and transmitting the OAM message. | 2010-01-07 |
20100002593 | METHOD FOR DETECTING FAULTS IN GATEWAY - A method for detecting gateway ( | 2010-01-07 |
20100002594 | BUS GUARDIAN AS WELL AS METHOD FOR MONITORING COMMUNICATION BETWEEN AND AMONG A NUMBER OF NODES, NODE COMPRISING SUCH BUS GUARDIAN, AND DISTRIBUTED COMMUNICATION SYSTEM COMPRISING SUCH NODES - In order to provide a bus guardian ( | 2010-01-07 |
20100002595 | MOBILE STATION, BASE STATION, AND METHOD OF REPORTING WIRELESS CHANNEL QUALITY - A disclosed mobile station includes a wireless channel quality measuring unit configured to measure wireless channel quality; a wireless channel quality determining unit configured to determine to report the wireless channel quality to a base station if the wireless channel quality is greater than a threshold; and a transmission unit configured to report the wireless channel quality to the base station based on the determination result of the wireless channel quality determining unit. | 2010-01-07 |
20100002596 | METHOD AND DEVICE FOR POWER CONTROL IN HSDPA - The method for power control in HSDPA includes Step A, the UE with the highest priority and having data to be transmitted is selected according to the algorithm, the channel resource is distributed to the UE, and the original power level is set. Step B, the transmission power is deduced when the channel quality meets the condition; Otherwise the CQI is checked, if the value of CQI is under the highest rate level, or the data is the re-transmitting data, the transmission power is increased, or the power is kept the same level. Step C, channel resource and the UE with the highest priority are checked, if there exist, then go to step B, otherwise the method is ended. So the redundant power can be used when several UEs are controlled at the same time, the efficiency and the throughput performance are improved, and the interface is reduced. The device for power controlling is given at the same time. | 2010-01-07 |
20100002597 | FEEDBACK TO SUPPORT RESTRICTIVE REUSE - The scheduler in a base station needs CQI information from a terminal for all re-use sets every 5 ms. to decide on which re-use set to schedule a given terminal. For MIMO users, the problem is that the CQI cannot be reconstructed for all re-use sets, using the current design. Solution: (1) For Multiple Code Word MIMO users, a MIMO VCQI connection layer message enables the base station to reconstruct the MIMO-CQI for all reuse sets on a packet-by-packet basis. This will enable dynamic scheduling (RESTRICTIVE REUSE) gains. (2) For Single Code Word users, dynamic RESTRICTIVE REUSE can be obtained by changing the CQI reporting format, and also sending a MIMO-VCQI connection layer message. (3) For Single Code Word design, quasi-static scheduling gains can be obtained by sending a MIMO-VCQI connection layer message. | 2010-01-07 |
20100002598 | METHOD AND APPARATUS FOR MEASURING AND REPORTING A RANK AND A PRECODING MATRIX FOR MULTIPLE-INPUT MULTIPLE-OUTPUT COMMUNICATION - A method and apparatus for measuring and reporting a rank and/or a precoding matrix for multiple-input multiple-output (MIMO) communication are disclosed. A metric indicating a channel condition is measured and a rank is selected based on the metric. The metric may be a signal-to-interference and noise ratio (SINR), throughput, a block error rate (BLER), system capacity, a sum rate, or the like. An SINR for each radio block group (RBG) for each rank is calculated. A data rate is calculated for each RBG based on the SINR for each rank. An overall rate for all RBGs is calculated for each rank. At least one rank is selected based on the overall rate. At least one precoding matrix may be selected jointly with or separately from the at least one rank. | 2010-01-07 |
20100002599 | Devices and Methods for Matching Link Speeds Between Controllers and Controlled Devices - A controller system for detecting and matching link speeds. The present invention provides for a controller system. The controller system is a first controller and a first port. The first port is located in the first controller and has a first link speed. The first controller is adapted to match the first link speed to a second link speed of a second port of a first controlled device that is connectable to the first controller. | 2010-01-07 |
20100002600 | CHANNEL EFFICIENCY BASED PACKET SCHEDULING FOR INTERACTIVE DATA IN CELLULAR NETWORKS - The present packet scheduling algorithm gives cellular network operators greater flexibility in adjusting the way resources are allocated among interactive best-effort data users. The present packet scheduling algorithm is capable of allocating radio resource dynamically, not only based on channel conditions, but also to achieve different performance trade-offs among users with different link qualities. According to the algorithm, channel quality is determined for each user. Channel efficiency is calculated and the channel efficiency value is used as the primary factor in weighting the delivery of packets to (or from) a given user. In a packet schedule weighting equation, a value of exponent may be varied from negative to positive to give good (or bad) users better service. However, performance of users with bad channel qualities degrades the performance of good channel users in a disproportionate manner. | 2010-01-07 |
20100002601 | METHODS FOR HARDWARE REDUCTION AND OVERALL PERFORMANCE IMPROVEMENT IN COMMUNICATION SYSTEM - The aim of the present invention is a method to achieve the customization of the communication network of a multicore communication system. This goal is achieved thanks to a method to design a multicore communication system, said communication system comprising a communication network having a plurality of switches and several elements communicating through the communication network, said method comprising the steps of: a) defining the communication network topology, comprising a number of switches, the architecture of said switches and the interconnection between said switches, b) defining routes to communicate among the elements through the switches according to the application running on the system, c) marking the input-to-output connections used within the switches traversed by these routes, d) removing all or part of the electronic components related to the non-marked connections. | 2010-01-07 |
20100002602 | System operable to enable mobile access - The present invention relates to a system ( | 2010-01-07 |
20100002603 | NETWORK ELEMENT CONFIGURATION SCHEME - In a configuration scheme for one or more network elements, a network management entity determines a set of at least one parameter value from a set of operable parameter values and sends the determined set to a network element. The network element then selects a parameter value from the received set and uses the selected parameter value to configure one or more aspects of the network element. | 2010-01-07 |