01st week of 2022 patent applcation highlights part 58 |
Patent application number | Title | Published |
20220005712 | Substrate Processing Apparatus, Method of Manufacturing Semiconductor Device and Method of Processing Substrate Support - Described herein is a technique capable of preventing a constituent contained in an aluminum alloy from being vaporized and scattered when the aluminum alloy is used in a process vessel which is heated to a high temperature. According to one aspect thereof, there is provided a technique including a process chamber; a substrate support configured to support a substrate in the process chamber; and a heater configured to heat the substrate supported by the substrate support, wherein the substrate support is made of an aluminum alloy containing magnesium, and a surface of the substrate support is coated by a coating film of aluminum oxide containing magnesium oxide and being substantially free of magnesium | 2022-01-06 |
20220005713 | CHAMBER MATCHING AND CALIBRATION - A method includes receiving a plurality of sets of sensor data associated with a processing chamber of a substrate processing system. Each of the plurality of sets of sensor data comprises a corresponding sensor value of the processing chamber mapped to a corresponding spacing value of the processing chamber. The method further includes providing the plurality of sets of sensor data as input to a trained machine learning model. The method further includes obtaining, from the trained machine learning model, one or more outputs indicative of a health of the processing chamber. The method further includes causing, based on the one or more outputs, performance of one or more corrective actions associated with the processing chamber. | 2022-01-06 |
20220005714 | Process-Induced Displacement Characterization During Semiconductor Production - A controller is configured to perform at least a first characterization process prior to at least one discrete backside film deposition process on a semiconductor wafer; perform at least an additional characterization process following the at least one discrete backside film deposition process; determine at least one of a film force or one or more in-plane displacements for at least one discrete backside film deposited on the semiconductor wafer via the at least one discrete backside film deposition process based on the at least the first characterization process and the at least the additional characterization process; and provide at least one of the film force or the one or more in-plane displacements to at least one process tool via at least one of a feed forward loop or a feedback loop to improve performance of one or more fabrication processes. | 2022-01-06 |
20220005715 | METROLOGY APPARATUS AND METHOD BASED ON DIFFRACTION USING OBLIQUE ILLUMINATION AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE METROLOGY METHOD - Provided are a diffraction-based metrology apparatus having high measurement sensitivity, a diffraction-based metrology method capable of accurately performing measurement on a semiconductor device, and a method of manufacturing a semiconductor device using the metrology method. The diffraction-based metrology apparatus includes a light source that outputs a light beam, a stage on which an object is placed, a reflective optical element that irradiates the light beam onto the object through reflection, such that the light beam is incident on the object at an inclination angle, the inclination angle being an acute angle, a detector that detects a diffracted light beam that is based on the light beam reflected and diffracted by the object and a processor that measures a 3D pupil matrix for the diffracted light beam and analyze the object based on the 3D pupil matrix. | 2022-01-06 |
20220005716 | SUBSTRATE TRANSPORTER AND SUBSTRATE PROCESSING APPARATUS INCLUDING SUBSTRATE TRANSPORTER - To provide an automated apparatus for conveying a rectangular substrate. According to one embodiment, there is provided a substrate conveying apparatus for conveying the rectangular substrate. The substrate conveying apparatus includes a plurality of conveyance rollers, a plurality of roller shafts, a motor, and a pusher. The plurality of conveyance rollers are configured to support a lower surface of the substrate. To the plurality of roller shafts, the plurality of conveyance rollers are mounted. The motor is configured to rotate the plurality of roller shafts. The pusher is for lifting the substrate on the plurality of conveyance rollers such that the substrate is separated away from the plurality of conveyance rollers. The pusher includes a stage configured to pass through a clearance between the plurality of roller shafts. | 2022-01-06 |
20220005717 | Method of Manufacturing Semiconductor Device, Substrate Processing Apparatus and Non-transitory Computer-readable Recording Medium - According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device, including: (a) heating a substrate retainer in a reaction chamber, wherein the substrate retainer is provided with a plurality of slots capable of accommodating a plurality of substrates in a multistage manner; (b) repeatedly performing a set including: (b-1) moving the substrate retainer so as to locate one or more of the slots outside the reaction chamber; and (b-2) charging one or more of the substrates into the one or more of the slots; and (c) moving the substrate retainer such that the plurality of substrates charged in the plurality of slots are accommodated in the reaction chamber. | 2022-01-06 |
20220005718 | CONTACTLESS WAFER SEPARATOR - The present disclosure is directed to a wafer container including: a housing configured for transporting a plurality of wafers, wherein the plurality of wafers are stacked on a base of the housing in a first direction; a plurality of wafer separator rings; each of the wafer separator rings configured to encircle a wafer of the plurality of wafers in a second direction that is substantially perpendicular to the first direction, each of the wafer separator rings including a top surface and a bottom surface, defining a thickness there between extending in the first direction, which is about 0.3 mm-1.4 mm; and each of the wafer separator rings including an inner side wall and an outer side wall defined by an inner diameter and an outer diameter, respectively, in the second direction, wherein the inner diameter of the wafer separator ring is greater than 300 mm and configured to be spaced apart from the wafer it is encircling. | 2022-01-06 |
20220005719 | APPARATUS FOR AND METHOD FOR ALIGNING DIPOLES AND METHOD OF FABRICATING DISPLAY DEVICE - An apparatus for aligning dipoles is provided. The apparatus includes: an electric field forming unit including a stage and a probe unit, the probe unit being configured to form an electric field on the stage; an inkjet printing device including an inkjet head, the inkjet head being configured to spray ink including a solvent and dipoles dispersed in the solvent onto the stage; a light irradiation device configured to irradiate light onto the stage; and a temperature control device including a temperature control unit, the temperature control unit being configured to control a temperature of the solvent sprayed on the stage. | 2022-01-06 |
20220005720 | Fluxless gang die bonding arrangement - The present invention comprises an arrangement and process for the fluxless manufacture of an integrated circuit component, comprising the steps of loading a solder ball and chip arrangement, solder ball side up or down, onto a first or a second donor chuck respectively; monitoring the solder ball and chip arrangement by a computer-controlled camera; removing the solder ball and chip arrangement from the donor chuck by a computer-controlled gripper mechanism; moving the solder ball and chip arrangement via the gripper mechanism onto a computer-controlled gang carrier, the monitored by a second computer controlled camera; flipping the gang carrier about a horizontal axis so as to arrange the solder ball and chip arrangement into an inverted, solder ball side down orientation over a receiver chuck substrate, monitored and positionally controlled by a third computer-controlled camera; and compressing the solder ball side down solder ball and chip arrangement onto the receiver chuck substrate by a computer-controlled compression rod so as to bond the solder ball side down solder ball and chip arrangement onto the receiver chuck substrate so as to form an integrated circuit assembly. | 2022-01-06 |
20220005721 | METHOD OF ALIGNING WAFER - A method of aligning a wafer includes defining a reference direction for aligning the wafer; capturing an image of the wafer held on a chuck; using an identifying module to analyze a straight line on the image of the wafer; calculating an offset angle between the straight line and the reference direction; and calibrating the offset angle to align the straight line with the reference direction by way rotating the chuck. | 2022-01-06 |
20220005722 | HEATER FOR SEMICONDUCTOR MANUFACTURING APPARATUS - A heater for a semiconductor manufacturing apparatus, the heater includes an AlN ceramic substrate and a heating element embedded inside the AlN ceramic substrate. The AlN ceramic substrate contains O, C, Ti, Ca, and Y as impurity elements, includes an yttrium aluminate phase as a crystal phase, and has a Ti/Ca mass ratio of 0.13 or more, and a TiN phase is not detected in an XRD profile measured with Cu K-α radiation. | 2022-01-06 |
20220005723 | ELECTROSTATIC CHUCK WITH IMPROVED TEMPERATURE CONTROL - Embodiments of the disclosure provide electrostatic chucks for securing substrates during processing. Some embodiments of this disclosure provide methods and apparatus for increased temperature control across the radial profile of the substrate. Some embodiments of the disclosure provide methods and apparatus for providing control of hydrogen concentration in processed films during a high-density plasma (HDP) process. | 2022-01-06 |
20220005724 | METHOD AND DEVICE FOR WAFER TAPING - A method for taping a wafer is disclosed. A wafer taping device comprising a wafer stage is provided. A wafer is mounted and secured on the wafer stage. A tape is delivered along a first direction over the wafer. The tape is forced into adhesion with a surface of the wafer in a non-contact manner. The tape is cut along a perimeter of the wafer. | 2022-01-06 |
20220005725 | PROCESSING APPARATUS - A processing apparatus includes a chuck table mechanism including a chuck table configured to hold the wafer and a table base configured to support the chuck table in a detachable manner. The chuck table includes a porous plate having a suction surface that sucks the wafer, a frame body surrounding surfaces of the porous plate other than the suction surface of the porous plate, a wafer suction hole formed in the frame body and configured to transmit a suction force to the suction surface of the porous plate, and a bolt hole formed in the frame body and configured to fix the frame body to the table base. | 2022-01-06 |
20220005726 | ROBOT APPARATUS, SYSTEMS, AND METHODS FOR TRANSPORTING SUBSTRATES IN ELECTRONIC DEVICE MANUFACTURING - Electronic device manufacturing systems, robot apparatus and associated methods are described. The robot apparatus includes an arm having an inboard end and an outboard end, the inboard end is configured to rotate about a shoulder axis; a first forearm is configured for independent rotation relative to the arm about an elbow axis at the outboard end of the arm; a first wrist member is configured for independent rotation relative the first forearm about a first wrist axis at a distal end of the first forearm opposite the elbow axis, wherein the first wrist member includes a first end effector and a second end effector. The robot apparatus further includes a second forearm configured for independent rotation relative to the arm about the elbow axis; a second wrist member configured for independent rotation relative the second forearm about a second wrist axis, wherein the second wrist member comprises a third end effector and a fourth end effector. The robot apparatus further includes a third forearm configured for independent rotation relative to the arm about the elbow axis; and a third wrist member configured for independent rotation relative the third forearm about a third wrist axis, wherein the second wrist member includes a fifth end effector and a sixth end effector. | 2022-01-06 |
20220005727 | TEMPERATURE CONTROL DEVICE - A temperature control device includes: a top plate that supports a substrate; a base plate connected to the top plate so as to form an internal space with the top plate; a thermoelectric module plate arranged in the internal space; a heat exchange plate that is arranged in the internal space and exchanges heat with the thermoelectric module plate; and a sealing member that comes into contact with each of the top plate and the base plate. | 2022-01-06 |
20220005728 | WAFER SUSCEPTOR AND CHEMICAL VAPOR DEPOSITION APPARATUS - Disclosed are a wafer susceptor and a chemical vapor deposition apparatus, which solve a problem of a decrease in yield due to uneven wavelength of deposited epitaxial material caused by uneven heating during a wafer manufacturing process. The wafer susceptor includes: a wafer carrying groove; and two convex structures disposed at the bottom of the wafer carrying groove. | 2022-01-06 |
20220005729 | SELECTIVE ETCHES FOR REDUCING CONE FORMATION IN SHALLOW TRENCH ISOLATIONS - Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation. | 2022-01-06 |
20220005730 | SEMICONDUCTOR DEVICE - A semiconductor device including a semiconductor substrate including a chip region and an edge region around the chip region; a lower dielectric layer and an upper dielectric layer on the semiconductor substrate; a redistribution chip pad that penetrates the upper dielectric layer on the chip region and is connected a chip pad; a process monitoring structure on the edge region; and dummy elements in the edge region and having an upper surface lower than an upper surface of the upper dielectric layer. | 2022-01-06 |
20220005731 | ETCH STOP LAYER REMOVAL FOR CAPACITANCE REDUCTION IN DAMASCENE TOP VIA INTEGRATION - A method of forming an interconnect structure includes forming at least one second-level interconnect in a sacrificial dielectric layer that is formed on an upper surface of a sacrificial etch stop layer, and removing the sacrificial dielectric layer and the sacrificial etch stop layer while maintaining the at least one second-level interconnect so as to expose an underlying dielectric layer. The method further includes depositing a replacement dielectric layer on an upper surface of the underlying dielectric layer to embed the at least one second-level interconnect in the replacement dielectric layer. Accordingly, an interconnect structure can be formed that includes one or more first-level interconnect in a dielectric layer and one or more second-level interconnects in a replacement dielectric layer stacked on the dielectric layer. The replacement dielectric layer directly contacts the dielectric layer. | 2022-01-06 |
20220005732 | TOP VIA WITH DAMASCENE LINE AND VIA - A method of forming a top via is provided. The method includes forming a sacrificial trench layer and conductive trench plug in an interlayer dielectric (ILD) layer on a conductive line. The method further includes forming a cover layer on the ILD layer, sacrificial trench layer, and conductive trench plug, and forming a sacrificial channel layer and a conductive channel plug on the conductive trench plug. The method further includes removing the cover layer and the ILD layer to expose the sacrificial trench layer and the sacrificial channel layer. The method further includes removing the sacrificial trench layer and the sacrificial channel layer, and forming a barrier layer on the conductive channel plug and conductive trench plug. | 2022-01-06 |
20220005733 | METHOD FOR FORMING SEMICONDUCTOR DIE AND SEMICONDUCTOR DEVICE THEREOF - A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing. | 2022-01-06 |
20220005734 | SEMICONDUCTOR STRUCTURE IMPLEMENTING SERIES-CONNECTED TRANSISTOR AND RESISTOR AND METHOD FOR FORMING THE SAME - A semiconductor structure includes an isolation structure disposed in a semiconductor substrate; a gate electrode and a resistor electrode disposed in the semiconductor substrate, wherein the isolation structure is disposed between the gate electrode and the resistor electrode, and the isolation structure is closer to the resistor electrode than the gate electrode. A source/drain (S/D) region is disposed in the semiconductor substrate and between the gate electrode and the isolation structure, wherein the S/D region is electrically connected to the resistor electrode. A conductive structure is disposed in the semiconductor structure and over the isolation structure, wherein the S/D region is electrically connected to the resistor electrode through the conductive structure. | 2022-01-06 |
20220005735 | SELF-LIMITING LINERS FOR INCREASING CONTACT TRENCH VOLUME IN N-TYPE AND P-TYPE TRANSISTORS - Embodiments of the invention include semiconductor devices having a first n-type S/D region, a second n-type S/D region, and a first layer of protective material over the second n-type S/D region, wherein the first layer of protective material includes a first type of material and a second type of material. A second layer of protective material is formed over the first layer of protective material, wherein the second layer of protective material includes an oxide of the second type of material. The devices further include a first p-type S/D region, a second p-type S/D region, and the second layer of protective material over the second p-type S/D region, wherein the second p-type S/D region second layer of protective material includes the first type of material and the second type of material, and wherein the second layer of protective material includes the oxide of the second type of material. | 2022-01-06 |
20220005736 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus that includes a substrate holder, a cup member, an elevating mechanism, a first nozzle, and a camera. The substrate holder holds a substrate and rotates the substrate. The cup member surrounds the outer circumference of the substrate holder. The elevating mechanism moves up the cup member so that the upper end portion of the cup member is located at the upper end position higher than the substrate held by the substrate holder. The first nozzle has a discharge port at a position lower than the upper end position, and discharges first processing liquid from the discharge port to an end portion of the substrate. The camera images an imaging region that includes the first processing liquid discharged from the discharge port of the first nozzle and is viewed from an imaging position above the substrate. | 2022-01-06 |
20220005737 | LASER PROCESSING METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND INSPECTING DEVICE - An inspecting device includes a stage configured to support a wafer in which a plurality of rows of modified regions are formed in a semiconductor substrate, a light source configured to output light, an objective lens configured to pass light propagated through the semiconductor substrate, a light detection part configured to detect light passing through the objective lens, and an inspection part configured to inspect whether or not there is a tip of a fracture in an inspection region between a front surface and the modified region closest to the front surface of the semiconductor substrate. The objective lens positions a virtual focus symmetrical with a focus with respect to the front surface in the inspection region. The light detection part detects light propagating from the back surface side of the semiconductor substrate to the back surface side via the front surface. | 2022-01-06 |
20220005738 | Substrate Processing Apparatus, Method of Manufacturing Semiconductor Device and Non-transitory Computer-readable Recording Medium - According to one aspect of the present disclosure, there is provided a technique that includes: a substrate retainer; a reaction tube; a heater configured to heat an inside of the reaction tube; a gas supplier configured to supply a process gas to substrates accommodated in the reaction tube; an exhauster configured to exhaust the process gas from the inside of the reaction tube; a temperature detector configured to measure an inner temperature of the reaction tube; a reflectance detector configured to measure a reflectance of a film formed by supplying the process gas through the gas supplier; and a controller configured to be capable of performing a feedback control of film-forming conditions on the substrates accommodated in the reaction tube by using temperature information measured by the temperature detector and reflectance information measured by the reflectance detector. | 2022-01-06 |
20220005739 | PLASMA PROCESSING APPARATUS AND CONTROL METHOD - A method of controlling plasma includes providing a plasma processing apparatus that includes N microwave introducing radiators disposed in a circumferential direction of a ceiling plate of a processing container so as to introduce microwaves for generating plasma into the processing container, wherein N≥2; and M sensors and configured to monitor at least one of electron density Ne and electron temperature Te of the plasma generated in the processing container, wherein M equals to N or a multiple of N. The method further includes controlling at least one of a power and a phase of the microwaves introduced from the microwave introducing radiators based on at least one of electron density Ne and electron temperature Te of the plasma monitored by the M sensors. | 2022-01-06 |
20220005740 | ATOMIC LAYER ETCH SYSTEMS FOR SELECTIVELY ETCHING WITH HALOGEN-BASED COMPOUNDS - A substrate processing system includes a processing chamber, a substrate support, a heat source, a gas delivery system and a controller. The substrate support is disposed in the processing chamber and supports a substrate. The heat source heats the substrate. The gas delivery system supplies a process gas to the processing chamber. The controller controls the gas delivery system and the heat source to iteratively perform an isotropic atomic layer etch process including: during an iteration of the isotropic atomic layer etch process, performing pretreatment, atomistic adsorption, and pulsed thermal annealing; during the atomistic adsorption, exposing a surface of the substrate to the process gas including a halogen species that is selectively adsorbed onto an exposed material of the substrate to form a modified material; and during the pulsed thermal annealing, pulsing the heat source multiple times within a predetermined period to expose and remove the modified material. | 2022-01-06 |
20220005741 | Low Profile Integrated Circuit - A device is provided. The device may include one or more of a package base, a substrate, a die secured to the substrate, a plurality of bond connections, and a package lid. The package base includes a plurality of package leads and a package base body. The package base body includes an open cavity disposed through the entire package base body, a plurality of package bond pads, disposed within a periphery of the open cavity, and a mounting shelf, disposed within the open cavity. The substrate is secured to the mounting shelf, and includes a plurality of substrate bond pads. The plurality of bond connections are configured to provide electrical connections between one or more of the die, the substrate bond pads, and the package bond pads. The package lid is secured over the open cavity to the package base body. | 2022-01-06 |
20220005742 | Semiconductor Device with a Passivation Layer and Method for Producing Thereof - A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers include outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer. | 2022-01-06 |
20220005743 | SEMICONDUCTOR MODULE AND SEMICONDUCTOR DEVICE USED THEREFOR - A semiconductor module includes a first heat sink member, a semiconductor device, a second heat sink member, a lead frame, a second sealing member. The semiconductor device includes a semiconductor element, a first sealing member for covering the semiconductor element, a first wiring and a second wiring electrically connected to the semiconductor element, and a rewiring layer on the semiconductor element and the sealing member. The second heat sink member is disposed on the semiconductor device. The lead frame is electrically connected to the semiconductor device through a bonding member. The second sealing member covers a portion of the first heat sink member, the semiconductor and a portion of the second heat sink member. A surface of the second heat sink member faces the semiconductor device. The semiconductor device has a portion protruded from an outline of the second surface sink member. | 2022-01-06 |
20220005744 | SILVER-INDIUM TRANSIENT LIQUID PHASE METHOD OF BONDING SEMICONDUCTOR DEVICE AND HEAT-SPREADING MOUNT AND SEMICONDUCTOR STRUCTURE HAVING SILVER-INDIUM TRANSIENT LIQUID PHASE BONDING JOINT - A silver-indium transient liquid phase method of bonding a semiconductor device and a heat-spreading mount, and a semiconductor structure having a silver-indium transient liquid phase bonding joint are provided. With the ultra-thin silver-indium transient liquid phase bonding joint formed between the semiconductor device and the heat-spreading mount, its thermal resistance can be minimized to achieve a high thermal conductivity. Therefore, the heat spreading capability of the heat-spreading mount can be fully realized, leading to an optimal performance of the high power electronics and photonics devices. | 2022-01-06 |
20220005745 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor module having a wiring board, semiconductor assemblies that include a multilayer substrate on which semiconductor elements are mounted, and a sealing part; a cooler; and a heat conduction sheet which is placed between the semiconductor module and the mounting surface of the cooler and which is in contact with the bottom surfaces of the multilayer substrates. The heat conduction sheet has recesses corresponding to at least parts of the outer edges of second electrically conductive plates provided on the bottoms of the multilayer substrates. | 2022-01-06 |
20220005746 | ELEMENT MODULE - An element module includes an element, a plurality of conductive members, and a spacer member. The plurality of conductive members are connected to the element and arranged in a predetermined direction. The spacer member is disposed between two conductive members of the plurality of conductive members adjacent to each other in the predetermined direction and is in contact with parts of the two conductive members. | 2022-01-06 |
20220005747 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided, including: a substrate and a dielectric layer arranged on the substrate; a conductive plug, wherein a first part of the conductive plug is arranged in the substrate, and a second part of the conductive plug is arranged in the dielectric layer; and an isolation ring structure at least surrounding the second part of the conductive plug. | 2022-01-06 |
20220005748 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes a process of providing two source electrodes on a substrate, a process of providing a gate electrode on one surface of the substrate between the two source electrodes, a process of providing an insulating film on the gate electrode, the substrate, and side surfaces of the two source electrodes, a process of providing an airbridge foundation resist on the insulating film, providing an airbridge on the two source electrodes and the airbridge foundation resist, and a process of removing the airbridge foundation resist, in which surfaces of the two source electrodes at sides opposite to the substrate and a front surface of the airbridge foundation resist provided in the subsequent process are substantially coplanar. | 2022-01-06 |
20220005749 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a molding compound, a chip and a conductive pad, wherein the chip is electrically connected to the conductive pad and both are encapsulated in the molding compound. An anchor flange is formed around a top surface of the conductive pad by over plating. When the conductive pad is embedded in the molding compound, the anchor flange engages the molding compound to prevent the conductive pad from separation. Bottoms of a chip and the conductive pad are exposed from the molding compound for electrically soldering to a circuit board. | 2022-01-06 |
20220005750 | SEMICONDUCTOR DEVICE - In a semiconductor device, a first metal plate faces a first semiconductor element and a second semiconductor element and is electrically connected to a second terminal. A second metal plate faces the first metal plate while interposing the first semiconductor element between the first and second metal plates, and is electrically connected to a first terminal. A third metal plate faces the first metal plate while interposing the second semiconductor element between the first and third metal plates. The first semiconductor element has an electrode on a surface adjacent to the second metal plate and electrically connected to the second metal plate, and an electrode on a surface adjacent to the first metal plate and electrically connected to the third metal plate. The first semiconductor element is thermally connected to the first metal plate while being electrically insulated from the first metal plate by an insulator. | 2022-01-06 |
20220005751 | SEMICONDUCTOR DEVICE PACKAGE AND SEMICONDUCTOR DEVICE - A semiconductor device package is disclosed. The package according to one example includes a base having a main surface made of a metal, a dielectric side wall having a bottom surface facing the main surface, a joining material containing silver (Ag) and joining the main surface of the base and the bottom surface of the side wall to each other, a lead made of a metal joined to an upper surface of the side wall on a side opposite to the bottom surface, and a conductive layer not containing silver (Ag). The conductive layer is provided between the bottom surface and the upper surface of the side wall at a position overlapping the lead when viewed from a normal direction of the main surface. The conductive layer is electrically connected to the joining material, extends along the bottom surface, and is exposed from a lateral surface of the side wall. | 2022-01-06 |
20220005752 | Spacer Frame for Semiconductor Packages - A method of frame handling during semiconductor package production includes: providing a lead frame having leads secured to a periphery of the lead frame by first tie bars; providing a multi-gauge spacer frame having spacers secured to a periphery of the spacer frame by second tie bars, the spacers being thicker than the second tie bars; and aligning the multi-gauge spacer frame with the lead frame such that the spacers and the second tie bars of the multi-gauge spacer frame do not contact the leads of the lead frame. A power semiconductor module and a method of assembling a power semiconductor module are also described. | 2022-01-06 |
20220005753 | SEMICONDUCTOR DEVICE - Semiconductor device A | 2022-01-06 |
20220005754 | LEAD FRAME PACKAGE - A lead frame package including first conductive layer, first electronic component, lead frames, second conductive layer and package body. First conductive layer has conductive carriers. First electronic component has first pins. Lead frames and first pins are respectively electrically connected to conductive carriers. Second conductive layer has conductive joints respectively electrically connected to lead frames so as to be electrically connected to at least a part of conductive carriers via lead frames. Package body encapsulates first conductive layer, first electronic component, and lead frames. First conductive layer and second conductive layer are located on two opposite sides of first electronic component, respectively. | 2022-01-06 |
20220005755 | Semiconductor Device Package Comprising a Pin in the Form of a Drilling Screw - The semiconductor device package comprises a die carrier, at least one semiconductor die disposed on the carrier, the semiconductor die comprising at least one contact pad on a main face remote from the carrier, an encapsulant disposed above the semiconductor die, an electrical connector electrically connected with the contact pad, a drilling screw screwed through the encapsulant and connected with the electrical connector. | 2022-01-06 |
20220005756 | WIRING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers, a plurality of circuit layers in contact with the dielectric layers, and a plurality of dam portions in contact with the dielectric layers. The dam portions are stacked on and contact one another. The conductive through via extends through the dam portions. | 2022-01-06 |
20220005757 | INTERPOSER - The present disclosure relates to an interposer. The interposer includes: a support body formed of a ceramic material, a connection electrode configured to the top surface and bottom surface of the support body, and a shielding member disposed at an outer surface of the support body. At least a part of the support body is disposed along the edge of a substrate, and electrically connects the substrate and a substrate. The interposer is formed of a ceramic material and thus make it possible to implement a fine pattern, to improve dimensional stability by preventing the bending deformation of ceramic green sheets, and to raise the reliability of signal transmission. Therefore, the interposer can contribute to implementing high performance of an electronic device and reducing the size of the electronic device. | 2022-01-06 |
20220005758 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a first wafer, a conductive via, an isolation layer, and a spacer structure. The first wafer includes a semiconductor substrate, a multi-level interconnect structure, and a dielectric layer. The semiconductor substrate has a front side and a back side. The multi-level interconnect structure is disposed over the front side of the semiconductor substrate. The dielectric layer is disposed over the back side of the semiconductor substrate. The conductive via extends from the dielectric layer to a conductive line of the multi-level interconnect structure. The isolation layer is disposed between the conductive via and the first wafer. The spacer structure is disposed between the conductive via and the isolation layer, in which the spacer structure is spaced apart from the conductive line. | 2022-01-06 |
20220005759 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - A three-dimensional semiconductor memory device includes: a peripheral circuit structure; and a cell array structure on the peripheral circuit structure. The peripheral circuit structure includes a lower wiring on a substrate, a stopping insulating layer on the lower wiring, a contact via on the lower wiring, a floating via on the stopping insulating layer, and an upper wiring on the contact via. The floating via does not contact the lower wiring. The contact via contacts the lower wiring through a via hole in the stopping insulating layer. The upper wiring contacts the contact via. | 2022-01-06 |
20220005760 | SEMICONDUCTOR DIE WITH CONVERSION COATING - A die includes a semiconductor layer, an electrical contact on a first side of the semiconductor layer, a backside electrical contact layer on second side of the semiconductor layer. The die further includes a zinc layer over at least one of the electrical contact or the backside electrical contact layer of the die, and a conversion coating over the zinc layer. The conversion coating includes at least one of zirconium and vanadium. As part of an embedded die package including the die, at least a portion of the conversion coating may adjacent to an electrically insulating substrate of the embedded die package. | 2022-01-06 |
20220005761 | TOP VIA WITH NEXT LEVEL LINE SELECTIVE GROWTH - Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having a conductive thin metal layer on a top via that promotes the selective growth of the next level interconnect lines (the line above). In a non-limiting embodiment of the invention, a first conductive line is formed in a dielectric layer. A via is formed on the first conductive line and a seed layer is formed on the via and the dielectric layer. A surface of the seed layer is exposed and a second conductive line is deposited onto the exposed surface of the seed layer. In a non-limiting embodiment of the invention, the second conductive line is selectively grown from the seed layer. | 2022-01-06 |
20220005762 | METAL VIA STRUCTURE - A semiconductor device includes a stack structure having at least first, second and third interconnect levels. Each interconnect level has a patterned metal conductor including a first metallic material. A via spans the second and third interconnect levels and electrically couples with the patterned metal conductor of the first interconnect level. At least a segment of the super via includes a second metallic material different from the first metallic material. | 2022-01-06 |
20220005763 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure. | 2022-01-06 |
20220005764 | PARASITIC CAPACITANCE REDUCTION IN GAN-ON-SILICON DEVICES - Semiconductor structures with reduced parasitic capacitance between interconnects and ground, for example, are described. In one case, a semiconductor structure includes a substrate and a low dielectric constant material region in the substrate. The low dielectric constant material region is positioned between a first device area in the semiconductor structure and a second device area in the semiconductor structure. The semiconductor structure also includes a III-nitride material layer over the substrate. The III-nitride material layer extends over the substrate in the first device area, over the low dielectric constant material region, and over the substrate in the second device area. The semiconductor structure can also include a first device formed in the III-nitride material layer in the first device area, a second device in the III-nitride material layer in the second device area, and an interconnect formed over the low dielectric constant material region. The interconnect can provide a continuous conductive path of metal from the first device area, over the low dielectric constant material region, and to the second device area. | 2022-01-06 |
20220005765 | SUBSTRATE STRUCTURE - A substrate structure may include a printed circuit board including a first recess and a first junction pad disposed on a lower surface of the first recess; a first electronic component package disposed in the first recess, and including a first substrate and a first electronic device module disposed on at least one surface of the first substrate; and a first external junction portion connecting the first electronic component package and the first junction pad. | 2022-01-06 |
20220005766 | COMPOSITE HEAT INSULATION STRUCTURE FOR MONOCRYSTALLINE SILICON GROWTH FURNACE AND MONOCRYSTALLINE SILICON GROWTH FURNACE - Disclosed is a composite heat insulation structure for a monocrystalline silicon growth furnace, comprising a supporting layer and a laminated structure on the supporting layer. The laminated structure comprises one or more first refractive layers and one or more second refractive layers which have different refractivity and are disposed alternately. Also disclosed is a monocrystalline silicon growth furnace in which the composite heat insulation structure is disposed on a heat shield. When disposed on a heat shield to be applied to the monocrystalline silicon growth furnace, the composite heat insulation structure can improve ability of the heat shield to reflect heat energy, reduce heat dissipation of silicon melt, and play a role of heat insulation on a heat field, thereby improving the quality of the heat field to improve the quality and yield of monocrystalline silicon. | 2022-01-06 |
20220005767 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: two memory blocks; a first structure disposed between the two memory blocks; and a second structure separated from the two memory blocks, or a plurality of second structures. The two memory blocks include a plurality of first conductive layers and a plurality of first insulating layers alternately arranged. The first structure has one end, and the one end is closer to the substrate than the plurality of first conductive layers are. The second structure has one end, and the one end is closer to the substrate than at least apart of the first conductive layers among the plurality of first conductive layers is. Another end of the first structure and another end of the second structure are farther from the substrate than the plurality of first conductive layers are. The second structure is separated from the first structure. | 2022-01-06 |
20220005768 | SEMICONDUCTOR PACKAGE STRUCTURE - Provided is a semiconductor package structure including a redistribution layer (RDL) structure, a chip, an electronic device and a stress compensation layer. The RDL structure has a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the RDL structure. The electronic device is disposed in the RDL structure, electrically connected to the chip, and includes a dielectric layer disposed therein. The stress compensation layer is disposed in or outside the RDL structure. The dielectric layer provides a first stress between 50 Mpa and 200 Mpa in a first direction perpendicular to the second surface, the stress compensation layer provides a second stress between 50 Mpa and 200 Mpa in a second direction opposite to the first direction, and the difference between the first stress and the second stress does not exceed 60 Mpa. | 2022-01-06 |
20220005769 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure includes a wafer having a functional region and a non-functional region surrounding the functional region; a first dielectric layer formed on the wafer; a first opening formed in the first dielectric layer on the non-function region of the wafer; and a first connection layer formed in the first opening. The first connection layer closes a top portion of the first opening and a first void is formed in the first connection layer in the first opening. | 2022-01-06 |
20220005770 | INTEGRATED STRUCTURES WITH ANTENNA ELEMENTS AND IC CHIPS EMPLOYING EDGE CONTACT CONNECTIONS - Disclosed is an antenna apparatus including a substrate having a cavity in a first outer surface thereof. The substrate has a sidewall defining a portion of the cavity, and a first edge contact is formed at the sidewall. An IC chip is disposed within the cavity and has a side surface facing the sidewall and a second edge contact formed on the side surface electrically connected to the first edge contact. An antenna element, disposed at a second outer surface of the substrate opposite the first outer surface, is electrically connected to RF circuitry within the IC chip through a conductive via extending within the substrate. | 2022-01-06 |
20220005771 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an antenna zone and a routing zone. The routing zone is disposed on the antenna zone, where the antenna zone includes a first insulation layer and two or more second insulation layer and a thickness of the first insulation layer is different from that of the second insulation layer. | 2022-01-06 |
20220005772 | SEMICONDUCTOR STRUCTURE CONTAINING PRE-POLYMERIZED PROTECTIVE LAYER AND METHOD OF MAKING THEREOF - A method of forming a semiconductor structure includes providing a semiconductor wafer including a plurality of semiconductor dies, providing a polymerized material layer, attaching the polymerized material layer to the semiconductor wafer such that the polymerized material layer is polymerized prior to the step of attaching the polymerized material layer to the semiconductor wafer, applying and patterning an etch mask layer over the polymerized material layer, such that openings are formed through the etch mask layer, etching portions of the polymerized material layer that are proximal to the openings through the etch mask layer by applying an etchant into the openings through the etch mask layer in an etch process, and removing the etch mask layer selective to the polymerized material layer. Alternatively, a patterned polymerized material layer may be transferred from a transfer substrate to the semiconductor wafer. | 2022-01-06 |
20220005773 | SEMICONDUCTOR STRUCTURE CONTAINING PRE-POLYMERIZED PROTECTIVE LAYER AND METHOD OF MAKING THEREOF - A method of forming a semiconductor structure includes providing a semiconductor wafer including a plurality of semiconductor dies, providing a polymerized material layer, attaching the polymerized material layer to the semiconductor wafer such that the polymerized material layer is polymerized prior to the step of attaching the polymerized material layer to the semiconductor wafer, applying and patterning an etch mask layer over the polymerized material layer, such that openings are formed through the etch mask layer, etching portions of the polymerized material layer that are proximal to the openings through the etch mask layer by applying an etchant into the openings through the etch mask layer in an etch process, and removing the etch mask layer selective to the polymerized material layer. Alternatively, a patterned polymerized material layer may be transferred from a transfer substrate to the semiconductor wafer. | 2022-01-06 |
20220005774 | MICRODEVICE CARTRIDGE STRUCTURE - What is disclosed is structures and methods of integrating micro devices into system substrate. Further, the disclosure, also relates to methods and structures for enhancing the bonding process of micro-devices into a substrate. More specifically, it relates to expanding the micro device area or bonding area of micro devices. | 2022-01-06 |
20220005775 | STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD FOR BONDING TWO SUBSTRATES - A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad. | 2022-01-06 |
20220005776 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - A solid-state imaging device capable of achieving a further decrease in size such as a further decrease in height, a further increase in speed of wiring, and a further increase in density of wiring is to be provided. | 2022-01-06 |
20220005777 | SEMICONDUCTOR ASSEMBLY WITH DISCRETE ENERGY STORAGE COMPONENT - A semiconductor assembly, comprising: a first semiconductor die including processing circuitry and pads, said first semiconductor die having a first surface and a second surface opposite the first surface; a second semiconductor die including memory circuitry and pads, said second semiconductor die being arranged on one of the first surface and the second surface of said first semiconductor die, and pads of said second semiconductor die being coupled to pads of said first semiconductor die; and at least a first capacitor having terminals, said first capacitor being arranged on one of the first surface and the second surface of said first semiconductor die and the terminals of said capacitor being coupled to pads of said first semiconductor die. | 2022-01-06 |
20220005778 | SEMICONDUCTOR DEVICE WITH A HETEROGENEOUS SOLDER JOINT AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device with a heterogeneous solder joint includes: providing a semiconductor die; providing a coupled element; and soldering the semiconductor die to the coupled element with a first solder joint. The first solder joint includes: a solder material including a first metal composition; and a coating including a second metal composition, different from the first metal composition, the coating at least partially covering the solder material. The second metal composition has a greater stiffness and/or a higher melting point than the first metal composition. | 2022-01-06 |
20220005779 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a wiring board; a first semiconductor chip including a first surface, a second surface, and a connection bump on the first surface, the first semiconductor chip coupled to the wiring board through the connection bump; a resin layer covering the connection bump between the first semiconductor chip and the wiring board, an upper surface of the resin layer parallel to the second surface of the first semiconductor chip; and a second semiconductor chip including a third surface, a fourth surface, and an adhesive layer on the third surface, the second semiconductor chip adhering to the second surface of the first semiconductor chip and the upper surface of the resin layer through the adhesive layer. The upper surface of the resin layer projects outside a portion of at least an outer edge of the second semiconductor chip when viewed from the top. | 2022-01-06 |
20220005780 | ELECTRONIC DEVICE AND MANUFACTURING METHOD OF ELECTRONIC DEVICE - An electronic device comprising: an array substrate having a first electrode and a second electrode; a first connecting member arranged on the first electrode; a first LED chip mounted on the first connecting member; a second connecting member arranged on the second electrode and being thicker than the first connecting member; and a second LED chip mounted on the second connecting member. A distance from a reference surface of the array substrate to a top surface of the second connecting member is larger than a distance from the reference surface to a top surface of the first connecting member. | 2022-01-06 |
20220005781 | PALLADIUM-COATED COPPER BONDING WIRE, MANUFACTURING METHOD OF PALLADIUM-COATED COPPER BONDING WIRE, WIRE BONDING STRUCTURE USING THE SAME, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A Pd-coated Cu bonding wire of an embodiment contains Pd of 1.0 to 4.0 mass %, and a S group element of 50 mass ppm or less in total (S of 5.0 to 12.0 mass ppm, Se of 5.0 to 20.0 mass ppm, or Te of 15.0 to 50 mass ppm). At a crystal plane of a cross section of the wire, a <100> orientation ratio is 15% or more, and a <111> orientation ratio is 50% or less. When a free air ball is formed on the wire and a tip portion is analyzed, a Pd-concentrated region is observed on the surface thereof. | 2022-01-06 |
20220005782 | SEMICONDUCTOR DIE WITH MULTIPLE CONTACT PADS ELECTRICALLY COUPLED TO A LEAD OF A LEAD FRAME - The present disclosure is directed to a semiconductor die with multiple contact pads electrically coupled to a single lead via a single wire, and methods for fabricating the same. In one or more embodiments, multiple contact pads are electrically coupled to each other by a plurality of conductive layers stacked on top of each other. The uppermost conductive layer is then electrically coupled to a single lead via a single wire. | 2022-01-06 |
20220005783 | PRESSURE-CONTACT-TYPE SEMICONDUCTOR DEVICE - The present invention has an object to enhance manufacturability of a pressure-contact-type semiconductor device. A pressure-contact-type semiconductor device according to the present invention includes: a semiconductor chip, the semiconductor chip including a guard ring and a gate signal input/output part in the first main surface; a first external electrode being formed on a side of the first main surface of the semiconductor chip; a conductive pattern being formed on the first external electrode; a contact pin connecting the gate signal input/output part and the conductive pattern; a plate-like electrode being provided on the second main surface of the semiconductor chip; a disc spring being provided on the plate-like electrode; and a second external electrode being provided on the disc spring, the second external electrode and the first external electrode interposing the semiconductor chip. | 2022-01-06 |
20220005784 | LAYER STRUCTURES FOR MAKING DIRECT METAL-TO-METAL BONDS AT LOW TEMPERATURES IN MICROELECTRONICS - Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150° C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations. | 2022-01-06 |
20220005785 | METHOD FOR COLLECTIVE PRODUCTION OF A PLURALITY OF SEMICONDUCTOR STRUCTURES - A process for collectively fabricating a plurality of semiconductor structures comprises providing a substrate including a carrier having a main face, a dielectric layer on the main face of the carrier and a plurality of crystalline semiconductor growth islands on the dielectric layer. At least one crystalline semiconductor active layer is formed on the growth islands. After the step of forming the active layer, trenches are formed in the active layer and in the growth islands in order to define the plurality of semiconductor structures. | 2022-01-06 |
20220005786 | METHOD FOR FABRICATING ELECTRONIC PACKAGE - An electronic package and a method for fabricating the same are provided. Two packaging modules are stacked on each other. An area that an electronic package occupies a mother board is reduced during a subsequent process of fabricating an electronic product. Therefore, the electronic product has a reduced size. | 2022-01-06 |
20220005787 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - In one example, a semiconductor device comprises a first base substrate comprising a first base conductive structure, a first encapsulant contacting a lateral side of the first base substrate, a redistribution structure (RDS) substrate over the base substrate and comprising an RDS conductive structure coupled with the first base conductive structure, a first electronic component over the RDS substrate and over a first component terminal coupled with the RDS conductive structure, and a second encapsulant over the RDS substrate and contacting a lateral side of the first electronic component. Other examples and related methods are also disclosed herein. | 2022-01-06 |
20220005788 | SYSTEMS AND METHODS FOR POWERING AN INTEGRATED CIRCUIT HAVING MULTIPLE INTERCONNECTED DIE - The power on wafer assembly can include: a compliant connector, an integrated circuit, a printed circuit board (PCB), a power component, and a set of compliant connectors. The power on wafer assembly can optionally include: a compression element, a cooling system, a set of mechanical clamping components, and a power source. However, the power on wafer assembly can additionally or alternately include any other suitable components. | 2022-01-06 |
20220005789 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first and second substrates; and a first and second element layers respectively provided on an upper surface of the first and the second substrates. The first and second substrates respectively include a first and second vias. The first and second element layers respectively includes a first and second pads respectively electrically coupled to the first and second vias, and respectively provided on an upper surface of the first and second element layers. The upper surface of the second element layer is arranged so as to be opposed to the upper surface of the first element layer. The first and second pads are electrically coupled and symmetrically arranged with respect to a surface where the first and second element layers are opposed to each other. | 2022-01-06 |
20220005790 | DISPLAY DEVICE, DISPLAY MODULE, AND ELECTRONIC DEVICE - A display device with high display quality is provided. A display device with low power consumption is provided. In the display device, a first transistor, a second transistor, a first conductive layer, and a light-emitting diode package are included in a pixel. The light-emitting diode package includes a first light-emitting diode, a second light-emitting diode, a second conductive layer, a third conductive layer, and a fourth conductive layer. The first light-emitting diode includes a first electrode and a second electrode. The second light-emitting diode includes a third electrode and a fourth electrode. One of a source and a drain of the first transistor is electrically connected to the first electrode through the second conductive layer. One of a source and a drain of the second transistor is electrically connected to the third electrode through the third conductive layer. The first conductive layer is electrically connected to each of the second electrode and the fourth electrode through the fourth conductive layer. A constant potential is supplied to the first conductive layer. | 2022-01-06 |
20220005791 | DISPLAY PANEL, PREPARATION METHOD THEREOF AND DISPLAY DEVICE - Provided are a display panel and a preparation method of the display panel. The display panel includes a first substrate and a second substrate which are disposed opposite to each other, a plurality of light-emitting elements arranged between the first substrate and the second substrate and a plurality of auxiliary structures arranged between the first substrate and the second substrate; where the plurality of auxiliary structures surround the plurality of light-emitting elements and each auxiliary structure is provided with a notch structure on a side of the each auxiliary structure close to a respective one of the plurality of light-emitting elements and on a side of the each auxiliary structure close to a light-emitting surface of the display panel. | 2022-01-06 |
20220005792 | LIGHT EMITTING DEVICE AND DISPLAY APPARATUS HAVING THE SAME - A light emitting device including a first LED stack, a second LED stack disposed under the first LED stack, a third LED stack disposed under the second LED stack, and a plurality of pillars disposed adjacent to side surfaces of the first, second, and third LED stacks, the pillars including a first pillar commonly electrically connected to the first, second, and third LED stacks, and a second pillar, a third pillar, and a fourth pillar electrically connected to the first, second, and third LED stacks, respectively. | 2022-01-06 |
20220005793 | SEMICONDUCTOR PACKAGE - A semiconductor package is provided. The semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a heat sink structure comprising a lower heat sink pattern disposed on the first semiconductor chip, a metal film pattern disposed on the lower heat sink pattern, and an insulating film disposed on side walls of the lower heat sink pattern and side walls of the metal film pattern, an interposer disposed on the heat sink structure, and a solder ball which connects the heat sink structure and the interposer. | 2022-01-06 |
20220005794 | MICRO LIGHT-EMITTING ASSEMBLY, MICRO LIGHT-EMITTING DEVICE MANUFACTURED FROM THE SAME AND METHOD FOR MASS TRANSFER OF MICRO LIGHT-EMITTING DEVICES - A micro light-emitting assembly includes a base and at least one micro light-emitting device. The base contains a transitional substrate, a supporting layer disposed on the transitional substrate, and at least one supporting pillar having a bottom portion connected to the supporting layer and a top portion opposite to the bottom portion. The micro light-emitting device is supportively connected to the top portion of the supporting pillar. The micro light-emitting device has a recess-forming surface and a recess extending inwardly from the recess-forming surface to receive the top portion of the supporting pillar. A micro light-emitting device manufactured from the micro light-emitting assembly, and a method for mass transfer of micro light-emitting devices are also disclosed. | 2022-01-06 |
20220005795 | INTEGRATED COMPONENT AND PORWER SWITCHING DEVICE - The present application provides an integrated device, and a power switching device comprising the integrated device. The integrated device comprises a substrate, a die arranged inside the substrate, at least one capacitor arranged on a surface of the substrate, wherein the die and the at least one capacitor are electrically connected. The power switching device comprises at least one integrated device according to the aforementioned embodiments of the present application. The compact design of the integrated device enables a high frequency, high efficiency, high power density power switching device. | 2022-01-06 |
20220005796 | DISPLAY DEVICE AND TILED DISPLAY DEVICE INCLUDING THE SAME - A display device comprises a substrate including emission areas, and light blocking areas adjacent to the emission areas, a thin film transistor layer comprising a thin film transistor disposed on the substrate, and a connection line electrically connected to the thin film transistor, a light emitting element layer disposed on the thin film transistor layer and comprising light emitting elements corresponding to the emission areas, an encapsulation layer overlapping the light emitting element layer, and a pad portion disposed on the encapsulation layer and in electrical contact with the connection line through a contact hole in the encapsulation layer. | 2022-01-06 |
20220005797 | DISPLAY DEVICE - A display device comprises a first substrate, a conductive layer including a first electrode on the first substrate, an interlayer insulating layer on the conductive layer, a via layer on the interlayer insulating layer and including a hole exposing a part of a top surface of the interlayer insulating layer, a second electrode spaced apart from the hole and on the via layer, light emitting elements inside the hole of the via layer, a first contact electrode electrically connected to the first electrode and a first end of the light emitting elements, and a second contact electrode on the via layer and electrically connected to a second end of the light emitting elements. At least a part of the light emitting elements are placed on an inner wall of the hole. | 2022-01-06 |
20220005798 | Display Systems Having Monolithic Arrays of Light-Emitting Diodes - An electronic device may include a display having a monolithic array of light-emitting diodes mounted to a surface of a substrate layer. The diodes may include contact pads. Driver circuitry may independently drive each of the diodes in the array using drive signals. The driver circuitry may be formed on a driver integrated circuit. Bond pads may be formed on a surface of the integrated circuit. Copper pillars may be grown on the bond pads. In another suitable arrangement, the driver circuitry may be formed on a driver printed circuit board coupled to an interposer by a flexible printed circuit. The interposer may include bond pads and copper pillars grown on the bond pads. The contact pads on each of the diodes may be simultaneously bonded to the copper pillars. A surface of the substrate layer may be patterned to form light redirecting elements if desired. | 2022-01-06 |
20220005799 | LIGHT EMITTING DIODE DEVICE AND METHOD OF MANUFACTURING THE SAME - A light emitting diode device includes a thin film transistor substrate having a plurality of light emitting areas, a first diode electrode and a second diode electrode on the thin film transistor substrate, a first passivation pattern between the first diode electrode and the second diode electrode, a plurality of micro light emitting diodes on the first passivation pattern, a first bridge pattern on the micro light emitting diodes and electrically connecting the first diode electrode to the micro light emitting diodes, and a second bridge pattern on the first bridge pattern and electrically connecting the second diode electrode to the micro light emitting diodes, wherein each sidewall of each of the micro light emitting diodes and each sidewall of the first passivation pattern form a same plane. | 2022-01-06 |
20220005800 | INTEGRATED CIRCUIT INCLUDING CELLS WITH DIFFERENT HEIGHTS AND METHOD OF DESIGNING THE SAME - An IC includes: a plurality of first cells placed in a series of first rows extending in a first horizontal direction and each having a first height; and a plurality of second cells placed in a series of second rows extending in the first horizontal direction and each having a second height different from the first height, wherein a total height of the series of first rows corresponds to a multiple of a height of a first multi-height cell with a maximum height among the plurality of first cells, and a total height of the series of second rows corresponds to a multiple of a height of a second multi-height cell with a maximum height among the plurality of second cells. | 2022-01-06 |
20220005801 | INTEGRATED CIRCUIT INCLUDING MULTIPLE HEIGHT CELL AND METHOD OF DESIGNING THE SAME - An integrated circuit includes a standard cell continuously arranged on a first row and on a second row, the first row and second row extending parallel with each other in a first direction, the first row and the second row adjacent to each other in a second direction crossing the first direction, a first cell separator contacting a first row boundary of the standard cell on the first row and extending in the second direction, and a second cell separator contacting a second row boundary of the standard cell on the second row and extending in the second direction. The first cell separator and the second cell separator are discontinuous on a first row to second row boundary of the first row and the second row. | 2022-01-06 |
20220005802 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A layout of a semiconductor device and a method of forming a semiconductor device, the semiconductor device include a first fin and a second fin disposed on a substrate, a gate and a spacer. The first fin and the second fin both include two opposite edges, and the gate completely covers the two opposite edges of the first fin and only covers one sidewall of the two opposite edges of the second fin. The spacer is disposed at two sides of the gate, and the spacer covers another sidewall of the two opposite edges of the second fin. | 2022-01-06 |
20220005803 | ELECTRO-STATIC DISCHARGE PROTECTION DEVICES HAVING A LOW TRIGGER VOLTAGE - An electro-static discharge (ESD) protection device includes a first well region and a second well region disposed to contact each other, a first diffusion region and a second diffusion region disposed in the first well region spaced apart from each other, a third diffusion region and a fourth diffusion region disposed in the second well region spaced apart from each other, a resistive pattern coupled to the first diffusion region through a first contact plug, a first electrode coupled to the second diffusion region through a second contact plug and electrically coupled to the resistive pattern, and a second electrode coupled to the third diffusion region through a third contact plug and coupled to the fourth diffusion region through a fourth contact plug. | 2022-01-06 |
20220005804 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device with an insulated-gate field-effect transistor and its manufacturing method. The cell region EFR defined in the first region of one main surface side of semiconductor substrate (SUB), an insulated gate-type field-effect transistor (MFET) is formed, the gate pad region GPR defined in the first region, snubber circuit SNC is formed snubber region SNR is defined. Within the first and second regions, first and second deep trenches spaced apart from each other are formed, and at least one width of the plurality of second deep trenches formed in the second region is smaller than that of the first deep trench formed in the first region. | 2022-01-06 |
20220005805 | 3D SEMICONDUCTOR APPARATUS MANUFACTURED WITH A CANTILEVER STRUCTURE AND METHOD OF MANUFACTURE THEREOF - Aspects of the disclosure provide a method of forming a semiconductor apparatus. A stack of dielectric layers is formed over a semiconductor layer on a substrate of the semiconductor apparatus. Multiple openings are formed in the stack of dielectric layers. Multiple pillars including first sub-pillars and second sub-pillars are formed in the multiple openings. A cantilever structure that includes a first cantilever beam and a second cantilever beam is formed. A cantilever supporting structure that includes a portion of a first subset of the multiple pillars is formed. The first cantilever beam connects the second cantilever beam and the cantilever supporting structure. One of the stack of dielectric layers is removed to expose first portions of the first sub-pillars and second portions of the second sub-pillars. Isolation structures are formed between the first sub-pillars and the respective second sub-pillars. | 2022-01-06 |
20220005806 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a III-V material layer, a first gate, a second gate, and a first passivation layer. The first gate and the second gate are on the III-V material layer. The first passivation layer is on the first gate. A first activation ratio of an element in the first gate is different from a second activation ratio of the element in the second gate. | 2022-01-06 |
20220005807 | MULTI-THRESHOLD VOLTAGE NON-PLANAR COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DEVICES - A device is provided. The device includes an interfacial layer on a semiconductor device channel. The device further includes a dipole layer on the interfacial layer, and a gate dielectric layer on the dipole layer. The device further includes a first work function layer associated with a first field effect transistor device; and a second work function layer associated with a second field effect transistor device, such that the first field effect transistor device and second field effect transistor device each have a different threshold voltage than a first field effect transistor device and second field effect transistor device without a dipole layer. | 2022-01-06 |
20220005808 | SEMICONDUCTOR DEVICE - A semiconductor device and a method of manufacturing a semiconductor device, the device including a substrate; a lower structure including pad patterns on the substrate, upper surfaces of the pad patterns being at an outer side of the lower structure; a plurality of lower electrodes contacting the upper surfaces of the pad patterns; a dielectric layer and an upper electrode sequentially stacked on a surface of each of the lower electrodes; and a hydrogen supply layer including hydrogen, the hydrogen supply layer being between the lower electrodes and closer to the substrate than the dielectric layer is to the substrate. | 2022-01-06 |
20220005809 | MEMORY DEVICE - A memory device includes a substrate, an active layer spaced apart from a surface of the substrate and laterally oriented in a first direction and including an opened first side, a closed second side, and a channel layer between the first side and the second side, and a word line laterally oriented in a second direction crossing the first direction while surrounding the channel layer. | 2022-01-06 |
20220005810 | 3-D DRAM CELL WITH MECHANICAL STABILITY - Described are memory devices having stacked DRAM cells, resulting in an increase in DRAM cell bit-density. The area of a unit cell is composed of a capacitor, a cell transistor, an isolation region and a connection region, where every capacitor and active region for the cell capacitor is electrically isolated. The memory cells have supporting bars. Methods of forming a memory device are described. The methods include patterning the isolation region with supporting bars, removing non-insulator layers after isolation region patterning, and filling the opened region with an insulator. | 2022-01-06 |
20220005811 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a plurality of first conductive patterns extending parallel in a first direction on a substrate, a plurality of second conductive patterns extending parallel in a second direction crossing the first direction on the substrate, a plurality of buried contacts connected to the substrate between the plurality of first conductive patterns and between the plurality of second conductive patterns, and a landing pad connected to each of the buried contacts on the plurality of buried contacts. The landing pad includes a first side surface extending in the first direction in plan view and a second side surface extending in a third direction in plan view. The third direction is different from the first direction and the second direction in plan view. | 2022-01-06 |