01st week of 2011 patent applcation highlights part 35 |
Patent application number | Title | Published |
20110003406 | FLAT PANEL DISPLAY WITH HIGH EFFICIENCY AND METHOD OF FABRICATING THE SAME - An organic light emitting device is disclosed. In one embodiment, the organic light emitting device includes red (R), green (G) and blue (B) lower electrodes formed on a substrate. R, G, B organic thin film layers are formed on the R, G, B lower electrodes, respectively. Additionally, an upper single or multilayer electrode is formed over the substrate. Portions of the upper electrode that correspond to the R, G, B organic thin film layers, respectively, are formed to each have a different thickness. Various methods for forming the upper electrode using a fine metal mask, a halftone mask, and single and multiple photolithography processes are also disclosed. | 2011-01-06 |
20110003407 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - There are provided a light emitting device and a method of manufacturing the same. A light emitting device according to the present invention includes a substrate; an N-type semiconductor layer, an active layer and a P-type semiconductor layer, sequentially formed on the substrate; one or more trenches formed to expose the N-type semiconductor layer by partially removing at least the P-type semiconductor and active layers; a first insulating layer formed on sidewalls of the trenches; and a conductive layer filled in the trenches having the first insulating layer formed therein. According to the present invention, it is possible to obtain a characteristic of uniform current diffusion, and thus, light is uniformly emitted to thereby enhance the light emitting efficiency. | 2011-01-06 |
20110003408 | FLAT PANEL DISPLAY AND METHOD FOR FABRICATING THE SAME - A flat panel display, having an anti-electrostatic configuration, comprising a plurality of gate lines and data lines formed on an insulating substrate having an emission region and a pad portion, an anti-electrostatic wire initially coupling the gate lines, and an anti-electrostatic circuit coupled to a data line. The anti-electrostatic wire between a gate line and an adjacent gate line is subsequently cut by an opening for cutting the anti-electrostatic wire to electrically isolate the respective gate lines. | 2011-01-06 |
20110003409 | LED CHIP PACKAGE STRUCTURE WITH AN EMBEDDED ESD FUNCTION AND METHOD FOR MANUFACTURING THE SAME - An LED chip package structure includes a conductive unit, a first package unit, an ESD unit, a second package unit, a light-emitting unit and a second package unit. The conductive unit has two conductive pins adjacent to each other which form a concave space between each other. The first package unit encloses one part of each conductive pin in order to form a receiving space communicating with the concave space and to expose an end side of each conductive pin. The ESD unit is received in the concave space and electrically connected between the two conductive pins. The second package unit is received in the concave space in order to cover the ESD unit. The light-emitting unit is received in the receiving space and electrically connected between the two conductive pins. The third package unit is received in the receiving space in order to cover the light-emitting unit. | 2011-01-06 |
20110003410 | METHOD OF MANUFACTURING A LIGHT EMITTING DIODE ELEMENT - A method of manufacturing a light emitting diode element is provided. A first patterned semi-conductor layer, a patterned light emitting layer, and a second patterned semi-conductor layer are sequentially formed on an epitaxy substrate so as to form a plurality of epitaxy structures, wherein the first patterned semi-conductor layer has a thinner portion in a non-epitaxy area outside the epitaxy structures. A passivation layer covering the epitaxy structures and the thinner portion is formed. The passivation layer covering on the thinner portion is partially removed to form a patterned passivation layer. A patterned reflector is formed directly on each of the epitaxy structures. The epitaxy structures are bonded to a carrier substrate. A lift-off process is performed to separate the epitaxy structures from the epitaxy substrate. An electrode is formed on each of the epitaxy structures far from the patterned reflector. | 2011-01-06 |
20110003411 | METHOD OF MANUFACTURING COLOR PRINTED CIRCUIT BOARD - Disclosed herein is a method of manufacturing a color printed circuit board. The method includes non-consecutively printing a conductive ink on a flexible insulation board in a piezoelectric inkjet manner to form an electrically conductive pattern, applying an electrically conductive bonding agent to a light emitting chip mounting portion of the electrically conductive pattern for mounting a light emitting chip, forming a waterproof layer on an overall surface of a resultant after mounting the light emitting chip on the light emitting chip mounting portion of the electrically conductive pattern to which the electrically conductive bonding agent is applied, and forming a color pattern on an overall surface of the light emitting diode using a color ink. | 2011-01-06 |
20110003412 | LED PACKAGE STRUCTURE AND MANUFACTURING METHOD, AND LED ARRAY MODULE - An LED package includes a substrate having an electrically conductive portion and an electrically non-conductive portion composed of an oxide of the conductive portion; an LED mounted on the conductive portion and electrically connected to the conductive portion; a first electrode disposed on the non-conductive portion and electrically connected to the LED by a wire; and a second electrode disposed on the substrate and electrically connected to the LED. | 2011-01-06 |
20110003413 | MANUFACTURING METHOD OF SEMICONDUCTOR PHOTONIC DEVICE SUBSTRATE - In a manufacturing method of a semiconductor photonic device substrate, before multi-layer films different in material composition are successively and gradually crystal-grown in one chamber, an inter-layer growth rate model showing a relation in growth rate between each layer is defined, a growth rate of a film corresponding to at least one or more layers is obtained by actual crystal growth using an individual substrate, a growth rate of a film corresponding to other layers is estimated from the obtained growth rate by the inter-layer growth rate model, and a growth time is determined in accordance with a film thickness of each layer of the semiconductor photonic device substrate based on the actually obtained growth rate and the estimated growth rate. These steps are carried out by using a computer system connected to an MOCVD equipment, and then, a crystal growth of the semiconductor photonic device substrate is performed. | 2011-01-06 |
20110003414 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND FABRICATING METHOD THEREOF - An organic light emitting diode display device includes a switch TFT and a drive TFT formed on a substrate; an overcoat layer formed on the TFTs; a drain contact hole exposing portions of a drain electrode of the drive TFT by removing portions of the overcoat layer; a first electrode contacting to the drain electrode of the drive TFT; a bank pattern exposing an aperture area of a pixel; an organic layer formed on the first electrode; and a second electrode formed on the organic layer, wherein the bank pattern blocks regions where the drain contact hole is formed. | 2011-01-06 |
20110003415 | HIGH EFFICIENCY LIGHT-EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - A high efficiency light-emitting diode and a method for manufacturing the same are described. The high efficiency light-emitting diode comprises: a permanent substrate; a first contact metal layer and a second contact metal layer respectively deposed on two opposite surfaces of the permanent substrate; a bonding layer deposed on the second contact metal layer; a diffusion barrier layer deposed on the bonding layer, wherein the permanent substrate, the bonding layer and the diffusion barrier layer are electrically conductive; a reflective metal layer deposed on the diffusion barrier layer; a transparent conductive oxide layer deposed on the reflective metal layer; an illuminant epitaxial structure deposed on the transparent conductive oxide layer, wherein the illuminant epitaxial structure includes a first surface and a second surface opposite to the first surface; and a second conductivity type compound electrode pad deposed on the second surface of the illuminant epitaxial structure. | 2011-01-06 |
20110003416 | LIGHT EMITTING DIODE HAVING VERTICAL TOPOLOGY AND METHOD OF MAKING THE SAME - An LED having vertical topology and a method of making the same is capable of improving a luminous efficiency and reliability, and is also capable of achieving mass productivity. The method includes forming a semiconductor layer on a substrate; forming a first electrode on the semiconductor layer; forming a supporting layer on the first electrode; generating an acoustic stress wave at the interface between the substrate and semiconductor layer, thereby separating the substrate from the semiconductor layer; and forming a second electrode on the semiconductor layer exposed by the separation of the substrate. | 2011-01-06 |
20110003417 | Active matrix substrate, method of making the substrate, and display device - An active matrix substrate includes base substrate, gate lines, data lines, thin-film transistors and pixel electrodes. The gate lines are formed on the base substrate. The data lines are formed over the gate lines. Each of the data lines crosses all of the gate lines with an insulating film interposed therebetween. The thin-film transistors are formed over the base substrate. Each of the thin-film transistors is associated with one of the gate lines and operates responsive to a signal on the associated gate line. Each of the pixel electrodes is associated with one of the data lines and one of the thin-film transistors and is electrically connectable to the associated data line by way of the associated thin-film transistor. Each of the pixel electrodes and the associated thin-film transistor are connected together by way of a conductive member. Each of the pixel electrodes crosses one of the gate lines, while the conductive member for the pixel electrode crosses another one of the gate lines that is adjacent to the former gate line. | 2011-01-06 |
20110003418 | DISPLAY DEVICE INCLUDING TRANSISTOR AND MANUFACTURING METHOD THEREOF - An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced. | 2011-01-06 |
20110003419 | LASER INDUCED THERMAL IMAGING APPARATUS AND FABRICATING METHOD OF ORGANIC LIGHT EMITTING DIODE USING THE SAME - A laser induced thermal imaging apparatus and a fabricating method of organic light emitting diodes using the same, which laminate an acceptor substrate and a donor film using a magnetic force in vacuum, and are used to form a pixel array on the acceptor substrate. A substrate stage includes a magnet or magnetic substance. The acceptor substrate has a pixel region for forming first, second, and third sub-pixels, and the donor film has an organic light emission layer to be transferred to the pixel region. A laser oscillator irradiates a laser to the donor film. A contact frame is adapted to be disposed between the substrate stage and the laser oscillator, and is used to form a magnetic force with the substrate stage. The contact frame includes an opening through which the laser passes. A contact frame feed mechanism moves the contact frame in a direction of the substrate stage. | 2011-01-06 |
20110003420 | Fabrication method of gallium nitride-based compound semiconductor - The present invention discloses a method for fabricating gallium nitride(GaN)-based compound semiconductors. Particularly, this invention relates to a method of forming a transition layer on a zinc oxide (ZnO)-based semiconductor layer by the steps of forming a wetting layer and making the wetting layer nitridation. The method not only provides a function of protecting the ZnO-based semiconductor layer, but also uses the transition layer as a buffer layer for a following epitaxial growth of a GaN-based semiconductor layer, and thus, the invention may improve the crystal quality of the GaN-based semiconductor layer effectively. | 2011-01-06 |
20110003421 | METHOD OF FORMING MONOLITHIC CMOS-MEMS HYBRID INTEGRATED, PACKAGED STRUCTURES - A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contact area; applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one another contact area on the chip; applying a second insulating layer overlying the metallization layer on the at least one chip; applying at least one interfacial layer; applying at least one rigid substrate overlying the interfacial layer; and applying at least one secondary protective layer overlying the rigid substrate. | 2011-01-06 |
20110003422 | METHOD OF FORMING MONOLITHIC CMOS-MEMS HYBRID INTEGRATED, PACKAGED STRUCTURES - A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contact area; applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one another contact area on the chip; applying a second insulating layer overlying the metallization layer on the at least one chip; applying at least one interfacial layer; applying at least one rigid substrate overlying the interfacial layer; and applying at least one secondary protective layer overlying the rigid substrate. | 2011-01-06 |
20110003423 | Trench Process And Structure For Backside Contact Solar Cells With Polysilicon Doped Regions - A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the P-type doped region from the N-type doped region. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. The trench structure may include a textured surface for increased solar radiation collection. Among other advantages, the resulting structure increases efficiency by providing isolation between adjacent P-type and N-type doped regions, thereby preventing recombination in a space charge region where the doped regions would have touched. | 2011-01-06 |
20110003424 | Back Side Contact Solar Cell Structures And Fabrication Processes - In one embodiment, active diffusion junctions of a solar cell are formed by diffusing dopants from dopant sources selectively deposited on the back side of a wafer. The dopant sources may be selectively deposited using a printing method, for example. Multiple dopant sources may be employed to form active diffusion regions of varying doping levels. For example, three or four active diffusion regions may be fabricated to optimize the silicon/dielectric, silicon/metal, or both interfaces of a solar cell. The front side of the wafer may be textured prior to forming the dopant sources using a texturing process that minimizes removal of wafer material. Openings to allow metal gridlines to be connected to the active diffusion junctions may be formed using a self-aligned contact opening etch process to minimize the effects of misalignments. | 2011-01-06 |
20110003425 | Process for making multi-crystalline silicon thin-film solar cells - Dichlorosilane and diborane are deposited on the titanium-based alloy film to grow a p | 2011-01-06 |
20110003426 | PHOTOELECTRIC CONVERSION DEVICE METHOD FOR PRODUCING PHOTOELECTRIC CONVERSION DEVICE AND IMAGE PICKUP SYSTEM - A photoelectric conversion device includes a photoelectric conversion region having a plurality of photoelectric conversion elements and a first MOS transistor configured to read a signal in response to an electric charge of each photoelectric conversion element; and a peripheral circuit region having a second MOS transistor configured to drive the first MOS transistor and/or amplify the signal read from the photoelectric conversion region, the photoelectric conversion region and the peripheral circuit region being located on the same semiconductor substrate, wherein an impurity concentration in a drain of the first MOS transistor is lower than an impurity concentration in a drain of the second MOS transistor. | 2011-01-06 |
20110003427 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer including a channel formation region using an oxide semiconductor layer, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer. | 2011-01-06 |
20110003428 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer having a channel formation region, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer and reduce impurities such as moisture. Moreover, the oxide semiconductor layer subjected to the heat treatment is slowly cooled under an oxygen atmosphere. | 2011-01-06 |
20110003429 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a method to manufacture a thin film transistor having an oxide semiconductor as a channel formation region. The method includes; forming an oxide semiconductor layer over a gate insulating layer; forming a source and drain electrode layers over and in contact with the oxide semiconductor layer so that at least portion of the oxide semiconductor layer is exposed; and forming an oxide insulating film over and in contact with the oxide semiconductor layer. The exposed portion of the oxide semiconductor may be exposed to a gas containing oxygen in the presence of plasma before the formation of the oxide insulating film. The method allows oxygen to be diffused into the oxide semiconductor layer, which contributes to the excellent characteristics of the thin film transistor. | 2011-01-06 |
20110003430 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - An object is to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, impurities such as moisture existing in the gate insulating layer are reduced before formation of the oxide semiconductor film, and then heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor film and reduce impurities such as moisture. After that, slow cooling is performed in an oxygen atmosphere. Besides impurities such as moisture existing in the gate insulating layer and the oxide semiconductor film, impurities such as moisture existing at interfaces between the oxide semiconductor film and upper and lower films provided in contact therewith are reduced. | 2011-01-06 |
20110003431 | METHOD OF DIE REARRANGEMENT PACKAGE STRUCTURE HAVING PATTERNED UNDER BUMP METALLURGIC LAYER CONNECTING METAL LEAD - A die rearrangement package structure is provided and includes a die; an encapsulated structure is covered around the four sides of the die to expose the active surface and the reverse side of the die; a patterned protective layer is formed on the encapsulated structure and the active surface of the die, and the pads is to be exposed; one end of fan-out patterned metal layer is electrically connected the pads and other end is extended to cover the patterned protective layer; patterned second protective layer is provided to cover the patterned metal layer to expose the portions surface of the patterned metal layer; patterned UBM layer is formed on the exposed surface of the patterned metal layer; and a conductive component is formed on the patterned UBM layer, and electrically connected the patterned metal layer. | 2011-01-06 |
20110003432 | FLIP CHIP MLP WITH FOLDED HEAT SINK - A semiconductor package assembly including a molded leadless package (MLP) having an exposed top emitter pad and an exposed bottom source pad. A folded heat sink is attached to the exposed top emitter pad of the MLP by a soft solder attach process. The folded heat sink has a planar member generally coextensive in size with the MLP and in electrical and thermal contact with the top emitter pad of the MLP, and also has one or more leads extending generally perpendicularly to the planar member in a direction towards the lower surface of the MLP. These heat sink leads may provide the emitter connection to a printed circuit (PC) board. | 2011-01-06 |
20110003433 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A disclosed device includes a manufacturing method of semiconductor device including preparing a semiconductor substrate including semiconductor chip forming regions, scribing regions surrounding these regions, and cutting regions formed in the scribing regions and narrower than the scribing regions, forming check patterns and semiconductor chips, forming a resist film, forming through grooves narrower than the scribing regions and wider than the check patterns and the cutting regions, removing the check patterns with a wet blast process using the resist film and collectively forming grooves at portions of a protection film and the semiconductor substrate facing the through grooves, removing the resist film, forming internal connection terminals on the contacting faces, forming an insulating resin layer, forming a wiring forming face by removing until connecting faces are exposed, forming wiring patterns, and cutting the semiconductor substrate, the insulating resin layer, and a solder resist layer to separate into individual semiconductor devices. | 2011-01-06 |
20110003434 | SEMICONDUCTOR CHIP PACKAGE STRUCTURE FOR ACHIEVING FACE-UP ELECTRICAL CONNECTION WITHOUT USING A WIRE-BONDING PROCESS AND METHOD FOR MAKING THE SAME - A semiconductor chip package structure for achieving face-up electrical connection without using a wire-bonding process includes a package unit, a semiconductor chip, a substrate unit, a first insulative unit, a first conductive unit, a second conductive unit, and a second insulative unit. The package unit has a central receiving groove and an outer receiving groove formed around the central receiving groove. The semiconductor chip has a plurality of conductive pads. The first insulative unit has a first insulative layer formed between the conductive pads. The first conductive unit has a plurality of first conductive layers. The second conductive unit has a plurality of second conductive layers formed on the first conductive layers. The second insulative unit is formed between the first conductive layers and between the second conductive layers. | 2011-01-06 |
20110003435 | ELECTROMAGNETIC SHIELD FORMATION FOR INTEGRATED CIRCUIT DIE PACKAGE - Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure. | 2011-01-06 |
20110003436 | Placement Method of an Electronic Module on a Substrate - The aim the disclosed process is to ensure maximum precision both at the level of the manufacturing of an electronic assembly from a chip with small dimensions as well as the level of the placement of such an assembly on an insulating substrate. This aim is achieved by a placement process on a substrate, of at least one electronic assembly comprising a chip having at least one electric contact on one of its faces, said contact being intended to be electrically connected to a conductive track segment. The electronic assembly is built on a holding device which seizes and holds at least one conductive track segment previously formed and a chip. A placement device places this electronic assembly thus built at a predetermined position relative to the substrate and embeds or inserts said electronic assembly into the substrate. | 2011-01-06 |
20110003437 | METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A POST/BASE/FLANGE HEAT SPREADER AND A CAVITY IN THE FLANGE - A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a first conductive layer on the adhesive including aligning the post with an aperture in the first conductive layer, then flowing the adhesive between the post and the first conductive layer, solidifying the adhesive, then etching the post to form a first cavity in the adhesive above the post, depositing a second conductive layer into the first cavity to form a second cavity that extends into the first cavity, providing a conductive trace that includes a pad, a terminal and a selected portion of the first conductive layer, providing a heat spreader that includes the post, the base and a flange that includes a selected portion of the second conductive layer that defines the second cavity, mounting a semiconductor device on the flange in the second cavity, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader. | 2011-01-06 |
20110003438 | THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE - A method of forming a semiconductor structure includes coupling a semiconductor structure to an interconnect region through a bonding region. The interconnect region includes a conductive line in communication with the bonding region. The bonding region includes a metal layer which covers the interconnect region. The semiconductor structure is processed to form a vertically oriented semiconductor device. | 2011-01-06 |
20110003439 | SEMICONDUCTOR DEVICE PACKAGE HAVING FEATURES FORMED BY ELECTROPLATING - Embodiments in accordance with the present invention relate to the fabrication of packages for semiconductor devices, and in particular to the use of electroplating techniques to form features on the surface of a metal lead frame. In accordance with one embodiment, electroplating is used to fabricate non-integral pin portions shaped to remain securely encapsulated within the plastic molding of the package. In accordance with another embodiment, electroplating may be used to fabricate protrusions on the underside of the lead frame for elevating the package above the PC board, thereby preserving the rounded shape of solder balls used to secure the diepad to the PC board. In accordance with yet another embodiment, electroplating may be used to fabricate raised patterns on the upper surface of the diepad for ensuring uniform spreading of adhesive used to secure the die to the diepad, thereby ensuring level attitude of the die within the package. | 2011-01-06 |
20110003440 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device or a substrate is described. The method includes providing a chip attached to a carrier or providing a substrate. A foil is held over the chip and the carrier or the substrate. A laser beam is directed onto the foil, and substance at the foil is ablated and deposited on the chip and the carrier or on the substrate. | 2011-01-06 |
20110003441 | LIGHT ACTIVATED SILICON CONTROLLED SWITCH - The present invention provides an optically triggered switch and a method of forming the optically triggered switch. The optically triggered switch includes a silicon layer having at least one trench formed therein and at least one silicon diode formed in the silicon layer. The switch also includes a first thyristor formed in the silicon layer. The first thyristor is physically and electrically isolated from the silicon diode by the trench and the first thyristor is configured to turn on in response to electromagnetic radiation generated by the silicon diode. | 2011-01-06 |
20110003442 | METHOD FOR MANUFACTURING FLEXIBLE SEMICONDUCTOR DEVICE - A method for making a flexible semiconductor device includes the following steps. A rigid substrate is provided. A flexible substrate is provided, and placed on the rigid substrate. A semiconductor device is directly formed on the flexible substrate using a semiconductor process. After the rigid substrate is removed, the flexible semiconductor device is formed. | 2011-01-06 |
20110003443 | METHOD FOR PRODUCING A TRANSISTOR WITH METALLIC SOURCE AND DRAIN - A method for producing a transistor with metallic source and drain including the steps of:
| 2011-01-06 |
20110003444 | PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING INSULATING LAYERS HAVING DIFFERENT STRAINS - An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region. | 2011-01-06 |
20110003445 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device is provided which can uniformly form a good and thin silicon oxide film or the like at a relatively low temperature. In step | 2011-01-06 |
20110003446 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device includes an insulating layer, a channel structure, an insulating structure and a gate. The channel structure includes a channel bridge for connecting two platforms. The bottom of the channel bridge is separated from the insulating layer by a distance, and the channel bridge has a plurality of separated doping regions. The insulating structure wraps around the channel bridge, and the gate wraps around the insulating structure. | 2011-01-06 |
20110003447 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH VERTICAL TRANSISTOR - A method for fabricating a semiconductor device includes forming a plurality of first active pillars by etching a substrate using a hard mask layer as an etching barrier, forming a gate conductive layer surrounding sidewalls of the first active pillars and the hard mask layer, forming a word line conductive layer filling gaps defined by the gate conductive layer, forming word lines and vertical gates by simultaneously removing portions of the word line conductive layer and the gate conductive layer on the sidewalls of the hard mask layer, forming an inter-layer dielectric layer filling gaps formed by removing the word line conductive layer and the gate conductive layer, exposing surfaces of the first active pillars by removing the hard mask layer, and growing second active pillars over the first active pillars. | 2011-01-06 |
20110003448 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING VERTICAL-TYPE CHANNEL - A method for fabricating a semiconductor device includes the following steps. A device isolation layer with a trench type is etched in a predetermined portion of a substrate to define an active region. Predetermined portions where gate lines traverse in the device isolation layer are etched to a certain depth to form a plurality of first recesses. A pair of gate lines filling the first recesses and traversing over the active region is formed. Portions of the active region which storage nodes contact on one sides of the gate lines are etched to form a plurality of second recesses. An ion-implantation process is performed to form a plurality of first junction regions beneath the second recesses and to form a second junction region in a portion of the active region between the gate lines such that the second junction region contacts bit lines. | 2011-01-06 |
20110003449 | Power Device With Trenches Having Wider Upper Portion Than Lower Portion - A method of forming a semiconductor device includes the following. Removing portions of a silicon layer such that a trench having sidewalls which fan out near the top of the trench to extend directly over a portion of the silicon layer is formed in the silicon layer; and forming source regions in the silicon layer adjacent the trench sidewall such that the source regions extend into the portions of the silicon layer directly over which the trench sidewalls extend. | 2011-01-06 |
20110003450 | METHOD FOR MANUFACTURING SEMICONDUTOR DEVICE WITH STRAINED CHANNEL - A method for forming a semiconductor device includes forming a gate pattern over a silicon substrate, forming gate spacers over both sidewalls of the gate pattern, forming a dummy gate spacer over a sidewall of each one of the gate spacers, forming a recess region having inclined sidewalls extending in a direction to a channel region under the gate pattern by recess-etching the silicon substrate, filling the recess region with an epitaxial film, which becomes a source region or a drain region, through a selective epitaxial growth process, and removing the dummy gate spacer. | 2011-01-06 |
20110003451 | INTERMEDIATE PRODUCT FOR A MULTICHANNEL FET AND PROCESS FOR OBTAINING AN INTERMEDIATE PRODUCT - An intermediate product in the manufacture of a vertical multiple-channel FET device containing alternating —Si—[(SiGe)—Si]u- stacked layers is shown, as well as a process for selectively etching the SiGe layers in such a stacked layer system, and products obtained from such selective etching. Differential Ge content is added to the successive layers to provide uniform removal of the sacrificial SiGe layers. | 2011-01-06 |
20110003452 | HIGH-k CAPPED BLOCKING DIELECTRIC BANDGAP ENGINEERED SONOS AND MONOS - A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably includes a high-κ material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used. | 2011-01-06 |
20110003453 | MANUFACTURING METHOD OF CAPACITOR IN SEMICONDUCTOR - A manufacturing method of a capacitor of a semiconductor device includes a first step of forming a graphene seed film over a substrate; a second step of increasing surface energy of the graphene seed film and performing a first plasma process to the graphene seed film; a third step of growing a graphene on the graphene seed film; a fourth step of growing a nano tube or a nano wire using the graphene as a mask; and a fifth step of sequentially forming a dielectric film and a conductive layer over the nano tube or the nano wire. | 2011-01-06 |
20110003454 | LATERAL PHASE CHANGE MEMORY - A lateral phase change memory includes a pair of electrodes separated by an insulating layer. The first electrode is formed in an opening in an insulating layer and is cup-shaped. The first electrode is covered by the insulating layer which is, in turn, covered by the second electrode. As a result, the spacing between the electrodes may be very precisely controlled and limited to very small dimensions. The electrodes are advantageously formed of the same material, prior to formation of the phase change material region. | 2011-01-06 |
20110003455 | METHODS FOR FABRICATING IMPROVED GATE DIELECTRICS - Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPDX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPDX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region. | 2011-01-06 |
20110003456 | SILICON CARBIDE AND RELATED WIDE-BANDGAP TRANSISTORS ON SEMI INSULATING EPITAXY - A method of making a semi-insulating epitaxial layer includes implanting a substrate or a first epitaxial layer formed on the substrate with boron ions to form a boron implanted region on a surface of the substrate or on a surface of the first epitaxial layer, and growing a second epitaxial layer on the boron implanted region of the substrate or on the boron implanted region of the first epitaxial layer to form a semi-insulating epitaxial layer. | 2011-01-06 |
20110003457 | SEMICONDUCTOR COMPONENT WITH TRENCH INSULATION AND CORRESPONDING PRODUCTION METHOD - The invention relates to a semiconductor component with trench isolation and to an associated fabrication method, a trench isolation (STI, TTI) having a deep isolation trench with a covering insulation layer ( | 2011-01-06 |
20110003458 | METHOD OF FORMING DEVICE ISOLATION LAYER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided are a method of forming a device isolation layer and a method of fabricating a semiconductor device. The method includes: forming a first trench and a second trench in a substrate, wherein the second trench is connected to the first trench and has a width smaller than the first trench; forming a liner insulation layer in the second trench such that the liner insulation layer is buried in the second trench; and forming a gap fill insulation layer on the liner insulation layer such that the gap fill insulation layer is buried in the first trench. | 2011-01-06 |
20110003459 | METHOD FOR FABRICATING BURIED GATE USING PRE LANDING PLUGS - A method for fabricating a semiconductor device is provided, the method includes forming a plug conductive layer over an entire surface of a substrate, etching the plug conductive layer to form landing plugs, etching the substrate between the landing plugs to form a trench, forming a gate insulation layer over a surface of the trench and forming a buried gate partially filling the trench over the gate insulation layer. | 2011-01-06 |
20110003460 | METHOD FOR TREATING SURFACE OF SOI SUBSTRATE - A method for minimizing thickness variation of a substrate in an anneal step and achieving the smoothing of the surface of the substrate. Specifically provided is a method for treating the surface of a SOI substrate, including the steps of treating the surface of the SOI substrate by the PACE method using a plasma or the GCIB method using a gas cluster ion beam and subjecting the treated substrate to a heat treatment in argon atmosphere or an inert gas atmosphere containing 4 vol % or less of hydrogen so that the treated SOI substrate can be annealed. | 2011-01-06 |
20110003461 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An SOI substrate having a single crystal semiconductor layer with high surface planarity is manufactured. A semiconductor substrate is doped with hydrogen, whereby a damaged region which contains large quantity of hydrogen is formed. After a single crystal semiconductor substrate and a supporting substrate are bonded together, the semiconductor substrate is heated, whereby the single crystal semiconductor substrate is separated in the damaged region. While a heated high-purity nitrogen gas is sprayed on a separation plane of the single crystal semiconductor layer separated from the single crystal semiconductor substrate, laser beam irradiation is performed. By irradiation with a laser beam, the single crystal semiconductor layer is melted, whereby planarity of the surface of the single crystal semiconductor layer is improved and re-single-crystallization is performed. | 2011-01-06 |
20110003462 | METHOD FOR MANUFACTURING SOI WAFER - Provided is a method for manufacturing an SOI wafer, which is capable of: efficiently removing an ion-implanted defect layer existing in an ion implanted layer in the vicinity of a peeled surface peeled by an ion implantation peeling method; ensuring the in-plane uniformity of a substrate; and also achieving cost reduction and higher throughput. The method for manufacturing an SOI wafer includes at least the steps of: bonding a silicon wafer with or without an oxide film onto a handle wafer to prepare a bonded substrate, wherein the silicon wafer has an ion implanted layer formed by implanting hydrogen ions and/or rare gas ions into the silicon wafer; peeling the silicon wafer along the ion implanted layer, thereby transferring the silicon wafer onto the handle wafer to produce a post-peeling SOI wafer; immersing the post-peeling SOI wafer in an aqueous ammonia-hydrogen peroxide solution; and performing a heat treatment at a temperature of 900° C. or higher on the immersed post-peeling SOI wafer, and/or polishing a silicon film layer of the immersed post-peeling SOI wafer, through CMP polishing by 10 to 50 nm. | 2011-01-06 |
20110003463 | DOPING METHOD - Methods of doping a III-V compound semiconductor film are disclosed. | 2011-01-06 |
20110003464 | METHODS OF USING A SILICON NANOPARTICLE FLUID TO CONTROL IN SITU A SET OF DOPANT DIFFUSION PROFILES - A method of forming a multi-doped junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front substrate surface, and depositing an ink on the front substrate surface in an ink pattern, the ink comprising a set of nanoparticles and a set of solvents. The method further includes heating the substrate in a baking ambient to a first temperature of between about 200° C. and about 800° C. and for a first time period of between about 3 minutes and about 20 minutes in order to create a densified film ink pattern. The method also includes exposing the substrate to a dopant source in a diffusion furnace with a deposition ambient, the deposition ambient comprising POCl | 2011-01-06 |
20110003465 | Methods of forming a multi-doped junction with silicon-containing particles - A method of forming a multi-doped junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front substrate surface. The method further includes depositing an ink on the front substrate surface in a ink pattern, the ink comprising a set of silicon-containing particles and a set of solvents. The method also includes heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a densified film ink pattern. The method further includes exposing the substrate to a dopant source in a diffusion furnace with a deposition ambient, the deposition ambient comprising POCl | 2011-01-06 |
20110003466 | METHODS OF FORMING A MULTI-DOPED JUNCTION WITH POROUS SILICON - A method of forming a multi-doped junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front crystalline substrate surface; and forming a mask on the front crystalline substrate surface, the mask comprising exposed mask areas and non-exposed mask areas. The method also includes exposing the mask to an etchant, wherein porous silicon is formed on the front crystalline substrate surface defined by the exposed mask areas; and removing the mask. The method further includes exposing the substrate to a dopant source in a diffusion furnace with a deposition ambient, the deposition ambient comprising POCl | 2011-01-06 |
20110003467 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes the following processes. A nitrogen-diffusion region is selectively formed in a semiconductor substrate having first and second regions. The nitrogen-diffusion region is at a shallow level of the first region. A first heat treatment is carried out to form a first oxide layer over the semiconductor substrate. The first oxide layer includes first and second portions. The first portion is in the first region. The second portion is in the second region. The first portion is thinner than the second portion. | 2011-01-06 |
20110003468 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED GATES - A method for fabricating a semiconductor device, including forming a trench by etching a semiconductor substrate, forming a gate insulation layer over a surface of the trench, forming a gate conductive layer over the gate insulation layer, performing a first recess process by etching the gate conductive layer, forming a protection pattern over the gate insulation layer, and performing a second recess process by etching the gate conductive layer. | 2011-01-06 |
20110003469 | Methods Of Forming Memory Cells; And Methods Of Forming Vertical Structures - Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions. | 2011-01-06 |
20110003470 | METHODS AND STRUCTURES FOR A VERTICAL PILLAR INTERCONNECT - In wafer-level chip-scale packaging and flip-chip packaging and assemblies, a solder cap is formed on a vertical pillar. In one embodiment, the vertical pillar overlies a semiconductor substrate. A solder paste, which may be doped with at least one trace element, is applied on a top surface of the pillar structure. A reflow process is performed after applying the solder paste to provide the solder cap. | 2011-01-06 |
20110003471 | Fabrication of interconnects in a low-k interlayer dielectrics - A method for forming deep lithographic interconnects between a first metal and a second metal is provided. The method comprises depositing a first insulator layer on a semiconductor substrate; etching the first insulator layer at a selected location to provide at least a first via to the semiconductor substrate; depositing the first metal on the semiconductor substrate to form at least a first metal contact plug in the first via in contact with the semiconductor substrate; treating the semiconductor substrate with an in-situ plasma of a nitrogen containing gas wherein the plasma forms a nitride layer of the first metal at least capping a top surface of the first metal plug in the first via; and forming a second metal contact to the metal nitride layer capping at least the top surface of the first metal plug. | 2011-01-06 |
20110003472 | WIRING SUBSTRATE FOR MOUNTING SEMICONDUCTORS, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE - A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates. | 2011-01-06 |
20110003473 | STRUCTURE FOR METAL CAP APPLICATIONS - An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material. | 2011-01-06 |
20110003474 | Germanium-Containing Dielectric Barrier for Low-K Process - A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a conductive wiring in the first dielectric layer; and a copper germanide nitride layer over the conductive wiring. | 2011-01-06 |
20110003475 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for producing a semiconductor device including a first conductor disposed on a semiconductor substrate; an oxygen-containing insulation film disposed on the semiconductor substrate and on the first conductor, the insulation film having a contact hole which extends to the first conductor and a trench which is connected to an upper portion of the contact hole; a zirconium oxide film disposed on a side surface of the contact hole and a side surface and a bottom surface of the trench; a zirconium film disposed on the zirconium oxide film inside the contact hole and inside the trench; and a second conductor composed of Cu embedded into the contact hole and into the trench. | 2011-01-06 |
20110003476 | METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING LANDING PADS FORMED BY ELECTROLESS PLATING - A semiconductor device in which an increase of contact resistance Rc between a metal contact and a plug due to misalignment between the metal contact and the plug can be reduced and the difficulty of a Cu filling process during the process of forming the plug may be reduced. The semiconductor device includes a substrate including an active area and a device isolation layer; a metal contact that is formed on the substrate and is electrically connected to the active area; a landing pad formed on the metal contact by electroless plating; and a plug that is formed on the landing pad and is electrically connected to the metal contact via the landing pad. | 2011-01-06 |
20110003477 | METHODS OF FORMING A SEMICONDUCTOR DEVICE INCLUDING A METAL SILICON NITRIDE LAYER - Provided are methods of forming a semiconductor device. The methods include providing a first precursor and a substitute gas into a reaction chamber having a substrate therein, the first precursor having a first substituent and further providing a second precursor into the reaction chamber. Either the first precursor or the second precursor includes a metal element and the other includes a silicon element, at least one of the first substituents of the first precursor are substituted with the substitute gas, the first precursor substituted with the substitute gas is adsorbed onto the substrate, and the second precursor is reacted with the adsorbed first precursor. | 2011-01-06 |
20110003478 | POLYMER FOR ORGANIC ANTI-REFLECTIVE COATING LAYER AND COMPOSITION INCLUDING THE SAME - A polymer which has siloxane group at a main chain thereof and a composition including the same, for forming an organic anti-reflective coating layer are disclosed. The polymer for forming an organic anti-reflective coating layer is represented by following Formula. | 2011-01-06 |
20110003479 | METHODS OF MAKING SELF-ALIGNED NANO-STRUCTURES - A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer layer over the dielectric layer. The polymer layer is applied uniformly and fills the apertures at different rates depending on the geometry of the apertures, or on the presence or absence of growth accelerating material. The polymer creates spacers for the etching of additional structure in between the spacers. The method is capable of achieving structures smaller than current lithography techniques. | 2011-01-06 |
20110003480 | Silsesquioxane Resins - This invention pertains to silsesquioxane resins useful in antireflective coatings wherein the silsesquioxane resin is comprised of the units (Ph(CH | 2011-01-06 |
20110003481 | Method for manufacturing a semiconductor device - It is made possible to restrain generation of defects at the time of insulating film formation. A method for manufacturing a semiconductor device, includes: placing a semiconductor substrate into an atmosphere, thereby forming a nitride film on a surface of the semiconductor substrate, the atmosphere containing a first nitriding gas nitriding the surface of the semiconductor substrate and a first diluent gas not actually reacting with the semiconductor substrate, the ratio of the sum of the partial pressure of the first diluent gas and the partial pressure of the first nitriding gas to the partial pressure of the first nitriding gas being 5 or higher, and the total pressure of the atmosphere being 40 Torr or lower. | 2011-01-06 |
20110003482 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING SYSTEM - Provided is a method of manufacturing a semiconductor device. In the method, an aluminium-containing insulation film is formed on an electrode film of a substrate by alternately repeating a process of supplying an aluminium precursor into a processing chamber in which the substrate is accommodated and exhausting the aluminium precursor from the processing chamber and a process of supplying an oxidizing or nitriding precursor into the processing chamber and exhausting the oxidizing or nitriding precursor from the processing chamber; and a high permittivity insulation film different from the aluminium-containing insulation film is formed on the aluminium-containing insulation film by alternately repeating a process of supplying a precursor into the processing chamber and exhausting the precursor from the processing chamber and a process of supplying an oxidizing precursor into the processing chamber and exhausting the oxidizing precursor from the processing chamber. In addition, heat treatment is performed on the substrate. | 2011-01-06 |
20110003483 | GLASS PLATE FOR DISPLAY PANELS, PROCESS FOR PRODUCING IT, AND PROCESS FOR PRODUCING TFT PANEL - To provide a glass plate for display panels which has a low 8 | 2011-01-06 |
20110003484 | MASK FOR CRYSTALLIZING SILICON, APPARATUS HAVING THE MASK AND METHOD OF CRYSTALLIZING WITH THE MASK - A mask for crystallizing silicon includes a first, a second, and a third pattern part arranged in a longitudinal direction, each of the first, second, and third pattern parts including a plurality of unit blocks for transmitting and blocking a portion of light. At least two of the first, second and third pattern parts have a corresponding pattern to each other. Advantageously, scans using the aforementioned mask effectively remove a boundary on the silicon formed by the difference in the amount of laser beam irradiation received by the silicon, thereby improving electronic characteristics of the silicon. | 2011-01-06 |
20110003485 | Optical Cavity Furnace for Semiconductor Wafer Processing - An optical cavity furnace | 2011-01-06 |
20110003486 | ELELCTRICAL CONNECTOR WITH MAGNETIC BOARD LOCK - An electrical connector includes an insulative housing, a plurality of terminals secured in the housing, a metallic cover pivotally mounted to a rear end of the insulative housing and covering the insulative housing and at least one magnetic board lock secured at one side of the insulative housing and spaced with a distance from the rear end of the insulative housing. The at least one magnetic board lock assist to hold the cover by magnetic attractive force produced between the at least one magnetic board lock and the metallic cover on the insulative housing. | 2011-01-06 |
20110003487 | METHOD FOR REDUCING THE FITTING THRUST OF GOLDEN FINGER AND PCB - A method for reducing the fitting thrust of golden finger ( | 2011-01-06 |
20110003488 | CONNECTOR AND INTERPOSER USING CONNECTOR - A connector conducting electricity between external electrodes while the connector is being compressed, the connector including: a columnar main body made of an elastic dielectric; a first contact terminal made of an inelastic conductor including first and second electrode sections provided on a top surface and a side surface of the columnar main body and a coupling section interconnecting the first and second electrode sections; a second contact terminal made of an inelastic conductor including third and fourth electrode sections provided on a bottom surface and a side surface of the columnar main body and a coupling section interconnecting the third and fourth electrode sections, the fourth electrode section being disposed in a position in which the fourth electrode section does not contact the second electrode section; and a conductor provided outside the main body and conducting electricity between the second and fourth electrode sections. | 2011-01-06 |
20110003489 | ELECTRICAL CONNECTOR - The present invention provides an electrical connector for electrically connecting a mating device having pads, comprising: a body with a stopping portion and a plurality of terminals with contact parts contacting the pads. The terminals have a first and a second movement path. During the first path, contact part and mating device move toward stopping portion simultaneously. During the second path, contact part moves toward stopping portion relative to mating device, and the horizontal displacement of terminals is smaller than width of the pads. Compared with prior art, it is guaranteed the relative displacement between terminal and pad is reduced under the condition of fixed horizontal displacement of terminal. As the relative displacement still exists, terminal and pad can scrape the grime on surface while allowing movement of contact part within the area of the pads. | 2011-01-06 |
20110003490 | CONNECTOR AND ELECTRONIC DEVICE HAVING THE SAME - An electronic device and a connector thereof are provided. The electronic device includes a circuit board and an electronic device and the connector disposed on the circuit board. The connector includes a slot and a cap. The slot is configured for a card module to be plugged in along a plugging direction. A first pillar portion and a second pillar portion are at two opposite sides of the slot. The cap is disposed on a top of the first pillar portion and has a first protruding portion. The first protruding portion protrudes out of a side of the first pillar portion away from the second pillar portion while observing along the plugging direction. | 2011-01-06 |
20110003491 | SOCKET - The present invention relates to a socket including a connector insulatedly disposed inside the socket, the connector including contacts electrically connected to a source of input current. The socket further includes a slot for receiving an electronic card in the socket for connecting it to the connector, and a conductor for coupling the connector to at least one blade contact in the socket. According to a preferred embodiment of the present invention, the socket further includes an insulating body defining at least one plug blade receiving slot for disposing the blade contact therein, and a card slot which extends to the connector, and the electronic card is further having contacts complementary to each of the connector contacts. | 2011-01-06 |
20110003492 | BOARD HAVING CONNECTION TERMINAL - A board includes a board body; a first conductor provided at a first surface of the board body; and an electrically conductive connection terminal having a spring property. The connection terminal includes a first end part fixed to the first conductor; a second end part to be connected to a first object of connection to be placed opposite the first surface of the board body; and a projection part provided on the first end part so as to project toward the first conductor. | 2011-01-06 |
20110003493 | USB MEMORY CARD HAVING AN INSULATOR FOR RETAINING RESELIENT CONTACTS - An USB memory card ( | 2011-01-06 |
20110003494 | Electrical outlet safety device and method of use - The danger associated with an electrical plug partially withdrawn from an electrical outlet to exposed prongs of the plug while in electrical connection is reduced using a safety device comprising a resilient, compressible block of electrical insulating material mounted to a connection side of the plug. The prongs are inserted into passageways in the block that extend from one side of the block to another side of the block. With the block mounted to the plug, the user pushes the prongs into the outlet so the prongs are essentially completely within the outlet and the block is essentially completely compressed. The compressed block expands to cover the exposed, electrically connected plug portions upon partial removal of the prongs from the electrical outlet. | 2011-01-06 |
20110003495 | Electrical Connector Assembly - An electrical connector assembly has a socket, a plug, a sliding slot, and a fastener. The socket includes having a slot and a first latch disposed at one side of the slot. The plug is insertable into the slot of the socket, and is provided with a second latch corresponding to the first latch of the socket. The sliding slot is disposed on the second latch corresponding to the first latch of the socket. The fastener is positioned on the second latch of the plug. When the plug is inserted into the socket, the fastener can be moved to connect the first and second latches to fasten together the plug and socket. Furthermore, the fastener can be moved along the sliding slot in a direction away from the first latch to unfasten the plug and the socket. | 2011-01-06 |
20110003496 | CARD CONNECTOR WITH SWITCH ELEMENT - A card connector ( | 2011-01-06 |
20110003497 | FLUORESCENT LAMP HOLDER ASSEMBLY - The invention discloses a fluorescent lamp holder assembly comprising a lamp holder and a socket for receiving said lamp holder. The lamp holder has a body which houses a pair of electrical pin terminals. The body includes a pair of openings on one wall. The opening located at a position corresponds to the position of the electrical pin terminal such that each opening leads to one respective pin terminal. The lamp holder includes a pair of parallel spaced-apart electrical prongs of which one end of each electrical prong is in electrical communication with a pin terminal and the free end of each electrical prong protrudes from said body. The socket has a pair of spaced-apart electrical terminals, each having an opening capable of receiving one electrical prong of the lamp holder. The socket includes a pair of insertion holes for wire connection and includes a horizontal recess on the external walls for coupling to the luminaire. The lamp holder is coupled to the socket by means of inserting a corresponding electrical prong of the lamp holder to the corresponding terminal of the socket. | 2011-01-06 |
20110003498 | Coaxial Cable Connector Seal - A connector seal including at least one cylindrical coaxial cable connector, and an elastic sleeve rolled upon itself. The sleeve is configured to unroll to enclose at least a portion of the connector. The portion of the connector may be a connection location between two of the connectors. The portion of the connector may have at least one of differing surface shapes and differing diameters. The elastic sleeve may be fastened to an exterior portion of the connector, may be pre-positioned on the connector, and may be configured to be removed entirely from the connector. A release liner covering one side of the elastic sleeve may be rolled up with the elastic sleeve. The release liner may be elastic and may be latex. | 2011-01-06 |
20110003499 | CARD CONNECTOR - A card insertion slot in the card connector through which two types of cards, large and small cards, can be selectively installed in a card accommodation space include first and second guideways in corresponding to the sizes of the cards. The card connector includes first and second contacts, a lock bracket configured to detect the width of the large card, an actuator configured to be rotatable, and a partition member including a partition plate configured to be movable. When the large card is inserted into the card connector, the lock bracket is moved from the first position to the second position. When the large card is further fed into the card connector, the actuator is rotated from the first position to the second position, and the partition plate is moved from the first position to the second position. | 2011-01-06 |
20110003500 | ELECTRICAL CONNECTOR HAVING ADAPTER WITH HOOK SO AS TO PREVENT AND REDUCE DISTORTION OF THE ADAPTER - An electrical connector ( | 2011-01-06 |
20110003501 | CABLE INSERTION HAVING UPSTREAM MOUNTING FIXTURE - The present disclosure relates to a cable insertion ( | 2011-01-06 |
20110003502 | CABLE ASSEMBLY WITH STRAIN RELIEF MEMBER - A cable assembly ( | 2011-01-06 |
20110003503 | POWER SUPPLY WIRE RECEIVING STRUCTURE - The present invention discloses a power supply wire receiving structure comprising a cable take-up unit and a charging wire. The charging wire is applicable to an electronic device and made of bullet-proof material so as to have high tensile strength. The charging wire is flat-shaped so that it is easy to be received in the cable take-up unit. The combination of the charging wire and the cable take-up unit enables the charging wire to be received in the cable take-up unit and facilitates the arrangement of the wire. Furthermore, the cable take-up unit can be coupled to a charging unit which has an accommodating groove so that the cable take-up unit is received in the accommodating groove of charging unit to reduce the product volume and be easy to carry. | 2011-01-06 |
20110003504 | INTERFACE ELEMENT, INTERFACE ELEMENT HOLDER, AND ELECTRICAL APPLIANCE - The invention relates to an interface element to be fixed on and/or in an interface element holder of an electrical appliance, which element includes a hard component portion. The invention provides a positioning portion which is formed from an elastic material and makes it possible for the hard component portion to move relative to the interface element holder as a result of deformation. The invention also relates to an interface element holder and to an electrical appliance. | 2011-01-06 |
20110003505 | IN-FLIGHT ENTERTAINMENT SYSTEM CONNECTOR - An In-flight Entertainment (IFE) system connector assembly has a connector module receiver for provision in a seat. The receiver includes a number of pockets in which connector modules can be docked. Each connector module provides a required connector type for a device to be connected to the IFE. Modules can be replaced if different connector types are required to be supported. | 2011-01-06 |