01st week of 2013 patent applcation highlights part 35 |
Patent application number | Title | Published |
20130003406 | Attachment System for Light-Conducting Fibers - In an embodiment, an attachment system for communicating light energy from a light source to a light-conducting fiber includes a light pipe body sufficiently designed to engage a distal end of a light pipe, the light pipe body comprising at least one opening configured to dissipate heat buildup from light energy; a front assembly sufficiently designed to engage the light pipe body, the front assembly comprising an orifice and at least one opening configured to dissipate heat buildup from light energy; a light-conducting fiber body sufficiently designed to engage the front assembly and to hold a proximal portion of a light-conducting fiber, the light-conducting fiber body positioned in the orifice of the front assembly; and an optical taper assembly sufficiently designed to hold an optical taper, the optical taper assembly positioned between and spaced apart from the front assembly, and positioned between and spaced apart from the light pipe. | 2013-01-03 |
20130003407 | DISPLAY APPARATUS AND BACKLIGHT ASSEMBLY - A display apparatus includes a light source part, a light guide plate, and a display panel. The light source part includes first light sources and second light sources alternately arranged to emit a light having a color different from a color of a light emitted from the second light sources. The light guide plate includes an incident surface having at least one light incident surface facing the light source to guide the light. The display panel receives the light from the light guide plate to display an image. A distance between end portions of the incident surface and the first and second light sources disposed and corresponding to each end portion of the light incident surface is different from a distance between a center portion of the light incident surface and the first and second light sources disposed and corresponding to the center portion. | 2013-01-03 |
20130003408 | SYMMETRIC SERRATED EDGE LIGHT GUIDE FILM HAVING CIRCULAR TIP AND BASE SEGMENTS - The present invention provides a planar light guide film for a backlight unit having at least one point light source, the light guide film comprising a light input surface for receiving light from the point light source, a light redirecting surface for redirecting light received from the light input surface and a light output surface for outputting at least the light redirected from the light redirecting surface. The light input surface further comprises a composite lens structure having a circular tip segment with a first contact angle, and a first and second circular base segments with a second contact angle, the second contact angle being less than the first contact angle and the second contact angle being equal to each other. Further, the circular tip segment satisfies the following equation: | 2013-01-03 |
20130003409 | light mixing module, and a luminaire comprising such a light mixing module - A light mixing module ( | 2013-01-03 |
20130003410 | LIGHT-CONDENSING FILM HAVING SUPERIOR ANTI-ADHESION PERFORMANCE AND SUPERIOR MOIRE PREVENTION EFFECTS, BACKLIGHT UNIT COMPRISING SAME, AND DISPLAY DEVICE COMPRISING THE BACKLIGHT UNIT - Provided are a condensing film, a backlight unit including the condensing film, and a display device including the backlight unit. The condensing film includes a plurality of lens structures extending in an extension direction on a surface thereof, a first protrusion part disposed on the lens structures and comprising a plurality of protrusions arrayed in the extension direction of the lens structure, and a second protrusion part disposed on the lens structures and comprising a plurality of protrusions arrayed in an array direction forming a certain angle with the extension direction of the lens structure. | 2013-01-03 |
20130003411 | SYMMETRIC SERRATED EDGE LIGHT GUIDE HAVING CIRCULAR BASE SEGMENTS - The present invention provides a planar light guide film for a backlight unit having at least one point light source, the light guide film comprising a light input surface for receiving light from the point light source, a light redirecting surface for redirecting light received from the light input surface and a light output surface for outputting at least the light redirected from the light redirecting surface. The light input surface further comprises a composite lens structure having a circular tip segment with a first contact angle, and a first and second circular base segments with a second contact angle, the second contact angle being greater than the first contact angle and the second contact angle being equal to each other. Further, the circular tip segment satisfies the following equation: | 2013-01-03 |
20130003412 | SURFACE LIGHT SOURCE DEVICE, LIGHT GUIDE ELEMENT USED FOR SURFACE LIGHT SOURCE DEVICE, AND METHOD FOR PRODUCING LIGHT GUIDE ELEMENT - Disclosed is a plate-like light guide element ( | 2013-01-03 |
20130003413 | SYMMETRIC SERRATED EDGE LIGHT GUIDE FILM HAVING ELLIPTICAL BASE SEGMENTS - The present invention provides a planar light guide film for a backlight unit having at least one point light source, the light guide film comprising a light input surface for receiving light from the point light source, a light redirecting surface for redirecting light received from the light input surface and a light output surface for outputting at least the light redirected from the light redirecting surface. The light input surface further comprises a composite lens structure having a circular tip segment with a first contact angle, and a first and second elliptical base segments with a second contact angle, the second contact angle being less than the first contact angle and the second contact angle being equal to each other and | 2013-01-03 |
20130003414 | SYMMETRIC SERRATED EDGE LIGHT GUIDE FILM HAVING ELLIPTICAL BASE SEGMENTS - The present invention provides a planar light guide film for a backlight unit having at least one point light source, the light guide film comprising a light input surface for receiving light from the point light source, a light redirecting surface for redirecting light received from the light input surface and a light output surface for outputting at least the light redirected from the light redirecting surface. The light input surface further comprises a composite lens structure having a circular tip segment with a first contact angle, and a first and second elliptical base segments with a second contact angle, the second contact angle being greater than the first contact angle and the second contact angle being equal to each other and | 2013-01-03 |
20130003415 | PATTERNED LIGHT GUIDE PANEL, MANUFACTURING METHOD THEREOF, AND BACKLIGHT UNIT INCLUDING THE PATTERNED LIGHT GUIDE PANEL - A patterned light guide panel, a manufacturing method thereof, and a backlight unit including the patterned light guide panel, the patterned light guide panel including a base layer; and a skin layer stacked on the base layer, the skin layer having a lenticular pattern extending orthogonally to a light entrance plane of the light guide panel. | 2013-01-03 |
20130003416 | THERMALLY CONDUCTIVE THERMOPLASTIC RESIN COMPOSITIONS AND RELATED APPLICATIONS - Thermally conductive thermoplastic resin compositions are provided containing thermoplastic resin and thermally conductive filler and fibrous filler, along with articles made therefrom. In certain instances when the thermally conductive filler and fibrous filer are more restricted, and other ingredients are present, the thermally conductive composition exhibits an improved volume resistibility and is suitable for fabricating a chassis for LCD display. Also described are the thermally conductive resin compositions, especially when the polymer is LCP. Such compositions are useful for items such as electrical and electronic housings requiring highly thermally conduciveness. | 2013-01-03 |
20130003417 | LED LIGHT WITH SPECIAL EFFECTS - An LED light device with special effects utilizes persistence of vision theory to cause an LED(s) or LED array to change faster than the human eye response time of 1/16 to 1/24 second to display a special message, time, drawing, light patterns, or color changes. In addition, the light device may be provided with a sealed-unit arranged to receive a variety of eye-catching shades. | 2013-01-03 |
20130003418 | PULSE PATTERN GENERATING CONFIGURATION FOR THREE-PHASE CURRENT SOURCE ELECTRIC POWER CONVERTER - A pulse pattern generating configuration for a three-phase current source electric power converter is provided that ensures a minimal switching loss regardless of the level of power factor, and thus improves the electric power conversion efficiency. | 2013-01-03 |
20130003419 | Automatic Breaker Apparatus for USB Power Supply - An automatic breaker apparatus for the USB power supply, comprising a manual switch module, a relay, a high frequency transformer, a PWM power source master control module, a drive module, a signal filter module, an MCU master control module, a lighting instruction module and at least one USB power output end. When a user presses down the manual switch module, the relay becomes conductive, thus causing the electronic apparatus connected to the USB power source input end to be charged, and determining through the MCU master control module whether the electronic apparatus is using the electric current based on the pulsed filter signal outputted by the signal filter module thereby driving the relay to disconnect and also starting the lighting instruction module to generate light. Upon disconnection in the relay, electric power can no longer be transferred to the USB power output end so as to embody the objective of automatic power break, thereby achieving the features of environment protection, reduced energy consumption and power saving. | 2013-01-03 |
20130003420 | PRIMARY VOLTAGE SENSING AND CONTROL FOR CONVERTER - A controller for a DC/DC converter can include a first error analog to digital converter (EADC) configured to detect a primary voltage from a secondary side of a transformer and generate a first error signal corresponding to the primary voltage. The first error signal is generated based on a comparison between a first reference voltage and the detected primary voltage. A first accelerator can be configured to process the first error signal and generate a first compensation signal that is a primary voltage variation signal used for feedforward control. A second EADC and a second accelerator can be configured to provide a output voltage feedback control. A compensation signal of the first accelerator can be used to scale the second accelerator output to facilitate fast feedforward control. | 2013-01-03 |
20130003421 | SYSTEMS AND METHODS FOR ADJUSTING CURRENT CONSUMPTION OF CONTROL CHIPS TO REDUCE STANDBY POWER CONSUMPTION OF POWER CONVERTERS - System and method for regulating a power conversion system. For example, a system controller includes a signal generator and one or more power-consumption components. The signal generator is configured to receive a feedback signal related to an output signal of the power conversion system, a current sensing signal and an input voltage, and to generate a control signal based on at least information associated with the feedback signal, the current sensing signal and the input voltage. The power-consumption components are configured to receive the control signal. The signal generator is further configured to determine whether the feedback signal is smaller than a feedback threshold for a first predetermined period of time, the current sensing signal is smaller than a current sensing threshold for a second predetermined period of time, and the input voltage is smaller than a first threshold for a third predetermined period of time in magnitude. | 2013-01-03 |
20130003422 | SWITCHED MODE POWER SUPPLY WITH VOLTAGE REGULATOR - A power supply and method for reliable turn-on of a switched mode power supply (SMPS) in which the same transformer is used for providing power from the primary side to both the main output of the SMPS and a secondary side voltage regulator a train of voltage pulses are transmitted, from the primary side to the secondary side. The voltage regulator generates a feedback signal indicating when it has turned on and is operating, and the transmission of pulses within the train is controlled based on the detection of feedback signal. In this way, only the required amount of power to switch on the voltage regulator is transferred to the secondary side during a start-up operation and excess power at the main output is prevented, thereby avoiding distortion of the desired start-up ramp figure. | 2013-01-03 |
20130003423 | MULTI-INPUT BIDIRECTIONAL DC-DC CONVERTER WITH HIGH VOLTAGE CONVERSION RATIO - A multi-input bidirectional DC-DC converter with a high voltage conversion ratio is provided. The multi-input bidirectional DC-DC converter with a high voltage conversion ratio implements phase control loops independent from one another so as to realize independent control of charge and discharge in a plurality of energy storage modules, and thus a failure in one of energy storage modules does not affect the other energy storage modules. In addition, it is possible to easily add or remove a control loop that is controlled independently from other control loops. | 2013-01-03 |
20130003424 | MULTI-PHASE INTERLEAVED BIDIRECTIONAL DC-DC CONVERTER WITH HIGH VOLTAGE CONVERSION RATIO - A multi-phase interleaved bidirectional DC-DC converter with a high voltage conversion ratio is provided. The multi-phase interleaved bidirectional DC-DC converter with a high voltage conversion ratio allows effective control of charge/discharge in multi-energy storage modules including a battery cell module or a super capacitor module, which is characterized in low voltage and high current output. Accordingly, a high-efficiency bidirectional DC-DC converter for use in battery charge/discharge can be implemented. | 2013-01-03 |
20130003425 | DC/DC CONVERTER, AND ELECTRIC GENERATING SYSTEM USING SOLAR CELL HAVING THE SAME - Disclosed herein is an electric generating system using a solar cell which converts a voltage generated in the solar cell into an Alternating Current (AC) voltage, and applies the converted voltage to a power system. The electric generating system includes; a Direct Current (DC)/DC converter that converts the voltage generated in the solar cell into a DC voltage, and has a synchronous rectifier including a synchronous switch; and a controller that detects one of a phase and a voltage of the power system, and selectively connects the synchronous switch of the synchronous rectifier in accordance with one of the phase and voltage of the power system. Here, the electric generating system reduces a conduction loss, and increases overall efficiency of the electric generation system. | 2013-01-03 |
20130003426 | SWITCHING POWER SUPPLY DEVICE - During a soft start period at the time of startup, a PWM control is carried out. After the soft start period ends, the PWM control is converted into a frequency control, so that stress of a switching element is suppressed and the audible oscillation frequency is removed. As a result, it is possible to obtain a switching power supply device having high power conversion efficiency. | 2013-01-03 |
20130003427 | POWER FACTOR CORRECTION CONVERTER AND POWER FACTOR CORRECTION CONVERSION DEVICE - A power factor correction converter and a power factor correction conversion device, includes two groups of bidirectional switches, an autotransformer, a boost inductor, a bus filter capacitor, two front bridge arms; and a rear bridge arm; the front end of each group of bidirectional switches are connected to a coil of the autotransformer in one-to-one correspondence, and a rear end of each group of bidirectional switches is connected to one end of an AC input power grid; a central tap of the autotransformer is connected to an output end of the boost inductor, and an input end of the boost inductor is connected to the other end of the AC input power grid; a front end of each group of bidirectional switches is connected to a front bridge arm, and a rear end is connected to the rear bridge arm. | 2013-01-03 |
20130003428 | POWER SUPPLY SYSTEM AND ELECTRICAL DEVICE WITH SAME - An exemplary power supply system is used to provide one or more operation voltages to a plurality of loads individually. The power supply system includes a timing circuit configured to control a starting time that the corresponding loads start to receive their corresponding operation voltages. The timing circuit includes a first capacitor arranged to be charged by the corresponding DC voltage, and the starting time is determined according to a charging characteristic of the first capacitor. | 2013-01-03 |
20130003429 | POWER CONVERSION DEVICE - A power conversion device includes a main circuit unit (direct-current main circuit) that converts direct-current power into alternating-current power, and a control unit that controls the direct-current main circuit. The direct-current main circuit includes a voltage detector (detector) that detects a capacitor voltage and a discharge circuit that discharges energy accumulated in a capacitor. The control unit includes a detection circuit that estimates a capacitor voltage during a normal operation based on a voltage transmitted from the voltage detector in a state where the main circuit unit is disconnected from a power supply and that detects a sign that a short circuit fault occurs in the capacitor, and a control circuit that outputs a control signal for controlling the discharge circuit to operate when the control circuit receives a detection signal from the detection circuit. | 2013-01-03 |
20130003430 | OPTIMIZATION OF A POWER CONVERTER EMPLOYING AN LLC CONVERTER - A power converter includes an input stage connected to receive an input signal and to provide an intermediate DC voltage, and an output stage having an LLC converter connected to receive the intermediate DC voltage and to provide a DC output voltage. Additionally, the power converter includes a control unit connected to the input and output stages to regulate the DC output voltage and set a target operating parameter of the LLC converter based on controlling the intermediate DC voltage. A method of operating a power converter is also provided. | 2013-01-03 |
20130003431 | MULTILEVEL POWER CONVERTER AND METHODS OF MANUFACTURING AND OPERATION THEREOF - A power converter includes an input stage connected to receive a three phase AC input voltage and to provide multiple DC voltage levels. The power converter also includes an output stage of a plurality of interleaved LLC converters having series-connected inputs coupled to the multiple DC voltage levels and parallel-connected outputs to provide a DC output voltage. Additionally, the power converter includes a balancing circuit interconnected to the input and output stages to provide substantially balanced output currents from the plurality of interleaved LLC converters for the DC output voltage. Methods of manufacturing and operating a power converter are also provided. | 2013-01-03 |
20130003432 | METHOD FOR OPERATING AN ELECTRICAL CIRCUIT AND ELECTRICAL CIRCUIT - A method for operating an electrical circuit, in particular of a converter is described. The circuit, in at least one embodiment, includes a line-side converter that is coupled to a capacitor. The line-side converter includes at least two series connections, each including at least two power semiconductor elements, and each of the at least two series connections being connected parallel to the capacitor. The line-side converter is coupled to an energy supply system. The DC voltage that is present at the capacitor is determined. A maximum voltage is predetermined. If the DC voltage present at the capacitor is determined to be greater than the maximum voltage, then at least two of the power semiconductor elements are switched into their conductive state in such a manner that the capacitor is discharged in the direction of the energy supply system. | 2013-01-03 |
20130003433 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction. | 2013-01-03 |
20130003434 | METHOD FOR OPERATING A SEMICONDUCTOR STRUCTURE - A method for operating a semiconductor structure is provided. The semiconductor structure comprises a substrate, a first stacked structure, a dielectric element, a conductive line, a first conductive island and a second conductive island. The first stacked structure is formed on the substrate. The first stacked structure comprises first conductive strips and first insulating strips stacked alternately. The first conductive strips are separated from each other by the first insulating strips. The dielectric element is formed on the first stacked structure. The conductive line is formed on the dielectric element. The first conductive island and the second conductive island on opposite sidewalls of the first stacked structure are separated from each other. The method for operating the semiconductor structure comprises respectively applying a first voltage to the first conductive island and applying a second voltage to the second conductive island. | 2013-01-03 |
20130003435 | Memory Arrays - Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about | 2013-01-03 |
20130003436 | AMORPHOUS SILICON RRAM WITH NON-LINEAR DEVICE AND OPERATION - A non-volatile memory device includes a resistive switching device having a first electrode, a second electrode, and a resistive switching element, wherein the resistive switching element comprises a silicon material disposed in an overlapping region between the first electrode and the second electrode, wherein the second electrode comprises at least a metal material physically and electrically in contact with the resistive switching material, wherein the resistive switching element is characterized by a resistance depending on an electric field in the resistive switching element, and a non-linear device coupled between the first electrode and the resistive switching element, wherein the non-linear device is configured to conduct electric current when a voltage greater than a first voltage is applied to the second electrode, wherein the resistive switching device is configured to change from a first state to a second state in response to the first voltage. | 2013-01-03 |
20130003437 | Multilayer Cross-Point Memory Array Having Reduced Disturb Susceptibility - A multi-layer cross-point memory array comprises one or more word line (WL) layers, one or more bit line (BL) layers interleaved with the one or more WL layers, and a plurality of memory layers, each memory layer disposed between an adjacent WL layer and an adjacent BL layer, and each memory layer including memory elements configured between cross-points of WLs and BLs of the adjacent WL and BL layers. Memory elements in successive memory layers of the memory array are configured with opposing orientations, so that half-selected memory elements arising during times when data operations are being performed on selected memory elements in the memory array are subjected to stress voltages of a polarity of which they are least susceptible to being disturbed. The memory elements can be discrete re-writeable non-volatile two-terminal memory elements that are fabricated as part of a BEOL fabrication process used to fabricate the memory array. | 2013-01-03 |
20130003438 | THERMAL MANAGEMENT APPARATUSES WITH TEMPERATURE SENSING RESISTIVE RANDOM ACCESS MEMORY DEVICES AND METHODS THEREOF - An apparatus includes one or more temperature sensing and memory devices each having one or more memristors. A controller device is coupled to the temperature sensing and memory devices A processing device is coupled to the controller device and includes at least one of hardware logic configured to be capable of implementing or a processor coupled to a memory and configured to execute programmed instructions stored in the memory comprising: issuing a record instruction and a write instruction with a write address to the controller device to record the write time for the memristor at the write address to transition from one of the first and second states to the other states; receiving from the controller device the recorded time; determining and providing a temperature of the memristor at the write address based on the received. | 2013-01-03 |
20130003439 | NONVOLATILE VARIABLE RESISTANCE MEMORY ELEMENT WRITING METHOD, AND NONVOLATILE VARIABLE RESISTANCE MEMORY DEVICE - A method of writing data to a variable resistance element ( | 2013-01-03 |
20130003440 | Single Device Driver Circuit to Control Three-Dimensional Memory Element Array - A memory device includes diode plus resistivity switching element memory cells coupled between bit and word lines, single device bit line drivers with gates coupled to a bit line decoder control lead, sources/drains coupled to a bit line driver, and drains/sources coupled to bit lines, single device word line drivers with gates coupled to a word line decoder control lead, sources/drains coupled to a word line driver output, and drains/sources coupled to word lines, a first bleeder diode coupled between a bit line and a first bleeder diode controller, and a second bleeder diode coupled between a word line and a second bleeder diode controller. The first bleeder diode controller connects the first bleeder diode to low voltage in response to a bit line decoder signal. The second bleeder diode controller connects the second bleeder diode to high voltage in response to a word line decoder signal. | 2013-01-03 |
20130003441 | SEMICONDUCTOR DEVICE AND A METHOD FOR DRIVING THE SAME - It is an object to reduce power consumption of a 2Tr1C type semiconductor memory device. The absolute value of the threshold voltage of a reading transistor is made larger than a fluctuation range of a data potential of a bit line (or the fluctuation range of the data potential of the bit line is made smaller than the absolute value of the threshold voltage of the reading transistor), whereby the potential of a source line can be fixed, a fluctuation in a potential of a writing word line can be made smaller, and a potential of a reading word line is fluctuated only at the time of reading. Further, a gate of such a transistor the absolute value of the threshold voltage of which is large is formed using a material having a high work function, such as indium nitride. | 2013-01-03 |
20130003442 | CANARY BASED SRAM ADAPTIVE VOLTAGE SCALING (AVS) ARCHITECTURE AND CANARY CELLS FOR THE SAME - A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank. | 2013-01-03 |
20130003443 | 8T SRAM CELL WITH HIGHER VOLTAGE ON THE READ WL - The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes a write transistor gated by a write word line. The circuitry also includes a read buffer circuit coupled to the SRAM cell core to read the cell without disturbing the state of the cell. The read buffer circuit includes a read transistor gated by a read word line, the read transistor coupled between a read bit-line and a read driver transistor that is further coupled to a voltage source Vss. The read driver transistor and a first driver transistor of the cell core are both gated by one output of the cell core. The read transistor has an electrical characteristic that differs from that of the core cell first driver transistor. | 2013-01-03 |
20130003444 | SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREFOR - Provided is a semiconductor memory device including: first and second SRAM cells; a first hit line pair provided with the first SRAM cell; a second bit line pair provided with the second SRAM cell; a first switch circuit provided between the first bit line pair and the second bit line pair; and a controller that controls the first switch circuit to render the first bit line pair and the second bit line pair conductive, in a case of testing the first SRAM cell. | 2013-01-03 |
20130003445 | SRAM CELLS, MEMORY CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF - A static random access memory (SRAM) cell includes a pair of cross-coupled inverters having a first node and a second node. A first transistor is coupled between the first node and a first bit line. A second transistor is coupled between the second node and a second bit line. A third transistor is coupled with the first node. The third transistor has a threshold voltage that is higher than that of a fourth transistor of the pair of cross-coupled inverters by about 10% or more. A fifth transistor is coupled between the third transistor and a third bit line | 2013-01-03 |
20130003446 | Method for Extending Word-Line Pulses - An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to turn off the plurality of current paths one-by-one in response to a reduction in a positive power supply voltage on the positive power supply node. The integrated circuit further includes a charging node receiving a summation current of the plurality of current paths, wherein a voltage on the charging node is configured to increase through a charging of the summation current. | 2013-01-03 |
20130003447 | SENSING CIRCUIT - A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of a not-AND (NAND) circuit. | 2013-01-03 |
20130003448 | MRAM DIODE ARRAY AND ACCESS METHOD - A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode. | 2013-01-03 |
20130003449 | DESELECT DRIVERS FOR A MEMORY ARRAY - Asymmetric select and deselect drivers are provided for select lines driven to a resistive cross-point memory array. An address may be fully decoded to determine the active select driver, but a partial decode may be performed for the deselect drivers. Some embodiments may manage the odd and even deselect drivers as two sets of drivers and some embodiments may use sub-optimal transistors as the deselect drivers to save die area. Some embodiments may implement the deselect drivers as modified memory elements to reduce die area further. | 2013-01-03 |
20130003450 | MIXED MODE PROGRAMMING FOR PHASE CHANGE MEMORY - Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory. | 2013-01-03 |
20130003451 | REFRESH ARCHITECTURE AND ALGORITHM FOR NON-VOLATILE MEMORIES - Methods and systems to refresh a non-volatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level. | 2013-01-03 |
20130003452 | Method and Structure for Integrating Capacitor-less Memory Cell with Logic - Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of the logic device, and fabricating a capacitor-less memory cell on the intermediate semiconductor substrate. Integrated circuits with capacitor-less memory cells formed on a surface of a logic device are also disclosed, as are multi-core microprocessors including such integrated circuits. | 2013-01-03 |
20130003453 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device is operated by, inter alia: precharging a bit line, providing a first voltage to a coupling circuit for coupling the bit lines and cell strings of a plurality of memory cells, providing a program voltage to a selected word line coupled to a memory cell on which a program operation will be performed among the plurality of memory cells, providing a pass voltage to unselected word lines, providing a second voltage lower than the first voltage to the coupling circuit, discharging the bit line by loading program data, and providing a third voltage lower than the second voltage to the coupling circuit. | 2013-01-03 |
20130003454 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device according to embodiments has a memory cell array and a reading circuit, and, in a reading sequence, the reading circuit executes a prereading operation of supplying a first reading voltage to an adjacent word line and supplying a first reading pass voltage to a selected word line, and after executing the prereading operation, executes a main reading operation of supplying a fixed second reading voltage to the selected word line and supplying a fixed second reading pass voltage to the adjacent word line while sensing a plurality of electrical physical amounts of a target memory cell with different reading conditions. | 2013-01-03 |
20130003455 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH ADVANCED MULTI-PAGE PROGRAM OPERATION - A nonvolatile semiconductor memory device for an efficient program of multilevel data includes a memory cell array having a plurality of banks and a cache block corresponding to each of the plurality of banks. The cache block has a predetermined data storage capacity. A page buffer is included which corresponds to each of the plurality of banks. A programming circuit programs all of the plurality of banks except a last of said banks with page data. The page data is loaded through each page buffer and programmed into each cache block such that when page data for the last bank is loaded into the page buffer, the loaded page data and the page data programmed into the respective cache blocks are programmed into respective corresponding banks. | 2013-01-03 |
20130003456 | SCALABLE MULTI-FUNCTIONAL AND MULTI-LEVEL NANO-CRYSTAL NON-VOLATILE MEMORY DEVICE - A multi-functional and multi-level memory cell comprises a tunnel layer formed over a substrate. In one embodiment, the tunnel layer comprises two layers such as HfO | 2013-01-03 |
20130003457 | APPARATUS, SYSTEM, AND METHOD FOR USING MULTI-LEVEL CELL SOLID-STATE STORAGE AS REDUCED-LEVEL CELL SOLID-STATE STORAGE - A controller is used for an electronic memory device which has multi-level cell (MLC) memory elements. Each MLC memory element is capable of storing at least two bits. The controller includes a physical interface to couple the controller to the electronic memory device. The controller also includes a processing unit coupled to the physical interface. The processing unit operates the electronic memory device in a single-level cell (SLC) mode using a restricted number of programming states for a single data bit. The restricted number of programming states includes a first state which is an erase state. The restricted number of programming states also includes a second state, other than the erase state, which is closest to a natural threshold voltage of the MLC memory elements. | 2013-01-03 |
20130003458 | NAND ARCHITECTURE MEMORY WITH VOLTAGE SENSING - A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or floating node field effect transistor memory cells using a voltage sensing data read/verify process. The voltage sensing process utilized a reference NAND string and reference memory cell that is coupled to a reference bit line. A voltage is precharged onto a bit line to be read and an associated reference bit line. The bit line is then coupled to a NAND string and selected memory cell while the reference bit line is coupled to a reference NAND string and selected reference memory cell. The relative voltage level of the bit line and reference bit line are then set by the relative currents flowing through the coupled NAND string and reference NAND string, and the voltage differential read by a coupled voltage sense amplifier. | 2013-01-03 |
20130003459 | Read Error Recovery for Solid-State Memory Based on Cumulative Background Charges - A read error is determined that affects a page of solid-state, non-volatile memory. The page is associated with a selected word line that crosses a plurality of NAND strings coupled to respective grounds and bit lines. Word lines of the memory are ordered from a lower end proximate the ground to a higher end proximate the bit lines. Cumulative background charges each associated with one of the memory cells of the page are determined. The cumulative background charges are based on charge levels of respective cells of a plural subset of the word lines that are lower in order than the selected word line. A recovery operation is performed on the page using the cumulative background charges. | 2013-01-03 |
20130003460 | USE OF EMERGING NON-VOLATILE MEMORY ELEMENTS WITH FLASH MEMORY - Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array. | 2013-01-03 |
20130003461 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING CHIP SIZE - According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines. | 2013-01-03 |
20130003462 | CONTROL SYSTEM FOR MEMORY DEVICE - A nonvolatile memory device includes a discharge circuit configured to selectively connect circuit nodes to discharge terminals through corresponding discharge paths, and an accumulation device for accumulating electric charge. A driving circuit is for driving the discharge circuit in such a way to connect at least a part of such circuit nodes to the discharge terminals if the value of the external supply voltage falls below a corresponding threshold. A supply circuit is for supplying the driving circuit with an intermediate supply voltage. Each one of the intermediate supply voltages is the corresponding external supply voltage when the value of the external supply voltage is higher than the corresponding threshold, or it is an internal voltage locally generated by the supply circuit by exploiting the electric charge stored by the accumulation device when the value of the external supply voltage is lower than the corresponding threshold. | 2013-01-03 |
20130003463 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - Bit lines connected to each nonvolatile memory cell are selected by corresponding selective transistors. A first drive circuit for driving the gate of one of the selective transistors receives a voltage selected by a first voltage switch, and a second drive circuit for driving the gate of the other selective transistor receives a voltage selected by a second voltage switch. A transistor constituting the first drive circuit is different in structure from a transistor constituting the second drive circuit. | 2013-01-03 |
20130003464 | CIRCUITS, SYSTEMS, AND METHODS FOR DRIVING HIGH AND LOW VOLTAGES ON BIT LINES IN NON-VOLATILE MEMORY - An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias transistor through which an input signal is coupled to the respective bit line. The bit line driver system includes a bias voltage circuit that generates a bias voltage that is coupled to the respective gates of the bias transistors. The bias voltage circuit initially accelerates the charging of the transistor gates, and subsequently completes charging the gates at a slower rate. The bias voltage is generated using a diode-coupled transistor having electrical characteristics the match those of the bias transistors so that the bias voltage varies with process or temperature variations of the integrated circuit in the same manner as the threshold voltage of the bias transistors vary with process or temperature variations. | 2013-01-03 |
20130003465 | LOCAL SENSING IN A MEMORY DEVICE - Methods for sensing, memory devices, and memory systems are disclosed. In one such memory device, a local sense circuit provides sensing of an upper group of memory cells while a global sense circuit provides sensing of a lower group of memory cells. Data sensed by the local sense circuit is transferred to the global sense circuit over local data lines or a global transfer line that is multiplexed to the local data lines. An alternate embodiment uses the local sense circuit to sense both upper and lower groups of memory cells. | 2013-01-03 |
20130003466 | APPLICATION CIRCUIT AND OPERATION METHOD OF SEMICONDUCTOR DEVICE - An application circuit and an operation method of a semiconductor device are provided. A leakage current among a control gate diffusion layer, a source diffusion layer and a drain is reduced by adjusting biases applied on a double well region, so as to reduce the product cost and improve the accuracy of a battery-less electronic timer that uses the semiconductor device. | 2013-01-03 |
20130003467 | DIGIT LINE COMPARISON CIRCUITS - A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier. | 2013-01-03 |
20130003468 | MEMORY MODULE BUS TERMINATION VOLTAGE (VTT) REGULATION AND MANAGEMENT - Embodiments of the present disclosure describe memory module bus termination voltage (VTT) regulation and management techniques and configurations. A method includes receiving, by a register, a signal that is driven over a bus to a memory device comprising a plurality of memory cells and setting, within the register, a termination voltage (VTT) for the bus based on the signal. Other embodiments may be described and/or claimed. | 2013-01-03 |
20130003469 | CIRCUITS AND METHODS FOR MEMORY - Embodiments for data dependent boosted (DDB) bit cells that may allow for smaller minimum cell supplies (Vmin) without necessarily having to increase device dimensions are presented. | 2013-01-03 |
20130003470 | INDEPENDENT LINK AND BANK SELECTION - Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller. | 2013-01-03 |
20130003471 | MEMORY CELL EMPLOYING REDUCED VOLTAGE - A memory array has a memory cell that comprises a storage element storing a logical state at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line. The reduced voltage is reduced relative to an operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell. | 2013-01-03 |
20130003472 | MEMORY WITH CORRELATED RESISTANCE - Methods, systems, and devices are disclosed, such as a system for sequentially writing to a data locations coupled to one another in series. In certain embodiments, the system includes a plurality of data locations and a controller. The controller is configured to sequentially write data values to the plurality of data locations, starting with the data location at an end of the series and then sequentially writing to each adjacent data location. | 2013-01-03 |
20130003473 | STACKED DEVICE REMAPPING AND REPAIR - Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described. | 2013-01-03 |
20130003474 | PROVIDING A READY-BUSY SIGNAL FROM A NON-VOLATILE MEMORY DEVICE TO A MEMORY CONTROLLER - A common standard may be used for both dynamic random access memories and non volatile memories, despite the fact that the non-volatile memory generally needs bidirectional communications to coordinate writing with a memory controller. In one embodiment, a package connector on the non-volatile memory may be used for one function that does not involve communications with the memory controller during reading and may be used for communications with the memory controller during writing. Particularly, those communications during writing may be to indicate to the memory controller when the memory is ready for writing and when the memory is busy so that a write must be deferred until the memory is ready to be written to. | 2013-01-03 |
20130003475 | Memory Access Alignment In A Double Data Rate ('DDR') System - Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations. | 2013-01-03 |
20130003476 | MEMORY DEVICE INCLUDING A MEMORY BLOCK HAVING A FIXED LATENCY DATA OUTPUT - A memory block includes a memory circuit and a clock generation unit. The memory circuit may output read data in response to receiving a read command and being clocked by a first clock signal having a selectable delay dependent upon a propagation delay for the read data to be output by a memory core. The clock generation unit is configured to generate a second clock signal having a selectable delay based on a system clock signal. The read data provided by the memory block in response to the second clock signal such that the read data has a latency that approximately the same, or is relatively fixed, for different frequencies of the system clock signal. | 2013-01-03 |
20130003477 | SEMICONDUCTOR MEMORY DEVICE INCLUDING SPARE ANTIFUSE ARRAY AND ANTIFUSE REPAIR METHOD OF THE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including an antifuse cell array and a spare antifuse cell array are provided. An antifuse cell array includes a first set of antifuse cells arranged in a first direction and each one of the first set of antifuse cells is connected to a corresponding one of first through nth word lines. The spare antifuse cell array includes a first spare set of antifuse cells arranged in the first direction and each one of the first spare set of antifuse cells is connected to a corresponding one of first through kth spare word lines. A first operation control circuit is configured to program antifuses of the antifuse cell array and the spare antifuse cell array, and to read a status of each of the antifuses. The first operation control circuit is commonly connected to the first set of antifuse cells and the first spare set of antifuse cells. | 2013-01-03 |
20130003478 | Embedded Memory Databus Architecture - A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors. | 2013-01-03 |
20130003479 | SEMICONDUCTOR MEMORY CELL ARRAY AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A semiconductor memory cell array includes a plurality of bit-lines, a plurality of word-lines, a plurality of memory cells, a plurality of dummy memory cells, a plurality of dummy bit-lines, and a plurality of dummy word-lines. The dummy bit-lines are in outer regions of the bit-lines. The dummy word-lines are in outer regions of the word-lines. The dummy bit-lines are maintained in a floating state. The dummy word-lines retain a turn-off voltage | 2013-01-03 |
20130003480 | SMART BRIDGE FOR MEMORY CORE - An apparatus includes a first memory die including a first memory core, a second memory die including a second memory core, and a periphery die coupled to the first memory die and to the second memory die. The periphery die includes periphery circuitry corresponding to the first memory core and periphery circuitry corresponding to the second memory core. The periphery die is responsive to a memory controller and configured to initiate a first memory operation at the first memory core and a second memory operation at the second memory core. | 2013-01-03 |
20130003481 | HIDDEN REFRESH METHOD AND OPERATING METHOD FOR PSEUDO SRAM - In an exemplary hidden refresh method for a pseudo SRAM, a system clock is received. A duty-on period of the system clock signal is adapted for performing a data access operation such as write or read operation. A refresh clock signal subjected to the control of the system clock signal is generated. A duty-on period of the refresh clock signal is non-overlapped with the duty-on period of the system clock signal. A refresh control pulse then is triggered by a starting edge of the duty-on period of the refresh clock signal to activate a word line, for performing a refresh operation. | 2013-01-03 |
20130003482 | SELF-REFRESH CONTROL CIRCUIT AND MEMORY INCLUDING THE SAME - An self-refresh control circuit for controlling a self-refresh operation of a memory device includes a self-refresh control logic block configured to control the memory device to perform the self-refresh operation and an initial refresh control block configured to activate the self-refresh control logic block in an initialization period of the memory device. | 2013-01-03 |
20130003483 | WIDE FREQUENCY RANGE DELAY LOCKED LOOP - A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power. | 2013-01-03 |
20130003484 | PARTIAL WRITE ON A LOW POWER MEMORY ARCHITECTURE - A memory includes memory cells, data lines, block select lines, and selection circuitry. The data lines provide data to and from the memory cells and may be grouped into blocks. Each block includes data lines. Each of the block select lines is associated with a respective one of the blocks. The selection circuitry is select a block in response to a respective block select line and the memory performs a memory operation using the selected bit line block. | 2013-01-03 |
20130003485 | MICRO-BUBBLE GENERATING DEVICE - A micro-bubble generating device is provided which is capable of mixing or dispersing micro-bubbles into a liquid with high stability and has a simple structure that permits reduction of a cost of manufacture. A first member and a first packing are superposed on each other on one side of a gas-permeable film, while a second member and a second packing are superposed on each other on the other side of the gas-permeable film. A pressurized gas delivered via a gas inlet of the first member flows through a fluid passage of the first packing, permeates through the gas-permeable film, and is ejected as micro-bubbles into a liquid flowing through a fluid passage in the form of a narrow shallow strip-like groove provided in the second packing. | 2013-01-03 |
20130003486 | SYSTEMS AND METHODS FOR AUTOMATED CONTROL OF MIXING AND AERATION IN TREATMENT PROCESSES - A system and method for automatically controlling aeration and mixing processes are disclosed. | 2013-01-03 |
20130003487 | Small Bottle Shaker - An embodiment of the invention provides a small bottle shaker with a housing unit that contains a variable speed motor that is attached to a rotary drive unit. The rotary drive unit is attached to a bottle holder that has a lid with a positive retention device that keeps the lid closed when a bottle is being shaken. The bottle holder also has a bottle retention assembly that holds a bottle being shaken in position and protects it from damage. | 2013-01-03 |
20130003488 | FLEXIBLE MIXING BAG FOR MIXING SOLIDS, LIQUIDS, AND GASES - In an embodiment, an apparatus includes a disposable and flexible mixing tank, configurable as a bag, having a sealed sleeve therein for arrangement of a mixing device. The volume of the mixing tank is defined by an inner wall of the mixing tank and an inner wall of the sleeve. The mixing tank may be used to mix, store, reconstitute and/or dispense materials therein. Draining of a mixture may be aided with pressurized gas. Heating or cooling of the contents of a mixing tank may be accomplished with a thermal exchange fluid disposed within a thermal exchange vessel and in thermal communication with the tank. | 2013-01-03 |
20130003489 | Stick Mixer - A hand held stick mixer device has a motor housing, a stem and a blade housing. The blade housing has an interior sidewall below the floor having a distance across a transverse axis that is smaller than a distance across a perpendicular axis. | 2013-01-03 |
20130003490 | KITCHEN APPLIANCE - The invention relates to a kitchen appliance ( | 2013-01-03 |
20130003491 | METHOD FOR CONTROLLING A SYSTEM FOR METERING AND MIXING A PRODUCT HAVING A PLURALITY OF COMPONENTS, METERING AND MIXING SYSTEM AND SPRAYING OR EXTRUSION FACILITY COMPRISING SAME - A system includes a first pump feeding a first component into a mixer, and a second pump feeding a second component into the mixer. The movement of the piston of each pump can be reversed from a direction of suction and of expulsion of the volume of the pump to a direction of expulsion of the component and vice versa. A movement detector is associated with each pump and is connected to a controller programmed to trigger the reversal of a pump after having determined that the volume remaining in the pump is insufficient to ensure the predetermined metering ratio. The controller is programmed to provide the continuous feeding of the first component into the mixer through the operation of the system, and the intermittent feeding of the second component into the mixer in order to carry out cycles of feeding doses of the second component into the mixer. | 2013-01-03 |
20130003492 | Stirrers for minimizing erosion of refractory metal vessels in a glass making system - Stirring apparatuses for stirring molten glass are disclosed. The method includes stirring a molten glass with a stirrer comprising a layer containing at least about 50% iridium. An apparatus comprising an iridium-containing layer is also presented. In one embodiment, an apparatus for stirring molten glass includes a cylinder comprising a bore. A stirrer may be disposed in the bore. The stirrer may include a platinum or platinum alloy shaft coaxial with the cylinder. A plurality of impellers may project radially from the shaft into close proximity of a wall of the cylinder. Each impeller may include an arcuate distal end portion farthest from the shaft. The distal end portion of each impeller consists of iridium or an iridium alloy and the remainder of the impeller consists of platinum or a platinum alloy. The stirring apparatuses reduce metal loss from the refractory metal of the stirring apparatus. | 2013-01-03 |
20130003493 | RETRACTABLE MIXER SYSTEM AND METHOD OF USING SAME - A retractable mixer system and a method of using the retractable mixer system to clean sludge build-up in a tank is disclosed. The retractable mixer system includes a drive shaft, a retractable propeller assembly and a motor for rotating the drive shaft and the retractable propeller assembly attached to the drive shaft. By using the retractable mixer system at an existing access point or a newly created access point, the sludge build-up may be cleaned even when the sludge level is above the access point. | 2013-01-03 |
20130003494 | INLINE STATIC MIXER - A static mixer ( | 2013-01-03 |
20130003495 | PROPELLER ASSEMBLY COMPRISING ONE HUB AND AT LEAST TWO BLADES - The inventions refer to a mixer assembly for generating and maintaining a movement within waste water, comprising a hub ( | 2013-01-03 |
20130003496 | ROTARY JOINT/SWIVEL DEVICE - A rotary joint or swivel device for ensuring a continuous connection between two items that rotates with respect to each other, for example between an instrumentation unit on a fixed installation and sensor elements in a cable on a rotating cable reel or drum, is provided. The rotary joint or swivel device comprises a minimum of two spools | 2013-01-03 |
20130003497 | STREAMER CABLE FOR USE IN MARINE SEISMIC EXPLORATION AND METHOD FOR REDUCING NOISE GENERATION IN MARINE SEISMIC EXPLORATION - The present invention relates to a streamer cable for use in marine seismic exploration. Further, a method for reducing noise generation in marine seismic exploration is described, as well as a method for the preparation of the said seismic cables. | 2013-01-03 |
20130003498 | METHOD FOR ESTIMATING AN UNDERWATER ACOUSTIC SOUND VELOCITY IN A NETWORK OF ACOUSTIC NODES, CORRESPONDING COMPUTER PROGRAM PRODUCT, STORAGE MEANS AND DEVICE - A method for estimating an underwater acoustic sound velocity in a network of acoustic nodes arranged along towed acoustic linear antennas and in which a plurality of acoustic signals are transmitted between the nodes. The method includes: obtaining two predetermined distances each separating a couple of nodes placed along a same first acoustic linear antenna ( | 2013-01-03 |
20130003499 | INTERFEROMETRIC METHOD OF ENHANCING PASSIVE SEISMIC EVENTS - The interferometric method of enhancing passive seismic events includes the step of cross-correlation (CC) of the trace recorded at a reference receiver location with the traces recorded at the rest of receiver locations. Next, the CC traces are aligned to zero timing by applying shifts that are calculated by searching for the position of the maximum CC trace value. Subsequently, the aligned CC traces are summed to produce a stacked CC trace that has a signal-to-noise ratio (SNR) better than the individual CC traces. Lastly, the stacked CC trace is convolved with each raw trace to put the MS event at the correct timing. Due to this process, the timing of the MS event on the i-th convolved trace, tccasci, will be equal to the timing of the MS event on the corresponding i-th raw trace, i.e., tccasci=ti. | 2013-01-03 |
20130003500 | Seismic Data Processing - The invention includes a method for reducing noise in migration of seismic data, particularly advantageous for imaging by simultaneous encoded source reverse-time migration (SS-RTM). One example embodiment includes the steps of obtaining a plurality of initial subsurface images; decomposing each of the initial subsurface images into components; identifying a set of components comprising one of (i) components having at least one substantially similar characteristic across the plurality of initial subsurface images, and (ii) components having substantially dissimilar characteristics across the plurality of initial subsurface images; and generating an enhanced subsurface image using the identified set of components. For SS-RTM, each of the initial subsurface images is generated by migrating several sources simultaneously using a unique random set of encoding functions. Another embodiment of the invention uses SS-RTM for velocity model building. | 2013-01-03 |
20130003501 | METHODS AND APPARATUS FOR LOCATING HIDDEN OR BURIED NON-CONDUCTIVE PIPES AND LEAKS THEREFROM - Methods and apparatus for locating a hidden or buried non-conductive fluid pipe and leaks therefrom are presented in which a current signal is injected into fluid in a hidden or buried non conductive pipe and the resulting induced magnetic field is detected to determine the location of the pipe and leaks therefrom according to the spatial variation of the intensity of the magnetic field. In one approach, a pulser injects a plurality of individual electrical current pulses directly into water in pipe. The pulsed currents in the pipe can be returned to the pulser by a wire conductor independent from ground. A coil detector senses the magnetic fields created in the water in the pipe. Leak detection can be enhanced by providing a current path through earth ground for leakage current due to water leaks in the water pipe and utilizing a variable resistor to control the amount of current returning to the pulser. | 2013-01-03 |
20130003502 | CONFIGURABLE ULTRASOUND MEASUREMENT LOGIC IN A MOBILE COMPUTING DEVICE - A device, system, method, and machine readable medium for configurable ultrasound Doppler measurements from a mobile device are disclosed. In one embodiment, the device includes an oscillator capable of generating an ultrasound frequency sound wave. The device also includes an ultrasound emission module capable of emitting a first ultrasound wave at a first frequency and at a first power level and a second ultrasound wave at a second frequency and at a second power level. The device also an ultrasound receiver and amplifier module capable of receiving and amplifying ultrasound emission waves. The device also includes processing logic capable of receiving the first and second ultrasound waves and displaying those waves on a display device. | 2013-01-03 |
20130003503 | METHOD AND DEVICE OF OBTAINING A NODE-TO-SURFACE DISTANCE IN A NETWORK OF ACOUSTIC NODES, CORRESPONDING COMPUTER PROGRAM PRODUCT AND STORAGE MEANS - A method for obtaining a node-to-surface distance between a reference surface and a first node belonging to a network of a plurality of nodes arranged along towed acoustic linear antennas. A plurality of acoustic sequences are sent between the nodes. Each sequence is used to estimate an inter-node distance as a function of a propagation duration of the sequence between nodes. After emission by the first node of a given signal: the first node measures a first propagation duration of a first reflection by the reference surface of the given signal, and a first value of the node-to-surface distance is obtained as a function of that first propagation duration; and/or a second node measures a second propagation duration of a second reflection by the reference surface of the given signal, and a second value of the node-to-surface distance is obtained as a function of that second propagation duration. | 2013-01-03 |
20130003504 | UNIVERSAL TIMEPIECE DIAL, ANALOGICAL TIMEPIECE AND DIGITAL TIMEPIECE COMPRISING THE DIAL. - A world timepiece dial comprising a first ring ( | 2013-01-03 |
20130003505 | Electronic Device and Method Providing Improved World Clock Feature - An improved electronic device and method provide an improved clock feature that includes an improved world clock function. | 2013-01-03 |