| 01st week of 2013 patent applcation highlights part 24 |
| Patent application number | Title | Published |
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| 20130002306 | STAGE CIRCUIT AND SCAN DRIVER USING THE SAME - A stage circuit includes an output unit including a first transistor coupled between a first power source and an output terminal of the stage circuit, and having a gate electrode coupled to a first node, a second transistor coupled between the output terminal and a third input terminal of the stage circuit, and having a gate electrode coupled to a second node, and a third transistor coupled between the output terminal and a second power source, and having a gate electrode coupled to a third node; a progressive driver coupled to first, second, and sixth input terminals of the stage circuit; and a concurrent driver coupled to at least one of fourth and fifth input terminals of the stage circuit. In the stage circuit, clock signals supplied to the first, second, and third input terminals during the second period are concurrently set to a gate-on or gate-off voltage. | 2013-01-03 |
| 20130002307 | STAGE CIRCUIT AND SCAN DRIVER USING THE SAME - A stage circuit and a scan driver using the same that is capable of concurrently (e.g., simultaneously) or progressively supplying a scan signal to a plurality of scan lines. The stage circuit includes a progressive driver and a concurrent driver. | 2013-01-03 |
| 20130002308 | DRIVE CIRCUIT - A drive circuit that outputs low-voltage differential signals to an external load circuit, including: first and second nodes to which the external load circuit is connected; a first series circuit including first and second switching elements, connected in series using the first node as a common node; a second series circuit including third and fourth switching elements, connected in series using the second node as a common node; and a first current source that outputs a predetermined current to the first and second series circuits, in which a back gate of a transistor of a first conductivity type included in at least one of the first and third switching elements or the first current source is forward-biased. | 2013-01-03 |
| 20130002309 | METHOD OF DRIVING A GATE LINE AND GATE DRIVE CIRCUIT FOR PERFORMING THE METHOD - A pull-up driving part maintains a signal of a first node at a high level by receiving a turn-on voltage in response to one of a previous stage or a vertical start signal. A pull-up part outputs a clock signal through an output terminal in response to the signal of the first node. A first holding part maintains a signal of a second node at a high level or a low level when the signal of the first node is respectively low or high. A second holding part maintains the signal of the first node and a signal of the output terminal at a ground voltage in response to the signal of the second node or a delayed and inverted clock signal. | 2013-01-03 |
| 20130002310 | GATE DRIVING CIRCUIT - A gate driving circuit includes a thermal sensing unit for sensing temperature to output a sensing voltage, a compare unit for comparing the sensing voltage with a reference voltage to output a control voltage, a charging control module for controlling a pre-charging operation according to the control voltage, and a plurality of shift register stages. Each shift register stage includes an input unit for outputting a driving control voltage according to a first input signal, a clock input unit for outputting a driving voltage according to a system clock, a driving unit for outputting a gate signal according to the driving control voltage and the driving voltage, and a pull-down unit for pulling down the gate signal and the driving control voltage according to a second input signal. The driving voltage is also controlled by the pre-charging operation for enhancing driving ability. | 2013-01-03 |
| 20130002311 | TRANSMIT DRIVER CIRCUIT - A driver circuit includes a differential input, a differential output, a bias node, a first T-coil having a first node coupled to the negative output node and a second node coupled to a source of supply voltage, a second T-coil having a first node coupled to the positive output node and a second node coupled to the source of supply voltage, a first transistor having a current path coupled between the center tap of the first T-coil and a first intermediate node, a second transistor having a current path coupled between the center tap of the second T-coil and a second intermediate node, a third transistor having a current path coupled between the first intermediate node and ground, and a fourth transistor having a current path coupled between the second intermediate node and ground. | 2013-01-03 |
| 20130002312 | DRIVER CIRCUIT, METHOD OF MANUFACTURING THE DRIVER CIRCUIT, AND DISPLAY DEVICE INCLUDING THE DRIVER CIRCUIT - Provided are a driver circuit which suppresses damage of a semiconductor element due to ESD in a manufacturing process, a method of manufacturing the driver circuit. Further provided are a driver circuit provided with a protection circuit with low leakage current, and a method of manufacturing the driver circuit. By providing a protection circuit in a driver circuit to be electrically connected to a semiconductor element in the driver circuit, and by forming, at the same time, a transistor which serves as the semiconductor element in the driver circuit and a transistor included in the protection circuit in the driver circuit, damage of the semiconductor element due to ESD is suppressed in the process of manufacturing the driver circuit. Further, by using an oxide semiconductor film for the transistor included in the protection circuit in the driver circuit, leakage current in the protection circuit is reduced. | 2013-01-03 |
| 20130002313 | SWITCHING POWER SUPPLY DEVICE AND A SEMICONDUCTOR INTEGRATED CIRCUIT - In a switching power source which controls a current which flows in an inductor through a switching element which performs a switching operation in response to a PWM signal, and forms an output voltage by a capacitor which is provided in series in the inductor, a booster circuit which is constituted of a bootstrap capacity and a MOSFET is provided between an output node of the switching element and a predetermined voltage terminal. The boosted voltage is used as an operational voltage of a driving circuit of the switching element, another source/drain region and a substrate gate are connected with each other, and a junction diode between one source/drain region and the substrate gate is inversely directed with respect to the boosted voltage which is formed by the bootstrap capacity. | 2013-01-03 |
| 20130002314 | METHOD AND APPARATUS FOR LOW JITTER DISTRIBUTED CLOCK CALIBRATION - A method and apparatus for generating an accurate clock generator timing source, comprising minimal jitter, excellent resolution, and an extended calibration range, for use, for example, in a system requiring accurate low power operation. In particular, a clock generation system is adapted to receive a generated clock input, a reference clock input, and an adjustment parameter comprising a sign bit and p data bits. The calibration logic system is further adapted to output and modify a calibrated clock, using distributed pulse modification. The adjustment parameter may be automatically generated. | 2013-01-03 |
| 20130002315 | ASYNCHRONOUS CLOCK ADAPTER - An asynchronous clock adapter is disclosed that transmits multiple data elements from a buffer in a source clock domain to a data register in a destination clock domain. The buffer can be selected by a pointer register in the destination clock domain and a round trip timing path exists from the pointer register to the data register. Data elements from the buffer can be sent on interleaved cycles of the destination clock such that each data element can have a delay constraint of more than one clock period. | 2013-01-03 |
| 20130002316 | RESET PULSE ENCODING AND DECODING SCHEME WITH NO INTERNAL CLOCK - An integrated circuit (IC) provides a reset function. The IC receives a command that is defined by a first sequence of counts of signal transitions of a first signal during windows of a second signal and provides a reset function when it is determined that the command is received. A device including the IC and a system including the device are provided. | 2013-01-03 |
| 20130002317 | DIGITAL PHASE LOCKED LOOP CIRCUITS WITH MULTIPLE DIGITAL FEEDBACK LOOPS - Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals. | 2013-01-03 |
| 20130002318 | WIDE-RANGE CLOCK MULTIPLIER - A variable-frequency input clock signal and a reference clock signal are compared during a frequency-compare interval to generate a value that indicates a ratio of their frequencies. The frequency-ratio value is then applied to configure a wide-range frequency-locking oscillator for operation with a narrowed input frequency range. Because the narrowed input frequency range is targeted to the input clock frequency, the wide-range oscillator is able to rapidly lock to a frequency multiple of the input clock frequency. Because the frequency-compare interval is also brief, an extremely fast-locking, clock-multiplying operation may be effected over a relatively wide range of input clock frequencies | 2013-01-03 |
| 20130002319 | Frequency Divider and Phase Locked Loop Including the Same - A frequency includes a first edge detection unit configured to generate a first count signal responsive to detecting first edges of an input signal and a second edge detection unit configured to generate a second count signal responsive to detecting the first edges of the input signal in a first operation mode and to generate the second count signal responsive to detecting second edges of the input signal in a second operation mode. One of the first and second edges is a rising edge and the other of the first and second edges is a falling edge. A pulse triggered buffer unit generates an output signal responsive to the first and second count signals. The output signal is divided by a target division ratio with respect to the input signal that is an odd number division ratio in one mode and an even number division ratio in the other mode. | 2013-01-03 |
| 20130002320 | DELAY-LOCKED LOOP - A delay-locked loop (DLL) which receives a reference clock signal and outputs an output clock signal is provided. The DLL includes a phase detector, a delay chain, an anti-false lock (AFL) circuit, and a loop filter. The phase detector outputs a first comparison signal according to a phase comparison between the reference clock signal and the output clock signal. The delay chain generates a plurality of strobe clock signals and the output clock signal by delaying the reference clock signal for different intervals. The AFL circuit outputs a second comparison signal according to a phase comparison between the reference clock signal and the strobe clock signals. The loop filter controls the delay time of the output clock signal according to the first and the second comparison signals in order to lock the delay time of the output clock signal at a preset value. | 2013-01-03 |
| 20130002321 | CLOCK SIGNAL GENERATING CIRCUIT AND POWER SUPPLY INCLUDING THE SAME - The present invention relates to a clock signal generating circuit and a power supply including the same. The present invention includes: a counter for counting one period of an input clock signal by using a reference clock signal, and generating a count signal; and a clock signal generator for receiving the count signal and the reference clock signal, dividing the count signal to generate a quotient and a remainder, setting the quotient as a reference period of an output clock signal, and distributing and disposing the remainder to the output clock signal with a plurality of periods occurring for one period of the input clock signal. | 2013-01-03 |
| 20130002322 | SEMICONDUCTOR DEVICE - A semiconductor device includes a delay unit configured to delay an inputted clock to generate a delay clock, a selection unit configured to select and output one of the inputted clock and the delay clock, a delay locked loop configured to perform a delay locking operation using a signal delivered from the selection unit, and a selection control unit configured to control the selection unit in response to a comparison of one period of the inputted clock and a maximum delay value of the delay locked loop. | 2013-01-03 |
| 20130002323 | DUTY CYCLE CORRECTION CIRCUIT - A duty cycle correction circuit includes a duty correction block configured to generate a first pre-corrected signal and a second pre-corrected signal in response to a duty code and an input signal; a duty-corrected signal generation block configured to generate a duty-corrected signal in response to a first select signal, a second select signal, the first pre-corrected signal and the second pre-corrected signal; and a control block configured to generate the duty code, the first select signal and the second select signal in response to the duty-corrected signal and the input signal. | 2013-01-03 |
| 20130002324 | CIRCUITS AND METHODS FOR CLOCK SIGNAL DUTY-CYCLE CORRECTION - Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for correcting duty-cycle distortion of differential output clock signals provided from a clock distribution network. In one such method, a single-ended clock signal is generated from differential input clock signals for distribution over a clock distribution network and from which the differential output clock signals are generated. A delay of a model delay path is matched to a propagation delay of the clock distribution network, and the single ended clock signal is adjusted to compensate for duty-cycle distortion. | 2013-01-03 |
| 20130002325 | CONSTANT SWITCHING CURRENT FLIP-FLOP - A constant switching current flip-flop includes a latch circuit that provides latch outputs of the flip-flop, whereby the latch outputs are reset to zero at the beginning of each clock cycle to eliminate pattern dependent switching currents. The latch circuit is reset responsive to control signals provided without significant delay. | 2013-01-03 |
| 20130002326 | LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE - In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×10 | 2013-01-03 |
| 20130002327 | BIAS TEMPERATURE INSTABILITY-RESISTANT CIRCUITS - Standard cells that include transistors subject to aging as a result of BTI-related operating conditions are identified and replaced with BTI-resistant standard cells, for example. The BTI-resistant standard cells are typically functionally equivalent circuits (such as circuits included in standard cells in a design library) and are arranged to ensure that critical transistors are protected (e.g., by either extending recovery times and/or turning the transistor off in response to a critical edge transition). | 2013-01-03 |
| 20130002328 | SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING FLIP-FLOP - A semiconductor integrated circuit includes a first retention flip-flop configured in a first type in which a retention flip-flop is able to retain data based on one of a low-level clock signal and a high-level clock signal, and unable to retain data based on another one of the low-level clock signal and high-level clock signal, and a second retention flip-flop configured in a second type in which a retention flip-flop is able to retain data based on the low-level clock signal and also able to retain data based on the high-level clock signal. | 2013-01-03 |
| 20130002329 | DELAY CONTROL DEVICE - A delay control device that controls a relative delay time between two signals and is easy to be miniaturized is provided. Signal routes | 2013-01-03 |
| 20130002330 | Systems and Methods for Crossover Delay to Prevent Power Module Faults - Systems and methods detect when a transition from a first power module to a second power module is taking place and generates a lockout pulse when the transition is detected. The lockout pulse initiates the blocking of a predetermined number of gate pulses from reaching the second power module. When the predetermined number of gate pulses are blocked, the systems and methods reset to allow complete gate pulses to reach the second module, and continues to detect when the next transition takes place. | 2013-01-03 |
| 20130002331 | SEMICONDUCTOR DEVICE AND DESIGNING METHOD OF THE SAME - A semiconductor device includes a control target circuit section and a voltage control section configured to dynamically control a supply voltage to the control target circuit section. The control target circuit section includes a delay monitor circuit configured to measure a delay in the control target circuit section as a monitor delay and a target delay register configured to store target delay data for a target value of the monitor delay and which is set before the measuring of the delay, based on an external signal. The delay monitor circuit compares the monitor delay and the target delay and sends a comparison resultant signal to the voltage control section to show a result of the comparison. The voltage control section controls the supply voltage based on the comparison resultant signal such that the monitor delay approaches to the target delay. | 2013-01-03 |
| 20130002332 | BUS SWITCH CIRCUIT - A bus switch circuit according to an embodiment includes a signal transmission circuit connected between a first terminal and a second terminal. The bus switch circuit includes a first switch element controlled by a first control signal. The bus switch circuit includes a second switch element controlled by a second control signal. The bus switch circuit includes a delay signal generating circuit that outputs a delay signal based on a first signal varying with a first voltage applied to the first terminal and a second signal varying with a second voltage applied to the second terminal. The bus switch circuit includes a control signal generating circuit that outputs the first control signal and the second control signal based on the first signal, the second signal, and the delay signal. | 2013-01-03 |
| 20130002333 | Receiver side combining in LINC Amplifier - A new method of combing signals of equal magnitude using the space-time (ST) 2×1 code at the receiver in a linear amplification with nonlinear components (LINC) is provided to obviate the combiner power loss and isolation requirements inherent in using traditional methods. | 2013-01-03 |
| 20130002334 | INTEGRATED CIRCUIT, ELECTRONIC DEVICE AND METHOD FOR CONFIGURING A SIGNAL PATH FOR A TIMING SENSITIVE SIGNAL - An integrated circuit comprising at least one signal path for a timing sensitive signal. At least one section of the signal path comprises a first section path comprising a first propagation timing factor, at least one further section path comprising a second propagation timing factor different to the first propagation timing factor, and a path selection component arranged to enable the selection of one of the first and at least one further section paths via which the timing sensitive signal is to propagate through the at least one section of the signal path based on at least one from a group consisting of: the first propagation timing factor, second propagation timing factor. | 2013-01-03 |
| 20130002335 | DEVICE AND METHOD FOR ELECTRICALLY DECOUPLING A SOLAR MODULE FROM A SOLAR SYSTEM - Devices and methods for electrically decoupling a solar module from a solar system are described. In one embodiment, a solar system includes a string of a plurality of solar modules coupled with an inverter through a DC power line. An AC input is coupled with the DC power line. A device is also included and is configured to provide a closed circuit for one of the plurality of solar modules if an AC signal voltage from the AC input is present on the DC power line, and is configured to provide an open circuit for the one of the plurality of solar modules if no AC signal voltage from the AC input is present on the DC power line. | 2013-01-03 |
| 20130002336 | BIDIRECTIONAL SWITCH - A bidirectional switch according to one embodiment switches bidirectionally the direction of current flowing between a first and a second terminal, and includes: first and second series circuit sections including first and second semiconductor switch elements that do not have a tolerance in a reverse direction, and first and second reverse current blocking diode sections serially connected to the first and second semiconductor switch elements in a forward direction. The first series circuit section and the second series circuit section are connected in parallel between the first and second terminals so that the forward directions of the first and second semiconductor switch elements face opposite to each other. Each of the first and second reverse current blocking diode sections is configured by connecting in parallel a diode containing GaN as a semiconductor material and a diode containing SiC as a semiconductor material. | 2013-01-03 |
| 20130002337 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Disclosed here is a semiconductor integrated circuit device configured to suppress a voltage drop over the route for transmitting voltages from a power cut-off switch to a power cut-off region without lowering the degree of freedom in routing signal wires in that region. The semiconductor integrated circuit device includes a semiconductor chip in which the power cut-off switch and power cut-off region are provided. A reduction in the number of wiring channels in the power-cut off region is avoided by locating the power cut-off switch outside the power cut-off region. Over the substrate, a substrate-side feed line is formed to transmit a power-supply voltage from the semiconductor chip to outside thereof via the power cut-off switch, before introducing the voltage again into the chip to feed the power cut-off region, thus suppressing the voltage drop between the power cut-off switch and the power cut-off region. | 2013-01-03 |
| 20130002338 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - SOI MOSFETs are used for the transistors for switching of an antenna switch and yet harmonic distortion is significantly reduced. Capacitance elements are respectively added to either the respective drains or gates of the transistors comprising the through MOSFET group of reception branch of the antenna switch. This makes the voltage amplitude between source and gate and that between drain and gate different from each other. As a result, the voltage dependence of source-drain parasitic capacitance becomes asymmetric with respect to the polarity of voltage. This asymmetry property produces signal distortion having similar asymmetry property. Therefore, the following can be implemented by setting it so that it has the same amplitude as that of second-harmonic waves arising from the voltage dependence of substrate capacitance and a phase opposite to that of the same: second-order harmonic distortion can be canceled out and thus second-order harmonic distortion can be reduced. | 2013-01-03 |
| 20130002339 | LOW-POWER, LOW-LATENCY POWER-GATE APPARATUS AND METHOD - A low-power, low-latency power-gate (LPLLPG) circuit is used to shut off or otherwise reduce power that is provided to electronic component(s), such as in a sleep or standby mode. ON-rush current is controlled by sizing at least one transistor in the power-gate circuit, and power consumption of the power-gate circuit in both standby state and active state is reduced by not using additional delay elements. Ramping up a gated voltage supply with low ON-rush current is performed by applying/using logic rather than delay signals. This logic does not turn ON transistors in the power-gate circuit until the gated voltage supply has ramped up close to a level of an ungated voltage supply. By not using additional delay cells, faster turn OFF of the gated voltage supply is obtained. | 2013-01-03 |
| 20130002340 | STAGE CIRCUIT AND SCAN DRIVER USING THE SAME - A stage circuit is capable of concurrently or progressively supplying scan signals. The stage circuit includes a progressive driver including a first transistor and a second transistor, and a concurrent driver including an 11 | 2013-01-03 |
| 20130002341 | INPUT APPARATUS WITH HAPTIC FEEDBACK - The input device has a printed circuit board ( | 2013-01-03 |
| 20130002342 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes first and second chips sharing first and second data channels. The first and second chips output normal data of the respective chips through the first and second data channels in a normal operation, and the first chip outputs test data of the first chip through the first data channel, and the second chip outputs test data of the second chip through the second data channel in a test operation. | 2013-01-03 |
| 20130002343 | HIGH VOLTAGE REGULATION IN CHARGE PUMPS - High voltage regulation in charge pumps. A circuit includes a voltage regulator with a first input in communication with a reference voltage. The circuit also includes a data latch having a signal input coupled to receive an output of the voltage regulator and coupled to receive a clock input from a clock source. The circuit further includes a delay circuit having an input coupled to receive the clock input from the clock source. Further, the circuit includes a logic gate having a first input coupled with an output of the data latch and a second input coupled with an output of the delay circuit. Moreover, the circuit includes a charge pump having an input coupled with an output of the logic gate and an output coupled with a second input of the voltage regulator. The output of the charge pump provides an output voltage. | 2013-01-03 |
| 20130002344 | ANALOG DELAY LINES AND ADAPTIVE BIASING - Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive biasing. Embodiments of adaptive biasing are described and may generate a bias signal for an analog delay line during start-up. The bias signal may be based in part on the frequency of operation of the analog delay line. | 2013-01-03 |
| 20130002345 | ADAPTIVE FILTER - An adaptive filter includes: a filter configured to perform a filtering process for an input signal with a filter coefficient set therein, and output the processed input signal as an output signal; a calculating unit configured to calculate a value indicative of an error between an amplitude of the output signal and a reference amplitude; an output unit configured to output a first constant as a parameter when the amplitude of the output signal is greater than the predetermined amplitude, the parameter used when updating the filter coefficient, and output a second constant as the parameter when the amplitude of the output signal is smaller than the predetermined amplitude; and an updating unit configured to update the filter coefficient with an update amount corresponding to the parameter and the value indicative of the error, such that the error is reduced. | 2013-01-03 |
| 20130002346 | Parallel Correction Amplifier - There is disclosed a power supply stage, and a method of controlling such, comprising: a means for generating an intermediate supply signal in dependence on a reference signal representing a desired power supply; and a plurality of adjusting means, each adapted to generate an adjusted supply signal tracking the reference signal, in dependence on the generated intermediate supply signal and the reference signal. | 2013-01-03 |
| 20130002347 | COUPLING SYSTEM FOR DATA RECEIVERS - A data receiver, a method of operating a data receiver, and an integrated coupling system in a data receiver are disclosed. In one embodiment, the data receiver comprises an input terminal for receiving an input data signal, an input amplifier for amplifying selected components of the input data signal, and an input signal path for transmitting specified high-frequency components and a baseline component of the input data signal from the input terminal to the input amplifier. The data receiver further comprises a feed-forward resistive network connected to the input terminal and to the input amplifier. This feed forward resistive network is used to forward a low-frequency drift compensation signal from the input terminal to the input amplifier, using a passive resistive network, to compensate for low frequency variations in the input data signal, and to develop a desired bias voltage at the input amplifier. | 2013-01-03 |
| 20130002348 | AMPLIFIER WITH IMPROVED NOISE REDUCTION - An amplifier with improved noise reduction is disclosed. In one implementation, an amplifier is provided that includes a main output stage configured to output an amplified signal at a main output terminal, a secondary output stage configured to output a copy of the amplified signal at a secondary output terminal, and a signal coupler configured to provide a variable resistance coupling between the secondary output terminal and the main output terminal to reduce noise at the main output terminal. | 2013-01-03 |
| 20130002349 | Bypass Power Amplifier For Improving Efficiency At Low Power - Embodiments of a two-stage bypass power amplifier are provided. In general, the two-stage bypass power amplifier is configured to receive a RF signal that is to be transmitted to a remote device and provide gain to the RF signal prior to the RF signal being transmitted to the remote device. The two-stage bypass power amplifier is configured to operate efficiently (in terms of power) at two different gain or output power levels and can be extended to operate efficiently at additional gain or output power levels. | 2013-01-03 |
| 20130002350 | Differential Comparator - A comparator includes a differential amplifier having first and second input terminals and first and second output terminals. An input stage is operable to receive first and second input signals. The input stage includes first and second capacitors coupled to the first and second input terminals, respectively. Circuitry is operable to selectively couple the first input signal to the first capacitor and the second input signal to the second capacitor, while coupling the first and second capacitors to the first and second output terminals, respectively, during an offset cancellation phase, and selectively couple the second input signal to the first capacitor and the first input signal to the second capacitor, while isolating the first and second capacitors from first and second output terminals during a comparison phase. | 2013-01-03 |
| 20130002351 | VOLTAGE GENERATING CIRCUIT AND METHOD - A circuit comprises a first amplifier and a second amplifier. The first amplifier is configured to amplify a first voltage difference between a first voltage and a second voltage, and to generate a third voltage. The second amplifier is configured to amplify a second voltage difference between the third voltage and an input voltage, and to generate an output voltage. The first voltage is a voltage at a first terminal of a first transistor. The second voltage is a voltage at a second terminal of a second transistor. A first gate of the first transistor is adapted to receive the third voltage. A second gate of the second transistor is adapted to receive the input voltage. Threshold voltage values of the first transistor and the second transistor differ. | 2013-01-03 |
| 20130002352 | SENSING CIRCUIT - A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of an operational amplifier. | 2013-01-03 |
| 20130002353 | MULTI-INPUT OPERATIONAL AMPLIFIER AND OUTPUT VOLTAGE COMPENSATION METHOD THEREOF - An output error compensation method adapted to a multi-input operational amplifier is disclosed. The output error compensation method includes following steps. A plurality of original transconductances of a plurality of differential pairs is obtained regarding a specific combination of input voltages received by the differential pairs. Transconductance differences of a plurality of adjustable differential pairs among the differential pairs are obtained according to the original transconductances. Adjusted transconductance of the adjustable differential pairs are obtained according to the original transconductances and the transconductance differences. Transconductances of the adjustable differential pairs are respectively adjusted according to the adjusted transconductances, so that an output voltage can match an expected value when each of a plurality of combinations of the input voltages is received. | 2013-01-03 |
| 20130002354 | SIGNALING SYSTEMS, PREAMPLIFIERS, MEMORY DEVICES AND METHODS - Signaling systems, preamplifiers, memory devices and methods are disclosed, such as a signaling system that includes a transmitter configured to receive a first digital signal. The transmitter provides a transmitted signal corresponding to the digital signal to a signal path. A receiver system coupled to the signal line includes a preamplifier coupled to receive the transmitted signal from the signal path. The preamplifier includes a common-gate amplifying transistor that is configured to provide an amplified signal. The receiver system also includes a receiver coupled to receive the amplified signal from the preamplifier. The receiver is configured to provide a second digital signal corresponding to the amplified signal received by the receiver. Such a signaling system may be used in a memory device or in any other electronic circuit. | 2013-01-03 |
| 20130002355 | DIFFERENTIAL AMPLIFIER AND COMPARATOR - According to one embodiment, a differential amplifier includes a differential circuit, an output circuit, and a clipper circuit. The differential circuit generates a pair of differential currents in accordance with a difference in potential between a pair of input signals. The output circuit receives the pair of differential currents and generates an output voltage in accordance with the current difference. The clipper circuit suppresses the output voltage within a range to be able to convert to a low level or to a high level being higher than the low level. | 2013-01-03 |
| 20130002356 | OPERATIONAL AMPLIFIER - An operational amplifier including a primary differential input pair, a primary tail current source module, N auxiliary differential input pairs, and N auxiliary tail current source modules is disclosed. A first and a second input terminal of the primary differential input pair respectively receive a first and a second input signal, wherein first input signal and the second input signal are differential to each other. The primary tail current source module supplies a tail current to the primary differential input pair during a first time interval. A first and a second input terminal of each of the auxiliary differential input pairs respectively receive the first and the second input signal. Each of the auxiliary tail current source modules supplies an auxiliary tail current to the corresponding auxiliary differential input pair during a second time interval. The first time interval and the second time interval partially overlap each other. | 2013-01-03 |
| 20130002357 | Providing Automatic Power Control For A Power Amplifier - A power control circuit is coupled to receive a feedback signal from a power amplifier (PA) and generate a control signal to control a variable gain amplifier (VGA) coupled to an input to the PA based on the feedback signal. The power control circuit may include, in one embodiment, a mute circuit to generate a mute signal to be provided to the VGA when the control signal is less than a first level and a clamp circuit to clamp a control voltage used to generate the control signal from exceeding a threshold level. | 2013-01-03 |
| 20130002358 | ELECTRONIC CIRCUITRY FOR HIGH-TEMPERATURE ENVIRONMENTS - A circuitry adapted to operate in a high-temperature environment of a turbine engine is provided. A relatively high-gain differential amplifier ( | 2013-01-03 |
| 20130002359 | AMPLIFIER WITH HIGH POWER SUPPLY NOISE REJECTION - An amplifier with high power supply rejection is disclosed. In an exemplary implementation, an amplifier includes a first stage configured to receive a signal to be amplified, a second stage comprising an input transistor coupled to the first stage, and further comprising at least one additional transistor, and a voltage regulator configured to received a first supply voltage and generate a regulated supply voltage, the first supply voltage coupled to the at least one additional transistor, the regulated supply voltage coupled to the first stage and the input transistor of the second stage to improve power supply noise rejection of the apparatus. | 2013-01-03 |
| 20130002360 | SEMICONDUCTOR INTEGRATED CIRCUIT - A phase locked loop (PLL) which has a desired frequency characteristic even though a manufacturing process of a semiconductor integrated circuit has fluctuations. The semiconductor integrated circuit includes the PLL and a control unit. The PLL has a phase frequency detector, a loop filter, a voltage controlled oscillator (VCO) and a divider. The VCO comprises a voltage-current converter (VIC) and a ring oscillator. In response to a control voltage, the VIC generates a control current for setting each operating current of the ring oscillator. The control unit switches the PLL to a calibration operating period of its open loop and a normal operating period of its closed loop. | 2013-01-03 |
| 20130002361 | VCO INSENSITIVE TO POWER SUPPLY RIPPLE - A ring oscillator that is more insensitive to power supply ripple utilizes an amplifier circuit having a first input coupled to a reference voltage. A current is generated that represents a control voltage supplied to the oscillator control circuit. That current is mirrored and supplied as a control current to the oscillator. An amplifier is used in a feedback loop to ensure that incremental variations in source to drain voltage of a first transistor of the current mirror is present in a second transistor of the current mirror to make the control current more immune to supply ripple. | 2013-01-03 |
| 20130002362 | MAGNETORESISTIVE RADIOFREQUENCY OSCILLATOR - A radiofrequency oscillator comprises: a free layer ( | 2013-01-03 |
| 20130002363 | OUT-OF-PLANE RESONATOR - A microelectromechanical system (MEMS) device includes a resonator anchored to a substrate. The resonator includes a first strain gradient statically deflecting a released portion of the resonator in an out-of-plane direction with respect to the substrate. The resonator includes a first electrode anchored to the substrate. The first electrode includes a second strain gradient of a released portion of the first electrode. The first electrode is configured to electrostatically drive the resonator in a first mode that varies a relative amount of displacement between the resonator and the first electrode. The resonator may include a resonator anchor anchored to the substrate. The first electrode may include an electrode anchor anchored to the substrate in close proximity to the resonator anchor. The electrode anchor may be positioned relative to the resonator anchor to substantially decouple dynamic displacements of the resonator relative to the electrode from changes to the substrate. | 2013-01-03 |
| 20130002364 | SWITCHABLE ELECTRODE FOR POWER HANDLING - A MEMS oscillator includes a resonator body and primary and secondary drive electrodes to electrostatically drive the resonator body. Primary and secondary sense electrodes sense motion of the resonator body. The primary and secondary drive and sense electrodes are configured to be used together during start-up of the MEMS oscillator. The secondary drive electrode and secondary sense electrode are disabled after start-up, while the primary drive and sense electrodes remain enabled to maintain oscillation. | 2013-01-03 |
| 20130002365 | METHOD OF REGULATING A TIMEOUT DELAY INTRODUCED AT START-UP OF A DIGITAL SYSTEM TO ENSURE READINESS OF A MASTER AMPLITUDE-REGULATED CRYSTAL OSCILLATOR AND IMPLEMENTING CIRCUIT - A crystal oscillator circuit is configured to output an oscillation signal. A bias circuit responds to control signal to generate a bias current for application to the crystal oscillator circuit. A current generator generates a sense current from the control signal. The sense current is compared to a reference current by a comparator circuit. The comparator circuit generates a ready signal in response to the comparison. The ready signal is indicative of whether the oscillation signal output from the crystal oscillator circuit is ready for use by other circuitry. The reference current may be generated by a circuit which replicates the bias circuit. | 2013-01-03 |
| 20130002366 | COMPARATOR-LESS PULSE-WIDTH MODULATION - A pulse width modulation device includes a switching transistor for defining modulation phases, a capacitor, and switches arranged to: a) in a first phase, charge the capacitor to a voltage corresponding to the on/off threshold of the switching transistor, and b) in a second phase, connect the capacitor between a terminal for applying a setpoint voltage and the gate of the switching transistor. A constant current source is connected to apply a current in the capacitor tending to bring the gate of the switching transistor toward the on/off threshold. | 2013-01-03 |
| 20130002367 | WIDEBAND LOW FREQUENCY IMPEDANCE TUNER - Compact electro-mechanical impedance tuners for frequencies as low as 1 MHz use the concept of a cylindrical transmission line with the signal conductor being a spiral wire wound around a metallic cylinder and separated from it by a layer of dielectric material. A conductive wheel is running over the spiral wire and, as the cylinder rotates, the transmission phase between one terminal of the spiral wire and the wheel changes. By connecting a rotating parallel plate variable capacitor to the wheel creates an impedance tuner, capable of generating high reflection factors at very low frequencies at any area of the Smith chart. By cascading two or more such tuners allows tuning at harmonic frequencies at the rate of one frequency per tuner section. The reduction in size comparing with traditional transmission line tuners is of the order of 150:1. | 2013-01-03 |
| 20130002368 | Circuits and Methods for Providing an Impedance Adjustment - An apparatus includes a signal generator and a control circuit. The signal generator includes a control terminal and includes a current electrode coupled to a terminal that is configured to couple to a power line to receive direct current (DC) power from a power generator. The control circuit is coupled to the current electrode and the control terminal of the signal generator. The control circuit determines an impedance associated with the power generator and applies a control signal to the control terminal of the signal generator to produce an impedance adjustment signal on the current electrode for communication to the power generator through the power line in response determining the impedance. | 2013-01-03 |
| 20130002369 | ETHERNET END STATION - A communication system ( | 2013-01-03 |
| 20130002370 | CIRCUIT ARRANGEMENT WITH IMPROVED DECOUPLING - A circuit arrangement includes a component having a closed signal path, that closed signal path connected to a first port, a second port and at least a third port. The component has a directed signal flow of a signal applied to one of that ports. Such a coupling device can be connected to a transmitter and to a receiver path, respectively. | 2013-01-03 |
| 20130002371 | DUPLEXER - A duplexer includes: a reception filter connected between a reception terminal and an antenna terminal; a transmission filter connected between a transmission terminal and the antenna terminal; and a wiring substrate including the reception filter and the transmission filter in an upper surface, the reception terminal, the transmission terminal and the antenna terminal being formed in a lower surface, and a reception electrode electrically connected to the reception terminal, a transmission electrode electrically connected to the transmission terminal, an antenna electrode electrically connected to the antenna terminal, and a circular metal layer surrounding the reception, transmission and antenna electrodes, and electrically connected to a ground being formed in an upper surface, wherein a shortest distance between a side of the circular metal layer closest to the reception and transmission terminals and the reception electrode is larger than a width of the side of the circular metal layer. | 2013-01-03 |
| 20130002372 | LADDER FILTER AND DUPLEXER - A ladder filter including a series arm resonator and a parallel arm resonator disposed on the same common piezoelectric substrate achieves improved miniaturization. The ladder filter includes series arm resonators and parallel arm resonators, which include elastic wave resonators, and are disposed on the same common piezoelectric substrate, at least one parallel arm resonator of the series arm resonators and the parallel arm resonators includes a first resonator and a second resonator electrically connected in parallel to each other, and the first resonator and the second resonator are arranged in parallel or substantially in parallel in a direction perpendicular or substantially perpendicular to an elastic wave propagation direction, on one side outside one series arm resonator of remaining resonators in the elastic wave propagation direction thereof. | 2013-01-03 |
| 20130002373 | HIGH REJECTION BAND-STOP FILTER AND DIPLEXER USING SUCH FILTERS - The present invention relates to a high rejection stop band filter and a diplexer using such filters. | 2013-01-03 |
| 20130002374 | VARIABLE RESONATOR, VARIABLE BANDWIDTH FILTER, AND ELECTRIC CIRCUIT DEVICE - A variable resonator includes a ring-shaped conductor line ( | 2013-01-03 |
| 20130002375 | TRANSMISSION LINE STRUCTURE WITH LOW CROSSTALK - A transmission line structure is disclosed. The structure includes at least one signal transmission line and a pair of ground transmission lines embedded in a first level of a dielectric layer on a substrate, wherein the pair of ground transmission lines are on both sides of the signal transmission line. A first ground layer is embedded in a second level lower than the first level of the dielectric layer and a second ground layer is embedded in a third level higher than the first level of the dielectric layer. First and second pairs of via connectors are embedded in the dielectric layer, wherein the first pair of via connectors electrically connects the pair of ground transmission lines to the first ground layer and the second pair of via connectors electrically connects the pair of ground transmission lines to the second ground layer. | 2013-01-03 |
| 20130002376 | MISALIGNMENT TOLERANT CONTACTLESS RF COUPLING DEVICE - Some embodiments relate to a contactless RF coupling device that includes a first substrate and a second substrate. The RF coupling device may provide a broadband, low loss electrical connection without mechanical contact as would a conventional mechanical connector. The first substrate includes a first ground plane on one side and a first transmission line on an opposing side. The first transmission line includes an enlarged first coupling member at an end of the first transmission line. The second substrate includes a second ground plane on one side and a second transmission line on an opposing side. The second transmission line includes an enlarged second coupling member at an end of the second transmission line. The first ground plane may not extend under the first coupling member and the second ground plane may include an opening that is aligned with the second coupling member. | 2013-01-03 |
| 20130002377 | STRUCTURE - A second conductor ( | 2013-01-03 |
| 20130002378 | DIGITAL ELECTRONIC DEVICE - This invention provides a digital electronic device comprising: a grounded metal portion comprising a first metal plate electrically connected to ground and a first substrate disposed on the first metal plate; at least one layer of differential-mode reference metal portion comprising a second substrate and a second metal plate electrically connected to the first metal plate by at least one conductive structure; a pair of differential signal lines at least partially disposed on the second substrate of the at least one layer of differential-mode reference metal portion and electromagnetically coupled to the second metal plate of the at least one layer of differential-mode reference metal portion; and an equalizer electrically connected to the pair of differential signal lines. | 2013-01-03 |
| 20130002379 | HARMONIC IMPEDANCE TUNER WITH FOUR WIDEBAND PROBES AND METHOD - A method for calibrating multi carriage-multi probe impedance tuners for synthesizing distinct, user defined impedances at a number of harmonic frequencies, employs two-port s-parameter characterization of the tuning sections on a pre-calibrated vector network analyzer at a pre-selected number of probe positions. All tuner probes are wideband and capable of creating high reflection factor at all harmonic frequencies considered. The data are saved in memory and all permutations of the s-parameters at all harmonic frequencies are generated. Subsequently the data are organized blocks based on reflection factor values fitting in a number of segments of the Smith chart; this allows accelerated numeric search through a pre-selection of data block depending on the target reflection factor chosen. The method can be used for two three and four probe tuners. | 2013-01-03 |
| 20130002380 | ELECTRIC CONTACT ELEMENT AND METHOD FOR PRODUCING AN ELECTRIC CONTACT ELEMENT - The present invention relates to a method for producing an electric contact element from a semifinished product and to the electric contact element and the corresponding semifinished product. The method for producing an electric contact element ( | 2013-01-03 |
| 20130002381 | REVERSIBLE ELECTROMAGNETIC CONTACTOR - A reversible unit ( | 2013-01-03 |
| 20130002382 | MAGNETIC CUP ASSEMBLY HOLDING DEVICE WITH LOW MAGNETIC LEAKAGE FIELD - A magnetic cup assembly includes at least one of a plurality of magnets and a single magnet having multiple magnetic poles disposed inside a ferromagnetic material cup. The cup has a closed bottom and a open top. The poles of the magnet or magnets are arranged such that there is substantial magnetic neutrality above the open top. | 2013-01-03 |
| 20130002383 | METHOD OF MANUFACTURE FOR ENCASED COIL BODY AND ENCASED COIL BODY - [Problem] To provide a method of manufacture for an encased coil body, which is capable of easily manufacturing an encased coil body which is configured so as to be encased in a state where a coil is enclosed within an electrically insulating resin and is also capable of favorably preventing the coil from positional misalignment or deformation at the time of the manufacture, | 2013-01-03 |
| 20130002384 | REACTOR AND REACTOR MANUFACTURING METHOD - The disclosed reactor has a case and a cylindrical molded coil assembly which is disposed inside of the case and which is formed by covering a coil with a resin, wherein the coil assembly is sealed by an iron powder mixed resin to which iron powder has been admixed. The reactor has a pillar provided as a single body with the case, and one or multiple ring-shaped core members. The ring-shaped core members are disposed outside the outer surface of the pillar such that the pillar is inserted inside the inner surface of said ring-shaped core members, and the assembly coil is disposed outside the outer surface of the ring-shaped core members such that the ring-shaped core members are inserted inside the inner surface of said coil assembly. The ring-shaped core members are sealed by means of the aforementioned iron powder-mixed resin. | 2013-01-03 |
| 20130002385 | TRANSFORMER AND DISPLAY DEVICE USING THE SAME - There is provided a transformer, and more particularly, a transformer capable of minimizing leakage inductance while satisfying a safety standard. The transformer includes: a pipe shaped body part including a plurality of coils wound around an outer peripheral surface thereof while being stacked thereon; and flange parts extended from both ends of the body part in an outer diameter direction thereof, wherein one of the flange parts formed at one end of a winding part includes at least one lead groove therein, the lead groove being formed by being cut to be extended in the outer diameter direction, and the lead groove is divided into at least two outlets by a dividing protrusion disposed in an inner portion thereof. | 2013-01-03 |
| 20130002386 | TRANSFORMER AND DISPLAY DEVICE USING THE SAME - There is provided a transformer capable of significantly reducing leakage inductance while satisfying safety standards. The transformer includes: a winding part having a plurality of coils wound on an outer peripheral surface of a pipe shaped body part while being stacked thereon; and a terminal connection part extended from one end of the winding part in an outer diameter direction thereof and having a plurality of external connection terminals coupled to a distal end thereof, the terminal connection part including at least one catching groove formed such that the coils are led to the outside of the winding part therethrough, and a lead wire of at least one of the coils being led to the outside of the winding part while maintaining a winding direction of the coils. | 2013-01-03 |
| 20130002387 | METHOD FOR FABRICATING A CARRIER WITH A THREE DIMENSIONAL INDUCTOR AND STRUCTURE THEREOF - A method for fabricating a carrier with a three-dimensional inductor comprises the steps of providing a substrate having a protective layer; forming a first photoresist layer on the protective layer; patterning the first photoresist layer to form a second opening and a plurality of disposing slots; forming a first metal layer in second opening and disposing slots; removing the first photoresist layer; forming a first dielectric layer on the protective layer; forming a second photoresist layer on the first dielectric layer; patterning the second photoresist layer to form a plurality of slots; forming a second metal layer in slots to form a plurality of inductive portions; removing the second photoresist layer; forming a second dielectric layer on the first dielectric layer; forming a third photoresist layer on the second dielectric layer; patterning the third photoresist layer to form a plurality of slots; and forming a third metal layer in slots. | 2013-01-03 |
| 20130002388 | MULTILAYERED CERAMIC ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF - There is provided a multilayered ceramic electronic component capable of securing capacitance by controlling electrode connectivity. The multilayered ceramic electronic component includes: a ceramic main body; and internal electrodes formed in the interior of the ceramic main body and having a central portion and a tapered portion becoming thinner from the central portion toward edges thereof, respectively, wherein the ratio of the area of the tapered portion to the overall area of the internal electrodes is 35% or less. A desired capacitance can be obtained by controlling an electrode connectivity even in the small high capacitance multilayered ceramic capacitor. | 2013-01-03 |
| 20130002389 | GAP COMPOSITION OF MULTI LAYERED POWER INDUCTOR AND MULTI LAYERED POWER INDUCTOR INCLUDING GAP LAYER USING THE SAME - Disclosed are a multilayered power inductor, including: a body in which a plurality of magnetic layers formed with inner electrodes are stacked; and a plurality of gap layers, wherein the plurality of gap layers are formed so as not to contact external electrodes formed at both sides of the body, and a gap composition of the multilayered power inductor.
| 2013-01-03 |
| 20130002390 | TRANSFORMER AND DISPLAY DEVICE USING THE SAME - There are provided a transformer capable of being easily manufactured by facilitating insulation between coils and minimizing leakage inductance, and a display device using the same. The transformer includes: a bobbin including at least one partition wall formed on an outer peripheral surface of a body part having a pipe; a coil group including a plurality of coils wound while being stacked on the body part and at least one insulating wire wound between the plurality of coils; and a core electromagnetically coupled to the coils to thereby form a magnetic path, wherein the plurality of coils are individually wound so as to be uniformly disposed in a plurality of spaces partitioned by the at least one partition wall. | 2013-01-03 |
| 20130002391 | MULTILAYERED POWER INDUCTOR AND METHOD FOR PREPARING THE SAME - Disclosed herein are a multilayered power inductor including a magnetic layer having a structure in which a metal magnetic powder is distributed on a glass substrate, a composition for the magnetic layer, and a method for preparing a multilayered power inductor. According to an exemplary embodiment of the present invention, the multilayered power inductor including a magnetic layer obtained by mixing the metal magnetic powder having high Ms with the glass substrate has excellent bias characteristics having small variations in capacity even when high current is applied. In addition, the exemplary embodiment of the present invention can use Cu as an inner electrode, instead of an expensive precious metal Ag. | 2013-01-03 |
| 20130002392 | MAGNETIC CORE - A method of manufacturing a magnetic core includes joining first and second core stacks having a plurality of layers of magnetic core material arranged in a laminated structure so as to substantially align the magnetic core layers of the first core stack with those of the second core stack, and inserting a magnetic filler into gaps between the substantially aligned magnetic core layers so as to bridge the gaps between the substantially aligned magnetic core layers. | 2013-01-03 |
| 20130002393 | FUSE LINK STATUS INDICATOR FOR A LOW-VOLTAGE HIGH-POWER FUSE - Fuse link status indicator for a low-voltage high-power fuse, according to the invention, relates to the design of low-voltage high-power fuses, or, to be more specific, to the solution of its integral assembly which gives a visual indication of the state of the fuse link within the cartridge of the fuse, that is, reliably concluding whether the fuse link is blown or not. The substance of the invention contains the fact that the force F | 2013-01-03 |
| 20130002394 | BOLOMETER AND METHOD OF MANUFACTURING THE SAME - A polymer film | 2013-01-03 |
| 20130002395 | PTC Resistor - The present invention is related to a polymer fibre-based PTC resistor comprising a co-continuous polymer phase blend, said blend comprising a first and a second continuous polymer phase, wherein the first polymer phase comprises a dispersion of carbon nanotubes at a concentration above the percolation threshold, said first polymer phase presenting a softening temperature lower than the softening temperature of the second polymer phase. | 2013-01-03 |
| 20130002396 | COMMUNICATION DEVICE, COMMUNICATION CIRCUIT, AND METHOD - A communication device includes a controller configured to determine whether a plurality of communication lines coupled to the communication device are available, assign logical communication line numbers to communication lines selected from the communication lines included in the transmission path, which are determined to be available in accordance with results of the determination in ascending order or descending order of the communication line numbers, and perform a process of establishing a link of the transmission path in accordance with the assigned logical communication line numbers. | 2013-01-03 |
| 20130002397 | METHOD AND APPARATUS FOR A MERGED POWER-COMMUNICATION CABLE IN DOOR SECURITY ENVIRONMENT - A method controlling access to a door using a merged power-communication cable. An access controlled door lock in door is operated using merged power-communication cable. Access control identification mechanism in door may operate using merged power-communication cable. The access controlled door lock may include a piezoelectric controlled door lock or a standalone door lock or a solenoid controlled door lock. A processing module may operate in door to control access with power interface receiving at least part of the electrical power from the merged power-communication cable. The invention includes a strike plate containing a magnetic sensor aligns by a latch hole to a latch included an access control door lock. The invention also includes using a door conduit to provide the merged power-communication cable to at least the processing module in the door. | 2013-01-03 |
| 20130002398 | Apparatus, System, and Method for Providing Attribute Identity Control Associated with a Processor - Described herein are an apparatus, system, and method for attribute identity control in a processor. The apparatus comprises a logic unit including a radio-frequency identification (RFID) tag comprising a non-volatile memory; and a processor operable to access the non-volatile memory, wherein the non-volatile memory for storing an attribute identity associated with a group of processors, the attribute identity being different from an identity of the processor. | 2013-01-03 |
| 20130002399 | ACCESS CONTROL DEVICE - From the prior art, access control devices are already known in which a distinction is made between a first detection device ( | 2013-01-03 |
| 20130002400 | ELECTRONIC TRANSACTION VERIFICATION SYSTEM - An electronic transaction verification system for use with transaction tokens such as checks, credit cards, debit cards, and smart cards that gathers and transmits information about the transaction token and biometric data is described herein. The electronic verification system includes a biometric data device for recording and/or transmitting biometric data taken at the transaction location. The electronic system is adapted to accept or deny a transaction based on the comparison result generated by comparing the biometric data and the information obtained from the transaction token at the transaction location with information previously stored in one or more databases. | 2013-01-03 |
| 20130002401 | ELECTRONIC TRANSACTION VERIFICATION SYSTEM - An electronic transaction verification system for use with transaction tokens such as checks, credit cards, debit cards, and smart cards that gathers and transmits information about the transaction token and biometric data is described herein. The electronic verification system includes a biometric data device for recording and/or transmitting biometric data taken at a first location. The electronic system is adapted to determine if a transaction should be accepted or rejected based on the comparison result generated by comparing the biometric data and the information obtained from the transaction token obtained at the first location with information previously stored in one or more databases and transmit the decision to a second location. | 2013-01-03 |
| 20130002402 | SIGNALING DEVICE - A system and method for locating an object, the system including a signaling device for mounting on an object, the signaling device including a signaling transceiver transmitting an identification signal, and a signal locator including a locator transceiver for receiving a signal directly from the signaling device, a direction sensor for sensing a direction towards which the signal locator is pointing, a locator controller determining, from the received signal and from the sensed direction, a direction from which the identification signal is received by the signal locator, and an indicator indicating that direction. Preferably, the signaling device further includes a signaling controller coupled to the signaling transceiver, which automatically switches the transmitter between a contact mode, to establish contact with the signal locator, and an operational mode, to permit determination by the signal locator of that direction, after contact has been established. | 2013-01-03 |
| 20130002403 | RFID SYSTEM WITH IMPROVED COVERAGE AND INCREASED READING DISTANCE - A radio frequency identification (RFID) system with a parasitic element to improve coverage and increase reading distance of RFID tags is disclosed. The parasitic element may be a loop of a conductive material and is not physically connected to any circuit. One or more RFID tags may be located within a predetermined distance of the parasitic element. The parasitic element receives a first signal from an RFID reader and re-radiates the first signal. The re-radiation improves the coverage of the RFID system. An RFID tag receives the re-radiated first signal from the parasitic element and, in response, transmits a second signal. The parasitic element receives the second signal from the RFID tag and re-radiates the second signal. The RFID reader receives the re-radiated second signal from the parasitic element and reads the information sent in the second signal by the RFID tag. | 2013-01-03 |
| 20130002404 | PRINTED WIRING BOARD AND WIRELESS COMMUNICATION SYSTEM - A printed wiring board includes a circuit substrate on which sheets are laminated, a wireless IC element provided on the sheet, a radiator provided on the sheet, and a loop-shaped electrode defined by first planar conductors, via hole conductors, and one side of the radiator, coupled to the wireless IC element. The first planar conductors are coupled to the radiator and the second planar conductors by auxiliary electrodes. | 2013-01-03 |
| 20130002405 | METHOD AND APPARATUS FOR SENSORY TAGS PROVIDING SOUND, SMELL AND HAPTIC FEEDBACK - Systems and methods for creating “feelings” from tangible objects in a responsive and cost efficient manner are provided. In accordance with such systems and methods, near field communication (NFC) tags are embedded into tangible objects, e.g., Compact Discs (CDs), books, posters, etc., where the NFC tags include feeling/sensory feedback parameters associated with the object in which the NFC tag is embedded. That is, such NFC tags are able to stimulate one or more senses, such as the human senses of sight, hearing, touch, smell, and taste. Thus, sensory feedback is provided via tangible objects, where only minimal cost (e.g., a few cents) is added to the production/manufacture of such objects. | 2013-01-03 |
