| 01st week of 2013 patent applcation highlights part 23 |
| Patent application number | Title | Published |
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| 20130002206 | CONNECTORS IN A PORTABLE DEVICE - Circuits, methods, and apparatus that allow a portable electronic device to be placed in a second electronic device in more than one orientation. One example allows a portable computing device to be placed in a docking station in both landscape and portrait orientations. In this example, this is achieved by including two connector receptacles, one on each of at least two sides of the portable computing device. | 2013-01-03 |
| 20130002207 | Method for Calculating an Electric Current Provided by a Rechargeable Energy Storage System and Related Methods, Apparatuses, and Systems - Some embodiments include a method for calculating an electric current provided by a rechargeable energy storage system. Other embodiments of related methods, apparatuses, and systems are disclosed. | 2013-01-03 |
| 20130002208 | ACCUMULATOR BATTERY MONITORING OVER POWER CIRCUIT - The invention is in the field of monitoring and controlling of rechargeable battery arrays as used in telecommunications power plants and vehicles equipped with all-electrical or hybrid-electrical power train. The invention presents a method of embedding a microcontroller into each individual cell in the array, which executes measurements of cell voltage, temperature and optionally instantaneous current. These measurements are aimed to reflect the cell state-of-charge and its overall maintenance state, i.e. health or life expectancy. The measured data is thence transmitted over the same wires that conduct the electrical energy to and from the battery cells using a Rogowsky type coil (a.k.a. current transformer) to superimpose a high-frequency alternating-current modulated signal over any direct current flowing through the power wires. A central digital signal processor with a similar current transformer connected to the power lines detects, demodulates and decodes the measurements data for the use of overall battery array control and maintenance. | 2013-01-03 |
| 20130002209 | METHOD AND APPARATUS FOR DISCHARGING AN ENERGY STORE IN A HIGH-VOLTAGE POWER SUPPLY SYSTEM - A method and to a device for discharging an energy store, in particular an intermediate circuit capacitor, in a high-voltage power supply system, in particular a DC voltage intermediate circuit in a motor vehicle, a first discharge resistor being connected parallel to the energy store, and a second discharge resistor automatically being connected parallel to the first discharge resistor when a voltage at the energy store falls below a specified threshold value. | 2013-01-03 |
| 20130002210 | Method for Controlling Vehicle Launch - A method for improving starting of an engine that may be repeatedly stopped and started is presented. In one embodiment, the method adjusts a transmission actuator in response to engine combustion during an engine start. The method may improve vehicle launch for stop/start vehicles. | 2013-01-03 |
| 20130002211 | CONTROLLER, WIND PARK AND CONTROL METHOD - Described is a controller, wherein the controller is adapted: to control a transformation ratio of a park transformer of a wind turbine park including wind turbines connected to a first node. The park transformer is connected between a first node and a second node which is connected to a utility grid to which electric energy produced by the wind turbines is to be delivered. Further a wind park and a control method are described. | 2013-01-03 |
| 20130002212 | DC-DC CONVERTER - A DC-DC converter, having an input voltage and an output voltage, includes an inductor and a switch switching the input voltage to an input side of the inductor, where a feedback path controlling initiation of closing the switch includes capacitive coupling of the voltage at the input side of the inductor. | 2013-01-03 |
| 20130002213 | VOLTAGE REGULATOR STRUCTURE - A regulator structure includes a first differential amplifier having a first input coupled to a reference voltage node. A second differential amplifier has a first input coupled to the output of the first differential amplifier. A third differential amplifier has a first input coupled to the output of the first differential amplifier. A first pmos transistor has its gate coupled to the second differential amplifier output, and its drain coupled to a second input of each of the first and second differential amplifiers. A second pmos transistor has its gate coupled to the third differential amplifier output, and its drain configured to output a regulated voltage which is also a second input of the third differential amplifier. A circuit is configured to replicate the regulated voltage and couple the replicated regulated voltage to the drain of the first pmos transistor. | 2013-01-03 |
| 20130002214 | CURRENT BALANCE CIRCUIT - A current balance circuit includes a first branch and a second branch in parallel between a power supply unit and at least one load, which respectively include a switch. The current balance circuit detects and compares currents flowing through the first branch and the second branch. The current balance circuit also generates triangle waves and reversed triangle waves, compares voltage of a control pole of a first switch with the triangle waves, and compares voltage of the control pole of a second switch with the reversed triangle waves. Then the current balance circuit controls if the triangle waves and the reversed triangle waves are input to the first switch and the second switch according to the currents flowing through the first branch and the second branch to adjust impedance of the first switch and the second switch to balance the currents flowing through the first branch and the second branch. | 2013-01-03 |
| 20130002215 | DC-DC POWER CONVERSION APPARATUS - Disclosed is a DC-DC power conversion apparatus ( | 2013-01-03 |
| 20130002216 | POWER SUPPLY MODULE,ELECTRONIC DEVICE INCLUDING THE SAME AND POWER SUPPLY METHOD - A power supply module and a power supply method corresponding to an electronic device. The power supply module includes a low-dropout (LDO) voltage regulator to adjust an input signal received from a battery and output a stabilized output signal, and an external load calculation circuit to calculate an external load value at a power output node of the LDO voltage regulator and stabilize the output signal based on the external load value. | 2013-01-03 |
| 20130002217 | LEVEL DETECTOR, INTERNAL VOLTAGE GENERATOR INCLUDING LEVEL DETECTOR, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING INTERNAL VOLTAGE GENERATOR - A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage. | 2013-01-03 |
| 20130002218 | Low Noise Voltage Regulator - A low noise voltage regulator generally includes an output switching stage and an amplifier, both of which contribute current to produce an output voltage at a substantially constant level. The amplifier produces a current that is based on a difference between a reference voltage and a feedback of the output voltage. The current from the amplifier (and optionally also from a current ramp generator) counterbalances the current from the output switching stage to maintain the output voltage at the substantially constant level. The output switching stage is controlled in response to a level of the counterbalancing current. | 2013-01-03 |
| 20130002219 | Current Sink with Low Side Voltage Regulation - An integrated circuit contains a current sink that is used to control a channel of varying forward voltage, with a goal of maintaining a minimally sufficient voltage across the current sink. A target voltage for the current sink return is determined, and a switched inductor is used to maintain said voltage. Various target determination schemes are possible, and various enhancements improve startup time, efficiency, and effectiveness. | 2013-01-03 |
| 20130002220 | SEMICONDUCTOR INTEGRATED CIRCUIT FOR REGULATOR - Disclosed is a semiconductor integrated circuit for regulator including: a control transistor; a voltage divider circuit generating a feedback voltage proportional to an output voltage; a control circuit controlling the control transistor based on difference between the feedback voltage and a reference voltage; and a terminal through which an output voltage switching control signal is received, and being configured to switch the output voltage into a first voltage or into a second voltage lower than the first voltage, by varying division ratio in the voltage divider circuit in response to the signal. The semiconductor integrated circuit further includes: a discharging transistor between the output terminal and the ground; and a circuit outputting a signal for keeping the discharging transistor turned on over a period from change of the signal to fall of the output voltage from the first voltage down to the second voltage. | 2013-01-03 |
| 20130002221 | PSEUDO CONSTANT ON TIME CONTROL CIRCUIT AND STEP-DOWN REGULATOR - A step-down regulator comprising a pseudo constant on time control circuit is disclosed, comprising an on-time generator configured to receive a switching signal provided by the step-down regulator and a control signal provided by the pseudo constant on time control circuit, and generates an on-time signal; a feedback control circuit configured to receive a feedback signal representative of the output voltage of the step-down regulator and generate an output signal; and a logic control circuit coupled to the on-time generator and the feedback control circuit to receive the on-time signal and the output signal and generating the control signal, and a power stage configured to receive an input voltage and the control signal and generate the switching signal. | 2013-01-03 |
| 20130002222 | POWER SUPPLY CONTROLLER HAVING ANALOG TO DIGITAL CONVERTER - A power supply control method of performing a feedback control of an output voltage based on a deviation signal for a standard voltage value serving as a target value for the output voltage and a digital signal generated by analog/digital (A/D) conversion of the output voltage, the method includes selecting a range of the reference voltage for the A/D conversion based on the digital signal in a power supply startup period, and selecting a range of the reference voltage for the A/D conversion based on the deviation signal or a signal corresponding to the deviation signal in a steady state period. | 2013-01-03 |
| 20130002223 | CONSTANT ON-TIME CONVERTER AND CONTROL METHOD THEREOF - A constant ON-time converter is disclosed. The constant ON-time converter comprises a feedback circuit, a slope compensation circuit and a buffer circuit. The feedback signal comprises an output configured to provide a feedback signal indicating an output voltage of the constant ON-time converter. The slope compensation circuit comprises an output configured to provide a slope compensation signal. The buffer circuit is coupled between the output of the feedback circuit and the output of the slope compensation circuit to avoid the feedback signal and the output voltage of the constant ON-time converter is influenced by the slope compensation signal. | 2013-01-03 |
| 20130002224 | HIGH EFFICIENCY BOOST CONVERTER - A boost converter circuit receives an input power supply voltage and produces an output boosted supply voltage. The circuit includes a voltage regulator, boosting circuitry, and a timing controller. The voltage regulator provides a regulated voltage to the boosting circuitry, which controls switching a transistor to drive the output boosted supply voltage; and the timing controller controls switching the boost circuit from the start-up mode to the normal operation mode. In start-up mode, the regulated voltage is generated from the input power supply voltage. During normal operation mode, the regulated voltage is generated from the output boosted supply voltage. The circuitry performs a low-power start-up when the input power supply voltage is low, and maintains efficient low-power operation by driving the transistor to produce the output boosted supply voltage as the input power supply voltage decreases. | 2013-01-03 |
| 20130002225 | Current-Mode Active Termination - Embodiments of the present invention, as further described below, provide active termination circuits that can be used with power transmitter circuits. Embodiments reduce power loss due to impedance matching and increase power efficiency in power transmitter circuits. In particular, embodiments provide active termination circuits that can be configured to draw minimal amounts of the output current generated by the power transmitter circuits. At the same time, embodiments achieve optimal impedance matching, thus enabling optimal power transfer to the load. Further, embodiments can be controlled adaptively in real time to reduce parasitic effects on power transfer and to optimize impedance matching. Embodiments can be implemented using various transistor technologies (e.g., MOSFET, BJT, etc.), and can be used with a variety of power transmitter circuits, including, for example, power DACs, analog/digital RF transmitters, and analog/digital PAs. | 2013-01-03 |
| 20130002226 | Switching regulator and control circuit thereof and input voltage detection method therefor - The present invention discloses a switching regulator including: a power stage having an upper gate device and a lower gate device coupled with each other, for converting an input voltage to an output voltage and generating a phase voltage at a node between the upper gate device and the lower gate device; and a control circuit including: a switch operation circuit controlling the power stage, the switch operation circuit generating a test signal turning on the upper gate device for a period of time and then turning it off; and a comparator for generating a ready signal indicating that the input voltage is ready according to comparison between the phase voltage and a reference voltage after the upper gate device is turned off. | 2013-01-03 |
| 20130002227 | POWER CONVERTER - A power converter has one set of two semiconductor switches performing switching actions, each of which is formed of an FET and a free wheel diode connected in anti-parallel to the FET, and a smoothing capacitor, and convers power by complementary switching actions of the FETs in the semiconductor switches. The power converter is provided with a current sensor that detects a direction of a current flowing through the semiconductor switches and a gate generation portion that skips ON signals of PWM gate signals of the semiconductor switches when the direction of the current flowing through the semiconductor switches is negative. | 2013-01-03 |
| 20130002228 | CURRENT SOURCE WITH LOW POWER CONSUMPTION AND REDUCED ON-CHIP AREA OCCUPANCY - A current source with low power consumption and reduced on-chip area occupancy. The current source for providing a constant current to a load includes a first circuit that generates a reference current. The first circuit includes a first plurality of interconnected transistors. The current source also includes a characteristic resistor, coupled to the first circuit, that determines value of the reference current. The current source further includes a second circuit and a third circuit. The second circuit, coupled to the first circuit and to the load, generates an output current that is identical to the reference current. The second circuit includes a second plurality of interconnected transistors. The third circuit, coupled to the first circuit, drives a multiple of the reference current into the characteristic resistor. The third circuit includes a third plurality of interconnected transistors. | 2013-01-03 |
| 20130002229 | METHOD FOR OPTIMIZING PARAMETER SETTINGS OF ENERGY SUPPLY PARAMETERS OF A FIELD DEVICE POWER SUPPLY MODULE - A method for optimizing the parameter setting of at least one energy supply parameter of a field device power supply module. The field device power supply module is, in such case, connected exclusively to one field device. The connected field device is supplied with electrical energy by the field device power supply module. In the method, the system composed of field device and field device power supply module is operated and a parameter setting of at least one energy supply parameter varied. In such case, the operation of the field device is monitored. Parameter settings are ascertained, in the case of which a relatively low energy consumption of the field device and simultaneously a safe operation of the field device can be realized in the relevant operational phase. | 2013-01-03 |
| 20130002230 | AC LOAD SOFT START FOR VARIABLE-FREQUENCY POWER SOURCE - Systems and methods for providing variable-frequency soft start of an AC load are disclosed. In one exemplary embodiment, a method for starting an alternating current (AC) load with a variable-frequency AC power output includes receiving an indication of a duty cycle for chopping the AC power output during starting of the AC load, and determining a frequency of the AC power output. The method further includes chopping the AC power output at the duty cycle, based on the determined frequency of the AC power output, and providing the chopped AC power output to start the AC load. | 2013-01-03 |
| 20130002231 | ELECTROPHORETIC BREAKING RATE METER FOR ASPHALT EMULSIONS - Described herein is a device that can be used to measure the breaking rate and total breaking energy of an emulsion. Also described is a method of determining the breaking rate of an emulsion. | 2013-01-03 |
| 20130002232 | FRAME SEQUENCE FOR A CELL VOLTAGE MEASUREMENT SYSTEM WITH A LOW PROBABILITY OF NATURAL OCCURRENCE - A method for providing calibration and synchronization pulses in a pulse width modulation (PWM) signal including cell voltage measurement pulses, where the calibration pulses are four calibration pulses having a pattern of a narrow width high voltage pulse followed by a wide width low voltage pulse followed by a narrow width high voltage pulse followed by a wide width low voltage pulse that has a very low probability of occurring in a practical fuel cell system. The method modulates a combined sequence of the voltage measurement signals and the calibration pulses using an inverted saw tooth wave to provide the PWM signal, where a width of the pulses representing the voltage signals are proportional to a width of the pulses representing the calibration pulses. | 2013-01-03 |
| 20130002233 | CIRCUITS FOR DETECTING AC- OR DC-COUPLED LOADS - An integrated circuit includes an output terminal and a controller having a measurement input coupled to the output terminal, a first output adapted to couple to a current source to control a first current sourced into the output terminal, and a second output adapted to couple to a current sink to control a second current from the output terminal. The controller applies control signals to the first output and the second output to selectively enable the current source and disable the current sink during a first phase of a load detection period and to disable the current source and enable the current sink during a second phase of the load detection period. The controller detects the load coupled to the output terminal if a voltage at the measurement terminal during the first phase is substantially equal to a voltage at the measurement terminal during the second phase. | 2013-01-03 |
| 20130002234 | High precision algorithmically assisted voltage divider with fault detection - A method, an algorithm, and circuits for implementation of a high-accuracy voltage divider are described that include a capability of fault detection. The disclosure allows for correction of non-catastrophic faults, such as significant changes of the components' values. The performance of the circuit built as described is vastly superior to operations achievable with the modern-day components utilized in previous standard and known configurations. | 2013-01-03 |
| 20130002235 | TEST BOX FOR ELECTROSTATIC GENERATORS - A test box for electrostatic generators includes a housing and an electrostatic target. The housing is structured to define a shielded space for receiving a measuring device and is further structured to prevent outside electromagnetic radiation from entering the shielded space. The electrostatic target is mounted on an outside surface of the housing and electrically connected to the measuring device. Electrostatic signals emitted from the electrostatic generators are received and transmitted to the measuring device by the electrostatic target, thereby displaying waveforms of the electrostatic signals using the measuring device. | 2013-01-03 |
| 20130002236 | DEVICE FOR MEASURING THE ELECTRIC CURRENT FLOWING IN AN ELECTRIC APPARATUS, SAID DEVICE ENABLING POWER MEASUREMENT, AND AN ELECTRIC APPARATUS COMPRISING SAME - A device for measuring an electric quantity such as electric current flowing in an electric equipment unit, which device is in a case fitted on a mounting support, and having pass-through holes and terminals separated by insulating material, their number corresponding to the number of phases of the equipment unit, the holesto permit a conductor to pass therethrough, to be electrically connected to strips of terminals of the equipment unit the opposite end to electric contact strips of a load-side or line-side apparatus from the equipment unit and, for at least one terminal of the device, a magnetic core at least partially surrounding such terminal with an air-gap around which a secondary measuring coil is wound between two end portions of the magnetic core which define the air-gap, the coil(s) delivering a signal representative of the current flowing in the apparatus. | 2013-01-03 |
| 20130002237 | Mechanism for Monitoring Print System Energy Usage - A printer is disclosed. The printer includes one or more sub-components each having a meter to track energy usage at the sub-component during an event and a controller to receive energy usage data accrued at one or more of the meters during the event. | 2013-01-03 |
| 20130002238 | HIGH-FREQUENCY (HF) TEST PROD - A high frequency test prod for electrically contacting at least one contact point of a specimen, using an HF coaxial line to connect the test prod housing and the contact unit electrically and mechanically between the housing and the contact unit, the HF coaxial line having an external conductor, an internal conductor arranged coaxially to the external conductor, and a gas or vacuum dielectric arranged between the external conductor and internal conductor, the external conductor designed as a hollow profile section from a rigid, elastically deformable material, wherein the internal conductor is arranged coaxially to the hollow profile section. | 2013-01-03 |
| 20130002239 | High Voltage Sensing Mechanism with Integrated On-Off Switch - The present invention is an efficient high voltage sensing mechanism that operates only when an individual needs to test the voltage across a wire. The present invention attaches around a tested wire using a jaw and a hook. The hook is tensioned using an expansion spring. The operator propels the hook outwards from the jaw, around the tested wire; thereafter, the expansion spring retracts to latch onto the tested wire against the jaw. An on-off switch is integrated into the mechanical hook device. As the hook is propelled outwards, the on-off switch moves into the “on” position, which powers the electrical processing and voltage analysis equipment. Once the hook is returned to the initial position, the on-off switch moves to the “off” position. This arrangement allows the present invention to remain unpowered for any instance a wire is not being tested. The present invention detects voltage through capacitive coupling. | 2013-01-03 |
| 20130002240 | METHOD FOR DETERMINING COERCIVITY OF COERCIVITY DISTRIBUTION MAGNET - According to the present invention, a method for determining coercivity of a coercivity distribution magnet, whereby coercivity of each portion in the coercivity distribution magnet can be determined with good accuracy without, for example, cutting the coercivity distribution magnet into pieces and thus quality assurance can be achieved with good accuracy, is provided. | 2013-01-03 |
| 20130002241 | ENERGY SELF-SUFFICIENT APPARATUS AND METHOD FOR POSITION DETECTION - Energy self-sufficient apparatus with an energy converter, which comprises at least one permanent magnetic element, a second permanent magnetic element and a coil, wherein at least one of the permanent magnetic elements is arranged such that its magnetic field penetrates a coil and the second permanent magnetic element is arranged movable such that the magnetic field penetrating the coil can be changed by means of the movement. | 2013-01-03 |
| 20130002242 | BINARIZATION CIRCUIT FOR BINARIZING DETECTION SIGNAL REPRESENTING ROTATION OR MOVEMENT OF OBJECT - A differential amplifier generates an offset correction signal based on a rotation detection signal from a rotation detector apparatus and an offset signal. A comparator compares the offset correction signal with a threshold voltage, and outputs a binarized signal representing the comparison result. An average value signal generator circuit generates an average value signal representing the average value of the offset correction signal. The offset signal generator circuit generates the offset signal so that the signal voltage of the average value signal has a voltage value between a threshold voltage and a threshold voltage. | 2013-01-03 |
| 20130002243 | SYSTEM FOR USE WITH AN IMPLANTABLE MEDICAL DEVICE - A system for use with an implantable flow control device having an adjustable valve and a magnetic device coupled to the valve, the system including a locator tool and an electronic magnetic-based indicator tool. The locator tool includes a processing system and an electronic display. The indicator tool is configured to couple with the locator tool. The indicator tool includes an electronic compass module configured to detect and generate a first set of data based on an orientation of magnetic fields associated with the magnetic device as an indication of the setting of the valve and measure and generate a second set of data based on ambient background magnetic fields. The indicator tool electrically communicates the data to the locator tool. The processing system receives and uses the first and second sets of data generated from the electronic compass module to determine orientation of the magnetic device. | 2013-01-03 |
| 20130002244 | MEMS-BASED MAGNETIC SENSOR WITH A LORENTZ FORCE ACTUATOR USED AS FORCE FEEDBACK - A magnetic sensor utilizes a MEMS device that has at least one vibrating member and at least one conductive path integral with the vibrating member so that a current flows along the vibrating member and in the presence of a magnetic field interaction of the magnetic field and the point charges in the current on the conductive path due to the Lorentz force causes a change in vibration of the vibrating member. That change can be used to provide a measure of the magnetic field. | 2013-01-03 |
| 20130002245 | HIGH RESOLUTION AND HIGH PRECISION VECTOR MAGNETOMETER - The present invention relates to a vector magnetometer for measuring the components of an ambient magnetic field. This vector magnetometer comprises an optically pumped scalar magnetometer ( | 2013-01-03 |
| 20130002246 | MODIFIED PULSE SEQUENCE TO ESTIMATE PROPERTIES - Methods and related systems are described for estimating fluid or rock properties from NMR measurements. A modified pulse sequence is provided that can directly provide moments of relaxation-time or diffusion distributions. This pulse sequence can be adapted to the desired moment of relaxation-time or diffusion coefficient. The data from this pulse sequence provides direct estimates of fluid properties such as average chain length and viscosity of a hydrocarbon. In comparison to the uniformly-spaced pulse sequence, these pulse sequences are faster and have a lower error bar in computing the fluid properties. | 2013-01-03 |
| 20130002247 | CATALYTIC MULTIECHO PHASE UNWRAPPING SCHEME - A method of nuclear magnetic resonance imaging of an object is disclosed, the method including: receiving MR data including magnitude and phase information generated using an MR scan having a series of different echo times; generating one or more measured MR images based on the MR data; and processing the measured MR images to generate unaliased or substantially unaliased phase information for at least one pixel in the image. | 2013-01-03 |
| 20130002248 | METHOD FOR DETERMINING AND ORDERING K-SPACE VIEWS AND DIFFUSION WEIGHTING DIRECTIONS - A system and method for determining and ordering magnetic resonance imaging (MRI) acquisition parameters, such as k-space views or diffusion-weighting gradient directions, are provided. The MRI acquisition parameters are defined by generated points that are uniformly distributed on the surface of a sphere. These points may also be antipodally symmetric. The points are ordered by minimizing the electrostatic potential energy of different configurations of the points. | 2013-01-03 |
| 20130002249 | Method for Reducing Local Specific Absorption Rate In Magnetic Resonance Imaging Using Radio Frequency Coil Array Dark Modes - A method for reducing local specific absorption rate (“SAR”) during imaging of a subject with a magnetic resonance imaging (“MRI”) system is provided. A radio frequency (“RF”) excitation pattern is selected for an RF coil array to be used during the imaging. In this RF excitation pattern, locations in which local SAR exceeds a preselected threshold value are identified. Examples of threshold values include regulatory limits on local SAR. Using the identified local SAR hotspot locations, a cancellation electric field pattern that is defined by so-called “dark modes” of the coil array is determined. Imaging of the subject commences using the RF coil array and the MRI system, in which the RF coil array is used to simultaneously produce an RF excitation field and a cancellation electric field using the respective field patterns. This simultaneous production of the RF excitation and cancellation electric fields reduces local SAR at the hotspot locations. | 2013-01-03 |
| 20130002250 | QUANTITATIVE NMR CLINICAL ANALYZERS WITH AUTOMATIC NMR TEMPERATURE SENSITIVITY COMPENSATION THAT ACCOMMODATE LARGE AMBIENT OPERATIONAL TEMPERATURE RANGES - NMR analyzers and associated methods, circuits and computer program products that allow NMR operation in fluctuating ambient temperature environments of at least +/−5 degrees F. in a relatively large operating temperature range, typically between about 60-85 degrees F.) with the ability to still generate accurate quantitative measurements using an electronically applied temperature sensitivity adjustment based on an a priori model of temperature sensitivity and a detected temperature proximate the NMR signal acquisition (e.g., scan). The clinical NMR analyzers can be remotely accessed to evaluate linearity and temperature compensation adjustments. | 2013-01-03 |
| 20130002251 | NUCLEAR MAGNETIC RESONANCE PROBE COMPRISING SLIT SUPERCONDUCTING COIL WITH NORMAL-METAL OVERLAYER - A nuclear magnetic resonance (NMR) probe comprises a superconducting material formed in a spiral having a plurality of fingerlets separated by a plurality of slits, and a normal-metal overlayer formed on the spiral over the plurality of fingerlets and the plurality of slits. | 2013-01-03 |
| 20130002252 | SYSTEM AND APPARATUS FOR BALANCING RADIAL FORCES IN A GRADIENT COIL - A gradient coil apparatus for a magnetic resonance imaging (MRI) system includes an inner gradient coil assembly and an outer gradient coil assembly disposed around the inner gradient coil assembly. The outer gradient coil assembly has an outer surface, a first end and a second end. The gradient coil apparatus also includes a force balancing apparatus disposed around the outer surface of the outer gradient coil assembly. In one embodiment, the force balancing apparatus includes an active force balancing coil disposed around the outer surface of the outer gradient coil assembly. In another embodiment, the force balancing apparatus includes a first passive conducting strip disposed around the first end of the outer gradient coil assembly and a second passive conducting strip disposed around the second end of the outer gradient coil assembly. | 2013-01-03 |
| 20130002253 | ISOTROPIC METAMATERIAL LENS FOR MAGNETIC IMAGING APPLICATIONS - Examples of the present invention include metamaterial lenses that allow enhanced resolution imaging, for example in MRI apparatus. An example metamaterial may be configured to have μ=−1 along three orthogonal axes. Superior performance was demonstrated using such improved designs, and in some examples, imaging resolution better than λ/500 was obtained. The use of one or more lumped reactive elements in a unit cell, such as one or more lumped capacitors and/or one or more lumped inductors, allowed unit cell dimensions and hence resolution to be dramatically enhanced. In some examples, a cubic unit cell was used with an essentially isotropic magnetic permeability of μ=−1 obtained at an operating electromagnetic frequency and wavelength (λ). | 2013-01-03 |
| 20130002254 | METHOD FOR CREATING A MODULE FOR CONTROLLING A HIGH-FREQUENCY ANTENNA FOR A NUCLEAR MAGNETIC RESONANCE IMAGING APPARATUS - A method for creating a module for controlling a magnetic resonance imaging apparatus antenna, the method including: determining magnetic field distribution mapping B | 2013-01-03 |
| 20130002255 | INDICATING SYSTEM FOR A DOWNHOLE APPARATUS AND A METHOD FOR LOCATING A DOWNHOLE APPARATUS - A system for locating a downhole apparatus comprises a wellbore having an interior pressure cavity, wherein the apparatus is disposed in the pressure cavity, a magnetic device for generating a magnetic field in the pressure cavity, and a magnetic field indicator disposed external to the pressure cavity, the magnetic field indicator responsive to the magnetic field in the pressure cavity, wherein the magnetic field is indicative of a position of the apparatus in the pressure cavity. | 2013-01-03 |
| 20130002256 | ELECTROMAGNETIC PROXIMITY DETECTION METHOD AND UNIT - Electromagnetic proximity detection method for a buried structure executed with a mobile detection device, including sensing an electromagnetic field emitted from the structure as an analog electrical signal and digitalizing the analog electrical signal as a digital signal, performed after or while filtering the analog and/or digital signal. The proximity of the buried structure is determined by analyzing the digital signal, wherein the detection method can be alternatively executed in at least two of the following modes of detection: Power-Mode of detection, Radio-Mode of detection or Active-Mode of detection. An additional Switching-Mode of operation includes a repeated sequential detection in at least two of the mentioned modes of detection and is done by automatic subsequent alternating of the mode of detection with a minimum rate of alternation that an area of detection is coverable by the at least two modes of detection in a single execution of the detection method. | 2013-01-03 |
| 20130002257 | Method For Improving Wellbore Survey Accuracy And Placement - Methods for improving wellbore survey accuracy and placement are disclosed. The Earth's magnetic field may be measured at a magnetically clean surface location and correlated with a non-magnetic reference direction to obtain a direction of the Earth's field (e.g., a magnetic declination or a magnetic inclination). The direction of the Earth's magnetic field may in turn be processed in combination with magnetic measurements made in a subterranean borehole to obtain one or more survey parameters. | 2013-01-03 |
| 20130002258 | DEVICE FOR DIELECTRIC PERMITTIVITY AND RESISTIVITY HIGH TEMPERATURE MEASUREMENT OF ROCK SAMPLES - Systems and methods are described for determining dielectric permittivity for core plugs extracted from the field or cores re-saturated with various fluids. The relative dielectric constant of reservoir core plugs is measured in controlled condition of temperature, pressure and fluid saturation within a confined cell. Four-points resistivity measurements of the rock sample in the confined cell is also provided under the controlled temperature, pressure and fluid saturation conditions. | 2013-01-03 |
| 20130002259 | BATTERY VOLTAGE MEASUREMENT SYSTEM AND METHOD THEREOF - A battery voltage measurement system is disclosed. The system includes a measurement unit, a calibration unit, and a control unit. The calibration unit is coupled between the measurement unit and a battery, for providing several test voltages to the measurement unit. The control unit is coupled to the calibration unit and the measurement unit, for controlling the calibration unit and for receiving an output voltage of the measurement unit. Under a calibration mode, the calibration unit outputs test voltages to the measurement unit, and the control unit calculates a calibration value according to a relation between the test voltages and the output voltage of the measurement unit. Under a measurement mode, the calibration unit transmits a battery voltage to the measurement unit, and the control unit calibrates the output voltage of the measurement unit according to the calibration value for acquiring accurate value of the battery voltage. | 2013-01-03 |
| 20130002260 | MONITORING SYSTEM FOR AN ENERGY STORAGE CELL - A monitoring system for monitoring the state of an energy storage cell for storing electrical energy, in particular, an electrochemical energy storage cell or an energy storage cell having at least one capacitor. Integrated electronics for monitoring the state of the energy storage cell are arranged in the energy storage cell, the integrated electronics having a transmitting/receiving unit for wireless data exchange with a battery control system arranged outside the energy storage cell. Alternatively, the integrated electronics are connected to a transmitting/receiving unit for wireless data exchange with a battery control system arranged outside the energy storage cell. | 2013-01-03 |
| 20130002261 | BATTERY PACK - The battery pack is provided with an analog front-end that detects battery voltage, and a micro-controller connected to the analog front-end that accepts analog voltage signals from the analog front-end as input. The micro-controller switches voltage signals input from the analog front-end to determine failure of the analog front-end or the micro-controller. | 2013-01-03 |
| 20130002262 | VEHICLE-MOUNTED SYSTEM AND INSULATION FAILURE DIAGNOSIS UNIT - A vehicle-mounted system has a high-voltage supply system having a high-voltage battery and a plurality of vehicle-mounted loads electrically connected to the battery. The high-voltage supply system includes a plurality of load portions, each load portion including one or more electric devices which consume or generate electric power. The vehicle-mounted system has a plurality of diagnosis means for detecting an insulation failure. The diagnosis means has an output portion which is connected to the corresponding load portion, and outputs a diagnosis signal. The diagnosis mean has a detector detects a state signal of the system on the basis of the input of the diagnosis signal, and a diagnosis portion which determines whether or not there is an insulation failure. | 2013-01-03 |
| 20130002263 | RELIABILITY ASSESSMENT OF CAPACITOR DEVICE - A method of reliability testing of a semiconductor device is described. The embodiment, includes providing a capacitor including an insulating layer interposing two conductive layers. A plurality of voltages are provided to the capacitor including providing a first voltage and a second voltage greater than the first voltage. A leakage associated with the capacitor is measured while applying the second voltage. In an embodiment, the leakage measured while applying the second voltage indicates that a failure of the insulating layer of the capacitor has occurred. In an embodiment, the capacitor is an inter-digitated metal-oxide-metal (MOM) capacitor. The reliability testing may be correlated to TDDB test results. The reliability testing may be performed at a wafer-level. | 2013-01-03 |
| 20130002264 | ELECTRICAL IMPEDANCE TOMOGRAPHY DEVICE AND PROCESS - An EIT device has a plurality of electrodes ( | 2013-01-03 |
| 20130002265 | Methods and Devices for Determining Sensing Device Usability - Methods and devices for determining device usability, e.g., for point of care assay devices. In one embodiment, the invention is to a method of determining device usability in a sensing device, including the steps of: providing a device comprising a first electrical pad; a second electrical pad; and a first polymer layer contacting at least a portion of the first and the second electrical pads and a second polymer layer contacting the first polymer layer and not the first and second electrical pads; applying a potential across the first and the second electrical pads; measuring an electrical property associated with the first and the second polymer layers; and determining whether the measured electrical property associated with the first and the second polymer layers has exceeded a threshold level associated with the device usability. | 2013-01-03 |
| 20130002266 | HAND-HELD TEST METER WITH ELECTROMAGNETIC INTERFERENCE DETECTION CIRCUIT - A hand-held test meter for use with an analytical test strip in the determination of an analyte (such as glucose) in a bodily fluid sample (for example, a whole blood sample) includes a housing, a test meter control circuit block, and an electromagnetic interference detection circuit block with an antenna configured to sense electromagnetic fields of a predetermined frequency. The electromagnetic interference detection circuit block is configured to generate a signal representative of an electromagnetic field sensed by the antenna and to provide that signal to the test meter control circuit block. In addition, the test meter control circuit block is configured to interrupt operation of the hand-held test meter when the signal received from the electromagnetic interference detection circuit block is represents an electromagnetic field that interferes with the hand-held test meter's operation. | 2013-01-03 |
| 20130002267 | Impedance Mismatch Detection Circuit - A comparison circuit for detecting impedance mismatch between pull-up and pull-down devices in a circuit to be monitored includes a comparator operative to receive first and second signals and to generate, as an output, a third signal indicative of a difference between the first and second signals. A first signal generator is operative to generate the first signal indicative of a difference between reference pull-up and pull-down currents that is scaled by a prescribed amount. The reference pull-up current is indicative of a current flowing through at least one corresponding pull-up transistor device in the circuit to be monitored. The pull-down reference current is indicative of a current flowing through at least one corresponding pull-down transistor device in the circuit to be monitored. A second signal generator connected with the second input of the comparator is operative to generate the second signal as a reference voltage defining a prescribed impedance mismatch threshold associated with the circuit to be monitored. | 2013-01-03 |
| 20130002268 | DISTRIBUTED SENSORS TO MEASURE CEMENT STATE - A system for determining a curing state for cement disposed in a borehole penetrating the earth that includes a transceiver that includes a transmitting coil and that is configured to provide an input signal to the coil that sweeps through a frequency range and to measure the magnitude of the voltage across the coil. The system also includes a plurality of sensor nodes disposed in the concrete. The sensor nodes include a receiving coil and a capacitor coupled to the receiving coil to form a receiving circuit and that has a capacitance that changes as one of pressure or strain in the cement changes. | 2013-01-03 |
| 20130002269 | Capacitive Sensing - A multi-channel capacitive sensor comprises a sample capacitor having first and second terminals, a first diode having a first terminal coupled to the second terminal of the sample capacitor and a second terminal coupled to a first sense electrode, and a second diode having a first terminal coupled to the second terminal of the sample capacitor and a second terminal coupled to a second sense electrode. The sample capacitor and diodes are coupled to a control circuit. The control circuit is operable to apply a drive signal to the first terminal of the sample capacitor while simultaneously applying a bias signal to the second terminal of one or other of the diodes to prevent the diode from conducting the drive signal. | 2013-01-03 |
| 20130002270 | SYSTEMS FOR INSPECTION OF SHROUDS - A system to measure thickness of a shroud is provided. The system includes at least one resistive element embedded within the shroud. The system also includes an impedance measurement device that measures a total resistance associated with the at least one resistive element. | 2013-01-03 |
| 20130002271 | METHOD AND SYSTEM FOR CONTAMINATION SIGNATURE DETECTION DIAGNOSTICS OF A PARTICULATE MATTER SENSOR - A diagnostic method and system is described for diagnosing an operating condition of a conductive particulate matter sensor. The sensor has a substrate with electrical resistance that varies with temperature and two electrodes on the substrate adapted to collect particulate matter between the electrodes, thereby establishing an electrically conductive path through collected particulate matter between the electrodes that can be detected by measuring electrical resistance between the electrodes, R | 2013-01-03 |
| 20130002272 | FAULT MODE CIRCUITS - A test circuit and method for testing through-silicon-vias (TSVs) in three-dimensional integrated circuits (ICs) during each phase of manufacturing is disclosed. In one aspect, the method includes testing for faults in each individual TSV, TSV-under-test, shorts between a TSV-under-test, and TSVs in close proximity and for connections between the TSV-under-test and another tier in the ICs. A test circuit has three switchable current paths connected to a power supply via a pull-up resistor and switches: a calibration path, a short path, and a current measurement path. A power supply is connected to the measurement path, and the calibration path and the short path are connected to ground via respective pull-down resistors. For each TSV-under-test, the desired operation mode is selected by the closure of different combinations of switches. The current flowing through the pull-up resistor in each operation mode indicates whether the TSV-under-test has passed or failed the test. | 2013-01-03 |
| 20130002273 | SYSTEM AND METHOD FOR ELECTROSTATIC DISCHARGE TESTING OF DEVICES UNDER TEST - A system and method for electrostatic discharge (ESD) testing devices under test (DUTs) uses an ESD gun attached to a robotic arm to execute ESD tests. The system and method also uses cameras positioned around a DUT placed on a testing table to define at least one test point on a surface of the DUT. Using the defined test point, as well as settings on the ESD gun and a testing process scenario that includes actions to be executed by the system, the testing process is performed by the system. | 2013-01-03 |
| 20130002274 | AGING DEGRADATION DIAGNOSIS CIRCUIT AND AGING DEGRADATION DIAGNOSIS METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT - Provided is an aging degradation diagnosis circuit, including: a first delay circuit including a gate array for allowing aging degradation to progress, the first delay circuit being configured to delay an input signal and output a first output signal; a second delay circuit including a gate array having the same number of stages as the first delay circuit, the second delay circuit being configured to delay an input signal and output a second output signal; and an arbitrary delay unit, which is capable of varying a delay period in the second delay circuit by a predetermined amount. A delay comparison unit outputs comparison information obtained by relatively comparing delays between the first output signal and the second output signal. An adjustment unit uses the comparison information, to thereby readjust the delay period in the second delay circuit. | 2013-01-03 |
| 20130002275 | SYSTEM AND METHOD FOR MEASURING NEAR FIELD INFORMATION OF DEVICE UNDER TEST - A system and method for measuring near field information of a device under test (DUT) uses a reference probe and a measurement probe that are configured to sense a field. A probe calibration factor is used to determine corresponding field values for signals from the measurement probe at sampling locations about the DUT. The probe calibration factor is derived from measured signals about a conductive trace using a probe and simulated field information for the conductive trace when subjected to a simulated reference signal. | 2013-01-03 |
| 20130002276 | SEMICONDUCTOR APPARATUS AND TESTING METHOD THEREOF - A semiconductor apparatus includes a through via and a comparison unit. The through via is electrically connected with another chip. The comparison unit includes a reference capacitor, and compares a capacitance value of the through via and a capacitance value of the reference capacitor in response to a test start signal and a reset signal and generates a comparison result. | 2013-01-03 |
| 20130002277 | SEMICONDUCTOR MODULE, TEST SYSTEM AND METHOD EMPLOYING THE SAME - A semiconductor module includes a plurality of module pins and a semiconductor device. Module pins receive an identification pattern signal having M bits and outputs a test identification pattern, where M is a positive integer. The semiconductor device includes device pins, and outputs the identification pattern signal through the device pins in response to a connection identification control signal for identifying a configuration of pin connections between the module pins and the device pins. The semiconductor module effectively identifies a configuration of pin connections between the module pins and the device pins. | 2013-01-03 |
| 20130002278 | Methods and Devices for Determining Sensing Device Usability - Methods and devices for determining sensing device usability, e.g., for self-monitoring and point of care devices. In one embodiment, the invention is to a method of determining device usability, comprising the steps of providing a device comprising a first electrical pad; a second electrical pad; and a humidity-responsive polymer layer contacting at least a portion of the first and second electrical pads; applying a potential across the first and second electrical pads; measuring an electrical property associated with the humidity-responsive polymer layer; and determining whether the measured electrical property associated with the humidity-responsive polymer layer has exceeded a humidity threshold level associated with the device usability. | 2013-01-03 |
| 20130002279 | Methods and Devices for Determining Sensing Device Usability - Methods and devices for determining sensing device usability, e.g., for point of care immunoassay devices. In one embodiment, the invention is to a method of determining device usability, comprising the steps of providing a device comprising a first electrical pad; a second electrical pad; and a continuous polymer layer contacting at least a portion of the first and second electrical pads; applying a potential across the first and second electrical pads; measuring an electrical property associated with the continuous polymer layer; and determining whether the measured electrical property associated with the continuous polymer layer has exceeded a threshold level associated with the device usability. | 2013-01-03 |
| 20130002280 | TEST PROBE ALIGNMENT STRUCTURES FOR RADIO-FREQUENCY TEST SYSTEMS - Electronic devices may be tested using a test station with a test fixture. The test fixture may include a first holding structure in which a device under test may be placed and a second holding structure for supporting test probes. The second holding structure may be mated with a test probe alignment structure during test station setup operations. The test probe alignment structure may include registration features configured to set the relative position of the first and second holding structures to a known configuration and may include test probe alignment features that can be used to correctly position the placement of the test probes. If at least one of the test probes is not sufficiently aligned to its corresponding alignment feature, the test probe alignment structures will not be able to engage properly with the second holding structure, and the position of the problematic test probe may be adjusted accordingly. | 2013-01-03 |
| 20130002281 | CONTACT PROBE AND PROBE UNIT - A contact probe having a substantially flat plate shape, used to connect different substrates and having a uniform plate thickness includes: a first contact portion which has a side surface curved in an arc shape and which makes contact with one substrate at the side surface thereof; a second contact portion which has a side surface curved in an arc shape and which makes contact with the other substrate at the side surface thereof; a connection portion which connects the first contact portion and the second contact portion; and an elastic portion which extends from the second contact portion, has a portion curved in an arc shape, and is elastically deformed by a load applied to the first contact portion and the second contact portion. | 2013-01-03 |
| 20130002282 | Test Structures and Testing Methods for Semiconductor Devices - Test structures, methods of manufacturing thereof, and testing methods for semiconductors are disclosed. In one embodiment, a test structure for semiconductor devices includes a printed circuit board (PCB), a probe region, and a compliance mechanism disposed between the PCB and the probe region. A plurality of wires is coupled between the PCB and the probe region. End portions of the plurality of wires proximate the probe region are an integral part of the probe region. | 2013-01-03 |
| 20130002283 | Defect Detection by Thermal Frequency Imaging - A method can be used for detecting defects in an electronic integrated circuit that includes a power input and a data input. The electronic integrated circuit is powered with a periodic power signal having a frequency and an input signal is applied to the data input. A surface of the electronic integrated circuit is swept with a laser beam. A first image is generated using a laser beam reflected from the surface and a second image is generated using a selected part of the laser beam reflected from the surface. The selected part of the reflected laser beam has a frequency that corresponds to the frequency of the power signal. Defects in the integrated circuit can be detected by superposing the first image and the second image. | 2013-01-03 |
| 20130002284 | TEST PROBE WITH INTEGRATED TEST TRANSFORMER - A measuring device used for registering a test signal originating from a circuit structure applied to a wafer. The measuring device provides at least one test probe and at least one test transformer. The at least one test transformer is connected to the at least one test probe in an electrically conductive manner. In this context, the test transformer is arranged on the test probe. | 2013-01-03 |
| 20130002285 | Electrically Conductive Pins For Microcircuit Tester - The terminals of a device under test (DUT) are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane with a top facing the device under test, a bottom facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The bottom pins has a lower contact surface which includes an arcuate portion or ridge which increases contact pressure and ablates oxides by the rocking action of ridge when the DUT in inserted. | 2013-01-03 |
| 20130002286 | TEST APPARATUS AND PALLET FOR PARALLEL RF TESTING OF PRINTED CIRCUIT BOARDS - A test apparatus features an upper RF impermeable hood and lower RF impermeable hood, wherein each of the hoods have internal dividers. When in a closed position, the hoods and dividers create two or more RF impermeable chambers. The hoods are configured to enclose or sandwich a pallet supporting two or more printed circuit boards. One of the printed circuit boards is disposed in each chamber formed by the hoods and dividers. | 2013-01-03 |
| 20130002287 | APPARATUS FOR IMPROVING RELIABILITY OF ELECTRONIC CIRCUITRY AND ASSOCIATED METHODS - In an exemplary embodiment, an apparatus includes a first set of circuit elements and a second set of circuit elements. The first set of circuit elements is used in a first configuration of the apparatus, and the second set of circuit elements is used in a second configuration of the apparatus. The first configuration of the apparatus is switched to the second configuration of the apparatus in order to improve reliability of the apparatus. | 2013-01-03 |
| 20130002288 | Electronic Circuit Arrangement for Processing Binary Input Values - Electronic circuit arrangement for processing binary input values xεX of a word width n (n>1), with a first, second and third combinatory circuit components configured to process the binary input values x to form first, second and third binary output values. The arrangement further includes a majority voter element configured to receive the binary output values and provide a majority signal based on the received binary output values. The second and third combinatory circuit components are designed, as regards faults during processing of the binary input values x in the first combinatory circuit component, to process binary input values of a true non-empty partial quantity X | 2013-01-03 |
| 20130002289 | ELECTRONIC APPARATUS, CATEGORY DETERMINATION METHOD FOR TRANSMISSION CABLE AND TRANSMISSION CABLE - An electronic apparatus includes: a receptacle having a plurality of pins for connecting a plug of a transmission cable; and a transmission cable determination section adapted to apply a predetermined voltage to a predetermined one of the pins of the receptacle to determine a category of the transmission cable. | 2013-01-03 |
| 20130002290 | CONFIGURABLE MULTI-DIMENSIONAL DRIVER AND RECEIVER - Embodiments of the invention are generally directed to a configurable multi-mode driver and receiver. An embodiment of a communication system includes a communication channel, and a first device and a second device coupled with the communication channel. The first device includes a driver apparatus to drive data signals on the communication channel, the driver apparatus including circuits to receive and drive the data signals, where the circuits are configurable for termination resistance of the driver circuit apparatus, and each of the plurality of circuits is comprised of one or more circuit units, the circuit units being configurable for equalization control of the driver apparatus. The second device includes a receiver to receive data signals from the communication channel as an input. Either the first device or the second device includes configurable circuit elements to provide signal reflection control for the system. | 2013-01-03 |
| 20130002291 | SEMICONDUCTOR MEMORY DEVICE, MEMORY CONTROLLER AND MEMORY SYSTEM HAVING ON DIE TERMINATION AND ON DIE TERMINATION CONTROLLING METHOD - A semiconductor memory device includes a first memory chip including a first on die termination (ODT) unit electrically connected to a first pad, the first pad being connected to a first terminal to receive a first signal, and a second memory chip including a second ODT unit electrically connected to a second pad, the second pad being connected to the first terminal to receive the first signal, the first ODT unit being configured to turn on/off according to a memory operation, the second ODT unit being configured to turn off regardless of the memory operation, and the first and second ODT units are switchable. | 2013-01-03 |
| 20130002292 | RECONFIGURABLE INTEGRATED CIRCUIT DEVICE - A reconfigurable integrated circuit device includes plural processing elements each including an arithmetic circuit, and being configured in any computing state based on the configuration data; and an inter-processing element network which connects the processing elements in any state based on the configuration data. And the processing element inputs an input valid signal and an input data signal, and outputs an output valid signal and an output data signal, and includes an input data holding register, an arithmetic processing circuit, and an output data holding register which holds the computing result data, and when the configuration is updated by configuration data which makes a hold mode valid, regardless of the input valid signal, valid or invalid, the input data holding register holds the input data signal upon the update and the arithmetic processing circuit performs computing processing on the input data signal held in the input data holding register. | 2013-01-03 |
| 20130002293 | RECONFIGURABLE DYNAMIC LOGIC GATE WITH LINEAR CORE - A dynamically reconfigurable linear core logic gate is a device that allows logical outputs dependent upon configurable parameters set within device. The device is comprised of three blocks: The first block receives at least one input signal and determines whether the signal o signals are low or high in comparison with a threshold reference signal. The second block sums the logic signals of the first block with an offset signal. The third block determines if the sum realized in the second block is a low or high by checking whether the sum falls within a predetermined interval. | 2013-01-03 |
| 20130002294 | PROGRAMMABLE CIRCUIT - Provided is a programmable circuit. The programmable circuit includes a first path and a second path connected in parallel between a first voltage node and a second voltage node. The first path includes a first programmable element, a first node, a first pull-up transistor, a second node, and a first pull-down transistor connected in series between the first voltage node and the second voltage node. The second path includes a second programmable element, a third node, a second pull-up transistor, a fourth node, and a second pull-down transistor connected in series between the first and second voltage nodes. A gate electrode of the first pull-up transistor, a gate electrode of the first pull-down transistor, and the fourth node are electrically connected to one another. A gate electrode of the second pull-up transistor, a gate electrode of the second pull-down transistor, and the second node are electrically connected to one another. | 2013-01-03 |
| 20130002295 | APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE LOGIC AND ASSOCIATED METHODS - Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs. | 2013-01-03 |
| 20130002296 | THREE DIMENSIONAL INTEGRATED CIRCUITS - A three-dimensional semiconductor device, comprising: a circuit block located in a first module layer; and a configuration circuit to control the circuit block further comprising a configurable element in a second module layer positioned above the first module layer. | 2013-01-03 |
| 20130002297 | BIAS TEMPERATURE INSTABILITY-RESISTANT CIRCUITS - A Bias Temperature Instability- (BTI-) resistance circuit is arranged to propagate a received clock signal through a clock tree. The state of the clock signal is inverted at a midpoint of the clock tree that is about the halfway point of the path of the propagated clock signal through the clock tree. The inversion of the clock signal at the midpoint mitigates BTI-aging effects of the BTI-resistant circuit when the clock signal is blocked by a clock gating signal, for example. The clock tree can be used to latch a data signal at an input latch of a logic block using the received clock signal, and to latch a data signal at an output latch of a logic block using a propagated clock signal that is output from the endpoint of the clock tree. | 2013-01-03 |
| 20130002298 | Signal value storage circuitry with transition detector - A D-type flip-flop | 2013-01-03 |
| 20130002299 | LOGIC LEVEL TRANSLATOR AND ELECTRONIC SYSTEM - A logical level translator includes a first reference voltage provider, a second reference voltage provider, and a switching circuit. The first reference voltage provider provides a first reference voltage signal with a first logic level to a first connection terminal. The second reference voltage provider provides a second reference voltage signal with a second logic level to a second connection terminal. The switching circuit switches on a connection between the first connection terminal and the second connection terminal when a digital signal input to the first connection terminal or the second connection terminal is a logic high level signal. Then switches off the connection between the first connection terminal and the second connection terminal when the digital signals is a logic low level signal. | 2013-01-03 |
| 20130002300 | SERIALIZING TRANSMITTER - In embodiments of a serializing transmitter, the serializing transmitter includes one or more multiplexing drive units that each generate a series of output pulses derived from input data signals and multi-phase clock signals. Each of the multiplexing drive units includes a pulse-controlled push-pull output driver that has first and second inputs, and an output coupled to an output of the multiplexing drive unit. Each of the multiplexing drive units also includes a first M:1 (where M is two or more) pulse-generating multiplexer having an output coupled to the first input of the pulse-controlled push-pull output driver, and generating a first series of intermediate pulses at the output; and a second M:1 pulse-generating multiplexer having an output coupled to the second input of the pulse-controlled push-pull output driver, and generating a second series of intermediate pulses at the output. | 2013-01-03 |
| 20130002301 | SINGLE-ENDED CONFIGURABLE MULTI-MODE DRIVER - Embodiments of the invention are generally directed to a single-ended configurable multi-mode driver. An embodiment of an apparatus includes an input to receive an input signal, an output to transmit a driven signal generated from the input signal on a communication channel, a mechanism for independently configuring a termination resistance of the driver apparatus, and a mechanism for independently configuring a voltage swing of the driven signal without modifying a supply voltage for the apparatus. | 2013-01-03 |
| 20130002302 | COUNTERMEASURE METHOD AND DEVICE FOR PROTECTING DATA CIRCULATING IN AN ELECTRONIC COMPONENT - A countermeasure in a logic circuit having a logic gate supplying a binary output signal, the method including supplying binary data having random values to inputs of logic circuit during a precharge phase; supplying data to process to inputs of the logic circuit during a data processing phase; supplying on input of the logic circuit a precharge command signal launching a precharge phase; and under the effect of the precharge command signal, adapting the functioning of a logic gate of the logic circuit, statistically unbalanced, so that the output signal of the logic gate is in a binary state with a same probability as the random binary data supplied on input of the logic circuit during the precharge phase. | 2013-01-03 |
| 20130002303 | CMOS CIRCUIT WITH DYNAMIC PARASITIC NET PULLDOWN CIRCUIT - A complementary metal oxide semiconductor (CMOS) circuit is described. The CMOS circuit includes a plurality of CMOS gates, a plurality of logic inputs and a logic output. Each CMOS gate is connected to a negative power supply terminal (Vss) and a positive power supply terminal (Vdd). The CMOS circuit further includes parasitic nets connected to the CMOS gates, and net pulldown circuits for eliminating a charge accumulation on the parasitic nets while avoiding potential short circuit conditions. The CMOS gates may be OR-AND-INVERT (OAI) gates or AND-OR-INVERT (AOI) gates. | 2013-01-03 |
| 20130002304 | THRESHOLD TRACKING EDGE DETECTION - Techniques are disclosed relating to tracking edges of a signal of a buffer circuit. In one embodiment, an apparatus is disclosed that includes a sampling circuit configured to sample a pulse width modulation (PWM) signal to generate a threshold voltage based on an average of the high and low voltage levels of the PWM signal and to provide the threshold voltage to an input of a comparator of the apparatus. The comparator is configured receive the threshold voltage and the PWM voltage and perform edge detection on the threshold voltage and PWM signal. | 2013-01-03 |
| 20130002305 | METHOD OF UTILIZING DUAL COMPARATORS TO FACILITATE A PRECISION SIGNAL RECTIFICATION AND TIMING SYSTEM WITHOUT SIGNAL FEEDBACK - A method and an associated apparatus for a signal rectification and timing circuit. A variable amplitude input signal is generated. An upper threshold level is determined and a lower threshold level is determined. The variable amplitude input signal and the upper threshold level are input into a first comparator. The variable amplitude input signal and the lower threshold level are input into a second comparator. A first digital output signal is generated in the first comparator using a hysteresis circuit and a second digital output signal is generated in the second comparator using a hysteresis circuit. The first digital output signal and the second digital output signal are input into a logic array. A digital level pulse output signal is generated in the logic array that has a digital transition where the variable amplitude input signal passed through a threshold level. | 2013-01-03 |
