| 01st week of 2013 patent applcation highlights part 17 |
| Patent application number | Title | Published |
|---|
| 20130001605 | LIGHT-EMITTING DEVICE - A light-emitting device includes a circuit substrate including at least a pair of electrodes, an LED element electrically mounted on the circuit substrate, a phosphor plate disposed on an upper surface of the LED element, a diffuser plate disposed on an upper surface of the phosphor plate, and a white resin disposed on an upper surface of the circuit substrate and covering a peripheral side surface of the LED element, a peripheral side surface of the phosphor plate, and a peripheral side surface of the diffuser plate. The present invention makes it possible to obtain a planar light-emitting surface even with a plurality of LEDs, and also, a problem of color-ring occurrence caused by a phosphor may be less represented. | 2013-01-03 |
| 20130001606 | SUB-MOUNT, LIGHT EMITTING DEVICE INCLUDING SUB-MOUNT AND METHODS OF MANUFACTURING SUCH SUB-MOUNT AND/OR LIGHT EMITTING DEVICE - A sub-mount adapted for AC and DC operation of devices mountable thereon, light emitting devices including such a sub-mount, and methods of manufacturing such a sub-mount are provided. The sub-mount includes a base substrate having first and second surfaces, a conductive pattern on the first surface, first and second pairs of first and second electrodes on the second surface and vias extending through the base substrate between the first and second surfaces. The conductive pattern includes a first set of mounting portions and two via portions along a first electrical path between the first pair of first and second electrodes, and a second set of mounting portions and two via portions along a second electrical path between the second pair of first and second electrodes, the via portions connecting respective portions of the conductive pattern to respective electrodes. | 2013-01-03 |
| 20130001607 | LIGHT-EMITTING DEVICE AND PRODUCTION METHOD THEREOF - Light-emitting device including a supporting substrate, a partition wall dividing a plurality of EL elements on the supporting substrate, and the EL elements provided in a concave portion that is a space between the partition walls. Each EL element is constituted by a first electrode, a first resistance layer formed by an applying method, a second resistance layer having an electric resistance higher than that of the first resistance layer, a light-emitting layer, and a second electrode in this order so that the first electrode is located near the supporting substrate. The first resistance layer includes a creeping-up portion creeping up to a direction that is away from the supporting substrate and along the surface of the corresponding partition wall; and the second resistance layer is provided by ranging continuously over one EL element to another EL element that are adjacent to each other with the partition wall interposed therebetween. | 2013-01-03 |
| 20130001608 | LIGHT EMITTING DEVICE - It is an object of the present invention to prevent an insulating film from peeling in a section where the insulating film is adjacent to a sealing region. Over a first substrate | 2013-01-03 |
| 20130001609 | DISPLAY APPARATUS - In a display apparatus including an organic EL element utilizing the optical interference effect, and a lens, a diameter of the lens is set such that, of light radiated from the organic EL element into a protective layer, light radiated at a larger angle than an angle, at which a light intensity distribution of the light radiated into the protective layer with respect to a radiation angle of the light takes a local minimum value, is not output to the outside of the display apparatus. | 2013-01-03 |
| 20130001610 | DISPLAY APPARATUS - In a display apparatus in which light from a light-emitting element is extracted by an optical element, a difference in reflection characteristics between a display area including the optical element corresponding to the light-emitting element and a non-display area including no optical element impairs the appearance of the display apparatus. | 2013-01-03 |
| 20130001611 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light-emitting device includes a light emitting structure comprising a lower layer of the first conductivity type, an active layer, an upper layer of the second conductivity type, a first electrode connected to the lower layer of the first conductivity type, a second electrode connected to the upper layer of the second conductivity type, and an optical member seeded in the light emitting structure. The optical member can include a plurality of particles substantially transparent and having a lower refractive index than the light emitting structure. A plurality of discontinuities are formed at the boundary of the optical member in the light emitting structure. | 2013-01-03 |
| 20130001612 | Light Emitting Structure, Display Device Including a Light Emitting Structure and Method of Manufacturing a Display Device Including a Light Emitting Structure - A light emitting structure includes a first hole injection layer, a first organic light emitting layer, a charge generation layer, a second hole injection layer, a second organic light emitting layer, an electron transfer layer, and a blocking member. The light emitting structure has first, second, and third sub-pixel regions. The first organic light emitting layer may be on the first hole injection layer. The charge generation layer may be on the first organic light emitting layer. The second hole injection layer may be on the charge generation layer. The second organic light emitting layer may be on the second hole injection layer. The electron transfer layer may be on the second organic light emitting layer. The blocking member may be at at least one of the first to the third sub-pixel regions. | 2013-01-03 |
| 20130001613 | LIGHT EMITTING DIODE PACKAGE AND METHOD FOR MAKING THE SAME - A light emitting diode package includes a substrate with a first metal layer, a second metal layer and an insulating layer between the first metal layer and the second metal layer. A cavity is defined in the insulating layer and the second metal layer. The second metal layer surrounding the cavity is divided into a first conductive portion and a second conductive portion. An LED chip is positioned inside the cavity and on an upper surface of the first metal layer. The LED chip has two electrodes electrically connected to the first conductive portion and the second conductive portion respectively. The cavity is filled with an encapsulation to cover the LED chip. A method for manufacturing the LED package is also disclosed. | 2013-01-03 |
| 20130001614 | LIGHT-EMITTING DIODE DEVICE AND METHOD FOR FABRICATING THE SAME - A light-emitting diode device includes: a substrate including first and second conductors; a light-emitting diode die including first and second polarity sides, and a surrounding surface formed between the first and second polarity sides; an insulator disposed around the surrounding surface; a transparent conductive layer extending from the second polarity side of the light-emitting diode die oppositely of the substrate, along an outer surface of the insulator, and to the second conductor; and a reflecting cup formed on the substrate to define a space with the substrate. The light-emitting diode die, the insulator and the transparent conductive layer are disposed in the space. | 2013-01-03 |
| 20130001615 | LIGHT EMITTING DEVICE AND LIGHTING SYSTEM WITH THE SAME - Embodiments provide a light emitting device including a light emitting structure having a first conduction type semiconductor layer, an active layer, and a second conduction type semiconductor layer, a metal filter of an irregular pattern on the light emitting structure, and openings between the irregular patterns in the metal filter. | 2013-01-03 |
| 20130001616 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE INCLUDING THE SAME AND LIGHTING SYSTEM - Disclosed is a light emitting device including a light emitting structure comprising a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer, a first electrode disposed on the first conductive type semiconductor layer, a second electrode disposed on the second conductivity type semiconductor layer, and a low temperature oxide film disposed on the light emitting structure, with an irregular thickness. | 2013-01-03 |
| 20130001617 | LIGHT EMITTING DEVICE - Provided are a light emitting device, a light emitting device package, and a lighting system. The light emitting device comprises a reflective layer, a second conductive type semiconductor layer on the reflective layer, an active layer on the second conductive type semiconductor layer, a first conductive type semiconductor layer on the active layer, and a pad electrode on the first conductive type semiconductor layer. The reflective layer comprises a predetermined pattern. | 2013-01-03 |
| 20130001618 | LIGHT-EMITTING ELEMENT MOUNTING SUBSTRATE AND LED PACKAGE - A light-emitting element mounting substrate includes an insulative substrate including a single-sided printed circuit board, a pair of wiring patterns formed on one surface of the substrate, the wiring patterns being separated with a first distance, a pair of through-holes penetrating through the substrate in a thickness direction, the through-holes being separated with a second distance, and a pair of filled portions including a metal filled in the pair of through-holes to contact the pair of wiring patterns and to be exposed on a surface of the substrate opposite to the one surface. Each of the pair of filled portions has a horizontal projected area of not less than 50% of an area of each the pair of wiring patterns. | 2013-01-03 |
| 20130001619 | WAVELENGTH CONVERSION PARTICLE, WAVELENGTH CONVERSION MEMBER USING SAME, AND LIGHT EMITTING DEVICE - A wavelength conversion particle | 2013-01-03 |
| 20130001620 | Light-Emitting Device, Electronic Device, and Lighting Device - A high-quality light-emitting device having low power consumption, capability of emitting light of a bright color, and less luminance unevenness is provided. Provided is a light-emitting device in which a plurality of light-emitting units each include a light-emitting element which includes a layer (EL layer) containing an organic compound between a first electrode and a second electrode. The first electrode is separated between light-emitting elements. The EL layer includes a layer (light-emitting layer) containing a light-emitting substance and a layer containing a donor substance and an acceptor substance provided between the first electrode and the light-emitting layer. An inversely tapered partition is provided only between adjacent light-emitting units emitting light of different colors. | 2013-01-03 |
| 20130001621 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device formed in the substrate; a conducting layer disposed on the substrate, wherein the conducting layer is electrically connected to the optoelectronic device; an insulating layer disposed between the substrate and the conducting layer; a light shielding layer disposed on the second surface of the substrate and directly contacting with the conducting layer, wherein the light shielding layer has a light shielding rate of more than about 80% and has at least an opening exposing the conducting layer; and a conducting bump disposed in the opening of the light shielding layer to electrically contact with the conducting layer, wherein all together the light shielding layer and the conducting bump substantially and completely cover the second surface of the substrate. | 2013-01-03 |
| 20130001622 | SUBSTRATE FOR MOUNTING OPTICAL SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF, OPTICAL SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THEREOF - A substrate for mounting optical semiconductor elements is provided, including a base substrate having an insulating layer and a plurality of wiring circuits formed on the upper face of the insulating layer, and having at least one external connection terminal formation opening portion which penetrates the insulating layer and reaches the wiring circuits; and an optical reflection member, which is provided on the upper face of the base substrate, and which forms at least one depressed portion serving as an area for mounting an optical semiconductor element. | 2013-01-03 |
| 20130001623 | LIGHT-EMITTING APPARATUS AND MANUFACTURING METHOD THEREOF - A light-emitting apparatus includes a substrate, at least one light emitting diode (LED) die, a sealant align layer, and a first sealant. The substrate has a die disposing area. The LED die is disposed on the die disposing area. The sealant align layer is disposed on the substrate. The first sealant at least partially covers the LED die and contacts with the sealant align layer. The light-emitting apparatus can avoid the light emitted from the LED die to be blocked and can have higher light efficiency. | 2013-01-03 |
| 20130001624 | LIGHT-EMITTING DEVICE - A light-emitting device includes a semiconductor light-emitting stack; a current injected portion formed on the semiconductor light-emitting stack; an extension portion having a first branch radiating from the current injected portion and having a first width, and a first length greater than the first width, and a second branch extending from the first branch and having a second width larger than the first width, and a second length greater than the second width; and an electrical contact structure between the second branch and the semiconductor light-emitting stack. | 2013-01-03 |
| 20130001625 | LIGHT EMITTING DEVICE HAVING LIGHT EXTRACTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A nitride-based light emitting device capable of achieving an enhancement in emission efficiency and an enhancement in reliability is disclosed. The light emitting device includes a semiconductor layer, and a light extracting layer arranged on the semiconductor layer and made of a material having a refractive index equal to or higher than a reflective index of the semiconductor layer. | 2013-01-03 |
| 20130001626 | LIGHT EMITTING DEVICE - The luminance of different colors of light emitted from EL elements in a pixel portion of a light emitting device is equalized and the luminance of light emitted from the EL elements is raised. The pixel portion of the light emitting device has EL elements whose EL layers contain triplet compounds and EL elements whose EL layers contain singlet compounds in combination. The luminance of light emitted from the plural EL elements is thus equalized. Furthermore, a hole transporting layer has a laminate structure to thereby cause the EL elements to emit light of higher luminance. | 2013-01-03 |
| 20130001627 | LIGHT EMITTING DEVICE - According to one embodiment, a light emitting device includes first and second plate electrodes, a light emitting element and an insulator. The first plate electrode includes first and second major surfaces. The second plate electrode includes third and fourth major surfaces. The light emitting element is placed between the first surface and third major surfaces. The light emitting element includes a semiconductor stacked body having a fifth major surface and a sixth major surface, a first electrode and a second electrode. The semiconductor stacked body includes a light emitting layer. Optical axis is made perpendicular to a side surface of the semiconductor stacked body. The insulator is provided in contact with the first and second plate electrodes and including a window. The light beam is enabled to pass through the window and to be emitted outward. | 2013-01-03 |
| 20130001628 | WHITE LIGHT EMITTING LAMP AND WHITE LED LIGHTING APPARATUS INCLUDING THE SAME - An object is to provide a white light emitting lamp | 2013-01-03 |
| 20130001629 | LED AND METHOD FOR MANUFACTURING THE SAME - An LED (light emitting diode) includes a base, a pair of leads fixed on the base, a housing secured on the leads, a chip mounted on one lead and an encapsulant sealing the chip. The housing defines a cavity to receive the chip. The cavity includes an upper chamber and a lower chamber communicating with the upper chamber. The lower chamber is gradually expanded along a top-to-bottom direction of the LED, and the upper chamber is gradually expanded along a bottom-to-top direction of the LED. The encapsulant substantially fills the lower chamber and the upper chamber. | 2013-01-03 |
| 20130001630 | LIGHT-EMITTING DIODE STRUCTURE - A light-emitting diode structure includes first and second conductors, and a light-emitting diode unit. The light-emitting diode unit includes: a light-emitting diode die including first and second polarity sides, and a surrounding surface, the first polarity side being electrically connected to the first conductor; an insulator disposed around the surrounding surface; and a transparent conductive film extending from the second polarity side, along an outer surface of the insulator, and to the second conductor, so that the second polarity side is electrically connected to the second conductor through the transparent conductive film. | 2013-01-03 |
| 20130001631 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display device and a method of manufacturing the same. The organic light-emitting display device has a structure including an organic layer between a pixel electrode and an opposite electrode, the organic layer including a emissive layer and an insulating layer defining a light emission area. Accordingly, the insulating layer included in the organic layer functions as a pixel-defining layer, and thus, “edge open”, which is generated when forming an emissive layer on a thick pixel-defining layer according to the comparable art, may be reduced or prevented. | 2013-01-03 |
| 20130001632 | LIGHT-EMITTING ELEMENT MOUNTING SUBSTRATE, LED PACKAGE AND METHOD OF MANUFACTURING THE LED PACKAGE - A light-emitting element mounting substrate includes an insulative substrate, a pair of wiring patterns formed on one surface of the substrate, and a pair of filled portions including a metal filled in a pair of through-holes to contact the pair of wiring patterns and to be exposed on a surface of the substrate opposite to the one surface, the pair of through-holes penetrating through the substrate in a thickness direction. The pair of filled portions includes a protruding portion that protrudes outward from the pair of wiring patterns when viewed from the one surface side of the substrate. | 2013-01-03 |
| 20130001633 | LIGHT-EMITTING ELEMENT MOUNTING SUBSTRATE AND LED PACKAGE - A light-emitting element mounting substrate includes an insulative substrate including a single-sided printed circuit board, a pair of wiring patterns formed on one surface of the substrate, the wiring patterns being separated with a first distance, a pair of filled portions including a metal filled in a pair of through-holes to contact the pair of wiring patterns and to be exposed on a surface of the substrate opposite to the one surface, the pair of through-holes being formed to penetrate through the substrate in a thickness direction and to be separated with a second distance, and an insulation layer having a light reflectivity formed on the one surface of the substrate. The pair of filled portions each have a horizontal projected area of not less than 50% of each area the pair of wiring patterns, and the insulation layer includes an opening to expose the pair of wiring patterns. | 2013-01-03 |
| 20130001634 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A nitride semiconductor light emitting device includes a conductive substrate, a first metal layer, a second conductivity-type semiconductor layer, an emission layer, and a first conductivity-type semiconductor layer in this order. The nitride semiconductor light emitting device additionally has an insulating layer covering at least side surfaces of the second conductivity-type semiconductor layer, the emission layer and the first conductivity-type semiconductor layer. A method of manufacturing the same is provided. The nitride semiconductor light emitting device may further include a second metal layer. Thus, a reliable nitride semiconductor light emitting device and a method of manufacturing the same are provided in which short-circuit at the PN junction portion and current leak is reduced as compared with the conventional examples. | 2013-01-03 |
| 20130001635 | LIGHTING DEVICE - An object of the invention is to provide a lighting device which can suppress luminance nonuniformity in a light emitting region when the lighting device has large area. A layer including a light emitting material is formed between a first electrode and a second electrode, and a third electrode is formed to connect to the first electrode through an opening formed in the second electrode and the layer including a light emitting material. An effect of voltage drop due to relatively high resistivity of the first electrode can be reduced by electrically connecting the third electrode to the first electrode through the opening. | 2013-01-03 |
| 20130001636 | LIGHT-EMITTING DIODE AND METHOD FOR FORMING THE SAME - A light-emitting diode includes: an epitaxial substrate; a light-emitting unit including a lower semiconductor layer, and at least two epitaxial units that are separately formed on the lower semiconductor layer, the epitaxial units cooperating with the lower semiconductor layer to define two light-emitting sources that are capable of emitting different colors of light; and an electrode unit including a first electrode which is formed on an exposed portion of the lower semiconductor layer exposed from the epitaxial units, and at least two second electrodes each of which is formed on a corresponding one of the epitaxial units. A method for forming a light-emitting diode is also disclosed. | 2013-01-03 |
| 20130001637 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE - A nitride semiconductor light-emitting device has an n-type nitride semiconductor layer, a lower light-emitting layer, an upper light-emitting layer, and a p-type nitride semiconductor layer in this order. The lower light-emitting layer is formed by alternately stacking a plurality of lower well layers, and a lower barrier layer sandwiched between the lower well layers and having a large bandgap than the lower well layer. The upper light-emitting layer is formed by alternately stacking a plurality of upper well layers, and an upper barrier layer sandwiched between the upper well layers and having a larger bandgap than the upper well layer. Thickness of the upper barrier layer in the upper light-emitting layer is smaller than thickness of the lower barrier layer in the lower light-emitting layer. | 2013-01-03 |
| 20130001638 | SEMICONDUCTOR DEVICE - Plural gate trenches are formed in the surface of an n-type drift region. A gate electrode is formed across a gate oxide film on the inner walls of the gate trenches. P-type base regions are selectively formed so as to neighbor each other in the gate trench longitudinal direction between neighboring gate trenches. An n-type emitter region is formed in contact with the gate trench in a surface layer of the p-type base regions. Also, a p-type contact region with a concentration higher than that of the p-type base region is formed in the surface layer of the p-type base region so as to be in contact with the gate trench side of the n-type emitter region. An edge portion on the gate trench side of the n-type emitter region terminates inside the p-type contact region. | 2013-01-03 |
| 20130001639 | SEMICONDUCTOR DEVICE COMPRISING SEMICONDUCTOR SUBSTRATE HAVING DIODE REGION AND IGBT REGION - A semiconductor device includes a semiconductor substrate in which a diode region and an IGBT region are formed, wherein a lower surface side of the semiconductor substrate comprises a low impurity region provided between a second conductivity type cathode region of the diode region and a first conductivity type collector region of the IGBT region. The low impurity region includes at least one of a first conductivity type first low impurity region which has a lower density of first conductivity type impurities than that in the collector region and a second conductivity type second low impurity region which has a lower density of second conductivity type impurities than that in the cathode region. | 2013-01-03 |
| 20130001640 | SEMICONDUCTOR DEVICE HAVING A FLOATING SEMICONDUCTOR ZONE - A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region. | 2013-01-03 |
| 20130001641 | Defect Mitigation Structures For Semiconductor Devices - A method and a semiconductor device for incorporating defect mitigation structures are provided. The semiconductor device comprises a substrate, a defect mitigation structure comprising a combination of layers of doped or undoped group IV alloys and metal or non-metal nitrides disposed over the substrate, and a device active layer disposed over the defect mitigation structure. The defect mitigation structure is fabricated by depositing one or more defect mitigation layers comprising a substrate nucleation layer disposed over the substrate, a substrate intermediate layer disposed over the substrate nucleation layer, a substrate top layer disposed over the substrate intermediate layer, a device nucleation layer disposed over the substrate top layer, a device intermediate layer disposed over the device nucleation layer, and a device top layer disposed over the device intermediate layer. The substrate intermediate layer and the device intermediate layer comprise a distribution in their compositions along a thickness coordinate. | 2013-01-03 |
| 20130001642 | METHOD INCLUDING PRODUCING A MONOCRYSTALLINE LAYER - A method including producing a monocrystalline layer is disclosed. A first lattice constant on a monocrystalline substrate has a second lattice constant at least in a near-surface region. The second lattice constant is different from the first lattice constant. Lattice matching atoms are implanted into the near-surface region. The near-surface region is momentarily melted. A layer is epitaxially deposited on the near-surface region that has solidified in monocrystalline fashion. | 2013-01-03 |
| 20130001643 | METHOD OF MANUFACTURING PHOTODIODE WITH WAVEGUIDE STRUCTURE AND PHOTODIODE - A process to form a photodiode (PD) with the waveguide structure is disclosed. The PD processes thereby reduces a scattering of the parasitic resistance thereof. The process includes steps to form a PD mesa stripe, to bury the PD mesa stripe by the waveguide region, to etch the PD mesa stripe and the waveguide region to form the waveguide mesa stripe. In the etching, the lower contact layer plays a role of the etching stopper. | 2013-01-03 |
| 20130001644 | Nitride Semiconductor Epitaxial Substrate and Nitride Semiconductor Device - There is provided a nitride semiconductor epitaxial substrate having a group III nitride semiconductor layer with C-plane as a surface, grown on a substrate via a buffer layer of the group III nitride semiconductor containing Al, wherein the buffer layer has an inversion domain on the surface. | 2013-01-03 |
| 20130001645 | SEMICONDUCTOR EPITAXIAL SUBSTRATE - Provided is a semiconductor epitaxial substrate which has low semiconductor layer mosaicity and is suitable for the production of a semiconductor device. Specifically provided is a semiconductor epitaxial substrate formed by epitaxially growing a graded buffer layer which is compositionally graded such that the lattice constant increases in stages within a range from a first lattice constant to a second lattice constant larger than the first lattice constant, and a semiconductor layer produced from a semiconductor crystal having the second lattice constant on a semiconductor substrate having the first lattice constant. The angle formed by the (mnn) plane (m and n are integers except m=n=0) of the semiconductor layer and the (mnn) plane of the semiconductor substrate is set to +0.05° or more when the direction that rotates clockwise from the [100] direction to the [011] direction is positive. | 2013-01-03 |
| 20130001646 | ALGaN/GaN HYBRID MOS-HFET - A field effect transistor (FET) includes source and drain electrodes, a channel layer, a barrier layer over the channel layer, a passivation layer covering the barrier layer for passivating the barrier layer, a gate electrode extending through the barrier layer and the passivation layer, and a gate dielectric surrounding a portion of the gate electrode that extends through the barrier layer and the passivation layer, wherein the passivation layer is a first material and the gate dielectric is a second material, and the first material is different than the second material. | 2013-01-03 |
| 20130001647 | INTEGRATION OF VERTICAL BJT OR HBT INTO SOI TECHNOLOGY - In an embodiment, a bipolar transistor structure is formed on a silicon-on-insulator (SOI) structure that includes a semiconductor substrate, a buried oxide layer formed on the semiconductor substrate and a top silicon layer formed on the buried oxide layer. The bipolar transistor structure includes: an opening formed in the top silicon layer; an opening in the buried oxide layer beneath the opening in the top silicon layer, the opening in the buried oxide layer including a region that undercuts the opening in the top silicon layer at a side of the opening in the top silicon layer; conductive material having a first conductivity type formed in the opening in the buried oxide layer such that the conductive material includes a region that undercuts the top silicon layer at the side of the opening in the top silicon layer; isolation dielectric material formed in the top silicon layer over the region of conductive material that undercuts the top silicon layer to define a bipolar transistor collector region having the first conductivity type, the collector region being in contact with the region of conductive material; a bipolar transistor base region formed in contact with an upper surface of the collector region, the base region having a second conductivity type that is opposite the first conductivity type; and an emitter region formed in contact with the base region, the emitter region having the first conductivity type. | 2013-01-03 |
| 20130001648 | Gated AlGaN/GaN Schottky Device - Some exemplary embodiments of a semiconductor device using a III-nitride heterojunction and a novel Schottky structure and related method resulting in such a semiconductor device, suitable for high voltage circuit designs, have been disclosed. One exemplary structure comprises a first layer comprising a first III-nitride material, a second layer comprising a second III-nitride material forming a heterojunction with said first layer to generate a two dimensional electron gas (2DEG) within said first layer, an anode comprising at least a first metal section forming a Schottky contact on a surface of said second layer, a cathode forming an ohmic contact on said surface of said second layer, a field dielectric layer on said surface of said second layer for isolating said anode and said cathode, and an insulating material on said surface of said second layer and in contact with said anode. | 2013-01-03 |
| 20130001649 | SEMICONDUCTOR DEVICE EMPLOYING CIRCUIT BLOCKS HAVING THE SAME CHARACTERISTICS - A semiconductor device is disclosed, which comprises First and second inputs ports, first and second output nodes, and first and second transistors. The first transistor includes first and second diffusion regions defining a first channel region and a first gate electrode and connected to the first input port, the first diffusion region being connected to the first output node, the second diffusion region being disposed between the first diffusion region and the first input port and supplied with a first operating potential. The second transistor includes third and fourth diffusion regions defining a second channel region and a second gate electrode and connected to the second input port, the third diffusion region being supplied with the first operating potential, the fourth diffusion region being disposed between the third diffusion region and the second input port and connected to the second output node. | 2013-01-03 |
| 20130001650 | SOLID-STATE IMAGING DEVICE - The present invention provides a solid-state imaging device in which high S/N is achieved. A solid-state imaging device includes a photodiode, a transfer transistor, a floating diffusion, a floating diffusion wiring, an amplifying transistor, a power line, and first output signal lines, in which the first output signal lines are formed one on each side of the floating diffusion wiring in a layer having the floating diffusion wiring formed on a semiconductor substrate, and the power line is formed above the floating diffusion wiring. | 2013-01-03 |
| 20130001651 | SEMICONDUCTOR LIGHT DETECTING ELEMENT - A semiconductor light detecting element is provided with a silicon substrate having a semiconductor layer, and an epitaxial semiconductor layer grown on the semiconductor layer and having a lower impurity concentration than the semiconductor layer; and conductors provided on a surface of the epitaxial semiconductor layer. A photosensitive region is formed in the epitaxial semiconductor layer. Irregular asperity is formed at least in a surface opposed to the photosensitive region in the semiconductor layer. The irregular asperity is optically exposed. | 2013-01-03 |
| 20130001652 | MAGNETORESISTIVE ELEMENT AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a magnetoresistive element includes a storage layer having a variable and perpendicular magnetization, a tunnel barrier layer on the storage layer, a reference layer having an invariable and perpendicular magnetization on the tunnel barrier layer, a hard mask layer on the reference layer, and a sidewall spacer layer on sidewalls of the reference layer and the hard mask layer. An in-plane size of the reference layer is smaller than an in-plane size of the storage layer. A difference between the in-plane sizes of the storage layer and the reference layer is 2 nm or less. The sidewall spacer layer includes a material selected from a group of a diamond, DLC, BN, SiC, B | 2013-01-03 |
| 20130001653 | CHEMICALLY-SENSITIVE FIELD EFFECT TRANSISTOR BASED PIXEL ARRAY WITH PROTECTION DIODES - Methods and apparatus relating to FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions. | 2013-01-03 |
| 20130001654 | MASK-BASED SILICIDATION FOR FEOL DEFECTIVITY REDUCTION AND YIELD BOOST - A semiconductor device with reduced defect density is fabricated by forming localized metal silicides instead of full area silicidation. Embodiments include forming a transistor having a gate electrode and source/drain regions on a substrate, forming a masking layer with openings exposing portions of both the gate electrode and source/drain regions over the substrate, depositing metal in the openings on the exposed portions, forming silicides in the openings, and removing unreacted metal and the masking layer. | 2013-01-03 |
| 20130001655 | Heat Dissipation Structure of SOI Field Effect Transistor - The present invention discloses a heat dissipation structure for a SOI field effect transistor having a schottky source/drain, which relates to a field of microelectronics. The heat dissipation structure includes two holes connected with a drain terminal or with both a source terminal and a drain terminal, which are filled with an N-type material with high thermoelectric coefficient and a P-type material with high thermoelectric coefficient respectively. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a high potential with respect to the drain terminal, and a metal wire for the P-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a low potential with respect to the drain terminal. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the source terminal is applied a high potential with respect to the source terminal, and a metal wire for the P-type material in the vicinity of the source terminal is applied a lower potential with respect to the source terminal. By way of a Peltier effect, in the present invention heat can be absorbed at a contact portion between the thermoelectric material and the source/drain, and at the same time dissipated at a connection portion between the thermoelectric material and a bottom electrode metal, so that the heat generated in an active region of the device is effectively transferred to the substrate and dissipated through a heat sink. | 2013-01-03 |
| 20130001656 | VERTICALLY PINCHED JUNCTION FIELD EFFECT TRANSISTOR - A vertical junction field-effect transistor in a CMOS base-technology. The vertical junction field-effect transistor includes a semiconductor substrate having a source region and a drain region, a main-channel region formed between the source region and the drain region, a well region formed on the main-channel region between the source region and the drain region, vertical pinch-off regions formed at both source and drain ends or only on the source-end of the well region on the main-channel region in the source region and the drain region respectively, a source contact on the vertical pinch-off region in the source region, a drain contact on the vertical pinch-off region in the drain region, a gate contact on the well region between the source contact and the drain contact and shallow trench isolations formed on the well region. | 2013-01-03 |
| 20130001657 | SELF-ALIGNED III-V MOSFET DIFFUSION REGIONS AND SILICIDE-LIKE ALLOY CONTACT - A metal oxide semiconductor field effect transistor and method for forming the same include exposing portions on a substrate adjacent to a gate stack, forming a dopant layer over the gate stack and in contact with the substrate in the portions exposed and annealing the dopant layer to drive dopants into the substrate to form self-aligned dopant regions in the substrate. The dopant layer is removed. A metal containing layer is deposited over the gate stack and in contact with the substrate in the exposed portions. The metal containing layer is annealed to drive metal into the substrate to form self-aligned contact regions in a metal alloy formed in the substrate within the dopant regions. The metal layer is then removed. | 2013-01-03 |
| 20130001658 | CORNER TRANSISTOR AND METHOD OF FABRICATING THE SAME - A method of fabricating a corner transistor is described. An isolation structure is formed in a substrate to define an active region. A treating process is performed to make the substrate in the active region have sharp corners at top edges thereof. The substrate in the active region is covered by a gate dielectric layer. A gate conductor is formed over the gate dielectric layer. A source region and a drain region are formed in the substrate beside the gate conductor. | 2013-01-03 |
| 20130001659 | SELF-ALIGNED III-V MOSFET DIFFUSION REGIONS AND SILICIDE-LIKE ALLOY CONTACT - A metal oxide semiconductor field effect transistor and method for forming the same include exposing portions on a substrate adjacent to a gate stack, forming a dopant layer over the gate stack and in contact with the substrate in the portions exposed and annealing the dopant layer to drive dopants into the substrate to form self-aligned dopant regions in the substrate. The dopant layer is removed. A metal containing layer is deposited over the gate stack and in contact with the substrate in the exposed portions. The metal containing layer is annealed to drive metal into the substrate to form self-aligned contact regions in a metal alloy formed in the substrate within the dopant regions. The metal layer is then removed. | 2013-01-03 |
| 20130001660 | PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD - Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region. | 2013-01-03 |
| 20130001661 | HIGH FULL-WELL CAPACITY PIXEL WITH GRADED PHOTODETECTOR IMPLANT - Embodiments of a process for forming a photodetector region in a CMOS pixel by dopant implantation, the process comprising masking a photodetector area of a surface of a substrate for formation of the photodetector region, positioning the substrate at a plurality of twist angles, and at each of the plurality of twist angles, directing dopants at the photodetector area at a selected tilt angle. Embodiments of a CMOS pixel comprising a photodetector region formed in a substrate, the photodetector region comprising overlapping first and second dopant implants, wherein the overlap region has a different dopant concentration than the non-overlapping parts of the first and second implants, a floating diffusion formed in the substrate, and a transfer gate formed on the substrate between the photodetector and the transfer gate. Other embodiments are disclosed and claimed. | 2013-01-03 |
| 20130001662 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor element; a divider connected with an input portion of the semiconductor element; and a combiner connected with an output portion of the semiconductor element. The divider is disposed on a substrate and has a first divider portion including a first transmission line and a second transmission line, a second divider portion including a third transmission line and a fourth transmission line, and a first resistance and a second resistance respectively connected to both the first transmission line and the third transmission line. The first resistance is disposed in the space between the first and third transmission lines, the second resistance is disposed in the space between the first and third transmission lines, and the first resistance is disposed between the second resistance and the semiconductor element. | 2013-01-03 |
| 20130001663 | DRAM Layout with Vertical FETS and Method of Formation - DRAM cell arrays having a cell area of about 4F | 2013-01-03 |
| 20130001664 | DECOUPLING CAPACITOR CIRCUITRY - Integrated circuits with decoupling capacitor circuitry are provided. The decoupling capacitor circuitry may include density-compliance structures. The density-compliance structures may be strapped to metal paths driven by power supply lines. Strapping density-compliance dummy structures in this way may increase the capacitance per unit area of the decoupling capacitor circuitry. Strapping density-compliance dummy structures in this way may shield the decoupling capacitor from nearby noisy signal sources. | 2013-01-03 |
| 20130001665 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulating layer; a gate stack disposed on the semiconductor layer; a source region and a drain region embedded in the semiconductor layer and disposed on both sides of the gate stack; and a channel region embedded in the semiconductor layer and sandwiched between the source region and the drain region, wherein the MOSFET further comprises a back gate and a counter doped region, and wherein the back gate is embedded in the semiconductor substrate, the counter doped region is disposed under the channel region and embedded in the back gate, and the back gate has a doping type opposite to that of the counter doped region. The MOSFET can adjust a threshold voltage by changing the doping type of the back gate. | 2013-01-03 |
| 20130001666 | Memory Cells, Arrays Of Memory Cells, And Methods Of Forming Memory Cells - A memory cell includes a vertically oriented transistor having an elevationally outer source/drain region, an elevationally inner source/drain region, and a channel region elevationally between the inner and outer source/drain regions. The inner source/drain region has opposing laterally outer sides. One of a pair of data/sense lines is electrically coupled to and against one of the outer sides of the inner source/drain region. The other of the pair of data/sense lines is electrically coupled to and against the other of the outer sides of the inner source/drain region. An access gate line is elevationally outward of the pair of electrically coupled data/sense lines and is operatively adjacent the channel region. A charge storage device is electrically coupled to the outer source/drain region. Other embodiments and additional aspects, including methods, are disclosed. | 2013-01-03 |
| 20130001667 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MAKING THE SAME - A method for making a nonvolatile memory device includes the following steps. A conductive structure is formed, wherein the conductive structure has a first top portion. The first top portion is converted into a second top portion having a domed surface. | 2013-01-03 |
| 20130001668 | FLOATING GATE DEVICE WITH OXYGEN SCAVENGING ELEMENT - A floating gate device is provided. A tunnel oxide layer is formed over the channel. A floating gate is formed over the tunnel oxide layer. A high-k dielectric layer is formed over the floating gate. A control gate is formed over the high-k dielectric layer. At least one of the control gate and/or the floating gate includes an oxygen scavenging element. The oxygen scavenging element is configured to decrease an oxygen density at least one of at a first interface between the control gate and the high-k dielectric layer, at a second interface between the high-k dielectric layer and the floating gate, at a third interface between the floating gate and the tunnel oxide layer, and at a fourth interface between the tunnel oxide layer and the channel responsive to annealing. | 2013-01-03 |
| 20130001669 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor memory device includes a substrate and a plurality of rows of memory cells. The substrate comprises a plurality of isolation structures and a plurality of active regions. Each of the active regions is spaced apart from another active region by one of the isolation structures. In a cross-section of the substrate between two rows of memory cells in a direction parallel to the two rows of memory cells, a maximum height of each isolation structure with respect to a bottom of the substrate is lower than or equal to minimum heights of active regions adjacent thereto. | 2013-01-03 |
| 20130001670 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A conductive film having a first width in a first direction, an ONO film, and a control gate are formed above a tunnel gate insulating film. With the control gate as a mask, the conductive film is etched to form a floating gate. Then, an inter-layer insulating film is formed. A contact hole whose width in the first direction is larger than the first width is formed in the inter-layer insulating film. Then, sidewall spacer is formed on an inside wall of the contact hole. | 2013-01-03 |
| 20130001671 | SELECT GATES FOR MEMORY - Methods of forming memory and memory devices are disclosed, such as a memory device having a memory cell with a floating gate formed from a first conductor, a control gate formed from a second conductor, and a dielectric interposed between the floating gate and the control gate. For example, a select gate may be coupled in series with the memory cell and has a first control gate portion formed from the first conductor and a second control gate portion formed from a third conductor. A contact may be formed from the third conductor and coupled in series with the select gate. Other methods and devices are also disclosed. | 2013-01-03 |
| 20130001672 | SEMICONDUCTOR DEVICE - A semiconductor device includes a main active region provided in a semiconductor substrate and having a first side surface and a second side surface facing each other. A first auxiliary active region adjacent the first side surface of the main active region and spaced apart from the main active region by a first distance is provided. A second auxiliary active region adjacent the second side surface of the main active region and spaced apart from the main active region by the first distance is provided. A first conductive pattern crosses the main active region and includes first and second side portions facing each other. The first side portion of the conductive pattern is disposed between the first auxiliary active region and the main active region, and the second side portion of the conductive pattern is disposed between the second auxiliary active region and the main active region. | 2013-01-03 |
| 20130001673 | FORTIFICATION OF CHARGE STORING MATERIAL IN HIGH K DIELECTRIC ENVIRONMENTS AND RESULTING APPARATUSES - Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel dielectric and a protective film over the nanodots. In another memory cell, the charge storage node includes nanodots that include a ruthenium alloy. Memory cells can include an inter-gate dielectric over the protective film or ruthenium alloy nanodots and a control gate over the inter-gate dielectric. The protective film and ruthenium alloy can be configured to protect at least some of the nanodots from vaporizing during formation of the inter-gate dielectric. | 2013-01-03 |
| 20130001674 | SEMICONDUCTOR DEVICE WITH VOLTAGE COMPENSATION STRUCTURE - A semiconductor device with a high voltage compensation component is manufactured by etching a trench into an epitaxial semiconductor material doped with n-type dopant atoms and p-type dopant atoms and disposing a first semiconductor or insulating material along one or more sidewalls of the trench. The first semiconductor or insulating material has a dopant diffusion constant which is at least 2× different for the n-type dopant atoms than the p-type dopant atoms. A second semiconductor material is disposed in the trench along the first semiconductor or insulating material. The second semiconductor material has a different dopant diffusion constant than the first semiconductor or insulating material. More n-type dopant atoms or p-type dopant atoms are diffused from the epitaxial semiconductor material through the first semiconductor or insulating material into the second semiconductor material than the other type of dopant atoms so that a lateral charge separation occurs between the second semiconductor material and the epitaxial semiconductor material. | 2013-01-03 |
| 20130001675 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate including first trenches defining outer sidewalls of a pair of active pillars and a second trench defining opposing inner sidewalls of the pair of active pillars. The second trench may have a bottom surface located at a higher level than bottom surface of the first trench. Auxiliary conductive lines may be disposed in the first trenches to cover and cross the outer sidewalls of the pair of active pillars. A pair of main conductive lines may be disposed in a pair of recessed regions that are laterally recessed from lower portions of the inner sidewalls of the active pillars into the pair of active pillars. A common impurity region may be disposed in the semiconductor substrate under the second trench. Upper impurity regions may be disposed in upper portions of the active pillars. | 2013-01-03 |
| 20130001676 | THROUGH SILICON VIA DIRECT FET SIGNAL GATING - A system comprises a first integrated circuit (IC) chip that includes a first electronic component; a second IC chip that includes a second electronic component; a through silicon via (TSV) in the second IC chip that electrically couples the first electronic component to the second electronic component; and a signal gating transistor that fully occludes the TSV. | 2013-01-03 |
| 20130001677 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - The upper end of a gate electrode is situated below the surface of a semiconductor substrate. An insulating layer is formed over the gate electrode and over the semiconductor substrate situated at the periphery thereof. The insulating layer has a first insulating film and a low oxygen permeable insulating film. The first insulating film is, for example, an NSG film and the low oxygen permeable insulating film is, for example, an SiN film. Further, a second insulating film is formed over the low oxygen permeable insulating film. The second insulating film is, for example, a BPSG film. The TDDB resistance of a vertical MOS transistor is improved by processing with an oxidative atmosphere after forming the insulating layer. Further since the insulating layer has the low oxygen permeable insulating film, fluctuation of the threshold voltage of the vertical MOS transistor can be suppressed. | 2013-01-03 |
| 20130001678 | HIGH BREAKDOWN VOLTAGE SEMICONDUCTOR DEVICE WITH AN INSULATED GATE FORMED IN A TRENCH, AND MANUFACTURING PROCESS THEREOF - A semiconductor device includes: a semiconductor body; a trench having side walls and a bottom; a gate region made of conductive material, extending within the trench; an insulating region, extending along bottom portions of the side walls of the trench and on the bottom of the trench; a gate insulating layer, extending along top portions of the side walls of the trench, laterally with respect to the gate region; a conductive region, extending within the trench, surrounded at the top and laterally by the gate region and surrounded at the bottom and laterally by the insulating region; and a field insulating layer, arranged between the gate region and the conductive region. The gate insulating layer includes thickened portions, each of which contacts the insulating region and has a thickness that increases as the depth increases. | 2013-01-03 |
| 20130001679 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor layer, a gate trench formed in the semiconductor layer, a source region exposed at a front surface of the semiconductor layer and forming a curved portion of the gate trench, a channel region forming a planar portion of the gate trench, a drain region forming a bottom surface of the gate trench, a gate oxide film formed on an inner surface of the gate trench, a gate electrode embedded inside the gate trench in the planar portion, an embedding insulator film embedded inside the gate trench in the curved portion, a contact trench formed in the semiconductor layer in self-alignment with the curved portion of the gate trench, and a channel contact region formed on a bottom surface of the contact trench. | 2013-01-03 |
| 20130001680 | SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device (A | 2013-01-03 |
| 20130001681 | MOS-DRIVEN SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING MOS-DRIVEN SEMICONDUCTOR DEVICE - A mask used to form an n | 2013-01-03 |
| 20130001682 | SEMICONDUCTOR STRUCTURES INCLUDING BODIES OF SEMICONDUCTOR MATERIAL, DEVICES INCLUDING SUCH STRUCTURES AND RELATED METHODS - Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material. | 2013-01-03 |
| 20130001683 | FLEXIBLE CRSS ADJUSTMENT IN A SGT MOSFET TO SMOOTH WAVEFORMS AND TO AVOID EMI IN DC-DC APPLICATION - A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device. | 2013-01-03 |
| 20130001684 | METHOD OF MANUFACTURING TRENCH MOSFET USING THREE MASKS PROCESS HAVING TILT- ANGLE SOURCE IMPLANTS - In according with the present invention, a semiconductor device is formed as follows. A contact insulation layer is deposited on the top surface of said silicon layer. A contact mask is applied and following with a dry oxide etching to remove the contact insulation layer from contact open areas. The silicon layer is tilt-angle implanted with a source dopant through the contact open areas and the source dopant is diffused to form source regions, thereby a source mask is saved. A dry silicon etch is carried out to form trenched source-body contacts in the contact open areas, penetrating through the source regions and extending into the body regions. | 2013-01-03 |
| 20130001685 | Semiconductor Device - The present invention relates to an integrated circuit (semiconductor device) for which consolidation of a fine CMOS and a medium/high-voltage MOSFET is assumed to be carried out. A feature of the present invention is a small width (channel length) of a channel region CH. Specifically, when the width of the channel region planarly overlapped with a gate electrode is “L” and the thickness of the gate electrode is “t”, the channel region is formed to have the width of the channel region being larger than or equal to ⅕ times the thickness t of the gate electrode and smaller than or equal to the thickness t. Thus, the width L of the channel region can be reduced, and variations in the threshold voltage can be reduced. | 2013-01-03 |
| 20130001686 | ELECTRO-STATIC DISCHARGE PROTECTION DEVICE - An Electro-Static Discharge (ESD) protection device is provided. The ESD protection device includes a metal-oxide semiconductor (MOS) transistor, including a source area having a surface on which a first silicide is formed, the source area including a source connecting area including a first connecting portion formed on the first silicide, and a source extension area, a gate arranged in parallel with the source area, and a drain area arranged in parallel with the source area and the gate, the drain area having a surface on which a second silicide is formed, the drain area including a drain connecting area formed opposite the source extension area, the drain connecting area including second connection portion formed on the second silicide, and a drain extension area formed opposite the source connecting area. | 2013-01-03 |
| 20130001687 | Transistor with Reduced Channel Length Variation - According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor. | 2013-01-03 |
| 20130001688 | SELF-ALIGNED BODY FULLY ISOLATED DEVICE - A device having a self-aligned body on a first side of a gate is disclosed. The self-aligned body helps to achieve very low channel length for low Rdson. The self-aligned body is isolated, enabling to bias the body at different bias potentials. The device may be configured into a finger architecture having a plurality of transistors with commonly coupled, sources, commonly coupled gates, and commonly coupled drains to achieve high drive current outputs. | 2013-01-03 |
| 20130001689 | TEXTURED GATE FOR HIGH CURRENT THIN FILM TRANSISTORS - A textured thin film transistor is comprised of an insulator sandwiched between a textured gate electrode and a semi-conductor. A source electrode and drain electrode are fabricated on a surface of the semi-conductor. The textured gate electrode is fabricated such that a surface is modified in its texture and/or geometry, such modifications affecting the transistor current. | 2013-01-03 |
| 20130001690 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present application provides a MOSFET and a method for manufacturing the same. The MOSFET comprises: a semiconductor substrate; a first buried insulating layer on the semiconductor substrate; a back gate formed in a first semiconductor layer which is on the first buried insulating layer; a second buried insulating layer on the first semiconductor layer; source/drain regions formed in a second semiconductor layer which is on the second buried insulating layer; a gate on the second semiconductor layer; and electrical contacts on the source/drain regions, the gate and the back gate, wherein the back gate is only under a channel region and one of the source/drain regions and not under the other of the source/drain regions, and a common electrical contact is formed between the back gate and the one of the source/drain regions. The MOSFET improves an effect of suppressing short channel effects by an asymmetric back gate, and reduces a footprint on a wafer by using the common conductive via. | 2013-01-03 |
| 20130001691 | Semiconductor structure and method for manufacturing the same - The present invention provides a method for manufacturing a semiconductor structure, which comprises: providing an SOI substrate, and forming a gate structure on the SOI substrate; etching an SOI layer and a BOX layer of the SOI substrates on both sides of the gate structure, so as to form trenches exposing the BOX layer and extending partially into the BOX layer; forming metal sidewall spacers on sidewalls of the trenches, wherein the metal sidewall spacers is in contact with the SOI layer under the gate structure; forming an insulating layer filling partially the trenches, and forming a dielectric layer to cover the gate structure and the insulating layer; etching the dielectric layer to form first contact through holes that expose at least partially the insulating layer, and etching the insulating layer from the first contact through holes to form second contact through holes that expose at least partially the metal sidewall spacer; filling the first contact through holes and the second contact through holes to form contact vias, which are in contact with the metal sidewall spacers. The method provided by the present invention is capable of improving performance of semiconductor devices and alleviating manufacturing difficulty at the mean time. | 2013-01-03 |
| 20130001692 | Semiconductor Devices Including a Layer of Polycrystalline Silicon Having a Smooth Morphology - A method for controlling the morphology of deposited silicon on a layer of silicon dioxide and semiconductor devices incorporating such deposited silicon are provided. The method comprises the steps of: providing a layer of silicon dioxide; implanting hydrogen ions into the layer of silicon dioxide by plasma source ion implantation; and forming a layer of polycrystalline silicon on the layer of silicon dioxide. | 2013-01-03 |
| 20130001693 | BAND EDGE ENGINEERED Vt OFFSET DEVICE - Band edge engineered Vt offset devices, design structures for band edge engineered Vt offset devices and methods of fabricating such structures is provided herein. The structure includes a first FET having a channel of a first compound semiconductor of first atomic proportions resulting in a first band structure and a first type. The structure further includes a second FET having a channel of a second compound semiconductor of second atomic proportions resulting in a second band structure and a first type. The first compound semiconductor is different from the second compound semiconductor such that the first FET has a first band structure different from second band structure, giving rise to a threshold voltage different from that of the second FET. | 2013-01-03 |
| 20130001694 | LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR (TVS) WITH REDUCED CLAMPING VOLTAGE - A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer. | 2013-01-03 |
| 20130001695 | UNI-DIRECTIONAL TRANSIENT VOLTAGE SUPPRESSOR (TVS) - An epitaxial layer is supported on top of a substrate. First and second body regions are formed within the epitaxial layer separated by a predetermined lateral distance. Trigger and source regions are formed within the epitaxial layer. A first source region is transversely adjacent the first body region between first and second trigger regions laterally adjacent the first source region and transversely adjacent the first body region. A second source region is located transversely adjacent the second body region between third and fourth trigger regions laterally adjacent the second source region and transversely adjacent the second body region. A third source region is laterally adjacent the fourth trigger region. The fourth trigger region is between the second and third source regions. An implant region within the fourth trigger region is laterally adjacent the third source region. | 2013-01-03 |
| 20130001696 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A gate electrode and an electrode for protective diode are coupled to each other. An insulating film below the electrode for protective diode makes a leak current flow between the electrode for protective diode and an electron transit layer and an electron supply layer when a voltage equal to or more than a given value is applied to the gate electrode. The given value is higher than a voltage by which a HEMT is on-operated and lower than a breakdown voltage of a gate insulating film. | 2013-01-03 |
| 20130001697 | SEMICONDUCTOR DEVICE - A semiconductor device includes a signal input pad, a protection object circuit, a first connection node connected with the protection object circuit, a first resistance element connected between the signal input pad and the first connection node, a first protection circuit section arranged between a power supply line or a ground line and a second connection node between the signal input pad and the first resistance element, and a second protection circuit section. The second protection circuit section includes at least one of a first PMOS transistor having a source connected with the first connection node, a drain connected with the ground line and a gate and a back gate connected with the power supply line, and a first NMOS transistor having a source connected with said first connection node, a drain connected with the power supply line and a gate and a back gate connected with the ground line. | 2013-01-03 |
| 20130001698 | METHOD TO MODIFY THE SHAPE OF A CAVITY USING ANGLED IMPLANTATION - A method of modifying a shape of a cavity in a substrate. The method includes forming one or more cavities on a surface of the substrate between adjacent relief structures. The method also includes directing ions toward the substrate at a non-normal angle of incidence, wherein the ions strike an upper portion of a cavity sidewall, and wherein the ions do not strike a lower portion of the cavity sidewall. The method further includes etching the one or more cavities wherein the upper portion of a cavity sidewall etches more slowly than the lower portion of the sidewall cavity. | 2013-01-03 |
| 20130001699 | TRENCH JUNCTION BARRIER SCHOTTKY STRUCTURE WITH ENHANCED CONTACT AREA INTEGRATED WITH A MOSFET - An object of this invention is to provide a Schottky diode structure to increase the contact area at a Schottky junction between the Schottky Barrier metal and a semiconductor substrate. The larger contact area of the Schottky junction is, the lower of the forward voltage drop across the Schottky diode will be, thereby improving the performance and efficiency of the Schottky diode. | 2013-01-03 |
| 20130001700 | LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE - A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area. | 2013-01-03 |
| 20130001701 | Vertical Stacking of Field Effect Transistor Structures for Logic Gates - Vertically stacked Field Effect Transistors (FETs) are created where a first FET and a second FET are controllable independently. The vertically stacked FETs may be connected in series or in parallel, thereby suitable for use as a portion of a NAND circuit or a NOR circuit. Epitaxial growth over a source and drain of a first FET, and having similar doping to the source and drain of the first FET provide a source and drain of a second FET. An additional epitaxial growth of a type opposite the doping of the source and drain of the first FET provides a body for the second FET. | 2013-01-03 |
| 20130001702 | ENHANCING MOSFET PERFORMANCE BY OPTIMIZING STRESS PROPERTIES - A device and method for improving performance of a transistor includes gate structures formed on a substrate having a spacing therebetween. The gate structures are formed in an operative relationship with active areas formed in the substrate. A stress liner is formed on the gate structures. An angled ion implantation is applied to the stress liner such that ions are directed at vertical surfaces of the stress liner wherein portions of the stress liner in contact with the active areas are shielded from the ions due to a shadowing effect provided by a height and spacing between adjacent structures. | 2013-01-03 |
| 20130001703 | SEMICONDUCTOR DEVICE - A combined switching device includes a MOSFET disposed in a MOSFET area and IGBTs disposed in IGBT areas of a SiC substrate. The MOSFET and the IGBTs have gate electrodes respectively connected, a source electrode and emitter electrodes respectively connected, and a drain electrode and a collector electrode respectively connected. The MOSFET and the IGBTs are disposed with a common n-buffer layer. A top surface element structure of the MOSFET and top surface element structures of the IGBTs are disposed on the first principal surface side of the SiC substrate. Concave portions and convex portions are disposed on the second principal surface side of the SiC substrate. The MOSFET is disposed at a position corresponding to the convex portion of the SiC substrate. The IGBTs are disposed at positions corresponding to the concave portions of the SiC substrate. | 2013-01-03 |
| 20130001704 | Resistors Formed Based on Metal-Oxide-Semiconductor Structures - A device includes a metal-oxide-semiconductor (MOS) device, which includes a gate electrode and a source/drain region adjacent the gate electrode. A first and a second contact plug are formed directly over and electrically connected to two portions of a same MOS component, wherein the same MOS component is one of the gate electrode and the source/drain region. The same MOS component is configured to be used as a resistor that is connected between the first and the second contact plugs. | 2013-01-03 |
