01st week of 2009 patent applcation highlights part 69 |
Patent application number | Title | Published |
20090006814 | Immediate and Displacement Extraction and Decode Mechanism - An extraction and decode mechanism for acquiring and processing instructions and the corresponding constant(s) embedded within the instructions. The extraction and decode mechanism may be included within a processing unit, and may comprise an instruction decode unit and at least one constant steer network. During operation, the instruction decode unit may obtain and decode instructions which are to be executed by the processing unit. For each instruction, the instruction decode unit may also determine the location of one or more constants embedded within the instruction. The constant steer network may receive the location information from the instruction decode unit. While the instruction decode unit decodes the instruction, the constant steer network may obtain the constant(s) embedded within the instruction based on the location information and store the constant(s). The constant(s) embedded within the instruction may be immediate or displacement (imm/disp) constant(s). | 2009-01-01 |
20090006815 | SYSTEM AND METHOD FOR INTERFACING DEVICES - A system in one embodiment includes (i) an interface module to control and monitor the system; a plurality of power cells which act as a point of power delivery and monitor environmental variables that effect function and reliability, (ii) a radio frequency transmitter and receiver to manage nodes distributed across the plurality of power cells, (iii) a maintenance module presenting information requests to be forwarded to the plurality of power cells, and (iv) a communication bus for distribution of data throughout the system. | 2009-01-01 |
20090006816 | Inter-Cluster Communication Network And Heirarchical Register Files For Clustered VLIW Processors - A VLIW processor has a hierarchy of functional unit clusters that communicate through explicit control in the instruction stream and store data in register files at each level of the hierarchy. Explicit instructions transfer values between sub-clusters through a cluster level switch network. Transfer instructions issue in dedicated instruction issue slots in parallel with instructions that perform computation in functional units. The switch network can perform permutations on the data being moved. The switch network enables for operands to be broadcast between the sub-clusters, global register file and memory. | 2009-01-01 |
20090006817 | Mechanisms for Placing a Processor into a Gradual Slow Mode of Operation - Mechanisms for placing a processor into a gradual slow down mode of operation are provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe. | 2009-01-01 |
20090006818 | Method and Apparatus for Multiple Load Instruction Execution - A method and apparatus for executing instructions. The method includes receiving a first load instruction and a second load instruction. The method also includes issuing the first load instruction and the second load instruction to a cascaded delayed execution pipeline unit having at least a first execution pipeline and a second execution pipeline, wherein the second execution pipeline executes an instruction in a common issue group in a delayed manner relative to another instruction in the common issue group executed in the first execution pipeline. The method also includes accessing a cache by executing the first load instruction and the second load instruction. A delay between execution of the first load instruction and the second load instruction allows the cache to complete the access with the first load instruction before beginning the access with the second load instruction. | 2009-01-01 |
20090006819 | Single Hot Forward Interconnect Scheme for Delayed Execution Pipelines - A method and apparatus for forwarding data in a processor. The method includes providing at least one cascaded delayed execution pipeline unit having a first pipeline and a second pipeline, wherein the second pipeline executes instructions in a common issue group in a delayed manner relative to the first pipeline. The method further includes determining if a first instruction being executed in the first pipeline modifies data in a data register which is accessed by a second instruction being executed in the second pipeline. If the first instruction being executed in the first pipeline modifies data in the data register which is accessed by the second instruction being executed in the second pipeline, the modified data is forwarded from the first pipeline to the second pipeline. | 2009-01-01 |
20090006820 | Issue Unit for Placing a Processor into a Gradual Slow Mode of Operation - An issue unit for placing a processor into a gradual slow down mode of operation is provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe. | 2009-01-01 |
20090006821 | APPARATUS, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PROCESSING INFORMATION BY CONTROLLING ARITHMETIC MODE - An HW arithmetic unit executes a predetermined arithmetic operation. An arithmetic-mode determining unit determines, based on an attribute or a content of data relating to processing that has requested the arithmetic operation, either a synchronous mode that executes the processing after waiting for completion of the arithmetic operation by an arithmetic circuit or an asynchronous mode that executes the processing without waiting for completion of the arithmetic operation by the arithmetic circuit, as an execution mode of the arithmetic operation. An arithmetic-process control unit controls the arithmetic operation by the arithmetic circuit according to the determined execution mode. | 2009-01-01 |
20090006822 | Device and Method for Adding and Subtracting Two Variables and a Constant - A method device and a method. The method includes fetching an instruction, decoding an instruction that includes an instruction type field, a first variable field, a second variable field, a result field and a constant field; selecting an operation out of addition operation, a subtraction operation and another type of operation, in response to the content of the instruction type field; determining, in response to the value of the constant field, whether the result of the selected operation is responsive to the first and second variables or is responsive to the first variable, the second variable and the constant; and executing the selected operation, during a single instruction execution cycle, to provide the result. | 2009-01-01 |
20090006823 | DESIGN STRUCTURE FOR SINGLE HOT FORWARD INTERCONNECT SCHEME FOR DELAYED EXECUTION PIPELINES - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for forwarding data in a processor is provided. The design structure includes a processor. The processor includes at least one cascaded delayed execution pipeline unit having a first and second pipeline, wherein the second pipeline is configured to execute instructions in a common issue group in a delayed manner relative to the first pipeline, and circuitry. The circuitry is configured to determine if a first instruction being executed in the first pipeline modifies data in a data register which is accessed by a second instruction being executed in the second pipeline, and if the first instruction being executed in the first pipeline modifies data in the data register which is accessed by the second instruction being executed in the second pipeline, forward the modified data from the first pipeline to the second pipeline. | 2009-01-01 |
20090006824 | STRUCTURE FOR A CIRCUIT FUNCTION THAT IMPLEMENTS A LOAD WHEN RESERVATION LOST INSTRUCTION TO PERFORM CACHELINE POLLING - A design structure for a circuit function that implements a load when reservation lost instruction for performing cacheline polling is disclosed. Initially, a first process requests an action to be performed by a second process. The request is made via a store operation to a cacheable memory location. The first process then reads the cacheable memory location via a conditional load operation to determine whether or not the requested action has been completed by the second process, and the first process sets a reservation at the cacheable memory location if the requested action has not been completed by the second process. The conditional load operation of the first process is stalled until the reservation at the cacheable memory location has been lost. After the requested action has been completed, the reservation in the cacheable memory location is reset by the second process. | 2009-01-01 |
20090006825 | Method, Apparatus, and Computer Program Product in a Processor for Concurrently Sharing a Memory Controller Among a Tracing Process and Non-Tracing Processes Using a Programmable Variable Number of Shared Memory Write Buffers - A method, apparatus, and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data. | 2009-01-01 |
20090006826 | BRANCH PREDICTION METHODS AND DEVICES CAPABLE OF PREDICTING FIRST TAKEN BRANCH INSTRUCTION WITHIN PLURALITY OF FETCHED INSTRUCTIONS - A branch prediction method, capable of predicting a first taken branch instruction within a plurality of fetched instructions, includes: determining whether one of the fetched instructions is the first taken branch instruction to be predicted according to hint instruction(s) or according to latest statistics of whether respective fetched instructions have been taken. The branch prediction method further includes: if one of the fetched instructions is determined to be the first taken branch instruction, performing branch prediction on the first taken branch instruction. | 2009-01-01 |
20090006827 | Firmware Processing for Operating System Panic Data - A processor includes firmware and at least one instance of an operating system (OS). When the OS encounters an unrecoverable error (a “panic”), data regarding the error is pushed to the firmware via capsule services, rather than immediately being displayed to the screen via legacy video INT10h services. The panic data may be provided to the OS and displayed by the OS after a reset. Other embodiments are also described and claimed. | 2009-01-01 |
20090006828 | METHOD AND APPARATUS TO SIMPLIFY CONFIGURATION CALCULATION AND MANAGEMENT OF A PROCESSOR SYSTEM - Methods and apparatus to simplify configuration calculation and management of a processor system are disclosed. An example disclosed method reads system configuration data from registers of a processing system, caches the system configuration data in an allocated memory, and calculates new system configuration data for the processing system by operating on cached data. Other embodiments are also disclosed and claimed. | 2009-01-01 |
20090006829 | METHOD AND APPARATUS FOR CHANGING A CONFIGURATION OF A COMPUTING SYSTEM - Machine-readable media, methods, apparatus and system for caption detection are described. In some embodiments, during a non-quiesce state of a system, a configuration data for a configuration update of a configurable device of the system may be calculated, and it may be determined whether the configuration data is final configuration data or intermediate configuration data, wherein the final configuration data may be used to directly enact the configuration update during a quiesce state of the system, while the intermediate configuration data is used to indirectly enact the configuration update during the quiesce state of the system. Further, during the non-quiesce state of the system, if the configuration data is the intermediate configuration data, then codes associated with the configuration data may be determined, wherein the codes may be used to operate the configuration data to obtain the final configuration data during the quiesce state of the system. | 2009-01-01 |
20090006830 | ENCRYPTION ACCELERATION - The subject mater herein relates to data processing and, more particularly, to encryption acceleration. Various embodiments herein provide devices and systems including a standardized encryption application programming interface embedded in firmware to perform encryption services. Some such embodiments move encryption operations away from operating system processes into firmware. As a result, encryption operations are generally accelerated. | 2009-01-01 |
20090006831 | METHODS AND APPARATUSES FOR CONFIGURING ADD-ON HARDWARE TO A COMPUTING PLATFORM - In one embodiment a method is disclosed for adding hardware device to a computing platform and configuring the newly installed hardware device. The method may include coupling hardware device to a computing platform, where the hardware device has memory and the computing platform has memory. The operating system of the computing platform may be detected by the hardware device and the platform may download and execute code stored by the hardware device to and in response to the executed code the computing platform may locate a source for a download of driver information for the added hardware. Other embodiments are also described. | 2009-01-01 |
20090006832 | Method and System for linking Firmware Modules in a Pre-Memory Execution Environment - A BIOS includes a core and multiple modules. The modules include both those that are platform specific and those that are not platform specific. Each module has a standard interface that allows the core (or other module) to call the module. A platform vendor constructs a BIOS by selecting modules from one or more vendors, which when executed can select modules that are suitable for the platform the BIOS resides in. | 2009-01-01 |
20090006833 | IMAGE FORMING APPARATUS - An image forming apparatus includes: a hardware resource used in image formation; and a storage unit storing a program for processing the image formation; and a controller that is operable to: accepting rebooting commands for rebooting the hardware resource and the program; monitoring a state of the hardware resource and a state of the program and detecting whether or not at least one of the hardware resource and the program is in automatic adjustment processing; and rebooting the hardware resource and the program according to the rebooting commands after completion of the automatic adjustment processing, when the rebooting commands are accepted in a state that the hardware resource or the program is in the automatic adjustment processing. | 2009-01-01 |
20090006834 | PROXIED FIRMWARE UPDATES - The subject mater herein relates to computing systems and, more particularly, to proxied firmware updates. Some embodiments provide one or more of systems, methods, software, and firmware that, upon receiving a source of power, initialize an out-of-band controller that, may initialize a network interface to facilitate communication by the out-of-band controller with network resources and receive a firmware update payload from a remote network source over the network interface. These, and other embodiments may also include powering on a computing system including a BIOS and initializing at least a portion of the BIOS. If the computing system supports proxied firmware updates and a firmware update exists in a memory, such embodiments retrieve the payload and launching the payload to implement the firmware update. | 2009-01-01 |
20090006835 | ELECTRONIC DEVICE AND CONTROL METHOD THEREOF - An electronic device is disclosed. The electronic device includes a storage unit in which execution codes including a boot code and an application code are stored, a main memory in which the boot code is loaded, a CPU which performs booting by executing the boot code loaded in the main memory, and executes the application code; and a controller which reads the boot code of the execution codes, loads the boot code to the main memory, and controls the CPU to perform booting if it is determined that the boot code is completely loaded. | 2009-01-01 |
20090006836 | Information Processing Unit For Automatically Copying System Information - An information processing unit is provided, which includes a first memory, a second memory, and a controller. The first memory stores a BIOS program beforehand that is executed at a startup of the unit so as to allow peripheral devices to operate normally. The first memory also stores initial BIOS data beforehand. The second memory stores BIOS data with which the BIOS program is executed. The controller is configured to: (a) if the initial BIOS data is updated, read the updated BIOS data including updated data from the first memory and writes the updated BIOS data into the second memory; and (b) execute the BIOS program using the updated BIOS data written in the second memory. | 2009-01-01 |
20090006837 | METHOD AND APPARATUS FOR IMPROVED MEMORY RELIABILITY, AVAILABILITY AND SERVICEABILITY - Methods and apparatus dynamically reconfigure storage or channel capacities in a memory system. A fully-buffered dual in-line memory module (DIMM) is configured for a particular storage capacity and a particular channel capacity. An error may be detected at a memory address in some portion of the DIMM. To resolve the problem, the storage capacity or the channel capacity may be reduced and the DIMM may be dynamically reconfigured according to the reduced capacity. For one embodiment the DIMM may be reconfigured by mapping the portion of the DIMM containing the error as unavailable and taking that portion off-line without taking the entire DIMM off-line. For another embodiment the DIMM may be reconfigured by throttling the DIMM at a reduced frequency. The portion of the DIMM containing the error may be retested at the reduced frequency. If no errors are detected, the DIMM may be made available at the reduced frequency. | 2009-01-01 |
20090006838 | Methods for Downloading a Digital Work Automatically Bound with Characteristics of a Portable Device - Disclosed is a method for downloading a digital work automatically bound with characteristics of a portable device, which refers to a technology of digital rights protection using an embodied system. The method achieves convenient and safe binding of digital works for a portable device. A storage space of the portable device stores digital contents and an executable program which is executed automatically after the portable device is connected to a network terminal. By this method, copyright-protected digital contents can be purchased or borrowed, and downloaded to the portable device. | 2009-01-01 |
20090006839 | Communication device, communication log transmitting method suitable for communication device, and communication system - A communication device collects encrypted packet data passing through the communication device. The communication device extracts parameters required to generate a decryption key used when the collected packet data is decrypted. The communication device notifies a key managing device of the extracted parameters. The communication device acquires the decryption key, generated by the key managing device using the parameters of which notification has been given, from the key managing device. The communication device decrypts the collected packet data using the acquired decryption key and analyzes the decrypted packet data. The communication device extracts profile information from the analyzed packet data. The communication device transmits the extracted profile information and network information related to a network through which the encrypted packet data passes to a communication log device as a communication log. | 2009-01-01 |
20090006840 | Using an identity-based communication layer for computing device communication - A computer architecture for enterprise device applications provides a real-time, bi-directional communication layer for device communication. An identity-based communications layer provides for secure, end-to-end telemetry and control communications by enabling mutual authentication and encryption between the devices and the enterprise. The identity-based communications layer is situated between a network layer and an application layer and transmits a message between two devices identified by a global address. The global address specifies a protocol, a network, and an address meaningful for the combination of the protocol and the network. | 2009-01-01 |
20090006841 | SYSTEM AND METHOD FOR TESTING NETWORK FIREWALL FOR DENIAL-OF-SERVICE (DOS) DETECTION AND PREVENTION IN SIGNALING CHANNEL - A device may measure a first performance, associated with legitimate traffic without attack traffic, of a Session Initiation Protocol (SIP)-based protection device implementing authentication; measure a second performance, associated with legitimate traffic and attack traffic, of the SIP-based protection device implementing authentication; and measure a third performance, associated with legitimate traffic and attack traffic, of the SIP-based protection device implementing authentication and return routability filtering. The device may also measure a first performance associated with legitimate traffic of a Session Initiation Protocol (SIP)-based protection device implementing rate-limiting filtering; measure a second performance associated with legitimate traffic and attack traffic of the SIP-based protection device implementing scheme filtering; and measure a third performance associated with legitimate traffic of the SIP-based protection device not implementing rate-limiting filtering without attack traffic. | 2009-01-01 |
20090006842 | Sealing Electronic Data Associated With Multiple Electronic Documents - The description generally provides for systems and methods for a mobile communication network. Archives of seals can be sealed to protect the integrity of the seals and facilitate validation in the event a sealing party's sealed registration document is revoked. A document can be sealed multiple times to nest seals within other seals. Specific evidentiary metadata can be included by the sealing party. A main document including or associated with other documents can be sealed as a collection of documents. The seal of the main document can include external references to the files included in the main document to verify the external files were not changed or altered. | 2009-01-01 |
20090006843 | METHOD AND SYSTEM FOR PROVIDING A TRUSTED PLATFORM MODULE IN A HYPERVISOR ENVIRONMENT - A method is presented for implementing a trusted computing environment within a data processing system. A hypervisor is initialized within the data processing system, and the hypervisor supervises a plurality of logical, partitionable, runtime environments within the data processing system. The hypervisor reserves a logical partition for a hypervisor-based trusted platform module (TPM) and presents the hypervisor-based trusted platform module to other logical partitions as a virtual device via a device interface. Each time that the hypervisor creates a logical partition within the data processing system, the hypervisor also instantiates a logical TPM within the reserved partition such that the logical TPM is anchored to the hypervisor-based TPM. The hypervisor manages multiple logical TPM's within the reserved partition such that each logical TPM is uniquely associated with a logical partition. | 2009-01-01 |
20090006844 | VERIFYING CRYPTOGRAPHIC IDENTITY DURING MEDIA SESSION INITIALIZATION - An authentication agent may cryptographically identify a remote endpoint that sent a media initialization message even though intermediate devices may modify certain fields in the message after a signature is inserted. The originating endpoint's agent may create the signature over some fields of the message using an enterprise network's private key. The agent may insert the signature into the message and send the message to a recipient endpoint's authentication agent. The recipient agent may verify the signature, receive a certificate including a second public key, and challenge the identity of the originating endpoint in order to confirm that identity. This challenge may request a confirmation that the originating endpoint knows the private key corresponding to the second public key and may occur while running encrypted media at the endpoints. After the originating endpoint is authenticated, the endpoints may exchange encrypted and/or unencrypted media. | 2009-01-01 |
20090006845 | Management of Secure Access to a Secure Digital Content in a Portable Communicating Object - The invention concerns a terminal (T) comprising an agent (AS) for processing a secure content encrypted with a key (KCN) and transmitted by a first server (SCN). In order to manage a secure access to the secure content, an application (AG) of a portable communicating object, such as a chip card, associated with a terminal stores one type of related digital right (TDN) and a certificate and transmitted by the agent and stores an access right (DA) and the key (KCN) related to the secure content transmitted from a second server (SAD). The application adapts the access right and the key and modifies the secure content, based on the type of right, and produces a secure access file based on the adapted access right and the key and on the certificate, the produced file being accessible by the terminal so that the agent may process the modified content. | 2009-01-01 |
20090006846 | Bluetooth device as security access key - This application is directed to a system for remotely directing a host device to perform an operation using a key. The key may include a communications circuitry for transmitting data, for example a key identifier or an instruction to perform an operation, within a personal area network created by the communications circuitry. When a host device is within the personal area network, the key may transmit data received by a transceiver on the host device. In response to receiving the data, the host device may perform an operation (e.g., an authentication operation). In some embodiments, the key may transmit data identifying an operation for the host device to perform. In some embodiments, the host device may store in memory key identification information and an associated operation which may be retrieved when the key is brought in proximity of the host device. | 2009-01-01 |
20090006847 | Filtering kernel-mode network communications - Some embodiments of the invention are directed to techniques for determining whether a process on a computer system that is sending or receiving data, or is attempting to send or receive data, with another computer system is executing in kernel mode or user mode and providing an indicator of this determination to a security engine. In some embodiments, such an indication is provided to a security engine (e.g., a firewall) that implements a security policy based at least in part on whether the sending or receiving process is in kernel mode or user mode, and filter communications based on a process' operating mode. This enables a security engine to maintain security policies of greater specificity and thus improve security of a computer system. | 2009-01-01 |
20090006848 | Secure credential management - Apparatus and methods associated with providing secure credential management are described. One apparatus embodiment includes a data store to store authentication data and an authentication supplicant (AS) logic to provide a response to an authentication communication (ACM) received from an authentication process. An authentication management (AM) logic may receive the ACM from a connection management (CM) logic associated with a host operating system (HOS), provide the ACM to the AS logic, and provide the response back to the CM logic. The apparatus may include a device management (DM) client logic to provide a secure connection to an operator DM server associated with the authentication process and to store authentication data provided by the operator DM server in the data store. The AS logic, AM logic, and DM logic may reside in firmware that is not accessible to the HOS. | 2009-01-01 |
20090006849 | PEER-TO-PEER NAME RESOLUTION PROTOCOL (PNRP) SECURITY INFRASTRUCTURE AND METHOD - A security infrastructure and methods are presented that inhibit the ability of a malicious node from disrupting the normal operations of a peer-to-peer network. The methods of the invention allow both secure and insecure identities to be used by nodes by making them self-verifying. When necessary or opportunistic, ID ownership is validated by piggybacking the validation on existing messages. The probability of connecting initially to a malicious node is reduced by randomly selecting to which node to connect. Further, information from malicious nodes is identified and can be disregarded by maintaining information about prior communications that will require a future response. Denial of service attacks are inhibited by allowing the node to disregard requests when its resource utilization exceeds a predetermined limit. The ability for a malicious node to remove a valid node is reduced by requiring that revocation certificates be signed by the node to be removed. | 2009-01-01 |
20090006850 | Computer system for authenticating a computing device - A computer architecture for enterprise device applications provides a real-time, bi-directional communication layer for device communication. An identity-based communications layer provides for secure, end-to-end telemetry and control communications by enabling mutual authentication and encryption between the devices and the enterprise. A unique identity is assigned to each device, user and application to provide security services. A communications session is established between two devices using an authentication service that authenticates the device that is initiating the establishment of the communications session with another device. After authenticating the initiating device, the authentication service provides to the initiating device the network address of the other device and an authentication credential for use in the communications session between the initiating device and the other device. | 2009-01-01 |
20090006851 | CONFIDENTIAL MAIL WITH TRACKING AND AUTHENTICATION - A method for confidential electronic communication between a sender workstation and a receiver workstation is provided, whereby privacy is guaranteed for the electronic communications transmitted over the public Internet. The method of confidential communication is equipped with message tracking and message receipt verification. The system for implementing the method includes a sender server that creates a session content encryption key along with a message envelope that includes a content encryption key encrypted message and a confidential mail token. The content encryption key is stored securely inside the sender organization's system which transmits the message envelope to an intended recipient. The intended recipient processes the message envelope in order to generate a message receipt verification, which is transmitted to the sender. The message receipt verification is processed by the sender server to verify that the message envelope reached the intended recipient. The message receipt verification, which is comprised of the confidential mail token and unique verification data generated by the intended recipient allows the sender server to verify that the message envelope reached the intended receiver and that the message envelope identified as received is authentic. Following verification that the message transmitted by the sender reached the intended receiver and is authorized, the sender transmits the content encryption key to the intended receiver. | 2009-01-01 |
20090006852 | Method and Apparatus for Securing Unlock Password Generation and Distribution - A process may be utilized for securing unlock password generation and distribution. A first set of exclusive responsibilities, assigned to a trusted authority, includes random generation and encryption of an unlock password to compose a randomly generated encrypted unlock password. Further, a second set of exclusive responsibilities, assigned to a security agent, includes sending information associated with the unlock password and a digital signature of information associated with the unlock password to a communication device configured for a network in order to mate the unlock password to the communication device, and sending the randomly generated and encrypted unlock password along with mating data to a password processing center. In addition, a third set of exclusive responsibilities, assigned to a password processing center, includes decrypting the randomly generated and encrypted unlock password. | 2009-01-01 |
20090006853 | Security protocols for hybrid peer-to-peer file sharing networks - In a hybrid peer-to-peer file sharing network including a receiver peer and a provider peer, the receiver sends the provider a ticket [ | 2009-01-01 |
20090006854 | Secure time source operations for digital rights management - Various embodiments utilize hardware-enforced boundaries to provide various aspects of digital rights management or DRM in an open computing environment. Against the backdrop of these hardware-enforced boundaries, DRM provisioning techniques are employed to provision such things as keys and DRM software code in a secure and robust way. Further, at least some embodiments utilize secure time provisioning techniques to provision time to the computing environment, as well as techniques that provide for robustly secure storage. | 2009-01-01 |
20090006855 | Securely Computing a Similarity Measure - The present invention relates to a method and a system of securely computing a measure of similarity for at least two sets of data. A basic idea of the present invention is to securely compare two sets of encrypted data to determine whether the two sets of data resemble each other to a sufficient extent. If the measure of similarity complies with predetermined criteria, the two sets of data from which the encrypted sets of data originate are considered to be identical. | 2009-01-01 |
20090006856 | ADAPTIVE AUTHENTICATION SOLUTION THAT REWARDS ALMOST CORRECT PASSWORDS AND THAT SIMULATES ACCESS FOR INCORRECT PASSWORDS - In the invention, incorrect authentication information for accessing at least one secured computing asset can be received. A similarity score between the incorrect authentication information and correct authentication information can be determined. One of many different access levels can be assigned to a computing session based upon the similarity score. Access consistent with the assigned access level can be granted. One access level can be an emulation access level that grants access to at least one simulated asset designed to mimic the secured asset. Access to the simulated asset can be provided in a fashion so that a user, who is likely an intruder, is unaware that they are not receiving the secured asset information. A tracking action can he optionally initiated against the intruder. Further, user behavior with the simulated session or a limited access session can be compared against a behavior profile to dynamically increase or decrease session permissions. | 2009-01-01 |
20090006857 | METHOD AND APPARATUS FOR STARTING UP A COMPUTING SYSTEM - A computer system may be powered up or awakened from a power-saving state with one single user action. An authentication device may be used to detect a user action and to collect data from the user action. An authentication module may be used to authenticate a user based on the data collected by the authentication device. A controller may enable a user to access a non-volatile storage medium for user credentials necessary to power up or awaken the computer system. | 2009-01-01 |
20090006858 | Secure seed provisioning - A method is used for secure seed provisioning. Data is derived from inherent randomness in an authentication device. Based on the data, the authentication device is provisioned with a seed. | 2009-01-01 |
20090006859 | SYSTEM AND METHOD FOR OUT-OF-BAND ASSISTED BIOMETRIC SECURE BOOT - In some embodiments, the invention involves using a dedicated service processor with out-of-band capabilities to enable a secure boot using biometric data to authenticate the user. In some embodiments, at least a secondary token is used enhance the secure boot. An off-line database may be accessed by the service processor during boot to store or retrieve biometric templates to compare with scanned, live, biometric data. Other embodiments are described and claimed. | 2009-01-01 |
20090006860 | GENERATING MULTIPLE SEALS FOR ELECTRONIC DATA - The description generally provides for systems and methods for a mobile communication network. Archives of seals can be sealed to protect the integrity of the seals and facilitate validation in the event a sealing party's sealed registration document is revoked. A document can be sealed multiple times to nest seals within other seals. Specific evidentiary metadata can be included by the sealing party. A main document including or associated with other documents can be sealed as a collection of documents. The seal of the main document can include external references to the files included in the main document to verify the external files were not changed or altered. | 2009-01-01 |
20090006861 | Method and Apparatus for Preventing Internet Phishing Attacks - The invention provides secure access to a web page using a personal pass-phrase to prevent phishing attacks. Upon requesting a web page from a user device, a determination is made as to whether or not an encrypted cookie exists for the requested web page. An encrypted cookie includes the personal pass-phrase and at least one of an identifier of the user device, an identifier of a web browser from which the web page request is initiated, and information about the network path used to establish the personal pass-phrase. If an encrypted cookie does not exist, the user is provided a capability to create the encrypted cookie including a personal pass-phrase. If the encrypted cookie exists, the user device provides the encrypted cookie with the web page request for use by the web server to validate the web page request using information included in the encrypted cookie. If the web page request is valid, the web server propagates the web page toward the user device, otherwise the user device receives an indication that the web server is invalid. | 2009-01-01 |
20090006862 | Provisioning a computing system for digital rights management - Various embodiments utilize hardware-enforced boundaries to provide various aspects of digital rights management or DRM in an open computing environment. Against the backdrop of these hardware-enforced boundaries, DRM provisioning techniques are employed to provision such things as keys and DRM software code in a secure and robust way. Further, at least some embodiments utilize secure time provisioning techniques to provision time to the computing environment, as well as techniques that provide for tamper-resistant storage. | 2009-01-01 |
20090006863 | Storage system comprising encryption function and data guarantee method - This storage system includes a host computer for issuing a read command or a write command of data, a pair of logical volumes corresponding to a pair of virtual devices to be recognized by the host computer, and a device interposed between the host computer and the pair of logical volumes and having a function of encrypting and decrypting data. The storage system additionally includes a path management unit for specifying one path to each of the logical volumes from a plurality of data transfer paths between the host computer and the pair of logical volumes for transferring encrypted data or decrypted data which was encrypted or decrypted via the device with data encryption or decryption function based on a read command or a write command of data from the host computer. | 2009-01-01 |
20090006864 | MICROPROCESSOR WITH IMPROVED TASK MANAGEMENT AND TABLE MANAGEMENT MECHANISM - A tamper resistant microprocessor has a task state table for assigning a task identifier to a task that can take a plurality of states, and storing a state of the task in correspondence to the task identifier; a task register for storing the task identifier of a currently executed task; an interface for reading a program stored in a form encrypted by using a program key at an external memory, in units of cache lines, when a request for the task is made; an encryption processing unit for generating decryption keys that are different for different cache lines, according to the program key, and decrypt a content read by the interface; a cache memory formed by a plurality of cache lines each having a tag, for storing the task identifier corresponding to a decryption key used in decrypting each cache line in the tag of each cache line; and an access check unit for comparing the task identifier stored in the tag of each cache line with a value of the task register, and discarding a content of each cache line when the task identifier in the tag and the value of the task register do not coincide. | 2009-01-01 |
20090006865 | Efficient Remotely-Keyed Symmetric Cryptography For Digital Rights Management - An efficient symmetrical-cryptographic method for using a fast but insecure host to perform encryption/decryption based on a secret key in a secure, but slow hardware token, such as a smartcard or similar device, without revealing the secret key to the host, and such that the ciphertext and plaintext are exactly the same size. The present method is suitable for use in Digital Rights Management and Software Rights Management applications which require precise interchangeability of ciphertext and plaintext in pre-allocated areas of data storage. | 2009-01-01 |
20090006866 | STORAGE APPARATUS, MEMORY CARD ACCESSING APPARATUS AND METHOD OF READING/WRITING THE SAME - A storage apparatus having a non-volatile memory and a controller is provided, wherein the non-volatile memory includes a root directory area and a data area, and a password file is stored in the root directory area. The controller identifies a user by using a password in the password file, and the user can access the data area through an encryption/decryption unit of the controller only if the user passes the identification. By using the secured storage apparatus, the risk of the password and encrypted data being cracked is reduced. Accordingly, the protection over the data stored in the storage apparatus is enhanced. | 2009-01-01 |
20090006867 | System, device and method for providing data availability for lost/stolen portable communication devices - A system, device and method for providing data availability for a portable communication device, including various combinations of the following steps: notifying an operator that the portable communication device is missing; triggering encryption of data on the portable communication device; sending a data retrieval command to the portable communication device; authenticating the data retrieval command; retrieving data from the portable communication device; identifying a portion of the data retrieved from the portable communication device that is confidential; encrypting the identified confidential data on the portable communication device; and erasing the identified confidential data from the portable communication device or recovering the portable communication device and decrypting the confidential data on the portable communication device. | 2009-01-01 |
20090006868 | Secure storage for digital rights management - Various embodiments utilize hardware-enforced boundaries to provide various aspects of digital rights management or DRM in an open computing environment. Against the backdrop of these hardware-enforced boundaries, DRM provisioning techniques are employed to provision such things as keys and DRM software code in a secure and robust way. Further, at least some embodiments utilize secure time provisioning techniques to provision time to the computing environment, as well as techniques that provide for robustly secure storage. | 2009-01-01 |
20090006869 | Techniques for synchronizing and archive-versioning of encrypted files - Techniques are presented for synchronizing and archive-versioning encrypted files. Blocks of encrypted data are managed and metadata is maintained for the blocks. The metadata identifies a maximum number of blocks and an index or parameter string. The string includes transaction identifiers and relative block numbers. The metadata is used as parameter information to a hash algorithm along with a hash key to acquire a unique initialization vector for each block. Each initialization vector when supplied to a cipher service along with a particular block of data produces an encrypted version of the data supplied or supplies a decrypted version of the data supplied. The techniques are also applied to files being archived and versioned from a storage volume. | 2009-01-01 |
20090006870 | METHOD, SYSTEM, AND APPARATUS FOR DYNAMIC DATA-DRIVEN PRIVACY POLICY PROTECTION AND DATA SHARING - A method of sharing telematics data for a vehicle with service providers can include receiving the telematics data for the vehicle, where the telematics data dynamically changes over time, and comparing the telematics data with a privacy policy associated with the vehicle. The privacy policy can specify rules for selectively releasing items of the telematics data to one or more service providers. Data items of the telematics data can be selectively provided to the service providers according to the comparing step. | 2009-01-01 |
20090006871 | METHOD, SYSTEM, AND APPARATUS FOR A CORE ACTIVITY DETECTOR TO FACILITATE DYNAMIC POWER MANAGEMENT IN A DISTRIBUTED SYSTEM - A system and method to provide source controlled dynamic power management. An activity detector in a source determines expected future resource usage. Based on that expected usage, the source generates a power management command and sends that command to a destination. The destination then adjusts the power level of the resource based in the command. | 2009-01-01 |
20090006872 | REPRODUCER AND REPRODUCING METHOD - According to one embodiment, an acquiring unit for acquiring content information and a playlist of the content information, processing units for processing the content information by a plurality of processing modules supplied with power to function, and managing units for managing power delivery to the plurality of processing modules based upon the playlist, respectively, are included. | 2009-01-01 |
20090006873 | POWER THROTTLING OF COLLECTIONS OF COMPUTING ELEMENTS - An apparatus and method for controlling power usage in a computer includes a plurality of computers communicating with a local control device, and a power source supplying power to the local control device and the computer. A plurality of sensors communicate with the computer for ascertaining power usage of the computer, and a system control device communicates with the computer for controlling power usage of the computer. | 2009-01-01 |
20090006874 | INFORMATION PROCESSING APPARATUS - According to one embodiment, an information processing apparatus includes: an information processing apparatus main body receiving a supply of power from power supplies disposed at outside or inside; one or a plurality of connection connectors constituted to be able to attach/detach an external apparatus, and having at least one signal terminal transmitting/receiving signals between the information processing apparatus main body and the external apparatus and at least one power terminal supplying the power from the power supplies to the external apparatus; a power supply state changing portion having a switch provided between the power supply and the power terminal, and capable of changing the switch to either one of a connection state or a non-connection state; and a power supply state control portion having user setting information set by a user concerning a control method of the power supply state changing portion, and performing a control to change the switch to either one of the connection state or the non-connection state in accordance with the user setting information at a non-operation time of the information processing apparatus main body. | 2009-01-01 |
20090006875 | Media Device Power Conservation - Power is dynamically conserved in a device by analyzing past processing performance of the device and predicting the amount of power required for future execution. In an example embodiment, a video frame is analyzed to determine what portion of the video frame was needed to render data. If less than the full video frame was needed, at least one power conservation technique is applied to the device for subsequent rendering of data. Power conservation techniques include adjusting the operating frequency of circuitry utilized to render data, adjusting the voltage applied to circuitry utilized to render data, and/or turning off/on circuitry utilized to render data. | 2009-01-01 |
20090006876 | STORAGE SYSTEM COMPRISING FUNCTION FOR REDUCING POWER CONSUMPTION - For at least one of storage unit, processor and cache memory which are I/O process-participating devices related to I/O command process, when a load of one or more I/O process-participating devices or a part thereof is a low load equal to or less than a predetermined threshold value, a processing related to a state of one or more of the I/O process-participating devices or a part thereof is redirected to another one or more I/O process-participating devices or a part thereof, and the state of the one or more I/O process-participating devices or a part thereof is shifted to a power-saving state. | 2009-01-01 |
20090006877 | POWER MANAGEMENT IN A STORAGE ARRAY - A data storage system and associated method is provided within an enclosure supporting a self-contained plurality of discrete data storage devices configured for connecting with a network device via a network. The data storage system includes a redundant array of independent drives (RAID) container services module in the enclosure that allocates and manages a storage space of the data storage devices for storing primary and redundant data, and a policy engine in the enclosure that continuously and qualitatively characterizes the network load to the data storage system and manages a power distribution to each of the data storage devices based on a predicted utilization that differentiates between access commands for primary data and access commands for redundant data. | 2009-01-01 |
20090006878 | METHOD AND SYSTEM FOR MONITORING SYSTEM PROCESSES ENERGY CONSUMPTION - A method and system for monitoring power consumption of software applications. In a preferred embodiment of the present invention a new feature is inserted in a system availability monitoring product which estimates the power consumption of the system, starting from the measurement of some parameters collected by a Monitoring tool. All systems are impacted by energy consumption, by the usage of its resources (hard-disk, CPU, memory, CDROM, etc.); when the usage of these components increases, the energy consumption increases too. The usage of the resources can be calculated through Monitoring tool according to some specific parameters. The calculated metrics of the usage are based on the measurement of the time during which a resource is in a predetermined status. Each resource has an associated table, determining the expected power consumption according to the status. | 2009-01-01 |
20090006879 | Session Redundancy Using a Replay Model - A mechanism for synchronizing states of components in a first routing engine to corresponding components in a second routing engine is provided. In order to reduce the amount of data required to synchronize the state of the components and the time and resources required to perform the synchronization, the state-related information transmitted from the first routing engine to the second routing engine is limited to information used to build states of a subset of the components associated with the first routing engine. That subset of components is limited to those components that receive stimuli (e.g., data streams or data packets) from sources external to the routing engine. Other components on the second routing engine synchronize state by receiving information from those components on the second routing engine that received the external stimuli information. | 2009-01-01 |
20090006880 | SYSTEM AND METHOD FOR POWER SAVING DELAY LOCKED LOOP CONTROL - The delay locked loop (“DLL”) delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL is associated to the system clock. This is achieved by adding logic sensing when a DRAM device will not imminently be called upon to output data and when the device has stabilized. Waiting for the DLL delay interval to stabilize before locking the delay interval still allows the DLL to immediately and effectively resume operations when the DLL is needed to synchronize the output of the DRAM device with the system clock. The DLL delay interval can be locked, together with the DLL clock, after the DRAM device is deselected by the chip select control line, after a number of no operation commands have been received, and/or after any command issued to the DRAM device has been completed. | 2009-01-01 |
20090006881 | Data fetch circuit, data fetch system and control method of the data fetch circuit - To provide a data fetch circuit, which reliably cuts off transmission of a high impedance state of a data strobe signal even if a manufacture condition or an operation condition is changed, and a control method thereof. The data fetch circuit includes an RL measuring part | 2009-01-01 |
20090006882 | Method and Apparatus for Wireless Clock Regeneration - Methods and systems for operating a wireless clock system for multimedia datastream transmission and display. Source clock frames are compared with a reference clock frames and the clock difference are transmitted to a wireless clock receiver which also receives the same reference clock frames. Source clock frames are re-constructed using the reference clock frames, clock difference information and the receiver's local clock system. | 2009-01-01 |
20090006883 | Software error report analysis - Described herein is technology for, among other things, accessing error report information. It involves various techniques and tools for analyzing and interrelating failure data contained in error reports and thereby facilitating developers to more easily and quickly solve programming bugs. Numerous parameters may also be specified for selecting and searching error reports. Several reliability metrics are provided to better track software reliability situations. The reliability metrics facilitate the tracking of the overall situation of failures that happen in the real word by providing metrics based on error reports (e.g., failure occurrence trends, failure distributions across different languages). | 2009-01-01 |
20090006884 | AUTOMATICALLY MANAGING SYSTEM DOWNTIME IN A COMPUTER NETWORK - Embodiments are provided to automatically managing system downtime in a computer network. In one embodiment, an event is created in an application server to schedule a system downtime period for a web server. When the scheduled downtime occurs, the web server is automatically removed from the network and a downtime notification message is automatically communicated indicating that the web server is offline. In another embodiment, events may be created to schedule downtime for web-based applications, including websites. Prior to the scheduled downtime, requests to a web-based application may be automatically stopped and redirected to a specified location. In another embodiment, the operation of web servers is automatically monitored to detect the presence of a fault condition and, if a fault condition is present, then a determination may be made that the affected web servers are down and requests to the down web servers are automatically redirected to an alternate server. | 2009-01-01 |
20090006885 | Heartbeat distribution that facilitates recovery in the event of a server failure during a user dialog - An exemplary method facilitates automatic recovery upon failure of a server in a network responsible for replying to user requests. Periodic heartbeat information is generated by a first group of servers responsible for replying to user requests. The heartbeat information provides an indication of the current operational functionality of the first group of servers. A second group of servers determines that one of the first servers has failed based on the periodic heartbeat information. The second group of servers is disposed in communication channels between users and the first group of servers. One of the second group of servers receives a message containing a request from a first user having the one of the first group of servers as a destination. One of the second group of servers determines that the message is part of an ongoing dialog of messages between the first user and the one of the first group of servers. Stored dialog information contained in previous communications between the first user and the one of the first group of servers associated with the ongoing dialog is retrieved. Another message is transmitted from the one of the second group of servers to another of the first group of servers. The another message includes the request contained in the message and the retrieved dialog information. This enables the another server to process the request based on the retrieved dialog information without requiring the first user to have to retransmit previously transmitted information that was part of the dialog information. | 2009-01-01 |
20090006886 | SYSTEM AND METHOD FOR ERROR CORRECTION AND DETECTION IN A MEMORY SYSTEM - A system and method for error correction and detection in a memory system. The system includes a memory controller, a plurality of memory modules and a mechanism. The memory modules are in communication with the memory controller and with a plurality of memory devices. The mechanism detects that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the memory device failure. | 2009-01-01 |
20090006887 | System and method for addressing errors in a multiple-chip memory device - A multiple-chip memory device, comprising: a volatile memory element configured to store a plurality of bits of information, and later access the plurality of bits of information; a non-volatile memory element configured to store initial repair information identifying one or more errors in the volatile memory element; and a master memory controller configured to read the initial repair information, and to provide processed repair information and volatile memory control signals to the volatile memory element, wherein the volatile memory element is configured to store and access the plurality of bits of information based on the processed repair information and logical address information. | 2009-01-01 |
20090006888 | Fast primary cluster recovery - A cluster recovery process is implemented across a set of distributed archives, where each individual archive is a storage cluster of preferably symmetric nodes. Each node of a cluster typically executes an instance of an application that provides object-based storage of fixed content data and associated metadata. According to the storage method, an association or “link” between a first cluster and a second cluster is first established to facilitate replication. The first cluster is sometimes referred to as a “primary” whereas the “second” cluster is sometimes referred to as a “replica.” Once the link is made, the first cluster's fixed content data and metadata are then replicated from the first cluster to the second cluster, preferably in a continuous manner. Upon a failure of the first cluster, however, a failover operation occurs, and clients of the first cluster are redirected to the second cluster. Upon repair or replacement of the first cluster (a “restore”), the repaired or replaced first cluster resumes authority for servicing the clients of the first cluster. This restore operation preferably occurs in two stages: a “fast recovery” stage that involves preferably “bulk” transfer of the first cluster metadata, following by a “fail back” stage that involves the transfer of the fixed content data. Upon receipt of the metadata from the second cluster, the repaired or replaced first cluster resumes authority for the clients irrespective of whether the fail back stage has completed or even begun. | 2009-01-01 |
20090006889 | I2C Failure Detection, Correction, and Masking - A method of operation of a computer system having a master and slave Inter-IC (I2C) bus network includes detecting and isolating an I2C bus failure, configuring a failed I2C bus as offline, reconfiguring a remaining I2C bus as a multi-mastered bus, and masking the failed I2C bus from operation until the failed I2C bus can be repaired. A first test request is sent to a remote device from a local device. If the remote device receives the first test request, a remote bus mode is switched to a failure position, a local bus mode is switched to a multi-master position, and a second request is sent to the remote device to indicate position changes. | 2009-01-01 |
20090006890 | Storage system and control method of storage system - Provided is a storage system superior in fault tolerance. This storage system is composed of a controller having a plurality of processors and other units. When an error occurs in any one of the components in the controller, the storage system cuts off an I/O path of the controller, specifies the failed component in the cutoff status, and invalidates such failed component. Further, after invalidating the failed component, the storage system determines whether it is operable only with the normal components, cancels (releases) the cutoff of the I/O path when it determines that it is operable, and resumes operation by rebooting itself. | 2009-01-01 |
20090006891 | Apparatus, System, and Method for Hard Disk Drive Redundancy - An apparatus, system, and method are disclosed for hard disk drive redundancy. A demarcation module demarks a parity data block in each set of a specified number of data blocks on a hard disk drive. An association module associates a PBA of each un-demarked data block with a LBA. A write module writes the data to the un-demarked data blocks. A parity module calculates parity data for the data written to the un-demarked data blocks and the write module writes the parity data to the parity data block. | 2009-01-01 |
20090006892 | METHOD AND SYSTEM TO DETECT ERRORS IN COMPUTER SYSTEMS BY USING STATE TRACKING - Disclosed are a method and system for detecting errors in a computer system including a processing unit to perform tasks to change items. The method comprises the steps of assigning a task control block to the processing unit, and using the task control block to keep track of items being changed by the processing unit. The method comprises the further steps of at defined times, checking the task control block to identify items being changed by the processing unit, and checking the states of said identified items to determine if those states are correct. The preferred embodiment of the invention detects an error when it arises (where possible), and utilizes an infrastructure that allows simple and periodic consistency checks (for example, at designated code points) that detect the error before it causes follow-on problems. | 2009-01-01 |
20090006893 | Information processing apparatus, diagnosis method, and computer program product - A logical central processing unit (logical CPU) selects a target device. When the target device is shared by another logical CPU, the logical CPU determines whether the logical CPU is in charge of exclusively making diagnosis of the target device. When the target device is not shared by another logical central processing unit or when the logical CPU is exclusively in charge of making diagnosis of the target device, the logical CPU makes diagnosis of the target device and stores a result of diagnosis in a storage unit. | 2009-01-01 |
20090006894 | METHOD AND APPARATUS TO DEBUG AN INTEGRATED CIRCUIT CHIP VIA SYNCHRONOUS CLOCK STOP AND SCAN - An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software. | 2009-01-01 |
20090006895 | Method for debugging reconfigurable architectures - A method is described for debugging reconfigurable hardware. In one example embodiment, debugging information is written for each configuration cycle into a memory which is then evaluated by a debugger. | 2009-01-01 |
20090006896 | Failure analysis apparatus - Relating with board numbers of the boards mounted with the logic circuits and mounted places on the boards and in relation to log information to be collected from the logic circuits, analysis information describing information to be processed when the log information is generated, information of a condition for which the log information is to be valid, and information of a condition for which the log information is to be invalid are defined for analyzing failures using the analysis information based on the logic circuits. Upon the realization of the failure analysis based on the logic circuits, the analysis information further describes information of the priority of the log information to realize a thorough analysis of critical failures. | 2009-01-01 |
20090006897 | AUTOMATED SERVICE TESTING - A service test case generation and execution system is provided that automatically generates one or more test cases for the service according to a service definition associated with the service. The service definition can specify one or more methods available in the service and/or one or more parameters for the methods. Additionally, sets or ranges of valid values can be specified for the parameters (such as in a web service description language (WSDL) definition). Test cases can be automatically generated based on this information, including specifying a plurality of valid and invalid input parameters, and automatically executed to provide testing of many code paths of a service. Output can also be measured in this regard. | 2009-01-01 |
20090006898 | TRANSMISSION OF GENERIC DIGITAL MESSAGES THROUGH A MICROPROCESSOR MONITORING CIRCUIT - Embodiments of the invention concern a method for transmitting digital messages through a microprocessor monitoring circuit of specific type and integrated to a microprocessor, each message including an identifier and consisting of several groups of successive and juxtaposed bits divided into segments. The method consists in successively transmitting segments associated with a first group corresponding to the identifier and comprising a fixed number of bits; with second groups, at least one of the second group comprising a fixed number of bits depending on the type of monitoring circuit, the number of other second groups being independent of the type of monitoring circuit; with a third group comprising a number of bits greater than one; and with fourth groups comprising each a number of bits greater than one, the number of fourth groups depending on the identifier and on the type of monitoring circuit. | 2009-01-01 |
20090006899 | ERROR CORRECTING CODE WITH CHIP KILL CAPABILITY AND POWER SAVING ENHANCEMENT - A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data. | 2009-01-01 |
20090006900 | SYSTEM AND METHOD FOR PROVIDING A HIGH FAULT TOLERANT MEMORY SYSTEM - A system and method for providing a high fault tolerant memory system. The system includes a memory system having a memory controller, a plurality of memory modules and a mechanism. The plurality of memory modules are in communication with the memory controller and with a plurality of memory devices. The plurality of memory devices include at least one spare memory device for providing memory device sparing capability. The mechanism is for detecting that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the possible memory device failure. | 2009-01-01 |
20090006901 | Control Systems and Method Using a Shared Component Actuator - In one embodiment, a control system supports an unlimited number of feedback control loops all sharing control of a component. A component performance rate or “speed” is used as a common metric for negotiating control of the component. Each control loop continuously monitors a system parameter it is tasked with regulating, compares it to a setpoint for that system parameter, and “requests” a speed in relation to the deviation of the associated system parameter from the corresponding setpoint. A controller receives the requested speeds as dynamic inputs and selects one of the requested speeds according to predefined selection logic. The controller communicates the selected speed to an actuator, which causes the component to operate at the selected speed. In this manner, the control system in effect negotiates control of the component in a way that ensures that all of the system parameters are being managed within safe limits. | 2009-01-01 |
20090006902 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR REPORTING FRU FAILURES IN STORAGE DEVICE ENCLOSURES - Monitoring a plurality of field-replaceable units (FRUs) in an enclosure using two or more microcontroller-equipped power supplies to detect an FRU failure. Upon detection of an FRU failure, a first signal indicative of the failure is communicated from at least one of the microcontroller-equipped power supplies to one or more small computer system interface (SCSI) repeaters over an I | 2009-01-01 |
20090006903 | Network Alarm Management - In a fault management system, a method and a converting unit for converting correlated sequences of network alarms into a high level language format are disclosed. The method comprises receiving episodic alarm sequence for the correlated sequences obtaining a high level language scheme, and converting the episodic alarm sequence using the accessed high level language scheme into a high level language format, to enable more efficient and reliable fault management using the converted episodic alarm sequence in high level language format. | 2009-01-01 |
20090006904 | APPARATUS AND METHOD TO CHECK DATA INTEGRITY WHEN HANDLING DATA - An apparatus and method to check integrity when handling data. The method provides a storage array which includes a plurality of sectors. The method defines (N) data state identifiers and (N) parity state identifiers. The method receives a command to handle data, where that command designates a target sector. The method determines the data state identifier assigned to the target sector, determines the parity state identifier assigned to the target sector, and compares the data state identifier and the parity state identifier. If the method determines that the data state identifier and the parity state identifier are the same, the method performs the command to handle data. Alternatively, if the method determines that the data state identifier and the parity state identifier differ, the method generates an error message. | 2009-01-01 |
20090006905 | In Situ Register State Error Recovery and Restart Mechanism - Embodiments of the invention relate to methods and systems for error detection and recovery from errors during pipelined execution of data. A cascaded, delayed execution pipeline may be implemented to maintain a precise machine state. In some embodiments, a delay of one or more clock cycles may be inserted prior to a write back stage of each pipeline to facilitate error detection and recovery. Because a precise machine state is maintained error detection and recovery mechanisms may be built directly into register files of the system. If an error is detected execution of the instruction associated with the error and all subsequent instructions may be restarted. | 2009-01-01 |
20090006906 | Method and system for encoding data using rate-compatible irregular LDPC codes based on edge growth and parity splitting - In a system for parity encoding data using a low density parity check (LDPC) code, a rate-compatible, irregular LDPC code is generated by extending a base code using a constrained edge growth operation and a parity splitting operation. The base code is a “daughter” code having an encoding rate higher than a designated rate of the LDPC code. The daughter code is progressively extended to lower and lower rates such that each extension code (including the target LDPC code) is compatible with the previously obtained codes. The extension operation may involve introducing a set of new code symbols to the daughter code, by splitting check nodes of a base graph associated with the daughter code, and through constrained edge growth of the base graph. The LDPC code is used to parity encode a data message as a means for forward error correction across a communication channel. | 2009-01-01 |
20090006907 | METHOD AND APPARATUS FOR IDENTIFICATION OF PROGRAM CHECK ERRORS INDICATING CODE WITH HIGH POTENTIAL FOR STORAGE OVERLAY - In a data processing system, in order to provide its operating system with a better mechanism to identify and track addressing errors with a high potential to cause a storage overlay, it is first determined whether or not, a program interrupt has occurred. It is next determined whether or not this interrupt involves or occurs as a result of an address translation. It is then determined whether or not, the instruction involved calls for an update of storage. If it is determined that all three of these conditions are satisfied, then a flag is set in an area of storage accessible to the operating system so that it may provide a more specific event monitoring record. | 2009-01-01 |
20090006908 | SYSTEM AND METHOD FOR FAULT MAPPING OF EXCEPTIONS ACROSS PROGRAMMING MODELS - A system and method for mapping exceptions from a first programming model to a second programming model is disclosed. The system comprises a first device operating a first programming model and a second device operating a second programming model. The first device sends an instruction to, or invokes the second device to execute an instruction. As a result, a fault occurs during execution of the instruction in the second programming model. An exception based on the fault is raised, and returned to the first device. The system further comprises a fault mapping module configured to receive the exception from the first device. The fault mapping module attempts to determine the type of exception received. This determination may be accomplished by comparing an identifier within the exception with one or more predetermined identifiers that indicate exception type. The fault mapping module is also configured to interpret the exception according to a set of mapping data to generate an interpreted exception recognizable by the first programming model if the exception is determined to be of a predetermined type. | 2009-01-01 |
20090006909 | Methods and apparatus for event logging in an information network - Methods and apparatus for logging, analysis, and reporting of events such as reboots in a client device (e.g., consumer premises equipment in a cable network) using applications. In one aspect, an improved event logging and monitoring system is provided within the device with which the application(s) can interface to record event or error data. In one exemplary embodiment, the client device comprises a digital set-top box having Java-enabled middleware adapted to implement the various functional aspects of the event logging system, which registers to receive event notifications (including resource exhaustion data) from other applications running on the device. The network operator can also optionally control the operation of the logging system remotely via a network agent. Improved client device and network configurations, as well as methods of operating these systems, are also disclosed. | 2009-01-01 |
20090006910 | SELECTIVE HYBRID ARQ - Briefly, in accordance with one or more embodiments, a HARQ process may be selectively executed according to longer term and/or shorter term packet error rate statistics to be within one or more requirements of an application. As result, the number of retransmissions for the HARQ process may be reduced or minimized. | 2009-01-01 |
20090006911 | DATA REPLACEMENT PROCESSING METHOD - A data replacement processing method is disclosed. In the present invention, buffering and decoding are not interrupted when a data block to be replaced is found. The data block to be replaced can be a defect or a remapped block. The data block to be replaced is not processed until it is requested to be transferred. When the data block to be replaced is to be transferred, transferring is stopped and the data block to be replaced is processed. Therefore, efficiency of the optical disc drive can be promoted since interruption number of the buffering and decoding is decreased. In addition, the optical disc will not execute redundant processing for data blocks to be replaced which are not requested to be transferred. | 2009-01-01 |
20090006912 | Semiconductor memory device having burn-in test mode and method for driving the same - A semiconductor memory device includes: a pattern selector configured to receive a first test control signal and a second test control signal to output a plurality of pattern selection signals and a selection end signal in response to an entry signal; a shifting controller configured to receive the first test control signal and the second test control signal to output a shifting control signal in response to the selection end signal; and a pattern test signal generator configured to select a stress pattern corresponding to the pattern selection signals to generate a plurality of test mode signals for controlling a sequential entry into a plurality of test modes for executing the stress pattern in response to the shifting control signal. | 2009-01-01 |
20090006913 | Semiconductor memory device having test address generating circuit and test method thereof - A semiconductor memory device includes a test address generating circuit configured on the device. The test address generating circuit generates a plurality of test addresses for a test of the semiconductor memory device in response to at least one externally applied test address generation signal. As a result, the number of DUTs can increase, based on a reduction of required address pins, and manufacturing productivity and test efficiency of semiconductor memory devices can increase. | 2009-01-01 |