| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 716138000 | System-on-chip design | 6 |
| 20110010684 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DESIGNING THE SAME - A semiconductor integrated circuit comprising: a clock gating cell to which an enable signal and a clock signal are input, so as to output a gated clock signal generated by output-controlling said clock signal according to said enable signal; a first flip-flop circuit to which a first input data signal and said gated clock signal are input, so as to retain and output said first input data signal as a first output data signal in synchronization with said gated clock signal; and a second flip-flop circuit to which a second input data signal is input, so as to retain and output said second input data signal as a second output data signal in synchronization with said clock signal if the logical values of said second input data signal and said second output data signal differ from each other, or so as to retain said second output data signal if the logical values of said second input data signal and said second output data signal are the same. | 01-13-2011 |
| 20120047481 | IMPLEMENTING PHASE LOCKED LOOP (PLL) WITH ENHANCED LOCKING CAPABILITY WITH A WIDE RANGE DYNAMIC REFERENCE CLOCK - A method and a phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a Voltage Controlled Oscillator (VCO) and a plurality of filter comparators receiving a differential filter VCO control voltage. The plurality of filter comparators comparing the differential filter VCO control voltage values, provides a respective gate enable signal responsive to the compared differential filter VCO control voltage values. A clock signal is applied to an up/down counter responsive to the respective gate enable signal and the wide range dynamic reference clock. The count values of the up/down counter are provided to the VCO to select a respective frequency range for the VCO. | 02-23-2012 |
| 20140040853 | Semiconductor Device with Damage Detection Circuit and Method for Producing the Same - A semiconductor chip having a current source coupled between a first potential and an electrical node, a detection circuit having an input coupled to the electrical node, and a first active component coupled in series with the current source and further coupled between the electrical node and a second potential, wherein the first active component is coupled to the electrical node via a first conductive interconnect. | 02-06-2014 |
| 20140157223 | CIRCUIT AND LAYOUT DESIGN METHODS AND LOGIC CELLS FOR SOFT ERROR HARD INTEGRATED CIRCUITS - In various embodiments, an integrated circuit layout is disclosed. In one embodiments, the integrated circuit layout comprises a first contact area from a first logic cell and a second contact area from a second logic cell. The second contact area comprises a non-zero, non-opposing effect with respect to the first contact area. The first contact area and the second contact area comprise a first distance. When the first distance is below a predetermined threshold the first logic cell and the second logic cell are placed along a first R-line of the circuit and a third contact area comprising an opposing effect with respect to the first contact area and the second contact area is placed between the first contact area and second contact area. | 06-05-2014 |
| 20160140275 | USER EXPERIENCE BASED MANAGEMENT TECHNIQUE FOR MOBILE SYSTEM-ON-CHIPS - A method for designing a system-on-chip (SOC) for a wireless device includes receiving, at a design processor, first usage conditions for a first module of the SOC and second usage conditions for a second module of the SOC. The method further includes determining design parameters for the SOC. The design parameters are based on the first usage conditions and the second usage conditions. | 05-19-2016 |
| 20160180001 | SYSTEM ON CHIP CONFIGURATION METADATA | 06-23-2016 |
