| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 716137000 | PCB, MCM Design | 60 |
| 20110004860 | DESIGN METHOD AND TOOL FOR DESIGNING ELECTRONIC CIRCUITS ON A PRINTED CIRCUIT BOARD - The invention relates to a design method and tool for designing electronic circuits on a printed circuit board, wherein at least one self-contained, pre-composed domain is used, wherein the domain is a module chosen from a pre-composed architecture library, including self-contained pre-designed electronic modules represented by logical architecture and corresponding physical architecture. | 01-06-2011 |
| 20110004861 | METHOD OF DESIGNING A PRINTED CIRCUIT BOARD, AND PACKAGE TEST DEVICE HAVING THE PRINTED CIRCUIT BOARD - In a method of designing a printed circuit board, a package capacitance, a package inductance, and a chip capacitance of an actual memory device are calculated. A signal line capacitance and a signal line inductance per unit length of a signal line are calculated based on characteristics of the printed circuit board. A length of the signal line for each pin is determined based on the package capacitance and the signal line capacitance. | 01-06-2011 |
| 20110016446 | Method for the Construction of Flexible Printed Circuit Boards - A description is given of a method for the computer-aided construction of flexible printed circuit boards that are arranged in a housing ( | 01-20-2011 |
| 20110023005 | WIRING DESIGN ASSISTING APPARATUS, WIRING DESIGN ASSISTING METHOD, AND COMPUTER-READABLE INFORMATION RECORDING MEDIUM - A wiring design assisting apparatus includes an input part that has attribute information of a wiring pattern input thereto; a degradation degree process part that obtains a degradation degree in signal characteristics of a wiring pattern corresponding to attribute information that is input to the input part, based on position information of the wiring pattern corresponding to the attribute information input to the input part, position information and size information of a pattern removed area, and the degradation degree information; and an extracting process part that extracts, for re-wiring, wiring patterns that have degradation degrees equal to or more than a predetermined degree, from wiring patterns for which degradation degrees have been obtained by the degradation degree process part. | 01-27-2011 |
| 20110035720 | Dynamic Printed Circuit Board Design Reuse - Techniques for enabling the dynamic reuse of printed circuit board designs are provided. A master printed circuit board design comprising a plurality of modular flexible designs is received. Additionally, a target design that includes ones of the plurality of flexible designs is identified. Subsequently, as the master design, or ones of the plurality of flexible designs within the master design, are modified, the target design is correspondingly modified. With some implementations, the master design is housed within a library. The library may be used to implement versioning capability for the flexible designs. With further implementations, the master design may itself be a target design. | 02-10-2011 |
| 20110055796 | SYSTEM AND METHOD FOR REMOVING T-POINT ELEMENTS WITH UNUSED STUBS FROM A PCB LAYOUT DESIGN - A system and method for removing T-point elements with unused stubs from a printed circuit board (PCB) layout design obtains each signal line including one or more T-point elements in the PCB layout design, divides the obtained signal line into a plurality of lines according to the one or more T-point elements with unused stubs, and obtains properties of each of the plurality of lines. The system and method further deletes the original layout of the signal line and reconnects the plurality of lines according to the properties of each of the plurality of lines to generate a reconnected signal line, and outputs the reconnected signal line on a display device. | 03-03-2011 |
| 20110093831 | SYSTEM AND METHOD FOR ANALYZING TEMPERATURE RISE OF A PRINTED CIRCUIT BOARD - A system and method that can analyze a temperature rise of a printed circuit board (PCB). The system and method receives attribute parameters of the PCB from an input device, and generates a temperature rise formula according to the received attribute parameters. Additionally, the system and method calculates a temperature rise of a local area surrounding each component on the PCB according to the temperature rise formula. | 04-21-2011 |
| 20110093832 | PRINTED CIRCUIT BOARD DESIGN SUPPORT APPARATUS, METHOD, AND PROGRAM MEDIUM THEREFOR - In designing a printed circuit board, first and second copies of views of first and second major surfaces of the board respectively, are created. The first and second copies are positioned to contact each other. First and second segments on a side of the printed circuit board and normal to a first element in the first copy and a second element in the second copy respectively are obtained. A third segment joining ends of the first and second segments is obtained, and a point dividing the third segment according to a ratio of a distance from the first element to the side and a distance from the second element to the side is calculated. Distances from the first element to the point and from the point to the second element are calculated, and a creepage distance, a sum of the two distances and a thickness of the board, is obtained. | 04-21-2011 |
| 20110107292 | Extraction of Component Models from PCB Channel Scattering Parameter Data by Stochastic Optimization - Various embodiments herein include one or more of systems, methods, software, and/or data structures to extract models of components (e.g., vias and traces) for PCB channels from measurements (or simulations) taken from physical PCB channels. By applying stochastic optimization to measurements of two PCB channels having different channel lengths, s-matrices (e.g., two-port, four-port, and the like) of the components of a PCB channel may be accurately determined by searching the multi-dimensional parameter space for parameters that comply with the measured values. Once the models for the components have been accurately determined, they may be utilized in constructing a model library that includes component models and is based on physical measurement data. | 05-05-2011 |
| 20110145779 | Engineering Change Order Language for Modifying Integrated Circuit Design Files for Programmable Logic Device Implementation - In an embodiment, a method to automatically process modifications to a set of design files is contemplated. The design files describe at least a portion of an integrated circuit design, and may be coded in a hardware description language. The modifications may be made to prepare the design files for inclusion in a programmable logic device implementation of the integrated circuit (or portion thereof). Specifically, the modifications may be specified using a set of commands which may be assembled by a user. | 06-16-2011 |
| 20110145780 | Automated Pin Multiplexing for Programmable Logic Device Implementation of Integrated Circuit Design - In an embodiment, a method to automatically select groups of signals to be multiplexed on pins of a programmable logic device in a programmable logic device implementation of at least a portion of an integrated circuit is contemplated. The set of signals that may be candidates for multiplexing may be received (e.g., the set may be output by programmable logic device design tool). Clock domain tracing may be performed, and signals that have matching clock domains may be identified as candidates for multiplexing. Signals from matching clock domains may be grouped (up to a maximum number of signals that may be multiplexed on one pin) and assigned to pins of the programmable logic devices. | 06-16-2011 |
| 20110145781 | Automated Framework for Programmable Logic Device Implementation of Integrated Circuit Design - In an embodiment, a methodology for automating the generation of a programmable logic device implementation of at least a portion of an integrated circuit is contemplated. The methodology may operate on one or more hardware description language (HDL) files which describe the integrated circuit as an input. Additionally, one or more user-generated control files may be input to the methodology. The methodology may process the one or more HDL files, generating a bitstream to program one or more programmable logic devices to implement the described design. The methodology may include automated modification of the HDL files to prepare them for programmable logic device implementation, automated pad ring generation, automated pin multiplexing, daughter card definition, partitioning, etc. | 06-16-2011 |
| 20110214103 | ELECTRICAL CIRCUIT ARRANGEMENT AND METHOD FOR DESIGNING AN ELECTRICAL CIRCUIT ARRANGEMENT - The invention relates to an electrical circuit arrangement comprising a plurality of reconfigurable circuit cells, each reconfigurable circuit cell comprising —a plurality of nodes, —a plurality of links connectable to the nodes, —at least one circuit element, wherein the reconfigurable circuit cells are each configured to form either a node or a link of the electrical circuit arrangement. Furthermore the invention relates to a method for designing an electrical circuit arrangement | 09-01-2011 |
| 20120023474 | PRINTED CIRCUIT BOARD LAYOUT SYSTEM AND METHOD FOR PRINTED CIRCUIT BOARD LAYOUT - A printed circuit board layout system includes an input unit, an executing unit, a layout unit and a labeling unit. The input unit configured to respond to user operation to generate operation instructions. The operation instructions include execution, layout, and label instructions. The executing unit displays the PCB layout diagram file based on a circuit schematic diagram in response to execution instructions. The layout unit designs the first routes of the PCB layout diagram. The labeling unit labels at least one of the first routes. | 01-26-2012 |
| 20120066660 | METHOD OF MANAGING PROCESS FACTORS THAT INFLUENCE ELECTRICAL PROPERTIES OF PRINTED CIRCUIT BOARDS - In a method of managing process factors that influence electrical properties of printed circuit boards (PCBs), n process factors are arranged in an order according to different influence to one kind of electrical property of the PCBs. The different influence is determined by first experiments designed using the Taguchi method. M process factors that have important influence to the electrical property are obtained from the n process factors according to the order to design second experiments. A computing formula for the electrical property is fitted using the m process factors according to simulated results of the second experiments, and a variation range of each of the m process factors is computed according to the computing formula. | 03-15-2012 |
| 20120117529 | APPARATUS, DESIGN METHOD AND RECORDING MEDIUM - A computer-readable medium storing a design program causing a computer to execute a process is provided. The process includes virtually routing, when routing of a wire to be connected between a first component and a second component at least one of which includes a swapping pin is being designed, the wire to be connected between a first pin of the first component and a first counterpart pin of the second component such that implementation of an actual routed wire connected therebetween is secured regardless of a net allocated to the swapping pin, and swapping one of the virtually routed first pin and the virtually routed first counterpart pin with the swapping pin such that the net allocated to the swapping pin is identical to a net allocated to the other one of the virtually routed first pin and the virtually routed first counterpart pin. | 05-10-2012 |
| 20120124544 | METHOD FOR SETTING TEST POINT - A method for setting a test point is applied to dispose at least one test point on a circuit board in a trace file, which includes steps of reading the trace file, in which the trace file includes at least one trace; determining whether the trace has an initial test point; and setting a test point on the trace that does not have the initial test point. According to the method for setting a test point, cost and time for manually disposing the test point are saved, and an error rate when the test point is arranged is further reduced, thereby effectively improving production efficiency of the circuit board. | 05-17-2012 |
| 20120137266 | Method for Setting Width of Trace On Printed Circuit Board - A method implemented by a computer layout software for setting the width of the printed circuit board trace is disclosed. The method selects one from several traces set on the printed circuit board traces, obtains the corresponding trace name of the selected trace, obtains the device pin connected to the selected trace, acquires the pad corresponding to the device pin, reads the width of the pad, and adjusts the width of the pad. | 05-31-2012 |
| 20120174054 | PRINTED CIRCUIT BOARD LAYOUT SYSTEM AND METHOD - A computing system includes a drawing unit and a layout unit. The computing system sets components parameters to components of a circuit diagram of a printed circuit board (PCB). The drawing unit draws the circuit diagram by using the components with the components parameters. If the drawing unit wants to use a component more than once, the computing system copies the component and the corresponding components parameters. The drawing unit uses the copied components and the corresponding parameters. If the circuit diagram has been drawn, the layout unit loads the circuit diagram and wires the PCB according to the components and the components parameters in the circuit diagram. | 07-05-2012 |
| 20120180020 | PWB Voltage and/or Current Calculation and Verification - Disclosed is a layout tool that verifies the operability of a printed circuit board design. Electrical parameters may be calculated for wire traces that are laid out for a given design. Based on the voltage drop calculations and the voltage and current requirement of the various system components, the layout tool may determine if a given system component will remain within its required operating range. The layout tool may additionally be operable to verify proper spacing between traces that make up a differential signal and to verify that certain pins of integrated circuit are properly connected. | 07-12-2012 |
| 20120192140 | SUPPORT APPARATUS AND INFORMATION PROCESSING METHOD THEREOF - Layout information indicating locations of at least components and conductive layers in a printed circuit board, and layouts of conductive wiring patterns on the respective conductive layers and vias which electrically connect between the conductive layers is obtained from a memory. With reference to the layout information, path information indicating a path of one signal line is generated. With reference to the layout information and path information, a divide portion where a path of a return current corresponding to a signal current of the signal line is divided are detected. With reference to the layout information and path information, information indicating a detour path of the return current in a neighborhood of the divide portion is generated. | 07-26-2012 |
| 20120216170 | PRINTED CIRCUIT BOARD LAYOUT DEVICE CAPABLE OF AUTOMATICALLY ARRANGING ENCAPSULATED COMPONENT AND METHOD THEREOF - A computer-implemented method for component arrangement in a PCB layout device is provided. The device includes wiring diagrams. First, generates a PCB encapsulation diagram corresponding to the selected wiring diagram. Then, obtains the coordinates of each electronic component in the selected wiring diagram. Next, generates a prompt to prompt the user to select a reference point in the PCB encapsulation diagram. Then, obtains the coordinates of the reference point. Next, determines an abscissa difference and an ordinate difference between one component in the wiring diagram and the reference point. Then, determines the coordinates of each encapsulated component in the PCB encapsulation diagram according to the abscissa difference, the ordinate difference, and the coordinates of each electronic component in the wiring diagram. And last, moves each encapsulated component to the determined corresponding coordinates of each encapsulated component in the PCB encapsulation diagram. | 08-23-2012 |
| 20120240095 | ELECTRIC INFORMATION PROCESSING METHOD IN CAD SYSTEM, DEVICE THEREOF, PROGRAM, AND COMPUTER-READABLE STORAGE MEDIUM - It is possible to improve workability of a design work by handling electric information between one object and other objects associated with the object. A plurality of objects are inputted and electric information is inputted to the objects. Among the objects, mutually connected objects are virtually made into a single object. According to electric information in each of the objects, i.e., the virtually unified single object and the other objects excluding the virtually unified single object, objects having the common electric information are connected by straight lines. According to the straight lines, a figure connecting the objects is inputted. A condition for connecting the objects in the figure is inputted. According to the condition, circuit parts are built and signal information is set in a terminal of the circuit parts. | 09-20-2012 |
| 20120266127 | DESIGN METHOD AND TOOL FOR DESIGNING ELECTRONIC CIRCUITS ON A PRINTED CIRCUIT BOARD - The invention relates to a design method and tool for designing electronic circuits on a printed circuit board, wherein at least one self-contained, pre-composed domain is used, wherein the domain is a module chosen from a pre-composed architecture library, including self-contained pre-designed electronic modules represented by logical architecture and corresponding physical architecture. | 10-18-2012 |
| 20120304145 | ELECTRONIC DEVICE AND WIRING METHOD FOR CIRCUIT BOARDS - An electronic device includes a wiring unit. The wiring unit creates one or more circuit diagrams for a design of a first circuit board, and setting electrical rules for components of the first circuit board in each of the one or more diagrams. Based on the one or more diagrams having the electrical rules, the wiring unit generates a wiring diagram for the design of the first circuit board by executing a wiring application. If a second circuit board desires to use a circuit diagram of the first circuit board, the wiring unit copies the circuit diagram having the electrical rules into the wiring application. Then, based on the copied circuit diagram having the electrical rules and particular circuit diagrams of the second circuit board, and the wiring unit creates a wiring diagram for the design of the second circuit board by executing the wiring application. | 11-29-2012 |
| 20130014076 | Component Placement Tool for Printed Circuit Board - In one embodiment, creating a layout for a Printed Circuit Board (PCB) by creating n boundary lines at n locations, respectively, on the PCB and placing n sets of electronic components on the n boundary lines, respectively; and iteratively adjusting and evaluating the layout of the PCB until a set of layout requirements for the PCB has been satisfied. | 01-10-2013 |
| 20130031525 | APPARATUS AND METHOD FOR AIDING IN DESIGNING ELECTRONIC CIRCUITS - First and second pin groups are each formed from a plurality of pins associated with specific nets. Pins in the first pin group are to be wired to pins in the second pin group according to their associated nets. A candidate selection unit selects a set of pair candidates each specifying a first pair of pins in the first pin group and a second pair of pins in the second pin group. The first and second pairs of pins are associated with the same pair of nets, and their respective distances are within a specified range. A pair determination unit determines which pins in the first and second pin groups are to be wired in pairs, based on the pair candidates selected by the candidate selection unit. | 01-31-2013 |
| 20130055192 | Motherboard Assembly for Interconnecting and Distributing Signals and Power - Mechanisms for interconnecting and distributing signals and power between PCBs are provided. A first PCB having land grid arrays (LGAs) and a first wiring layer designed for interconnect components on the first PCB, and a second wiring layer for connecting the components to a second PCB, are provided. The second PCB has opposed parallel first and second surfaces, the first surface having a LGA. A wiring layer designed to interconnect components on the second PCB, and a layer for interconnecting the components on the second PCB with the components on the first PCB, are provided. A first interposer couples to a LGA of a first surface of the first PCB and connects a component to the first PCB. A second interposer is sandwiched between and couples to a LGA of a second surface of the first PCB and to the LGA of the first surface of the second PCB. | 02-28-2013 |
| 20130097577 | Impedance Compensation For A Differential Pair Of Conductive Paths - Methods, apparatus, and products for impedance compensation for a differential pair of conductive paths, including: determining the differential impedance and conductor geometry for the differential pair of conductive paths; determining the path length differential between the conductive paths in the differential pair of conductive paths; determining a centerline path to follow for a shorter conductive path in the differential pair of conductive paths, wherein the centerline path lengths the shorter conductive path such that the length of each conductive path in the differential pair of conductive paths is identical within a predetermined threshold; determining a number of subdivisions of one or more serpentine segments on one of the conductive paths in the differential pair; and determining, in dependence upon the differential impedance at each of the subdivisions of the one or more serpentine segments, a serpentine segment path width for the serpentine segment. | 04-18-2013 |
| 20130125084 | WIRING-DESIGN SUPPORT DEVICE, RECORDING MEDIUM FOR WIRING-DESIGN SUPPORT PROGRAM, AND METHOD FOR WIRING-DESIGN SUPPORT - A wiring-design support device supports wiring design of a printed circuit board. The processor executes a process that includes holding, in the memory, wiring information including information relating to a plurality of signal wires to be wired in parallel between two components on the printed circuit board, generating a wiring route illustrating a wiring area where the plurality of signal wires are wired between the two components and displaying the wiring route on a display unit based on the wiring information held in the holding. And the processor generates, upon or after the wiring route generated, a detailed wiring where each of the plurality of signal wires is wired along the wiring route based on the wiring route and a wiring rule included in the wiring information, and displaying the detailed wiring on the display unit along with the wiring route. | 05-16-2013 |
| 20130132926 | COMPUTER AIDED DESIGN SYSTEM AND METHOD - A computer aided design system comprises an interface creating module, a first calculating module, a dividing module and a second calculating module. The interface module creates a parameter setting interface to display the proposed design on the screen of the device formed with nets and cline segments and select at least one net in response to the user's operation. The first calculating module calculates the length of the cline segments of the potential net in order based on the coordinates of the cline segments and generates a dividing signal. The dividing module divides the cline segments into a first team and a second team based on the compared result with a predetermined width according to the dividing signal. The second calculating module adds the calculated cline segments length in the first team and in the second team to obtain a first length and a second length. | 05-23-2013 |
| 20130159959 | Phase Compensation In A Differential Pair Of Transmission Lines - Phase compensation in a differential pair of transmission lines, including: identifying, by a phase compensation module, a plurality of direction changes in the differential pair of transmission lines; determining, by the phase compensation module for each direction change in the differential pair of transmission lines, a direction change angle; and determining, by the phase compensation module for each direction change in the differential pair of transmission lines, the geometry of one or more phase correction humps to include in one transmission line of the differential pair of transmission lines in dependence upon the direction change angle. | 06-20-2013 |
| 20130326463 | Method to Determine Optimal Micro-Bump-Probe Pad Pairing for Efficient PGD Testing in Interposer Designs - The present disclosure relates to a method of routing probe pads to micro-bumps of an interposer. An interposer is provided having target micro-bumps and probe pads. The probe pads are initially unassigned. Target micro-bump locations and probe pad locations are obtained. Possible route assignments from the probe pads to the target micro-bumps are obtained. Costs are developed for the possible route assignments at least partially according to the target micro-bump locations and the probe pad locations. Final assignments are selected from the possible assignments according to the costs. | 12-05-2013 |
| 20140109035 | LAYOUT METHOD FOR PRINTED CIRCUIT BOARD - A layout method for a printed circuit board (PCB) is provided. A memory type of a dynamic random access memory (DRAM) to be mounted on the PCB is obtained. A module group is obtained from a database according to the memory type of the DRAM, wherein the module group includes a plurality of routing modules. A plurality of PCB parameters are obtained. A specific routing module is selected from the module group according to the PCB parameters. The specific routing module is implemented into a layout design of the PCB. The specific routing module includes layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip. | 04-17-2014 |
| 20140123098 | DYNAMIC PRINTED CIRCUIT BOARD DESIGN REUSE - Techniques for enabling the dynamic reuse of printed circuit board designs are provided. A master printed circuit board design comprising a plurality of modular flexible designs is received. Additionally, a target design that includes ones of the plurality of flexible designs is identified. Subsequently, as the master design, or ones of the plurality of flexible designs within the master design, are modified, the target design is correspondingly modified. With some implementations, the master design is housed within a library. The library may be used to implement versioning capability for the flexible designs. With further implementations, the master design may itself be a target design. | 05-01-2014 |
| 20140149960 | COMPUTING DEVICE AND METHOD FOR CHECKING WIRING DIAGRAMS OF PCB - In a method for checking wiring diagrams, one element is selected from a first printed circuit board (PCB) file. An element corresponding to the selected element in a second PCB file is searched according to information of the selected element, then the information is recorded into a different element list of the first PCB file, when the second PCB file does not have a corresponding element. The information is recorded into a same element list, when the second PCB file has a corresponding element and the corresponding element has the same information with the element in the first PCB file. The second PCB file and the same element list are compared to locate elements which are included in the second PCB file but not included in the same element list, and the information of the located elements is recorded into a different element list of the second PCB file. | 05-29-2014 |
| 20140165025 | COMPUTING DEVICE AND METHOD FOR CHECKING SIGNAL TRANSMISSION LINE - A signal transmission line check method to be executed by a computing device is described. A to-be-checked signal transmission line group in a displayed printed circuit board (PCB) layout is determined. Whether all signal transmission lines of the to-be-checked signal transmission line group are laid out in a same layer of the displayed PCB layout is checked according to an input serial number of a chipset and layer properties of the to-be-checked signal transmission lines. The signal transmission lines that do not satisfy design standards are determined when not all of the to-be-checked signal transmission lines are laid out in a same layer. A related computing device is also disclosed. | 06-12-2014 |
| 20140250418 | WIRING BOARD DESIGN SYSTEM AND WIRING BOARD DESIGN METHOD - An object of the present invention is to provide wiring board design system and wiring board design method to determine a component and a wiring pattern in real-time when designing a wiring on a circuit board. | 09-04-2014 |
| 20140310677 | BOARD DESIGN AID DEVICE, BOARD DESIGN AID METHOD, AND BOARD DESIGN AID PROGRAM - A board design aid device includes a calculating and correcting units. The calculating unit groups a plurality of layers in a multi-layer board into a plurality of pairs of layers based on design information of the multi-layer board, the plurality of layers being stacked and derives a difference of total amounts in respect to a board design element, each of the total amounts being related to each layer of a pair of layers of the plurality of pairs of layers, the board design element being related to a warp of the multi-layer board. The correcting units, based on the difference of the total amounts, corrects an amount of the board design element for at least one of layers among at least one of the plurality of the pairs of layers so that the difference of the total amounts of the board design element is maintained within a certain range. | 10-16-2014 |
| 20140325469 | APPARATUS AND METHOD FOR AIDING IN DESIGNING ELECTRONIC CIRCUITS - First and second pin groups are each formed from a plurality of pins associated with specific nets. Pins in the first pin group are to be wired to pins in the second pin group according to their associated nets. A candidate selection unit selects a set of pair candidates each specifying a first pair of pins in the first pin group and a second pair of pins in the second pin group. The first and second pairs of pins are associated with the same pair of nets, and their respective distances are within a specified range. A pair determination unit determines which pins in the first and second pin groups are to be wired in pairs, based on the pair candidates selected by the candidate selection unit. | 10-30-2014 |
| 20140351786 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, PROGRAM, AND BOARD MANUFACTURING SYSTEM - An information processing apparatus is configured to compute the shape of a conductive pattern to be formed on a board by a drawing apparatus that performs drawing on the board using conductive liquid droplets. The information processing apparatus includes an image data generation unit configured to generate image data in which dots each having a diameter determined according to a drawing condition of a conductive pattern by the drawing apparatus are arranged at respective positions which are indicated by data of a conductive pattern and at which conductive liquid droplets are to be landed. | 11-27-2014 |
| 20140380262 | METHOD OF DESIGNING POWER SUPPLY NETWORK - To design a power supply network of a | 12-25-2014 |
| 20150012904 | SYSTEM AND METHOD FOR SETTING ELECTRICAL SPECIFICATION OF SIGNAL TRANSMISSION LINE - A computer-based method for setting electrical specification of signal transmission lines of a printed circuit board (PCB) layout is provided. Data recorded in an electrical specification file is imported. The electrical specification file records a number of chips, pins of each chip, and electrical specification corresponding to each chip. The PCB layout is searched to find the chips and the pins recorded in the electrical specification file. The electrical specification of signal transmission lines connected to the found pins is set according to the electrical specification corresponding to each chip. | 01-08-2015 |
| 20150121331 | SURFACE REGION SELECTION FOR HEAT SINK PLACEMENT - A method for determining an area of a region for receiving a heat sink on a surface of a chip-supporting substrate is disclosed. The method can include determining, in response to a specified voltage drop associated with substrate wiring, a first set of wiring cross-sectional areas and corresponding lengths that satisfy the specified voltage drop. The method can also include determining, by selecting, in response to a specified thermal resistance associated with substrate wiring and insulating layers, from the first set, a second set of wiring cross-sectional areas and corresponding lengths that satisfy the specified thermal resistance. The method can also include selecting, from a set of placement areas corresponding to the second set of wiring cross-sectional areas and corresponding lengths, a heat sink placement area that is greater than a lower size for a placement area and less than an upper size for a placement area. | 04-30-2015 |
| 20150128102 | CIRCUIT DESIGN SYNTHESIS TOOL WITH EXPORT TO A COMPUTER-AIDED DESIGN FORMAT - A method (and related apparatus) includes receiving user input and generating at least one of schematic content for a circuit based on the received user input and a printed circuit board (PCB) layout based on the circuit. The method further includes generating a bill of material (BOM) for the circuit, and receiving a user selection of at least one of a computer-aided design (CAD) tool format and a PCB layout tool format. The method also includes receiving a user selection to include footprints for the components used in the schematic content or PCB layout and exporting at least one of the schematic content, and PCB layout as well as the PCB footprints to one or more files in accordance with the selected CAD and/or PCB layout tool format. | 05-07-2015 |
| 20150135157 | CIRCUIT-DESIGN SIMULATION SYSTEM AND CIRCUIT-DESIGN METHOD FOR PCB - A circuit-design method for a PCB is provided. A first user input is obtained via a user interface of a layout tool, wherein the first user input indicates that an object of a circuit diagram of the PCB is selected in the user interface. A plurality of constraint settings corresponding to an attribute are obtained from a database according to the attribute of the object. The plurality of constraint settings are displayed in a window of the user interface. A second user input is obtained via the user interface, wherein the second user input indicates that one of the plurality of constraint settings is selected in the window. At least one constraint parameter corresponding to the selected constraint setting is assigned to the object, and a tag corresponding to the attribute of the object is attached to the object of the circuit diagram. | 05-14-2015 |
| 20150302130 | METHOD AND SYSTEM FOR VERIFYING PRINTED CIRCUIT BOARD DESIGNS, AND CREATING OR VERIFYING RELATED ELECTRONIC COMPONENT PLACEMENT DATA FOR PRINTED CIRCUIT BOARD FABRICATION AND ASSEMBLY - A system for printed circuit board assembly includes a user interface provided on a display device for visual verification of printed circuit board design data, a user interface provided on the display device for inputting bill of material information, and a user interface provided on the display device for verification, alteration and creation of component placement data. | 10-22-2015 |
| 20150302131 | INFORMATION PROCESSING APPARATUS AND BACK ANNOTATION METHOD - A back annotation method includes a first process, a second process, and a third process. In the first process, first information is determined. In the second process, second information to be reflected into the first information is determined. In the third process, whether the first information is being locked is determined based on a log file. When it is determined that the first information is being locked, it is requested that a back annotation process for reflecting the second information into the first information is performed in the first process. When it is determined that the first information is not being locked, the back annotation process is performed in the third process. | 10-22-2015 |
| 20150331986 | INSULATION DISTANCE CHECK DEVICE - The insulation distance check device comprising: a unit which designates a high potential component, a conductive component and an insulation component to 3D CAD data; a unit which designates a distance condition; a unit which superimposes a layer surrounding the high potential component and creates a layer map associating the layer with a first distance; a unit which determines a second distance associated with the layer contacting with a portion of the conductive component, the second distance being a distance between the high potential component and the portion of the conductive component; a unit which compares the second distance and the distance condition; and a unit which displays at least one of a region occupied by the portion of the conductive component, on which the second distance having been determined to dissatisfy the distance condition is based; and a path connecting the high potential component and the conductive component. | 11-19-2015 |
| 20150342056 | TECHNOLOGY FOR TEMPERATURE SENSITIVE COMPONENTS IN THERMAL PROCESSING - A method for printed circuit board design of temperature sensitive components includes a scrub tool receiving a list of part numbers for electronic components of a printed circuit board assembly (“PCBA”). The scrub tool sends one or more queries for finding temperature and time limits of the electronic components to a database. A mapping tool receives a selection of one or more part numbers responsive to the one or more queries, wherein the selection is responsive to the temperature and time limits. The mapping tool sends a data structure to a physical design tool which is configured with physical design data for generating a graphic representation of the PCBA. The data structure from the mapping tool provides the received selection of one or more part numbers and configures the physical design tool to highlight components having part numbers of the selection on the PCBA graphic representation. | 11-26-2015 |
| 20150347656 | SYSTEM DESIGN MANAGEMENT - This application discloses a computing system implementing tools and mechanisms to generate a framework for a system-level design of an electronic system, wherein the system-level design includes multiple electronic designs from different electronic design automation tools. The tools and mechanisms can correlate design components in the electronic designs to different portions of the framework for the system-level design, and determine whether the electronic designs are congruent with the system-level design based, at least in part, on the correlation of the electronic designs to the different portions of the framework for the system-level design. | 12-03-2015 |
| 20150347658 | APPARATUS AND METHOD FOR FILE TRANSLATION - Methods and apparatuses for modifying a Gerber-compliant data structure that is representative of an existing printed circuit board (PCB) layout are described. This may include obtaining a Gerber-compliant data structure which includes layout information describing the physical layout of a PCB, obtaining modification information representing a modification to the physical layout of the PCB, and automatically modifying the Gerber-compliant data structure to seamlessly incorporate the modification information to create a new electrical connectivity structure for the Gerber-compliant data structure. | 12-03-2015 |
| 20150363538 | DESIGN SUPPORT DEVICE, DESIGN SUPPORT METHOD, AND PROGRAM - A design support device having a permissible power supply fluctuation deriving unit and a target impedance deriving unit. The permissible power supply fluctuation deriving unit derives the fluctuation in the power supply voltage that is permissible on the basis of jitter-voltage correlation information, which indicates the correlation between the power supply voltage fluctuation generated in an I/O buffer and the jitter generated by the power supply voltage fluctuations, and jitter constraint information, which is for stably transmitting a signal, for the generated jitter. The target impedance deriving unit derives a target impedance in the permissible range of impedance for a power supply circuit, on the basis of information on the signal operating current flowing through the power supply circuit of the I/O buffer, and the power supply voltage fluctuation. | 12-17-2015 |
| 20150379180 | LAYOUT METHOD FOR PRINTED CIRCUIT BOARD - A layout method for a printed circuit board (PCB) is provided. The method obtains a memory type of a dynamic random access memory (DRAM) to be mounted on the PCB, obtains a module group from a database according to the memory type of the DRAM, wherein the module group comprises a plurality of routing modules, obtains a plurality of PCB parameters, selects a specific routing module from the module group according to the PCB parameters, and implements the specific routing module into a layout design for PCB fabrication. The specific routing module comprises layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip. | 12-31-2015 |
| 20160085902 | System and Method of Determining High Speed Resonance due to Coupling From Broadside Layers - A method includes providing, on a printed circuit board, a first circuit trace having a first unit cell length and a second circuit trace having a second unit cell length, determining a time delay associated with the first unit cell length and the second unit cell length, estimating a floquet frequency associated with the time delay, where the floquet frequency is determined as | 03-24-2016 |
| 20160147930 | WIRING TOPOLOGY METHOD AND INFORMATION PROCESSING DEVICE - A wiring topology display method, includes: obtaining layout information indicating positions of components and wiring coupling the components; dividing first wiring into first pieces of partial wiring, and generating partial wiring information indicating the first pieces of partial wiring; identifying a first length of the partial wiring and a first angle of the partial wiring for a vector; identifying combinations of second pieces of partial wiring based on the first length and the first angle, the second pieces of partial wiring having second lengths which are a certain length or more, second angles which are different by a certain angle, and a distance which is a certain distance or less; identifying a group having the combinations including pieces of identical partial wiring; and symbolizing third pieces of partial wiring at both ends of the group and fourth pieces of partial wiring between the third pieces of partial wiring. | 05-26-2016 |
| 20160154919 | RECORDING MEDIUM HAVING STORED THEREIN DESIGN PROGRAM, INFORMATION PROCESSING APPARATUS, AND METHOD FOR DESIGNING | 06-02-2016 |
| 20160171146 | CIRCUIT DESIGN SYNTHESIS TOOL WITH EXPORT TO A COMPUTER-AIDED DESIGN FORMAT | 06-16-2016 |
| 20160188786 | TECHNOLOGY FOR TEMPERATURE SENSITIVE COMPONENTS IN THERMAL PROCESSING - For a printed circuit board assembly (“PCBA”) selected electronic components are highlighted on a graphic representation of the PCBA on a display of a computer system. The components are selected responsive to temperature and time limits of the selected components. Ones of the highlighted components are associated to respective temperature sensors on the PCBA. Responsive to where the one or more additional ones of the highlighted components are located on the PCBA relative to the at least one of the respective temperature sensors, one or more additional ones of the highlighted components are associated with at least one of the respective temperature sensors. The computer system receives data for respective signals indicating temperatures encountered by the respective temperature sensors when the PCBA is heated in a manufacturing process. The computer system shows whether any of the time and temperature limits were exceeded during the manufacturing process. | 06-30-2016 |
| 20160381807 | Current Redistribution in a Printed Circuit Board - In one implementation, a multilayered printed circuit board is configured to redirect current distribution. The current may be distributed by steering, blocking, or otherwise manipulating current flows. The multilayered printed circuit board includes at least one power plane layer. The power plane layer does not distribute current evenly. Instead, the power plane layer includes multiple patterns with different resistances. The patterns may include a hatching pattern, a grid pattern, a directional pattern, a slot, a void, or a continuous pattern. The pattern is a predetermined spatial variation such that current flows in a first area differently than current flows in a second area. | 12-29-2016 |
