| Entries |
| Document | Title | Date |
|---|
| 20100318956 | METHOD OF INTEGRATED CIRCUIT CHIP FABRICATION AND PROGRAM PRODUCT THEREFOR - A method of physical design for integrated circuit (IC) chip fabrication, physical design system and program product therefor. A design shape is fragmented into segments for Optical Proximity Correction (OPC) and a harmonic mean of the segments is determined. Electrical intent is determined for the shape and a harmonic mean is determined for the segments. Segments may be moved based on a effect on the harmonic mean from moving the segments, measured using a harmonic mean cost function. Finally segmented shapes are passed to OPC. | 12-16-2010 |
| 20100333059 | DESIGN SUPPORT APPARATUS AND DESIGN SUPPORT METHOD - According to one embodiment, a design support method includes generating first layout data when first electronic components and first positions of the first electronic components on a printed circuit board are specified, computing temperature distribution data showing a temperature distribution on a surface of the board, acquiring a maximum thermal resistance temperature of the second electronic component when the second electronic component is specified, calculating a first temperature on the surface at a second position based on the temperature distribution data when the second position is specified, determining whether the second electronic component can be arranged at the second position based on the first temperature and the maximum thermal resistance temperature, and prohibiting generation of a second layout data when it is determined that the second electronic component can be arranged at the second position, the second layout data showing the first positions and the second position. | 12-30-2010 |
| 20110023004 | ESTABLISHING BENCHMARKS FOR ANALYZING BENEFITS ASSOCIATED WITH VOLTAGE SCALING, ANALYZING THE BENEFITS AND AN APPARATUS THEREFOR - Methods for establishing benchmarks and for analyzing benefits associated with voltage scaling are provided. In one embodiment, the method for establishing benchmarks includes: (1) synthesizing a netlist from a RTL of a functional IC design; (2) implementing a layout of an IC from the netlist, wherein the synthesizing and the implementing are performed at designated voltages and frequencies over a voltage and a frequency range, the voltage range including a voltage scaling range and a voltage associated with a designated implementation of the IC; (3) obtaining measurements of at least one voltage scaling metric associated with the IC at each of the designated voltages and frequencies; and (4) normalizing measurements associated with the voltage scaling range to measurements associated with the designated implementation employing a processor to obtain normalized benchmarks for analyzing optimization of the IC associated with voltage scaling. EDA tools may be used for synthesizing, implementing and obtaining. | 01-27-2011 |
| 20110035718 | INTEGRATED CIRCUIT DESIGN SYSTEM AND METHOD - An electronic system design platform and method are presented. The electronic system design platform includes a computing system that hosts a virtual channel manager. The virtual channel manager provides a graphical editor for receiving user input specifying design specifications of the integrated circuit, and the design specifications specify a number of functional blocks and current physical communication conditions between pairs of the functional blocks. The virtual channel manager is further adapted for designing a virtual channel interface for the current physical communication conditions between the pairs of the functional blocks, and selecting a communication protocol that is best suited for each virtual channel interface. | 02-10-2011 |
| 20110035719 | PRINTED CIRCUIT BOARD LAYOUT SYSTEM AND METHOD THEREOF - A method for automatically checking signal areas includes: recording etching line information of etching lines which divide an internal plane of an opened PCB file into a plurality of signal areas, recording input signal names and positions where the input signal names are arranged, obtaining the outline information of the opened internal plane and the etching line information, obtaining position information of points within each signal areas according to the outline information and the etching line information, determining whether one signal area is associated with one input signal name, determining whether the one input signal name matches one standard signal name, and setting one input signal name as a name attribute of the signal area associated with the one input signal name if the one input signal name matches one standard signal name. A related PCB system is also provided. | 02-10-2011 |
| 20110041115 | NON-INVASIVE LEAKAGE POWER DEVICE CHARACTERIZATION OF INTEGRATED CIRCUITS USING DEVICE GROUPING AND COMPRESSIVE SENSING - Techniques are generally described for non-invasive, post-silicon characterization of—leakage power for devices of an integrated circuit (IC). A system of sparse leakage power equations may be developed for the devices (e.g. gates) within the IC to be solved using compressive sensing (CS) techniques. Input Vectors (IV) may be applied at input terminal of the IC, and power of the IC may be measured. The measurements may be used in conjunction with the set of sparse equations to determine leakage power values for individual devices, not directly accessible. Pre-processing and post-processing techniques may be employed to make the system of equations more sparse and further improve the efficiency of applying CS techniques to solve the equation. Example processing may include variable splitting, device grouping, IV and equation selection, measurement under elevated IC temperature, and bootstrapping. Other aspects may be disclosed and claimed. | 02-17-2011 |
| 20110055793 | TIMING CLOSURE ON MULTIPLE SELECTIVE CORNERS IN A SINGLE STATISTICAL TIMING RUN - An approach for covering multiple selective timing corners in a single statistical timing run is described. In one embodiment, a single statistical timing analysis is run on the full parameter space that covers unlimited process parameters/environment conditions. Results from the statistical timing analysis are projected for selected corners. Timing closure is performed on the corners having the worst slacks. | 03-03-2011 |
| 20110055794 | Method for Modeling a Magnetic Tunnel Junction with Spin-Polarized Current Writing - The junction comprising a stack of at least two magnetic layers, a first layer, for example a soft magnetic layer with controllable magnetization, and a second layer, for example a hard magnetic layer with fixed magnetization, the magnetization of the soft layer being described by a uniform magnetic moment, the dynamic behavior of the junction being modeled by an equivalent electrical circuit comprising at least two coupled parts: a first part representing the stack of the layers, through which a current flows corresponding to the polarized current flowing through said layers whose resistance across its terminals depends on three voltages representing the three dimensions of the magnetic moment along three axes, modeling the tunnel effect; a second part representing the behavior of the magnetic moment, comprising three circuits each representing a dimension of the magnetic moment by the three voltages, each of the three voltages depending on the voltages in the other dimensions and on the voltage across the terminals of the stack, modeling the torque effect exerted by the polarized current on the magnetization of the soft layer. | 03-03-2011 |
| 20110055795 | Design Support Apparatus and Design Support Method - According to one embodiment, a design support apparatus determines one of a first impedance between a power plane and a ground plane in the printed circuit board at an ON time of a high-side transistor in the switching power supply, a second impedance between the power plane and the ground plane at an ON time of a low-side transistor in the switching power supply, and a third impedance in an intermediate range between the first impedance and the second impedance to be an impedance between the power plane and the ground plane, based on ON-time information indicative of a ratio of an ON period of the high-side transistor to a switching cycle of the switching power supply in an operation period of the device. The apparatus evaluates capacitor information included in design information of the printed circuit by comparing the determined impedance and a target impedance. | 03-03-2011 |
| 20110066997 | MODELING AND SIMULATING DEVICE MISMATCH FOR DESIGNING INTEGRATED CIRCUITS - A user specifies layout styles for devices in a circuit schematic, where the layout styles capture features of device arrangements and device correlations. The resulting layout can be simulated by using a computer so that one or more performance metrics can be evaluated for the circuit. In some cases, test chips may be used to determine device correlations for arrangements corresponding to different layout styles. | 03-17-2011 |
| 20110072409 | OPTICAL SENSOR INCLUDING STACKED PHOTODIODES - A complementary metal-oxide-semiconductor (CMOS) image sensor comprises a first photosensitive diode comprising a first semiconductor material is formed in a first semiconductor substrate. A second photosensitive diode comprising a second semiconductor material, which has a different light detection wavelength range than the first semiconductor material, is formed in a second semiconductor substrate. Semiconductor devices for holding and detecting charges comprising a sensing circuit of the CMOS image sensor may also be formed in the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are bonded so that the first photosensitive diode is located underneath the second photosensitive diode. The vertical stack of the first and second photosensitive diodes detects light in the combined detection wavelength range of the first and second semiconductor materials. Sensing devices may be shared between the first and second photosensitive diodes. | 03-24-2011 |
| 20110088008 | METHOD FOR CONVERSION OF COMMERCIAL MICROPROCESSOR TO RADIATION-HARDENED PROCESSOR AND RESULTING PROCESSOR - A method is provided to convert commercial microprocessors to radiation-hardened processors and, more particularly, a method is provided to modify a commercial microprocessor for radiation hardened applications with minimal changes to the technology, design, device, and process base so as to facilitate a rapid transition for such radiation hardened applications. The method is implemented in a computing infrastructure and includes evaluating a probability that one or more components of an existing commercial design will be affected by a single event upset (SEU). The method further includes replacing the one or more components with a component immune to the SEU to create a final device. | 04-14-2011 |
| 20110113401 | T-COIL NETWORK DESIGN FOR IMPROVED BANDWIDTH AND ELECTROSTATIC DISCHARGE IMMUNITY - A method of generating a circuit design comprising a T-coil network includes determining inductance for inductors and a parasitic bridge capacitance of the T-coil network. The parasitic bridge capacitance is compared with a load capacitance metric that depends upon parasitic capacitance of a load coupled to an output of the T-coil network. An amount of electrostatic discharge (ESD) protection of the circuit design that is coupled to the output of the T-coil network and/or a parameter of the inductors of the T-coil network is selectively adjusted according to the comparison. The circuit design, which can specify inductance of the inductors, the amount of ESD protection, and/or the width of windings of the inductors, is outputted. | 05-12-2011 |
| 20110131542 | SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS, DESIGN STRUCTURE AND METHOD - Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure. | 06-02-2011 |
| 20110145778 | Automated Pad Ring Generation for Programmable Logic Device Implementation of Integrated Circuit Design - In an embodiment, a method to automatically generate a pad ring for a programmable logic device implementation of an integrated circuit is contemplated. The pad ring that will be used in the integrated circuit itself may include pad logic (e.g. to support boundary scan and other forms of testing), custom driver/receiver circuitry, etc. The pad ring in the programmable logic device, on the other hand, may be predetermined as part of the production of the programmable logic device. The generation may include removing the pad logic and other pad-related circuitry from one or more design files that represent the integrated circuit, as well as mapping the input, output, and input/output signals of the integrated circuit to the available programmable logic device pads. | 06-16-2011 |
| 20110161910 | DESIGN SUPPORT APPARATUS, METHOD, AND RECORDING MEDIUM - A design support apparatus includes: a circuit-data generation unit to generate circuit data based on layout information of a semiconductor integrated circuit; and a parameter determination unit to set a first parameter relating to mechanical stress exerted on a transistor including at least one of a plurality of gates in a diffusion region, wherein the circuit-data generation unit obtains a mobility of the transistor based on the first parameter and reflects the mobility in the circuit data. | 06-30-2011 |
| 20110167401 | Processing Wiring Diagrams in a Data Processing System - A method, computer program product, and apparatus for processing a wiring diagram is provided. Information associated with a number of components in the wiring diagram is identified. A scaling factor between a first format for the wiring diagram and a second format used by a software application configured to use wiring diagrams in the second format is identified. The scaling factor is applied to the information identified as being associated with the number of components in the wiring diagram to form processed information. | 07-07-2011 |
| 20110173586 | METHOD FOR CREATING ELECTRICALLY TESTABLE PATTERNS - The present invention provides a method and computer program product for designing an electrically testable pattern that is based on patterns derived from the desired chip layout to be printed. Such electrical test patterns are based on the features within a region of influence around critical sites. The critical sites may be identified, for example, by processing the chip layout through an OPC verification tool that flags potential failure sites. The electrical test pattern is formed from features within an region of influence (ROI) around the critical site, and also include electrical feed lines at terminal ends of one or more features having an electrical characteristic that is sensitive to changes in the printed environment of the critical site. The feed lines may be locate on the same or a different layer than the critical site, depending on the chip design. The electrical pattern is further defined by retaining features within a second trim region such that the printed features within the ROI are not substantially modified by the absence of features outside the second trim region. | 07-14-2011 |
| 20110185335 | DETERMINING AN ORDER FOR VISITING CIRCUIT BLOCKS IN A CIRCUIT DESIGN FOR FIXING DESIGN REQUIREMENT VIOLATIONS - Some embodiments of the present invention provide techniques and systems for determining an order for visiting circuit blocks of a circuit design for fixing design requirement violations. Fixing design requirement violations by visiting circuit blocks in this order can improve performance and quality of results. During operation, a system can determine a set of equal value segments in the circuit design. In some embodiments, the system determines equal value segments for multiple corners and combines the equal value segments to obtain the set of equal value segments. Next, the system can determine an order for visiting circuit blocks of the circuit design for fixing design requirement violations based at least on the set of equal value segments. Note that circuit block pins in an equal value segment are associated with the same parameter value, and parameter values indicate an amount or degree of a design requirement violation. | 07-28-2011 |
| 20110185336 | IMPEDANCE DESIGN METHOD - The invention discloses an impedance design method for a power network of a core chip within a chipset having N input/output (I/O) ports coupled to a voltage source which have an observation I/O port. The method includes calculating a first set of impedances at a predetermined frequency or the observation I/O port, if the voltage source is internally coupled to the N I/O ports within the chipset, and calculating a second set of impedances at the predetermined frequency for the observation I/O port, if the voltage source is externally coupled to the N I/O ports through a carrier coupling the core chip to the voltage source. The first set of impedances to the second set of impedances are compared, and the impedance of the power network or the impedance of the carrier is adjusted according to the comparison result. | 07-28-2011 |
| 20110191741 | DETERMINING A PREDICTED SOFT ERROR RATE FOR AN INTEGRATED CIRCUIT DEVICE DESIGN - A method for determining a predicted soft error rate (SER) for an integrated circuit device design includes calculating the SER based on a predicted amount of charge imparted by a one or more particles to the integrated circuit device based on the design. The SER is further based on a predicted sensitivity level of a region of the integrated circuit device to the charge imparted by the one or more particles, and can also be based on the energy spectrum of the particles. | 08-04-2011 |
| 20110191742 | SIGNAL TRACING THROUGH BOARDS AND CHIPS - Signal tracing across boards and chips can be used to greatly enhance failure analysis of the boards and chips. Concepts are disclosed for tracing one or more signal lines across a board, across a chip boundary, and across a chip. Signals may be traced through active circuitry on a chip along with paths through various logic cones. The result can be graphically and interactively presented. | 08-04-2011 |
| 20110214101 | METHOD OF THERMAL DENSITY OPTIMIZATION FOR DEVICE AND PROCESS ENHANCEMENT - The present disclosure provides an integrated circuit method. The method includes providing an integrated circuit (IC) design layout; simulating thermal effect to the IC design layout; simulating electrical performance to the IC design layout based on the simulating thermal effect; and performing thermal dummy insertion to the IC design layout based on the simulating electrical performance. | 09-01-2011 |
| 20110214102 | METHOD FOR TESTING INTEGRATED CIRCUITS - A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit. | 09-01-2011 |
| 20110219349 | PARAMETERIZED CELL CACHING IN ELECTRONIC DESIGN AUTOMATION - Some embodiments provide a system that improves performance during parameterized cell instantiation in an electronic design automation (EDA) application. During operation, the system persists evaluation results associated with a parameterized cell in the design within a session of the EDA application so that the evaluation results are available even after they have been flushed from memory. Further, the system can persist the evaluation results across sessions of the EDA application. Next, the system uses the persisted evaluation results to instantiate the parameterized cell without re-evaluating the parameterized cell. Finally, the system discards the persisted evaluation results based at least on a dependency associated with the parameterized cell. | 09-08-2011 |
| 20110219350 | STAGE EVALUATION OF A STATE MACHINE - The present invention provides a method and system for stage evaluation of a state machine model. Two types of transitions are used: first-stage transitions and second-stage transitions for a two-stage evaluation. In one embodiment, top-down processing and bottom-up processing may be combined using a two-stage evaluation. First-stage transitions are used with top-down processing while second-stage transitions are used with bottom-up processing. Certain conditions are used to determine if a switch from one type of stage processing to another type of stage processing is needed. | 09-08-2011 |
| 20110219351 | Method for Compensation of Process-Induced Performance Variation in a Mosfet Integrated Circuit - An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing. | 09-08-2011 |
| 20110283251 | Effective Gate Length Circuit Modeling Based On Concurrent Length And Mobility Analysis - Disclosed is a computer implemented method and computer program product to determine metal oxide semiconductor (MOS) gate functional limitations. A simulator obtains a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter comprising a slice gate width and a slice gate length. The simulator determines a current for each slice based on a slice gate length of the slice to form a length-based current for each slice. The simulator determines a length-based current for the MOS gate by summing the length-based current for each slice. The simulator calculates a stress profile for each slice. The simulator determines a slice carrier mobility for each slice based on the stress profile of each slice. The simulator determines a carrier mobility-based current for each slice, based on each slice carrier mobility. The simulator determines a carrier mobility for the MOS gate based on the carrier mobility-based current for each slice. The simulator determines an effective length for the MOS gate based on the length-based current. | 11-17-2011 |
| 20110289472 | LAYOUT QUALITY EVALUATION - A method for quantifying and improving layout quality of an IC is disclosed. The method includes receiving a drawn layout and placing essentially one dimensional measurement markers (chords) at various location in the drawn layout. This placement is done in such manner that contours of shapes in the drawn layout intersect a chord in at least two places. The length of the chord is defined as its portion delimited by the intersections, and a measurement of the chord is defined as obtaining its length. The drawn layout is subjected, with the exception of the chords, to a patterning simulation at a selected processing point. Following the simulation the chords are measured and the obtained lengths associated with the drawn layout and the processing point. The patterning simulation may be carried out at a variety processing points and the chord lengths following each simulation are associated with the respective processing point. The sets of lengths obtained at the various processing points are used to quantitatively evaluate the layout quality, to improve the layout quality and tune the processing window. | 11-24-2011 |
| 20110296369 | OPERATION ANALYZING METHOD, OPERATION ANALYZING APPARATUS, OPERATION ANALYZING PROGRAM, AND OPERATION ANALYZING SYSTEM FOR SEMICONDUCTOR INTEGRATED CIRCUITS - An operation analyzing apparatus ( | 12-01-2011 |
| 20110302548 | DELAY LIBRARY GENERATION DEVICE AND METHOD - A delay library generation device includes a grouping unit that generates a group including an output terminal of a sequential logic circuit and an input terminal of the sequential logic circuit that influences the output terminal based on circuit information of the sequential logic circuit, a signal pattern generation unit that generates a signal pattern set for the input terminal of the sequential logic circuit for each generated group based on a true value table of the sequential logic circuit and a library generation unit that measures a delay of the sequential logic circuit for each group and generates a delay library of the sequential logic circuit based on the measured delay. | 12-08-2011 |
| 20110320999 | DECOMPRESSORS FOR LOW POWER DECOMPRESSION OF TEST PATTERNS - Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing. | 12-29-2011 |
| 20110321000 | TECHNIQUE FOR CREATING ANALYSIS MODEL AND TECHNIQUE FOR CREATING CIRCUIT BOARD MODEL - According to a circuit board creation program presented herein, a simulation assuming a case in which an addition of a bypass capacitor near a another bypass capacitor provided between a pin and via of an LSI part can be performed, simply by adding a bypass capacitor property model and changing the value of a coefficient parameter by which the property value of an element of a line part is to be multiplied or divided. | 12-29-2011 |
| 20120030643 | ASSESSING PRINTABILITY OF A VERY-LARGE-SCALE INTEGRATION DESIGN - Printability of a very-large-scale integration design is assessed by: during a training phase, generating a training set of very-large-scale integration design shapes representative of a population of very-large-scale integration design shapes, obtaining a set of mathematical representations of respective shapes in the training set, identifying at least two classes of physical events causally linked to the printability for the very-large-scale integration design shapes, each of the classes being associated to a respective level of printability, labeling each mathematical representation of the set according to one of the identified classes, based on a lithography model, and selecting a probabilistic model function maximizing a probability of a class, given the set of mathematical representations; and during a testing phase, providing a very-large-scale integration design shape to be tested, testing the provided very-large-scale integration design shape, and labeling the provided very-large-scale integration design shape according to the identified class. | 02-02-2012 |
| 20120042297 | COMPUTER AIDED DESIGN SYSTEM AND METHOD - A computer aided design system comprises an interface creating module, a selecting module, a filling module and a measuring module. The interface module creates a user interface to display the design on the screen of the device with a plurality of to-be-checked patterns. The selecting module selects a pattern. The interface module further creates a parameter setting interface. The parameters comprises a predetermined width, the space value between the adjacent parallel filled lines and the rotation degree of the selected pattern. The filling module draws filled lines in the selected pattern according to the parameters. The measuring module detects whether the length of each filled line is at least the predetermined width value, if the length of the filled line is less than the predetermined width value, the dimension of the selected pattern is unqualified and the measuring module highlights the filled lines. | 02-16-2012 |
| 20120042298 | STRUCTURE HAVING SUBSTANTIALLY PARALLEL RESISTOR MATERIAL LENGTHS - A design structure including a pair of substantially parallel resistor material lengths separated by a first dielectric are disclosed. The resistor material lengths have a sub-lithographic dimension and may be spacer shaped. | 02-16-2012 |
| 20120060140 | Methods and Apparatus For Single Testing Stimulus - Methods and apparatus useful for improving the performance of testing and diagnostic operations on user circuit designs potentially across multiple phases of the development lifecycle and across multiple implementation technologies are described. As one example, a single testing and diagnostic stimulus source can variously provide test pattern data to different potential instantiations of the user circuit design by supporting and selectively utilizing a number of DUT-facing communication channels. | 03-08-2012 |
| 20120096424 | Interconnect and Transistor Reliability Analysis for Deep Sub-Micron Designs - A system and method for providing a statistical budgeting approach to modeling reliability effects such as interconnect electromigration (EM), transistor time-dependant dielectric breakdown (TDDB), hot-carrier injection effects (HCI) and bias temperature instability (BTI) is disclosed. A static analysis flow captures the effects of design topology, switching constraints, interactions between signal nets and supply rails as well as thermal gradients due to interconnect and transistor self as well as mutual heating, and was used to verify successive iterations of deep sub-micron integrated circuit designs. | 04-19-2012 |
| 20120102449 | METHOD AND APPARATUS FOR THERMAL ANALYSIS - Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout that includes numerous circuit modules. The method divides the IC design layout into a set of elements, where at least one element includes several wires. The method computes a set of conductivity groups of values for the set of elements. The method identifies a temperature distribution for the IC design layout based on the set of conductivity groups of values. In some embodiments, each of these elements corresponds to a particular portion of a particular layer of the IC design layout. Each element includes several nodes. Each conductivity group of values is defined by entry values. Each entry value describes how heat flow at a particular node of the element is affected by a temperature change at another particular node of the element. | 04-26-2012 |
| 20120117528 | SYSTEMS AND METHODS FOR CIRCUIT LIFETIME EVALUATION - Systems and methods for estimating the lifetime of an electrical system in accordance with embodiments of the invention are disclosed. One embodiment of the invention includes iteratively performing Worst Case Analysis (WCA) on a system design with respect to different system lifetimes using a computer to determine the lifetime at which the worst case performance of the system indicates the system will pass with zero margin or fail within a predetermined margin for error given the environment experienced by the system during its lifetime. In addition, performing WCA on a system with respect to a specific system lifetime includes identifying subcircuits within the system, performing Extreme Value Analysis (EVA) with respect to each subcircuit to determine whether the subcircuit fails EVA for the specific system lifetime, when the subcircuit passes EVA, determining that the subcircuit does not fail WCA for the specified system lifetime, when a subcircuit fails EVA performing at least one additional WCA process that provides a tighter bound on the WCA than EVA to determine whether the subcircuit fails WCA for the specified system lifetime, determining that the system passes WCA with respect to the specific system lifetime when all subcircuits pass WCA, and determining that the system fails WCA when at least one subcircuit fails WCA. | 05-10-2012 |
| 20120131536 | VERIFICATION APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND VERIFICATION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT - A verification apparatus for a semiconductor integrated circuit according to an embodiment includes a setting file storing unit having stored therein a list in which a scenario and a parameter used for verification are described and a transfer data generating unit configured to generate, on the basis of the list, transfer data used for the verification. The transfer data generating unit generates a tag in which information of the scenario is described. | 05-24-2012 |
| 20120159419 | MODEL LIBRARY IMPLEMENTATION AND METHODOLOGY FOR WORST CASE PERFORMANCE MODELING FOR SRAM CELLS - Worst case performance of an SRAM cell may be simulated more accurately with less intensive computations. An embodiment includes determining, by a processor, a process corner G of an SRAM cell, having pull-down, pass-gate, and pull-up devices, process corner G being defined as the worst performance of the cell when only global variations of parameters of the SRAM cell are included, setting each of the pull-down, pass-gate, and pull-up devices at process corner G, performing, on the processor, a number of Monte Carlo simulations of the SRAM cell devices around process corner G with only local variations of the parameters, generating a normal probability distribution for I | 06-21-2012 |
| 20120180019 | SYSTEM AND METHOD FOR STORING, USING AND EVALUATING MANUFACTURING DATA - A computer implemented method for evaluating quality control data of a product manufactured by a partially automated manufacturing process. In the method, a database is generated which includes design specifications for the product. Manufacturing data generated from inspection of the product at each stage of the partially automated process is then received. The manufacturing data is then compared with the design specifications to determine whether the manufacturing data meets the design specifications. In one embodiment, the product is an induction coil used in electric motors. | 07-12-2012 |
| 20120185818 | METHOD FOR SMART DEFECT SCREEN AND SAMPLE - A method for smart defect review is disclosed. The method includes pre-processing a design layout into a plurality of layout based pattern groups, dividing the design layout into a plurality of cells, overlapping the cells belong to the same layout based pattern groups, extracting a plurality of defect data of all defects on a wafer, constructing a plurality of layout based defect composite pattern groups, executing layout pattern match to obtain each individual layout based defect composite pattern group, performing some defect sample selection rules to each layout based defect composite pattern group, sorting the layout based defect composite pattern groups into different defect types, obtaining a defect image file by reviewing different sample number of defect image from each layout based defect composite pattern group, and generating a defect pattern library or a defect yield prediction by performing a defect yield diagnosis to the defect image file. | 07-19-2012 |
| 20120185819 | SYSTEM AND METHOD FOR VERIFYING PCB LAYOUT - In a method for verifying a printed circuit board (PCB) layout using a computing device, a PCB simulation file is obtained from a storage device of the computing device, and a PCB image is displayed on a display device according to the PCB simulation file. The PCB image includes multiple signal lines and switching voltage regulator nodes (SVRN). A SVRN to be checked is selected from the PCB image, and all signal lines around the SVRN are searched. The method calculates a layout distance between the selected SVRN and each of the searched signal lines, and generates a graphical window interface to position a signal line whose layout distance is equal to or less than the minimum distance. The method further modifies the layout of the positioned signal line to satisfy a layout design specification by increasing the layout distance to the minimum distance. | 07-19-2012 |
| 20120210291 | STATISTICAL FORMAL ACTIVITY ANALYSIS WITH CONSIDERATION OF TEMPORAL AND SPATIAL CORRELATIONS - Techniques for statistical formal activity analysis with consideration of temporal and/or spatial correlations are described herein. According to one embodiment, a sequential circuit having a feedback loop is unrolled into multiple unrolled circuits, where the sequential circuit is represented by a finite state machine (FSM). A temporal correlation is introduced to each of the unrolled circuits via a correlation network for an activity analysis of the sequential circuit. The temporal correlation represents a dependency relationship between a current logic state of a signal and a previous logic state of the signal. Other methods and apparatuses are also described. | 08-16-2012 |
| 20120216169 | DESIGN BASED DEVICE RISK ASSESSMENT - The present invention includes defining a multiple patterns of interest utilizing design data of the device; generating a design based classification database, the DBC database including design data associated with each of the POIs; receiving one or more inspection results; comparing the inspection results to each of the plurality of POIs in order to identify an occurrence of at least one of the POIs in the inspection results; determining yield impact of each POI utilizing process yield data; monitoring a frequency of occurrence of each of the POIs and the criticality of the POIs in order to identify process excursions of the device; and determining a device risk level by calculating a normalized polygon frequency for the device utilizing a frequency of occurrence for each of the critical polygons and a criticality for each of the critical polygons, the critical polygons defined utilizing design data of the device. | 08-23-2012 |
| 20120233582 | Coexistence Of Multiple Verification Component Types In A Hardware Verification Framework - Coexistence of multiple types of verification components in a single verification framework is provided. Particularly, the coexistence of proprietary e verification components in an open verification methodology framework is provided. | 09-13-2012 |
| 20120254820 | METHOD, A PROGRAM STORAGE DEVICE AND A COMPUTER SYSTEM FOR MODELING THE TOTAL CONTACT RESISTANCE OF A SEMICONDUCTOR DEVICE HAVING A MULTI-FINGER GATE STRUCTURE - Disclosed are embodiments for modeling contact resistance of devices, such as metal oxide semiconductor field effect transistors or varactors, that specifically have a multi-finger gate structure. In the embodiments, a set of expressions for total contact resistance are presented, in which (i) the total contact resistance is the sum of the resistance contribution from the contact (or the set of all contacts) in each diffusion region, (ii) the resistance contribution from the contact (or the set of all contacts) to the total contact resistance is the product of its resistance and the square of the relative electric current passing through it, and (iii) the electric current passing through the contact (or the set of all contacts) in a shared diffusion region (i.e., in an inner diffusion region) is twice of the electric current passing through the contact (or the set of all contacts) in an unshared diffusion region (i.e., in an outer diffusion region). | 10-04-2012 |
| 20120254821 | IMPLEMENTATION DESIGN SUPPORT METHOD AND APPARATUS - The disclosed method includes: identifying a first reference component from among first components defined in a first constraint condition that is a reference designated from among constraint conditions regarding a position relationship between plural components on a printed circuit board; identifying a second reference component from among second components defined in a second constraint condition that is to be compared with the first constraint condition and included in the constraint conditions; and identifying a fourth component that is a component other than the second reference component among the second components and has a correspondence with a third component, based on position relationships with the third component and an attribute of the third component, wherein the third component is a component other than the first reference component among the first components. | 10-04-2012 |
| 20120266126 | SYSTEMS AND METHODS OF DESIGNING INTEGRATED CIRCUITS - A method of designing an integrated circuit includes providing a cell library including a first and second cell structures. The cell structures each include a dummy gate electrode disposed on a boundary. An edge gate electrode is disposed adjacent to the dummy gate electrode. An oxide definition (OD) region has an edge disposed between the edge gate electrode and the dummy gate electrode. The method includes determining if the cell structures are to be abutted with each other. If so, the method includes abutting the cell structures. If not so, the method includes increasing areas of portions of the OD regions between the edge gate electrodes and the dummy gate electrodes. | 10-18-2012 |
| 20120278784 | ELECTRONIC DEVICE AND METHOD FOR CHECKING LAYOUT OF PRINTED CIRCUIT BOARD - In a method for checking layout of a printed circuit board (PCB) using an electronic device, a power line is selected from a layout diagram of the PCB. The method searches for one or more signal lines which are overlapping with the selected power line from the layout diagram of the PCB. The method further locates attribute data of the searched signal lines and the selected power line in the layout diagram of the PCB, and displays the attribute data of the searched signal lines and the selected power line on a display device of the electronic device. | 11-01-2012 |
| 20120278785 | RF CIRCUIT, CIRCUIT EVALUATION METHOD, ALGORITHM AND RECORDING MEDIUM - An RF circuit on a circuit simulator to be used in a microwave or millimeter wave range or a high-frequency range includes a function for being inserted by a first port and a second port thereof in a circuit to be observed, at an arbitrary cross-sectional point of the circuit, and evaluating a reflection coefficient (or a characteristic impedance) in the cross-section. The insertion loss between the first port and the second port is zero or approximately zero and is ignorable also for any finite system impedance other than zero. | 11-01-2012 |
| 20120291000 | ELECTRONIC DEVICE AND METHOD FOR DETECTING EQUIVALENT SERIES INDUCTANCE - In a method for detecting equivalent series inductances (ESL) of an electrical component of a printed circuit board (PCB), the electrical component and one or more signal lines connected with the electrical component are selected from a layout diagram of the PCB. The method selects a standard range of the ESL of the selected electrical component, calculates an ESL between each of the signal lines and a via hole corresponding to the signal line, and determines signal lines having ESL value that are not within the standard range. The method locates attribute data of the determined signal lines and the selected electrical component in the layout diagram of the PCB, and displays the attribute data of the determined signal lines and the selected electrical component on a display device. | 11-15-2012 |
| 20120297356 | COMPUTING DEVICE AND METHOD FOR INSPECTING LAYOUT OF PRINTED CIRCUIT BOARD - In a method for inspecting the layout of a printed circuit board (PCB), a component to be checked is determined from an electronic layout diagram of the PCB, and a power transmission line which may be serving that component is selected. The layout diagram is checked to determine whether the component is connected to the power transmission line, and further checked to determine whether more than one ground pins of the component is connected to the power transmission line. Vias that are shared by two or more ground pins of the component are determined if more than one ground pin is connected to the power transmission line. Shared vias are marked on the layout diagram. | 11-22-2012 |
| 20120297357 | METHOD AND APPARATUS FOR MULTI-DIE THERMAL ANALYSIS - Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies. | 11-22-2012 |
| 20120317533 | SYSTEM AND METHOD FOR DYNAMICALLY INJECTING ERRORS TO A USER DESIGN - A method and system for dynamically injecting errors to a user design is disclosed. In one embodiment, the user design having internal states and parameters is run in a design verification system. A reconfigurable design monitor monitors a plurality of error conditions based on the internal states and parameters of the user design and generates a trigger event when a predefined error condition is met. The reconfigurable design monitor transmits a trigger event to an error injector. The error injector injects dynamic errors associated with the triggering event to the user design via a control path to test the user design under the predefined error condition. | 12-13-2012 |
| 20120317534 | Merging Line and Condition Coverage Data - An approach is provided that receives a correlation data structure from a memory. The correlation data structure indicates a number of expected test event triggers that correspond to a test case that includes a number of test events. The test case is executed by a computer processor, the execution resulting in one or more resultant data structures stored in the memory. The resultant data structures indicate one or more actual test event triggers that occurred during the execution. A base key value is generated corresponding to each of the resultant data structures. A scalar array is searched for the base key values. In response to finding base key values, a counter corresponding to the base key values is incremented. However, if base key values are not found in the scalar array, then the base key values are added to the scalar array and the added entries are initialized. | 12-13-2012 |
| 20120324414 | BDD-BASED FUNCTIONAL MODELING - A computer-implemented method, apparatus, and computer program product for assisting in dynamic verification of a System Under Test (SUT). The method comprising obtaining a set of functional attributes and associated domains with respect to a System Under Test (SUT), and obtaining a set of restrictions over the functional attributes and associated domains. The method comprising encoding a Binary Decision Diagram (BDD) to represent a Cartesian cross-product test-space of all possible combinations of values of the functional attributes excluding combinations that are restricted by the set of restrictions, whereby the BDD symbolically represents the Cartesian cross-product test-space. The method may further comprise analyzing the Cartesian cross-product test-space by manipulating the BDD so as to assist in performing dynamic verification of the SUT. | 12-20-2012 |
| 20120331437 | ELECTRONIC DEVICE AND METHOD FOR CHECKING LAYOUT OF PRINTED CIRCUIT BOARD - In a method for checking layout of a printed circuit board (PCB) using an electronic device, a signal line is selected from a layout diagram of the PCB. The method searches for signal lines which have an acute angle when deviating from a straight line in the layout diagram of the PCB. The method further locates attribute data of the searched signal lines in the layout diagram of the PCB, and displays the attribute data of the searched signal lines on a display device of the electronic device. | 12-27-2012 |
| 20130007692 | TOOL AND METHOD FOR MODELING INTERPOSER RC COUPLINGS - A method comprises analyzing front side conductive patterns and back side conductive patterns on a semiconductor interposer using a machine implemented RC extraction tool, and outputting data representing a plurality of respective RC nodes from the RC extraction tool to a tangible persistent machine readable storage medium. A substrate mesh model of the semiconductor interposer is generated, having a plurality of substrate mesh nodes. Each substrate mesh node is connected to adjacent ones of the plurality of substrate mesh nodes by respective substrate impedance elements. A set of inputs to a timing analysis tool is formed. The plurality of RC nodes are connected to ones of the plurality of substrate mesh nodes of the substrate mesh model. The set of inputs is stored in a tangible machine readable storage medium. | 01-03-2013 |
| 20130014074 | Incremental Modification of Instrumentation Logic - A method and system for incremental updating of instrumentation logic in integrated circuit designs. During debugging of a circuit design, instrumented signals are modified without rerunning synthesis and place and route. According to an embodiment, instrumentation logic is incrementally changed by the following operations: Building a list of available signals, modifying one or more instrumented signals, connecting or disconnecting the modified signals, and rerouting the modified signals. | 01-10-2013 |
| 20130014075 | DESIGN-DEPENDENT INTEGRATED CIRCUIT DISPOSITION - A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of at least one test structure. | 01-10-2013 |
| 20130019222 | System and Method for Detecting Parasitic Thyristors in an Integrated CircuitAANM Domanski; KrzysztofAACI MuenchenAACO DEAAGP Domanski; Krzysztof Muenchen DEAANM Schneider; JensAACI MuenchenAACO DEAAGP Schneider; Jens Muenchen DEAANM Jungmann; AngelikaAACI UnterhachingAACO DEAAGP Jungmann; Angelika Unterhaching DE - In an embodiment, a method includes retrieving a layout of an integrated circuit design from a non-transitory computer readable medium, identifying a silicon controlled rectifier (SCR) structure in the layout, identifying a current injection site in the layout, and determining if a distance between the identified current injection site and the identified SCR structure is less than a first threshold. A violation is flagged if the determined distance is less than the first threshold. | 01-17-2013 |
| 20130042218 | METHOD OF SIMULATING AN ESD CIRCUIT LAYOUT - A method of simulating an electrostatic discharge (ESD) circuit layout is disclosed. A netlist of an electronic circuit is pre-simulated. A circuit layout, including an ESD circuit layout, is accordingly generated. Parasitic is extracted according to the generated circuit layout. The ESD circuit layout is post-simulated according to an ESD waveform and a result of the parasitic extraction. | 02-14-2013 |
| 20130047133 | VALIDATION OF CIRCUIT DEFINITIONS - Systems and methods for validating a circuit design are described. The circuit validation includes determining a subset of checks to apply to a portion of the overall circuit based on the pin type composition of the circuit portion. | 02-21-2013 |
| 20130055190 | COMPUTING DEVICE AND METHOD FOR CHECKING DESIGN OF PRINTED CIRCUIT BOARD LAYOUT FILE - A computing device reads a printed circuit board (PCB) layout file from a storage device. The PCB layout file includes arrangement information of signal lines, power lines, and power through-holes arranged on a PCB. Furthermore, the computing device sets a reference distance between a selected power through-hole and a neighboring signal line, and searches for one or more line segments of one or more signal lines where the a distance between each of the one or more line segment and the selected power through-hole is less than the reference distance. | 02-28-2013 |
| 20130055191 | Method and Software Tool for Analyzing and Reducing the Failure Rate of an Integrated Circuit - A software tool and method for analyzing the reliability or failure rate of an integrated circuit (IC) are disclosed. The IC may include a plurality of circuit designs, and the software tool and method may aid a designer of the IC in determining a reliability rating of the IC based on reliability ratings of transistors or other circuit devices used in the circuit designs. In particular, the IC may include one or more circuit designs that have multiple instances within the IC (i.e., the same circuit design is instantiated multiple times), and the software tool and method may take into account the multiple instances when determining the reliability rating of the IC. | 02-28-2013 |
| 20130061197 | WIRE HARNESS CONTINUITY INSPECTION METHOD AND WIRE HARNESS CONTINUITY INSPECTION PROGRAM - It is possible to optimize the time required for a success/failure determination step and the accuracy of the success/failure determination step by determining region-based connector/wiring information to be created and increasing or decreasing the number of patterns of the region-based connector/wiring information. When a wire harness is arranged in each partitioned area of a vehicle space, specifications satisfied by the vehicle are referenced, region-based connector/wiring information described for a wire harness arranged in each partitioned area realizing a predetermined specification is created, and the presence/absence of errors in connections of electric wires is inspected for the created region-based connector/wiring information. | 03-07-2013 |
| 20130080991 | PATTERN FORMING APPARATUS - According to one embodiment, a pattern forming apparatus includes a control unit. The control unit is configured to execute a test patterning to same patterns using probes under same conditions, obtain a position error and a size error by comparing a position and a size of the same patterns with a target value, select a normal probe in which the position error and the size error is in an allowable range among the probes, execute a correction process which adjusts sub patterning areas which are patterned by the normal probe among a main patterning area of a substrate, and execute a patterning of the sub patterning areas using the normal probe. | 03-28-2013 |
| 20130097576 | COMPUTING DEVICE AND METHOD FOR CHECKING VIA STUB - A computer-based method and a computing device for checking stub lengths of via stubs of a printed circuit board (PCB) layout are provided. The computing device displays a check interface, selects signal transmission line from a currently run PCB layout through the check interface, receives a reference stub length input through the check interface, and determines the actual stub length of each via stub of each via each selected signal transmission line connected to. The computing device further determines that a design of one via stub satisfies the design standards, if the actual stub length of the one stub via is less than or equal to the reference length, and determines that a design of one via stub does not satisfy the design standards if the actual stub length of the one via stub is greater than the reference stub length. | 04-18-2013 |
| 20130125082 | COMPUTING DEVICE AND METHOD FOR AUTOMATICALLY CHECKING WIRING INFORMATION - In a computing device, a computerized method and a non-transitory storage medium are applied in checking a stored wiring diagram for high-noise components in close proximity to signal lines. An electronic component is selected in a PCB wiring file. A checking range of the selected electronic component is determined for searching for one or more signal transmission lines which pass within the checking range in the PCB wiring file. Basic information of the one or more signal transmission lines is recorded into a result list which is displayed on a display unit of the computing device. | 05-16-2013 |
| 20130125083 | POWER-SUPPLY DESIGN SYSTEM, POWER-SUPPLY DESIGN METHOD, AND PROGRAM FOR POWER-SUPPLY DESIGN - A power-supply design system for designing a power supply of electronic equipment apparatuses. The system includes an input device for inputting circuit information about the power supply of the electronic equipment apparatus; a current deviation computation unit that computes an electric current deviation which indicates electric current variation of the electronic equipment apparatus, based on the circuit information input using the input device, and dispersion information that indicates a dispersion of an electric current variation, which corresponds to the circuit information; a target impedance computation unit that computes a target impedance as a target for the power supply indicated by the circuit information, based on the electric current deviation computed by the current deviation computation unit and a permissible range of a voltage variation, where the permissible range is indicated by the circuit information; and an output device that outputs the target impedance computed by the target impedance computation unit. | 05-16-2013 |
| 20130132925 | METHOD, SYSTEM AND PROGRAM STORAGE DEVICE FOR GENERATING ACCURATE PERFORMANCE TARGETS FOR ACTIVE SEMICONDUCTOR DEVICES DURING NEW TECHNOLOGY NODE DEVELOPMENT - Disclosed are embodiments of a method, system and program storage device for generating accurate performance targets for active semiconductor devices during technology node development in order to reduce the number of iterations required for model extraction and/or to improve model quality. In these embodiments, initial sets of performance targets for related semiconductor devices are generated, e.g., by making assumptions based on hardware measurements taken from semiconductor devices in prior technology nodes. Additional processes are then performed on the initial sets of performance targets prior to the modeling stage in order to detect and resolve any inconsistencies between the data in the sets. Specifically, plotting techniques are performed with respect to the performance targets. The results are analyzed to detect any inconsistencies indicating that the performance targets are inaccurate and adjustments are made to the performance targets in order to resolve those inconsistencies. | 05-23-2013 |
| 20130139123 | COMPUTING DEVICE AND METHOD FOR CIRCUIT DIAGRAM DATA CHECK - A method to check circuit diagram data using a computing device. The computing device inserts the circuit diagram data into an application having an ordering function. The computing device sets a condition to screen out the circuit diagram data in the application having the ordering function, and reads an item of the circuit diagram data. The computing device marks the item of the circuit diagram data if the item of the circuit diagram data does not satisfy the condition. | 05-30-2013 |
| 20130145340 | Determination Of Uniform Colorability Of Layout Data For A Double Patterning Manufacturing Process - Graph structures are obtained corresponding to geometric elements in the lowest hierarchical level of cells in a design of hierarchical layout data. Each graph structure then is analyzed for conflicts that would preclude an error-free partitioning of the represented geometric elements into two complementary sets. If there are no conflicts, then relevant portions of each graph structure are promoted into the corresponding parent cells of the next highest hierarchical level of the hierarchical layout design. This process of obtaining graph structures for cells of a hierarchical level, checking the graph structures to determine if they have conflicts, and promoting relevant portions of the graph structures to the graph structures for the next hierarchical level is iteratively repeated for each level in the hierarchical layout design, until a conflict is detected or until it is determined that no conflicts exist for the graph structure corresponding to the highest level cell. | 06-06-2013 |
| 20130145341 | SEMICONDUCTOR CIRCUIT DESIGN SUPPORT TECHNIQUE - A computer readable storage medium stores a semiconductor circuit design support program that causes a computer to execute a process. The process includes identifying wirings connected to a selected cell to be processed from an observation target circuit data storage device storing position data of each cell on a semiconductor chip on which an observation target circuit is implemented for which operations are observed in simulation and data of wirings connected to each cell. The process further includes determining an operational ratio for the selected cell from operational ratios of the identified wirings, reading out position data of the selected cell from the observation target circuit data storage device, and generating and outputting image data in which display data corresponding to the operational ratio of the selected cell is disposed according to the position data of the selected cell on a display area corresponding to the semiconductor chip. | 06-06-2013 |
| 20130152037 | COMPUTER AIDED DESIGN SYSTEM AND METHOD - A computer aided design system comprises an interface creating module, a reference layer setting module, a detecting module and a signing module. The interface module creates a parameter setting interface to select at least one net being composed of a plurality of cline segments, and set a stack distance. The reference layer setting module sets a reference layer for the layer contained the selected net based on the stack distance. The detecting module obtains a projection of the cline segment of the selected net on the reference layer, sets a region corresponding to the cline segment on the reference layer, detects whether the projection extends out of the set region, and generates a signing signal to sign the cline segment when the projection does extend out of the set region. The signing module signs the cline segment according to the sign signal. | 06-13-2013 |
| 20130167103 | System and Method For Use Case-Based Thermal Analysis of Heuristically Determined Component Combinations and Layouts In A Portable Computing Device - Various embodiments of methods and systems for heuristic determination and thermal analysis of component placement on a printed circuit board (“PCB”) for use in a portable computing device (“PCD”) are disclosed. It is an advantage of embodiments that thermal energy generating components, such as processors, may be heuristically selected and arranged on a selected PCB according to varying layouts and combinations and then evaluated for thermal dissipation efficiency under an assortment of use case scenarios. In this way, users of the system and method may quickly narrow down commercially feasible component layouts, identify the most efficient layouts and then heuristically modify the layouts to develop an optimal arrangement. | 06-27-2013 |
| 20130191805 | Simulation Of Circuits With Repetitive Elements - Aspects of the invention relate to simulation of circuits with repetitive elements. With various implementations of the invention, a circuit design for simulation is analyzed to derive information of memory-circuit device groups that comprise word-line-driven device groups. If the circuit design is hierarchically structured, the circuit design is flattened to the device level but keep the memory-circuit device groups intact. The circuit design is then partitioned into a plurality of subcircuits for simulation. During transient simulation, whether an instance of a word-line-driven device group is activated is first determined. If activated, whether device model values exist for the word-line-driven device group at a voltage state associated with the activated instance is then determined. If they exist, the device model values are associated with the activated instance. If they do not exist, the device model values are computed for, stored for and associated with the activated instance. | 07-25-2013 |
| 20130191806 | DESIGN SYSTEM FOR SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE AND METHOD FOR BONDING SUBSTRATES - The terminals that oppose each other when substrates are bonded are designed to be reliably joined. Comprised in a semiconductor device design system are a numerical value acquiring part, which acquires the respective numerical values of a plurality of calculation parameters, a junction estimating part, which, in the case in which a plurality of substrates has been pressed at a prescribed pressure so that the bump front end faces come into contact, estimates whether or not the respective mutually opposing bumps will be joined based on the respective numerical values of the calculation parameters acquired by the numerical value acquiring part, and a change processing part, which, in the case in which it has been estimated by the junction estimating part that any of the bumps will not be joined, gives a warning or performs processing so as to change the numerical value of at least one calculation parameter among the plurality of calculation parameters. | 07-25-2013 |
| 20130191807 | METHOD OF EVALUATING SYSTEMATIC DEFECT, AND APPARATUS THEREFOR - In order to enable an evaluation of systematic defects, a method of evaluating systematic defects was configured so as to sample a circuit pattern of a specific layer of a semiconductor device, evaluate the state of superimposition between the sampled circuit pattern and circuit patterns of layers other than the specific layer, using design data, classify the state of superimposition, calculate the ratio thereof as a reference ratio, evaluate the state of superimposition between a pattern in design data corresponding to a defect of the specific layer detected by another inspection apparatus and patterns at positions corresponding to the defects in layers other than the specific layer, classify the evaluated state of superimposition, calculate the ratio of the classification as inspection-result ratio, compare the calculated reference ratio and the calculated inspection-result ratio, and evaluate systematic defects by the comparison between the calculated reference ratio and the calculated inspection-result ratio. | 07-25-2013 |
| 20130227513 | GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS - In a first embodiment a TAP | 08-29-2013 |
| 20130227514 | Method of Generating RC Technology File - A method of generating resistance-capacitance (RC) technology files is disclosed. The method comprises receiving a plurality of metal schemes from an IC foundry and dividing the plurality of metal schemes into one or more modular RC groups. The method further comprises identifying a modular RC structure; calculating capacitance values of the modular RC structure by means of a field solver; calculating an equivalent dielectric constant and an equivalent height of the RC structure based upon a variety of interconnect layers not having interconnects; calculating an equivalent dielectric constant and an equivalent height for each of the plurality of metal schemes; and deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the modular RC structure. | 08-29-2013 |
| 20130232462 | EQUIVALENT CIRCUIT OF BIDIRECTIONAL SWITCH, SIMULATION METHOD FOR BIDIRECTIONAL SWITCH, AND SIMULATION DEVICE FOR BIDIRECTIONAL SWITCH - Provided is a simulation method for simulating electrical properties of a bidirectional switch formed as a single element and having a double gate structure. A simulation is performed using an equivalent circuit having a symmetrical structure in which a drain electrode of a JFET and a drain electrode of another JFET are connected via a resistor. | 09-05-2013 |
| 20130239083 | METHOD AND PROGRAM FOR CREATING EQUIVALENT CIRCUIT - In a method for creating an equivalent circuit for a three-terminal capacitor including first, second, third and fourth terminals, a first capacitor conductor connected between the first and second terminals, and a second capacitor conductor connected between the third and fourth terminals, the equivalent circuit includes a first line connecting the first terminal to the second terminal; a second line connecting the third terminal to the fourth terminal; a third line that includes a first capacitor component and that connects the first line to the second line; a first circuit component including at least one of a first inductor component and a first resistor component provided between a connection portion between the second line and the third line and the third terminal; and a second circuit component including at least one of a second inductor component and a second resistor component provided between the connection portion and the fourth terminal. | 09-12-2013 |
| 20130239084 | MEASURE OF ANALYSIS PERFORMED IN PROPERTY CHECKING - The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N. | 09-12-2013 |
| 20130246994 | WIRING CHECK DEVICE AND WIRING CHECK SYSTEM - The purpose of the present invention is to provide a wiring check device, a wiring check system, a wiring check method, a wiring check program, and a recording medium, which are capable of taking into account a difference in the shape of a slit to find a risk of the worsening of electromagnetic noise characteristics. A wiring check device comprising: a wiring information acquiring unit for acquiring the wiring information of wiring; a first plane conducting body detecting unit for detecting a first plane conducting body adjacent to the wiring; a crossing wiring determining unit for detecting overlapped projections of the wiring and the first plane conducting body, and determining whether or not the wiring is a crossing wiring crossing a border line between a forming region of the first plane conducting body and a non-forming region of the first plane conducting body; and a closed curve length detecting unit for detecting closed curve length of the border line if it is determined that the wiring is a crossing wiring. | 09-19-2013 |
| 20130263078 | METHOD FOR GENERATING TASK DATA OF A PCB AND INSPECTING A PCB - A method for generating PCB inspection task data and inspecting a PCB is disclosed. The method by which Gerber data and CAD coordinate file generated at the time of PCB designing is matched to each other facilitates to generate a task data and allows a higher inspection accuracy. The task data generating method comprises generating a Gerber data comprising information for pads on the PCB, loading a CAD coordinate file comprising a coordinate of a component mounted on the pads, inferring a shape of lead and body of the component within a pad area by matching the Gerber data and CAD coordinate file, and then setting a pad area where a tip-end of the body locates as an inspection area. | 10-03-2013 |
| 20130283227 | PATTERN REVIEW TOOL, RECIPE MAKING TOOL, AND METHOD OF MAKING RECIPE - A recipe necessary for a review tool or the like to image an image is efficiently made in order to identify a cause of a failed position on the basis of a result of a failure analysis system. | 10-24-2013 |
| 20130298101 | METHOD AND APPARATUS FOR IMPROVED INTEGRATED CIRCUIT TEMPERATURE EVALUATION AND IC DESIGN - A method and apparatus generates thermal partitions for metal interconnects of an integrated circuit, based on interconnect self heat data and mutual heat data. Each of the thermal partitions includes data identifying thermally related interconnects and respective temperature values associated with each of the thermally related interconnects. Thermally related partitions that can be computed efficiently and simultaneously and the results then integrated using superposition for the full chips. | 11-07-2013 |
| 20130298102 | Input Space Reduction for Verification Test Set Generation - Various embodiments provide for the determination of a test set that satisfies a coverage model, where portions of the search space need not be searched in order to generate the test set. With various embodiments, a search space defined by a set of inputs for an electronic design and a coverage model is identified. The search space is then fractured into subspaces. Subsequently, the subspaces are solved to determine if they include at least one input sequence that satisfies the coverage constraints defined in the coverage model. The subspaces found to include at least one input sequence that satisfies these coverage constraints, are then searched for unique input sequences in order to generate a test set. Subspaces found not to include at least one input sequence that satisfies the coverage constraints may be excluded from the overall search space. | 11-07-2013 |
| 20130305206 | Measurement Model Optimization Based On Parameter Variations Across A Wafer - An optimized measurement model is determined based a model of parameter variations across a semiconductor wafer. A global, cross-wafer model characterizes a structural parameter as a function of location on the wafer. A measurement model is optimized by constraining the measurement model with the cross-wafer model of process variations. In some examples, the cross-wafer model is itself a parameterized model. However, the cross-wafer model characterizes the values of a structural parameter at any location on the wafer with far fewer parameters than a measurement model that treats the structural parameter as unknown at every location. In some examples, the cross-wafer model gives rise to constraints among unknown structural parameter values based on location on the wafer. In one example, the cross-wafer model relates the values of structural parameters associated with groups of measurement sites based on their location on the wafer. | 11-14-2013 |
| 20130305207 | METHOD FOR DETECTING AND DEBUGGING DESIGN ERRORS IN LOW POWER IC DESIGN - A method for detecting anomalies in signal behaviors in a simulation of a low power IC includes receiving a circuit design and a power specification of the IC, determining at least one power sequence checking rule from the power specification, simulating the circuit design and the power specification to obtain a dump file, identifying at least one anomaly of the at least one power sequence checking rule based on the dump file, and generating information relevant to the identified anomaly of the at least one power sequence checking rule. The method further includes setting up a context in a debugger for debugging the anomaly by displaying a waveform of misbehaved signals associated with the anomaly in a waveform window, and a portion of the circuit design and/or a portion of the power specification associated with the anomaly in a text window. | 11-14-2013 |
| 20130305208 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR DESIGINING THE SAME - A semiconductor integrated circuit according to one embodiment includes a plurality of flip-flop groups configured by dividing a plurality of flip-flops, connected in series, for carrying out a serial operation of serially transferring data, a continuous signal determination circuit configured to output a first signal if outputs of the flip-flops contained in the flip-flop group match, and output a second signal in other cases; and a clock gating circuit configured not to provide a clock signal when receiving the first signal and to provide a clock signal when receiving the second signal with respect to the flip-flops other than a head of the flip-flop group. | 11-14-2013 |
| 20130311966 | CIRCUIT DESIGN SUPPORT APPARATUS, COMPUTER-READABLE RECORDING MEDIUM, AND CIRCUIT DESIGN SUPPORT METHOD - A circuit design support apparatus includes a simulating unit that simulates the operation of each circuit in a predetermined network on the basis of circuit information indicating the network, and generates simulated waveform information; a control unit that performs control so that simulated waveform information, which is information indicating a state of a signal of a terminal of each circuit in the network simulated by the simulating unit and is information for a period of time depending on the number of stages of sequential circuits in the circuit, is stored in a storage unit; and an output unit that outputs, when an error has been detected in a predetermined terminal, the simulated waveform information for the period of time stored in the storage unit to a waveform file for error analysis. | 11-21-2013 |
| 20130326461 | METHOD FOR DETECTING INTERFERENCE IN SPATIAL STRUCTURE - A method for detecting interference in spatial structure is provided. The method includes the following steps. A circuit board is obtained, wherein the circuit board has set a first height limit, and parts of the coordinate areas have set a plurality of second height limits respectively. The second height limits are lower than the first height limit. A Keep-out area is established according to the second height limits of the coordinate areas and the first height limit. The corresponding height of each coordinate area in a substrate-boarded space is compared according to the keep-out area to simulate and determine whether the circuit board is interfered in the substrate-boarded space. Thus, users can immediately check whether interference or clashed in space occurs between the circuit board and the substrate-boarded space. | 12-05-2013 |
| 20130326462 | Method and Device For Reconstructing Scan Chains Based On Bidirectional Preference Selection in Physical Design - Provided are methods and devices of organizing scan chains in an integrated circuit. One method comprises generating first preference information representing prioritized listing of a plurality of scanning elements for each of a plurality of scan chains based on a first criterion, generating second preference information representing prioritized listing of the plurality of scan chains for each of the plurality of scanning elements based on a second criterion and at a computing device, assigning each of the plurality of the scanning elements to one of the plurality of the scan chains based on the first preference information and the second preference information. | 12-05-2013 |
| 20130339919 | Method and Apparatus for Hierarchical Wafer Quality Predictive Modeling - A method for performing enhanced wafer quality prediction in a semiconductor manufacturing process includes the steps of: obtaining data including at least one of tensor format wafer processing conditions, historical wafer quality measurements and prior knowledge relating to at least one of the semiconductor manufacturing process and wafer quality; building a hierarchical prediction model including at least the tensor format wafer processing conditions; and predicting wafer quality for a newly fabricated wafer based at least on the hierarchical prediction model and corresponding tensor format wafer processing conditions. | 12-19-2013 |
| 20140013296 | ESD ANALYSIS APPARATUS - According to one embodiment, a chip model generating unit and a counter tester ground capacitance adding unit are provided. The chip model generating unit generates a chip model based on an ESD protection circuit network model to which an inter power net capacitance of a semiconductor chip is added. The counter tester ground capacitance adding unit adds a counter tester ground capacitance to the chip model. | 01-09-2014 |
| 20140033164 | MUTUAL INDUCTANCE EXTRACTION USING DIPOLE APPROXIMATIONS - Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for instance, a circuit description indicative of the layout of signal wires and ground wires in the circuit is received. The signal wires and the ground wires are grouped into at least a first bundle and a second bundle, wherein the first bundle and the second bundle each comprise a respective signal-wire segment and one or more corresponding ground-wire segments. A representative dipole moment is calculated for the first bundle. Using the representative dipole moment, the mutual inductance between the first bundle and the second bundle is calculated. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing design databases created or modified using any of the disclosed techniques are also disclosed. | 01-30-2014 |
| 20140040852 | SYSTEMS AND METHODS FOR CHARACTERIZING DEVICES - A device characterization system includes a characterization tool and a test flow development generator. The characterization tool is configured to perform testing on a product device according to a test flow and generate test data. The characterization tool includes a list of available test instances that can be performed. The test flow development generator is configured to automatically generate the test flow according to device specifications for the product device and selected test instances of the list of available test instances. | 02-06-2014 |
| 20140059511 | Generating Root Cause Candidates For Yield Analysis - Aspects of the invention relate to yield analysis techniques for generating root cause candidates for yield analysis. With various implementations of the invention, points of interest are first identified in a layout design. Next, regions of interest are determined for the identified points of interest. Next, one or more properties are extracted from the regions of interest. Based at least on the one or more properties, diagnosis reports of failing devices fabricated according to the layout design are analyzed to identify probable root causes. | 02-27-2014 |
| 20140115555 | VERIFICATION SUPPORT COMPUTER PRODUCT, APPARATUS, AND METHOD - A non-transitory, computer-readable recording medium stores therein a verification support program that causes a computer to execute identifying from a finite state machine model related to a circuit-under-test, an input count of transitions to a transition-end state and an output count of transitions from the transition-end state; determining the transition-end state to be a record/restore subject, if the identified output transition>the identified input transition count; embedding record-instruction information causing the record/restore subject to be recorded to a database, if a first element causing transition to the record/restore subject is included in a first test scenario that is in a test scenario group related to the circuit-under-test; and embedding restore-instruction information causing the record-restore subject to be restored from the database, if a second element causing transition to the record-restore subject is included in a series of elements making up a second test scenario that is in the test scenario group. | 04-24-2014 |
| 20140115556 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 04-24-2014 |
| 20140123096 | COMPUTING DEVICE AND METHOD FOR VIEWING RELEVANT CIRCUITS OF SIGNAL ON CIRCUIT DESIGN DIAGRAM - In a method for viewing relevant circuits of a signal on a circuit design diagram of a printed circuit board (PCB), a circuit design diagram and a circuit testing program of the PCB are read from a storage system. A state of each signal of the PCB on the circuit design diagram is determined. Accordingly, sub circuit design diagrams of the signal are obtained from the circuit design diagram and stored into the storage device. When a testing instruction is selected from the circuit testing program, a signal of the PCB is determined. Sub circuit design diagrams of the determined signal are retrieved from the storage device and displayed on a display device. | 05-01-2014 |
| 20140123097 | COMPACT MODEL FOR DEVICE/CIRCUIT/CHIP LEAKAGE CURRENT (IDDQ) CALCULATION INCLUDING PROCESS INDUCED UPLIFT FACTORS - A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis. | 05-01-2014 |
| 20140157222 | ESTIMATING POWER SUPPLY OF A 3D IC - Embodiments of present invention include a method and apparatus of estimating power supply of a 3D IC. The method particularly includes obtaining current information and layout information of circuit modules contained in a specific region of the 3D IC, gridding the specific region so as to form at least one three-dimensional grid having a plurality of side edges along chip stacking direction of the 3D IC, determining current of at least one of the plurality of side edges based on the current information and layout information of the circuit modules, and estimating power supply of the 3D IC based on the current of the at least one side edge. With the method and apparatus embodiments of the invention, power supply of a 3D IC may be effectively estimated and analyzed. | 06-05-2014 |
| 20140165023 | METHOD OF RECORDING AND REPLAYING CALL FRAMES FOR A TEST BENCH - A computer-implemented method to debug testbench code of a testbench associated with a circuit design by recording a trace of call frames along with activities of the circuit design. By correlating and displaying the recorded trace of call frames, the method enables users to easily trace as execution history of subroutines executed by the testbench thereby to debug the testbench code. In addition, users can trace source code of the testbench code by using the recorded trace of call frames. Furthermore, users can debug the testbench code utilizing a virtual simulation, which is done by post-processing records of the virtual simulation stored in a database. | 06-12-2014 |
| 20140165024 | STATISTICAL FORMAL ACTIVITY ANALYSIS WITH CONSIDERATION OF TEMPORAL AND SPATIAL CORRELATIONS - Techniques for statistical formal activity analysis with consideration of temporal and/or spatial correlations are described herein. According to one embodiment, a machine-implemented method for circuit analysis comprises unrolling a sequential circuit having a feedback loop into a plurality of unrolled circuits and introducing a spatial correlation via an encoding circuit coupled to the plurality of unrolled circuits for an activity analysis of the sequential circuit, the spatial correlation representing a dependency relationship between logic states of an input and logic states of other signals. | 06-12-2014 |
| 20140173546 | Method and system to view and analyze state model transition on host/semiconductor equipment for 300mm standards - The embodiments herein disclose a method and system to view and analyze state model transition on host/equipment for 300 mm standards. A state transition module is developed for effectively viewing and analyzing state model transition occurring on the host/equipment using 300 mm standards. The state transition module can be integrated with any host simulator software/equipment to validate the state machine. The transitions of state models can be viewed at runtime dynamically by reading the actual events from the network ports sent by the equipment/host. The method provides the user interface to know the state model transition including providing a statistical analysis of the job execution and the data collection events. | 06-19-2014 |
| 20140173547 | ANALYSIS OF CHIP-MEAN VARIATION AND INDEPENDENT INTRA-DIE VARIATION FOR CHIP YIELD DETERMINATION - Systems and methods for determining a chip yield are disclosed. One system includes a first level integration solver and a second level integration solver. The first level integration solver is configured to obtain a first probability distribution function modeling variations within a chip and to perform a discontinuous first level integration with the first probability distribution function. In addition, the second level integration solver is implemented by a hardware processor and is configured to perform a continuous second level integration based on a second probability distribution function modeling variations between dies to determine the chip yield. | 06-19-2014 |
| 20140173548 | Tool For Automation Of Functional Safety Metric Calculation And Prototyping Of Functional Safety Systems - A tool for performing a functional safety analysis of an integrated circuit device tailored to a customer's specific application and implementation of the device. Information regarding a user's specific implementation of a given integrated circuit device is provided by the customer as input to the safety analysis tool. The tool then automatedly performs a functional safety analysis based on the information regarding the user's specific implementation of the integrated circuit device. In one embodiment, the customer specifies specific functional modules of the integrated circuit device, and the tool performs a functional safety analysis of the integrated circuit device that considers the functional modules selected by the user. In another embodiment, the customer specifies diagnostic measures that are implemented in the user's application of the integrated circuit device, and the tool automatedly performs a functional safety analysis of the integrated circuit device taking into account the diagnostic measures selected by the user. | 06-19-2014 |
| 20140173549 | COMPUTING DEVICE AND METHOD OF CHECKING WIRING DIAGRAMS OF PCB - In a method for checking a wiring diagram in a printed circuit board (PCB) design, a pair of differential signal lines in a PCB file is located according to a designation of a user. Components connected by the differential signal lines and vias which the differential signal lines pass through are obtained from the PCB file. A determination of whether obtained components and the obtained vias meet predetermined requirements is made by checking whether copper foils between each pair of the obtained vias or between pins of the obtained components in ground layers and power layers of the PCB file are hollowed. | 06-19-2014 |
| 20140181780 | ELECTROMIGRATION ANALYSIS FOR STANDARD CELL BASED DESIGNS - Methods and media for analyzing electrical designs are provided. A method includes and the media are configured for providing or loading to an analysis tool a design that includes a plurality of cell instances of a standard cell and estimating a failure rate of the design using in context electrical parameters for the plurality of cell instances and a parameterized electromigration (EM) view of the standard cell. Another method includes providing a standard cell of a standard cell library and characterizing the standard cell to create a parameterized thermal model to compute a temperature of an internal structure of the standard cell and a parameterized current model to compute a current through the internal structure of the standard cell given in context electrical parameters. | 06-26-2014 |
| 20140181781 | DESIGN SYSTEM FOR SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE AND METHOD FOR BONDING SUBSTRATES - The terminals that oppose each other when substrates are bonded are designed to be reliably joined. Comprised in a semiconductor device design system are a numerical value acquiring part, which acquires the respective numerical values of a plurality of calculation parameters, a junction estimating part, which, in the case in which a plurality of substrates has been pressed at a prescribed pressure so that the bump front end faces come into contact, estimates whether or not the respective mutually opposing bumps will be joined based on the respective numerical values of the calculation parameters acquired by the numerical value acquiring part, and a change processing part, which, in the case in which it has been estimated by the junction estimating part that any of the bumps will not be joined, gives a warning or performs processing so as to change the numerical value of at least one calculation parameter among the plurality of calculation parameters. | 06-26-2014 |
| 20140181782 | WIRELESS ENERGY TRANSFER MODELING TOOL - A method includes defining and storing one or more attributes of a source resonator and a device resonator forming a system, defining and storing the interaction between the source resonator and the device resonator, modeling the electromagnetic performance of the system to derive one or more modeled values and utilizing the derived one or more modeled values to design an impedance matching network. | 06-26-2014 |
| 20140189635 | SEMICONDUCTOR DEVICE DESIGN METHOD, SYSTEM AND COMPUTER-READABLE MEDIUM - A semiconductor device design system comprising at least one processor is configured to define a resistance-capacitance (RC) extraction tool for determining a distance between first and second through-semiconductor-vias extracted from a layout of a semiconductor device. The semiconductor device has a semiconductor substrate and the first and second through-semiconductor-vias in the semiconductor substrate. The semiconductor device design system comprising the at least one processor is also configured to extract parasitic parameters of a coupling in the semiconductor substrate based on the distance determined by the RC extraction tool and a model of the coupling included in a simulation tool. | 07-03-2014 |
| 20140196000 | SYSTEM AND METHOD FOR CHECKING SIGNAL TRANSMISSION LINE - A method for checking signal transmission lines of a printed circuit board (PCB) layout includes determining differential pairs to be checked and dividing the differential pairs to be checked into a first group and a second group. A first reference distance between differential pairs belonging to the same group and a second reference distance between differential pairs belonging to different groups are set. A first box surrounding each line section of one to be checked signal differential line of the first group and a second box surrounding the first box are created. One first box surrounding each line section of the to be checked differential line of the second group is created. Whether or not in the first box and the second box there are differential lines which do not satisfy design standards is determined. | 07-10-2014 |
| 20140201699 | METHODS FOR MODELING OF FINFET WIDTH QUANTIZATION - A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (I | 07-17-2014 |
| 20140201700 | APPARATUS FOR MODELING OF FINFET WIDTH QUANTIZATION - A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (I | 07-17-2014 |
| 20140208287 | Energy Consumption Simulation and Evaluation System for Embedded Device - An energy consumption simulation and evaluation system for embedded device in energy consumption evaluation technology for electronic devices, which solves the problem that the energy consumption cannot be simulated under tasks operation condition with the existing systems. The present invention includes a graphical configuration management module for inputting graphical configuration parameters, a device energy consumption model building block for obtaining the AADL description model for software and hardware components through AADL abstract description of software and hardware at system-level, a model transformation module for AADL to GSPN model transformation; and a GSPN simulation module which utilizes QPME tool to simulate GSPN model; selectively loads an external energy-consuming event from the energy-consuming events sequence; and perform energy consumption simulation for the GSPN model in response to the external energy-consuming event by QPME tool to obtain a simulation result of the residual energy and lifetime of the system. | 07-24-2014 |
| 20140215429 | POWER/PERFORMANCE OPTIMIZATION THROUGH CONTINUOUSLY VARIABLE TEMPERATURE-BASED VOLTAGE CONTROL - Methods determine temperature and voltage relationships for integrated circuit library elements to produce a continuous temperature-voltage function. Some of the library elements can be used or combined to form an integrated circuit design. Further, the performance characteristics for integrated circuit chips produced according to the integrated circuit design can be defined, such performance characteristics include an operating temperature range, etc. The continuous temperature-voltage function is applied to the performance characteristics to determine a plurality of temperature/voltage combinations for the integrated circuit chips. Each of the temperature/voltage combinations comprises an operating voltage for each operating temperature within the operating temperature range of the integrated circuit chips. Next, the integrated circuit chips are produced according to the integrated circuit design. The temperature/voltage combinations are recorded in memory of the integrated circuit chips. | 07-31-2014 |
| 20140223405 | Method and Apparatus for Providing a Layout Defining a Structure to be Patterned onto a Substrate - A method provides a layout defining a structure to be patterned onto a substrate. The structure is registered with a predefined grid of the layout. The method includes locally stretching the grid in a first portion of a layout causing a problematic spot on the substrate. | 08-07-2014 |
| 20140245252 | METHOD AND CIRCUIT TO IMPLEMENT A STATIC LOW POWER RETENTION STATE - An apparatus to pre-condition an operating integrated circuit (IC) device in a static low power retention state. The apparatus includes a pseudo random number generator that generates a pseudo random number value to pre-condition the static low power retention state of the operating IC device. The apparatus also includes a controller that drives the pseudo random number value into a test scan chain linking logic elements of the operating IC device responsive to the operating IC device entering a sleep mode. Driving the pseudo random number value into the test scan chain by the controller places the operating IC device into the static low power retention state. | 08-28-2014 |
| 20140282348 | TRANSISTOR DESIGN FOR USE IN ADVANCED NANOMETER FLASH MEMORY DEVICES - Improved PMOS and NMOS transistor designs for sensing circuitry use in advanced nanometer flash memory devices are disclosed. | 09-18-2014 |
| 20140282349 | METHOD AND APPARATUS FOR CURRENT LIMIT TEST FOR HIGH POWER SWITCHING REGULATOR - A method can reuse at least one pin in demultiplexing (demuxing) a voltage from a pin. The method can be used to set an accurate current limit threshold in a design for test (DFT) phase and, thus, to accurately set a trimming code of a current limiter. The method uses the property that a power MOSFET has almost a same conductive resistance at a large drain current. Thus, the current limit threshold can be set according to an accurate drain-to-source voltage V | 09-18-2014 |
| 20140282350 | AUTOMATIC CLOCK TREE SYNTHESIS EXCEPTIONS GENERATION - Systems and techniques are described for automatically generating clock tree synthesis (CTS) exceptions. The process can use on one or more criteria to identify sequential circuit elements that can be ignored during clock skew minimization. For example, the process can identify sequential circuit elements whose clock skew cannot be balanced with other sequential circuit elements due to structural reasons, identify sequential timing elements that do not have a timing relationship with other sequential timing elements in the clock tree, and/or identify sequential circuit elements whose data pins have a sufficiently large slack so that clock skew is not expected to cause timing violations at any of the data pins. Next, the process can generate clock tree exceptions based on the identified sequential circuit elements. | 09-18-2014 |
| 20140289695 | EVALUATION OF PIN GEOMETRY ACCESSIBILITY IN A LAYER OF CIRCUIT - Evaluation of electrical accessibility within a layer of a circuit to pin geometries residing within a cell boundary of the circuit is provided. The evaluating includes, for instance, checking along substantially parallel pin geometry access paths of the layer to determine possible points at which a respective pin geometry of the pin geometries within the cell boundary may be accessed. The evaluating also includes identifying which points of the possible points are accessible access points by any route of the possible routes for electrically connecting to a respective pin geometry of the pin geometries from a first side or a second side of the cell boundary, wherein at least one point of the possible points is identified as not being an accessible access point based on the at least one point being inaccessible by the possible routes. | 09-25-2014 |
| 20140289696 | WIRING INSPECTION APPARATUS AND WIRING INSPECTION METHOD - A wiring inspection apparatus includes a dividing unit, a calculating unit, and an output unit. The dividing unit draws a boundary line in a predetermined area between a transmission component and a reception component, to divide the predetermined area into a first area containing the transmission component and a second area containing the reception component. The transmission component transmits a signal to the reception component via relay components. The calculating unit calculates a number of wirings that connect the components across the boundary line, based on positions of the transmission component, the reception component, and the relay components in the predetermined area. The output unit outputs information indicating the presence of a wiring extending in a direction opposite to a direction from the transmission component to the reception component, when the number of the wirings calculated by the calculating unit is equal to or greater than a predetermined value. | 09-25-2014 |
| 20140298285 | DESIGN ASSISTANCE DEVICE, DESIGN ASSISTANCE METHOD, AND DESIGN ASSISTANCE PROGRAM - A determination unit determines whether there is error allowance information having the same error identification ID and the same error object as error information, and determines whether error related information is also the same when there is the same error allowance information. As a result, when there is error allowance information having the same error identification ID and the same error object as the error information and different error related information from the error information, the disablement unit disables error allowance. | 10-02-2014 |
| 20140304674 | DESIGN SYSTEM FOR SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE AND METHOD FOR BONDING SUBSTRATES - The terminals that oppose each other when substrates are bonded are designed to be reliably joined. Comprised in a semiconductor device design system are a numerical value acquiring part, which acquires the respective numerical values of a plurality of calculation parameters, a junction estimating part, which, in the case in which a plurality of substrates has been pressed at a prescribed pressure so that the bump front end faces come into contact, estimates whether or not the respective mutually opposing bumps will be joined based on the respective numerical values of the calculation parameters acquired by the numerical value acquiring part, and a change processing part, which, in the case in which it has been estimated by the junction estimating part that any of the bumps will not be joined, gives a warning or performs processing so as to change the numerical value of at least one calculation parameter among the plurality of calculation parameters. | 10-09-2014 |
| 20140304675 | ELECTRONIC ELEMENT DESIGN SYSTEM AND METHOD - An exemplary electronic element design method includes obtaining a stored transfer function, determining electronic elements, determining information of the determined electronic elements, and obtaining the information of the electronic elements. Next, the method calculates a deviation value of the electronic element with the model number. The method then determines the model number of the electronic element having the greatest deviation value, and further determining the parameter of the electronic element with the determined model number. Next, the method inputs all the determined parameters into the obtained transfer function to generate a real value, and comparing the real value with a stored reference rule to determine whether all of the electronic elements are eligible. If yes, the method then controls a display unit to display information to prompt that all of the electronic elements are eligible. | 10-09-2014 |
| 20140304676 | ELECTRONIC ELEMENT DESIGN SYSTEM AND METHOD - An exemplary electronic element design method includes determining an element value, and determining an element value range. The method searches a stored bill of material table to determine groups of electronic elements, determines the accuracy of the groups of electronic elements, and obtains the information of the determined groups of electronic elements with the determined accuracy. The method also determines the parameters of each model number of each group of electronic element with the determined accuracy, inputs all the determined parameters into an obtained transfer function to generate actual values to determine whether one or more actual values satisfy a reference rule. The method can determine that the electronic elements with the model numbers corresponding to each determined actual value are eligible. The method can control a display unit to display the information of the electronic element with the determined model numbers. | 10-09-2014 |
| 20140310673 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR TRANSLATING A HARDWARE LANGUAGE INTO A SOURCE DATABASE - A system, method, and computer program product are provided for translating a hardware design. In use, a hardware design is received that is encoded as one or more data flows and one or more control constructs. A node is generated for each data flow of the one or more data flows and for each control construct of the one or more control constructs. Additionally, connectivity of the nodes is determined to generate a graph-based intermediate representation of the hardware design and the graph-based intermediate representation of the hardware design is stored in a source database. | 10-16-2014 |
| 20140310674 | SYSTEM AND METHOD FOR CHECKING SIGNAL TRANSMISSION LINE - A computer-based method for checking signal transmission lines of a printed circuit board (PCB) layout is provided. A design rules is set according to different length requirements and the quantity of storage devices input by users. A group of transmission line from a displayed PCB layout is selected. The quantity of branch lines of each transmission line to be checked and the length of each branch line of the group of transmission lines to be checked are computed. The design of which branch lines does not satisfy the design rules is determined according to the computed quantity of the branch lines of each transmission line to be checked, the length of each branch line of the group of transmission lines, and the design rules. | 10-16-2014 |
| 20140310675 | Methods and Apparatus for RC Extraction - The method for extracting a capacitance from a layout is disclosed. The method decomposes a first net into a first and a second component, and decomposes a second net into a third and a fourth component. The method may obtain a first capacitance for the first component and the third component by a first method, and obtain a second capacitance for the second component and the fourth component by a second method different from the first method. A library with a plurality of entries may be provided, wherein each entry has a component pair comprising a component of the first net and a component of the second net, and a pre-calculated capacitance for the component pair. The first method may be to search a library to find a pre-calculated capacitance. The second method may be to obtain the first capacitance by an equation solver on the fly. | 10-16-2014 |
| 20140310676 | METHODS FOR MODELING OF FINFET WIDTH QUANTIZATION - A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (I | 10-16-2014 |
| 20140317587 | COMPUTING DEVICE AND METHOD FOR TESTING LAYOUT OF POWER PIN OF CHIPSET ON CIRCUIT BOARD - A testing system for testing a layout of a power pin of a chipset on a circuit board includes a layout information obtaining module, a power pin sorting module, a transmission line sorting module, a transmission line length calculating module, and a report generating module. The layout information obtaining module obtains layout information of the printed circuit board. The power pin sorting module sorts the power pin from a number of pins of the chipset. The transmission line sorting module sorts transmission lines that are connected to the power pin and are located on outer layers of the printed circuit board. The transmission line length calculating module calculates a total length of the transmission lines sorted by the transmission line sorting module and compares the total length with a threshold length. The report generating module generates a testing report indicating whether or not the power pin is qualified. | 10-23-2014 |
| 20140317588 | Timing Operations In An IC With Configurable Circuits - Some embodiments provide a method that identifies a first physical design solution for positioning several configurable operations on several reconfigurable circuits of an integrated circuit (IC). The method identifies a second physical design solution for positioning the configurable operations on the configurable circuits. One of the identified physical design solutions has one reconfigurable circuit perform a particular configurable operation in at least two reconfiguration cycles while the other identified solution does not have one reconfigurable circuit perform the particular configurable operation in two reconfiguration cycles. The method costs the first and second physical design solutions. The method selects one of the two physical design solutions based on the costs. | 10-23-2014 |
| 20140325468 | STORAGE MEDIUM, AND GENERATION APPARATUS FOR GENERATING TRANSACTIONS FOR PERFORMANCE EVALUATION - A non-transitory computer-readable recording medium having stored therein a program for causing a computer to execute a process comprising: generating a transaction scenario that describes a dependency between operations of semiconductor elements included in a semiconductor circuit, according to a parameter for defining the dependency and waveform data that indicates a level transition of each signal output from each of the semiconductor elements; and generating transactions for testing the semiconductor circuit, according to the transaction scenario. | 10-30-2014 |
| 20140331199 | DETECTING CORRESPONDING PATHS IN COMBINATIONALLY EQUIVALENT CIRCUIT DESIGNS - A method, apparatus and product for detecting corresponding paths in combinationally equivalent circuit designs. The method comprising: obtaining a first circuit design and a second circuit design, the first and second circuit designs have corresponding sets of input and output elements; obtaining a path in the first circuit design, the path commencing in an input element and ending in an output element, wherein the input element and the output element are connected by combinational logic elements; automatically extracting, by a computer, a sensitization function of the path in the first circuit design; and automatically determining, by the computer, one or more paths in the second circuit design which are sensitized by the sensitization function of the path. | 11-06-2014 |
| 20140344772 | SEMI-LOCAL BALLISTIC MOBILITY MODEL - A transistor model defines the carrier mobility as a combination of both drift-diffusion mobility and ballistic mobility. The ballistic mobility is calculated based on the assumption that the kinetic energy of carriers near an injection point is no greater than the potential energy difference of carriers near that injection point. The abruptness of the onset of velocity saturation, as well as the asymptotic velocity associated therewith is made dependent on the degree to which the velocity is ballistically limited. The model further takes into account the inertial effects on the velocity and/or charge flux associated with carriers. The model computes the mobility and hence the velocity of carriers in accordance with their positions in the channel both along the direction of the current flow as well as the direction perpendicular to the current flow. | 11-20-2014 |
| 20140351785 | DIELECTRIC RELIABILITY ASSESSMENT FOR ADVANCED SEMICONDUCTORS - Embodiments relate to methods, computer systems and computer program products for performing a dielectric reliability assessment for an advanced semiconductor. Embodiments include receiving data associated with a test of a macro of the advanced semiconductor to a point of dielectric breakdown. Embodiments also include scaling the data for the macro down to a reference area and extracting a parameter for a Weibull distribution from the scaled down data for the reference area. Embodiments further include deriving a cluster factor (α) from the scaled down data for the reference area and projecting a failure rate for a larger area of the advanced semiconductor based on the extracted parameter, the cluster factor and the recorded data associated with the dielectric breakdown of the macro. | 11-27-2014 |
| 20140359550 | POWER DELIVERY NETWORK ANALYSIS - A method and apparatus for power delivery network (PDN) analysis comprises obtaining time-domain single-pulse current response of the PDN, computing a maximum transient simultaneous switching noise (SSN) of the PDN according to the time-domain single-pulse current response, and determining that noise performance of the PDN conforms to a design requirement of the PDN if the maximum transient SSN is less than a PDN SSN threshold. Transient characteristics of the PDN can be analyzed. | 12-04-2014 |
| 20140359551 | SYSTEMS AND METHODS FOR SEMICONDUCTOR VOLTAGE DROP ANALYSIS - Methods and systems are provided for computing IR drop, i.e., voltage drop, in a semiconductor device. The method includes generating a modeling element corresponding to the plurality of transistors. At least one of the transistors in the modeling element is replaced with a current source. The method also includes performing an IR drop analysis of the modeling element utilizing a software program to calculate the IR drop in the semiconductor device. | 12-04-2014 |
| 20140372962 | CIRCUIT VERIFYING APPARATUS, CIRCUIT VERIFYING METHOD, AND CIRCUIT VERIFYING PROGRAM - A circuit verifying apparatus, which calculates code coverage of a measurement-target logic circuit written in a hardware description language, including: a coverage observing unit which measures whether a code corresponding to a measurement-target signal extracted from each of plural observation points, which are arranged inside the measurement-target logic circuit, is carried out or not; and a coverage collecting unit which collects measurement results acquired by the coverage observing unit, and measures quantitatively a ratio of tested codes to whole codes which describe the measurement-target logic circuit, and outputs the ratio. | 12-18-2014 |
| 20140380261 | SEMICONDUCTOR DEVICE RELIABILITY MODEL AND METHODOLOGIES FOR USE THEREOF - Systems and methods for semiconductor device reliability qualification during semiconductor device design. A method is provided that includes defining performance process window bins for a performance window. The method further includes determining at least one failure mechanism for each bin assignment. The method further includes generating different reliability models when the at least one failure mechanism is a function of the process window, and generating common reliability models when the at least one failure mechanism is not the function of the process window. The method further includes identifying at least one risk factor for each bin assignment, and generating aggregate models using a manufacturing line distribution. The method further includes determining a fail rate by bin and optimizing a line center to minimize product fail rate. The method further includes determining a fail rate by bin and scrapping production as a function of a manufacturing line excursion event. | 12-25-2014 |
| 20150012903 | NON-INTRUSIVE MONITORING AND CONTROL OF INTEGRATED CIRCUITS - A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an incremental second set of configuration data based on the definition of the event and the set of corresponding actions. While the first IC is performing the operations of the user design, the method loads the incremental second set of configuration data into the first IC and monitors the signals received from the second IC at the first IC. | 01-08-2015 |
| 20150026657 | 3D DEVICE MODELING FOR FINFET DEVICES - Among other things, techniques and systems for 3D modeling of a FinFET device and for detecting a variation for a design layout based upon a 3D FinFET model are provided. For example, a fin height of a FinFET device is determined based upon imagery of the FinFET device. The fin height and a 2D FinFET model for the FinFET device are used to create a 3D FinFET model. The 3D FinFET model takes into account the fin height, which is evaluated to identify fin height variations amongst FinFET devices within the design layout. For example, a fin height variation is determined based upon a proximity pattern density, a fin pitch, a gate length, or other parameters/measurements. A voltage threshold variation is determined based upon the fin height variation. This allows the design layout to be modified to decrease the variation. | 01-22-2015 |
| 20150040096 | EMULATION-BASED FUNCTIONAL QUALIFICATION - Techniques for emulation-based functional qualification are disclosed that use an emulation platform to replace simulation in mutation-based analysis. A method for functional qualification of an integrated circuit design includes receiving an integrated circuit design having one or more mutations. Emulation setup and activation simulation are performed in parallel to maximize computing resources. A prototype board can then be programmed according to the integrated circuit design and a verification module. A set of test patterns and response generated by a simulation of the integrated circuit using the set of test patterns are stored in a memory of the prototyping board allowing enumeration of mutants to occur at in-circuit emulation speed. | 02-05-2015 |
| 20150046897 | GENERALIZED MOMENT BASED APPROACH FOR VARIATION AWARE TIMING ANALYSIS - A method and apparatus of a device that performs a generalized moment based variation aware timing analysis on a circuit design is described. The device receives a signal path that traverses a plurality of gates. For each of the plurality of gates, the device retrieves a statistical distribution that represents delay variation at the gate. The statistical distribution for each gate is measured by a number of statistical moments that include higher order statistical moments besides the mean and the standard deviation of the distribution. The device computes statistical moments to represent the timing variation on the signal path by propagating statistical distributions of the gates on the signal path. The device reconstructs a statistical distribution function for timing variation on the signal path based on the computed statistical moments. | 02-12-2015 |
| 20150067634 | METHOD FOR POWER ESTIMATION FOR VIRTUAL PROTOTYPING MODELS FOR SEMICONDUCTORS - The present invention may comprise an apparatus and method for calculating power consumption, including a unit for generating a clock-level analysis without synthesis of an algorithm description and calculating operating ratios of storage elements and arithmetic units. The invention may also comprise a method for estimating the power to be consumed by a SystemC model. By estimating this value, a user may gauge the amount of power a specific semiconductor design might consume, once manufactured into a chip. | 03-05-2015 |
| 20150074631 | DATA ERROR SUSCEPTIBLE BIT IDENTIFICATION - As consistent with one or more embodiments, electronic circuitry is characterized to provide an indication of susceptibility of the circuitry to error. As consistent with one or more embodiments, bits corresponding to a circuit component of a circuit design are evaluated using a software program that characterizes a hardware description language representing the circuit components and their interconnectivity. A noise power value is calculated for each bit, and bits are identified as being susceptible to data error based upon the noise power value and a signal-to-noise (SNR) ratio reference value. A characterization of the circuit components (e.g., a quality factor) is provided based upon a number of bits susceptible to data errors. | 03-12-2015 |
| 20150095873 | METAL LINES FOR PREVENTING AC ELECTROMIGRATION - A method is disclosed that includes the operations outlined below. An effective current pulse width of a maximum peak is determined based on a waveform function of a current having multiple peaks within a waveform period in a metal segment of a metal line in at least one design file of a semiconductor device to compute a duty ratio between the effective current pulse width and the waveform period. A maximum direct current limit of the metal segment is determined according to physical characteristics of the metal segment. An alternating current electromigration (AC EM) current limit is determined according to a ratio between the maximum direct current limit and a function of the duty ratio. The metal segment is included with the physical characteristics in the at least one design file when the maximum peak of the current does not exceed the AC EM current limit. | 04-02-2015 |
| 20150100939 | SEMICONDUCTOR DEVICE BURN-IN STRESS METHOD AND SYSTEM - Burn-in (BI) stress using stress patterns with pin-specific power characteristics. A control device for each conductive pathway from BI board (BIB) contacts to device under test (DUT) connectors/contacts can adjust power delivered to a respective connector/contact responsive to a controller. The control devices can be included in the BIB or an interposer (IP) can be used with existing equipment. Each control device can include a regulator, such as a latchable array of field effect transistors that can regulate power delivered to a respective package connector. | 04-09-2015 |
| 20150106780 | SEMICONDUCTOR DEVICE RELIABILITY MODEL AND METHODOLOGIES FOR USE THEREOF - Systems and methods for semiconductor device reliability qualification during semiconductor device design. A method is provided that includes defining performance process window bins for a performance window. The method further includes determining at least one failure mechanism for each bin assignment. The method further includes generating different reliability models when the at least one failure mechanism is a function of the process window, and generating common reliability models when the at least one failure mechanism is not the function of the process window. The method further includes identifying at least one risk factor for each bin assignment, and generating aggregate models using a manufacturing line distribution. The method further includes determining a fail rate by bin and optimizing a line center to minimize product fail rate. The method further includes determining a fail rate by bin and scrapping production as a function of a manufacturing line excursion event. | 04-16-2015 |
| 20150121330 | HIERARCHICAL ELECTROMIGRATION ANALYSIS USING INTELLIGENT CONNECTIVITY - Implementations of the present disclosure involve methods and systems for performing an electromigration analysis of a microelectronic circuit design. In particular, the implementations describe provide for performing a hierarchical extraction of the design, determining an approximate positioning and connection of two or more components of the design and performing electromigration analysis on the design. In one implementation, an intelligent connectivity may be applied to the hierarchical extraction to achieve an approximate location of the connection points between the blocks of the design. In one example, the intelligent connectivity technique may utilize a coordinate grid related to the design to approximate the connection points between the blocks of the design. Thus, by combining the hierarchical extraction with an intelligent connectivity technique, an electromigration analysis of a VLSI microelectronic design may be accomplished within the limitations of the analysis tools that is more accurate than previous electromigration analysis techniques | 04-30-2015 |
| 20150143325 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR MODELING RESISTANCE OF A MULTI-LAYERED CONDUCTIVE COMPONENT - Disclosed is a technique for modeling resistance of a conductive component of a device, where the component comprises multiple conductive materials. If necessary (e.g., for a complex conductive component), the component is divided into multiple conductive regions. For a given conductive region, current flow-through and current flow-in-and-terminate axes are determined and the conductive region is divided into layers. Relative electric currents flowing along the current flow-through axis in each layer and along the current flow-in-and-terminate axis in each layer are evaluated to determine a total resistance value for the conductive region. For a complex conductive component, these processes are repeated for all conductive regions and an overall resistance value is determined based on the corresponding total resistance values and, as calculated for each conductive region, a ratio of maximum electric current flowing in/out of the conductive region to the total electric current flowing out of the complex conductive component. | 05-21-2015 |
| 20150143326 | EFFICIENT CEFF MODEL FOR GATE OUTPUT SLEW COMPUTATION IN EARLY SYNTHESIS - A slew-based effective capacitance (C | 05-21-2015 |
| 20150302126 | TESTING SOC WITH PORTABLE SCENARIO MODELS AND AT DIFFERENT LEVELS - A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output. | 10-22-2015 |
| 20150339424 | COMPUTING SYSTEM AUTOMATICALLY GENERATING A TRANSACTOR - A computing system includes a memory device into which a design file for a predetermined intellectual property (IP) and a transactor generating tool are loaded, and a processor configured to execute the transactor generating tool loaded into the memory device. The transactor generating tool executed by the processor extracts port information of the IP from the design file, and generates at least one transactor corresponding to the IP based on the port information. | 11-26-2015 |
| 20150347652 | TIMING ANALYSIS OF ASYNCHRONOUS CLOCK DOMAIN CROSSINGS - Various implementations of a method, system, and computer program product for executing timing analysis of an asynchronous clock domain crossing are disclosed. In one embodiment, a signal group and a corresponding timing specification are determined for one or more signals of an electronic design. For each of the signals, a clock associated with the signal is renamed based, at least in part, on the signal group associated with the signal. The asynchronous clock domain between a transmit domain and a receive domain is identified in the electronic design based, at least in part, on identifying a signal path associated with one or more renamed clocks that is asynchronous to a clock associated with the receive domain. For each of the one or more renamed clocks, timing analysis is executed across one or more signals associated with the renamed clock at the asynchronous clock domain crossing. | 12-03-2015 |
| 20150363516 | TOPOGRAPHY SIMULATION APPARATUS, TOPOGRAPHYSIMULATION METHOD AND RECORDING MEDIUM - In one embodiment, a topography simulation apparatus includes a division module configured to divide topography of a substance of a semiconductor device into first to n-th layers, where n is an integer of two or more. The apparatus further includes a flux calculation module configured to calculate, for each of the first to n-th layers, a flux of particles which reach a surface of the substance in each layer. The apparatus further includes a topography calculation module configured to calculate, for each of the first to n-th layers, an amount of change of the topography of the substance in each layer based on the flux. | 12-17-2015 |
| 20160034620 | LATCH-UP SUPPRESSION AND SUBSTRATE NOISE COUPLING REDUCTION THROUGH A SUBSTRATE BACK-TIE FOR 3D INTEGRATED CIRCUITS - Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described. | 02-04-2016 |
| 20160042113 | Method for power estimation for virtual prototyping models for semiconductors - The present invention may comprise an apparatus and method for calculating power consumption, including a unit for generating a clock-level analysis without synthesis of an algorithm description and calculating operating ratios of storage elements and arithmetic units. The invention may also comprise a method for estimating the power to be consumed by a SystemC model. By estimating this value, a user may gauge the amount of power a specific semiconductor design might consume, once manufactured into a chip. | 02-11-2016 |
| 20160042115 | PATH-BASED FLOORPLAN ANALYSIS - Systems and techniques for computing a timing effort metric are described. According to one definition, the computed timing effort metric indicates a level of difficulty of fixing a timing violation associated with a timing path between two circuit objects in a circuit design layout. | 02-11-2016 |
| 20160042116 | APPARATUS AND METHOD FOR GENERATING TEST CASES FOR PROCESSOR VERIFICATION, AND VERIFICATION DEVICE - An apparatus for generating a test case includes a constrained description generator configured to define a plurality of constrained verification spaces in a total verification space, and generate a constrained description for each of the plurality of constrained verification spaces; and a test case generator configured to generate a test case using the constrained description. | 02-11-2016 |
| 20160063157 | PARAMETER MODELING FOR SEMICONDUCTOR ARRANGEMENTS - One or more systems and techniques for modeling are provided. An original device model, such as a SPICE model, is used as a basis for fabricating a semiconductor arrangement, such as an integrated circuit arrangement, upon a semiconductor wafer. Fabrication process variations cause measured e-parameters and measured size e-parameters of the semiconductor arrangement to vary from original design parameters of the original device model. Accordingly, a partial set of e-parameters and a partial set of size e-parameters are measured from the semiconductor arrangement, and are expanded into a full set of e-parameters and a full set of size e-parameters using e-parameter derivation and size-centric derivation. The original device model is retargeted using the full set of e-parameters and the full set of size e-parameters to create a new device model that more accurately represents the real-world or fabricated semiconductor arrangement. | 03-03-2016 |
| 20160063171 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR SCHEMATIC DRIVEN, UNIFIED THERMAL AND ELECTROMAGNETIC INTERFERENCE COMPLIANCE ANALYSES FOR ELECTRONIC CIRCUIT DESIGNS - Disclosed are methods and systems for by identifying or generating an electrical schematic, generating a thermal schematic by associating thermal RC circuits of the electronic design with the electrical schematic, performing at least two analyses of an electrical analysis, a thermal analysis, and an electromagnetic interference compliance (EMC) analysis with the electrical schematic and the thermal schematic of the electronic design. The electrical, thermal, and EMC analyses may be performed concurrently by forwarding intermediate or final analysis results to each other, and the analysis results may be presented simultaneously in one or more user interface windows. The thermal schematic may be obtained by extracting the thermal RC circuits, identifying corresponding electrical circuit components that correspond to the extracted thermal RC circuits, and importing the thermal RC circuits into the electrical schematic so that the electrical and thermal schematics have the same nodes. | 03-03-2016 |
| 20160078160 | METHOD OF SIMULATING FORMATION OF LITHOGRAPHY FEATURES BY SELF-ASSEMBLY OF BLOCK COPOLYMERS - A method of determining an uncertainty in the position of a domain within a self-assembly block copolymer (BCP) feature. The method includes simulating a BCP feature, calculating a minimum energy position of a first domain within the simulated BCP feature, simulating the application of a potential that causes the position of the first domain to be displaced from the minimum energy position, simulating release of the potential back toward the minimum energy, recording a plurality of energies of the BCP feature during the release and recording at each of the plurality of energies a displacement of the first domain from the minimum energy position, calculating, from the recorded energies and recorded displacements, a probability distribution indicating a probability of the first domain being displaced from the minimum energy position, and, from the probability distribution, calculating an uncertainty in the position of the first domain within the BCP feature. | 03-17-2016 |
| 20160085894 | SYSTEM AND METHOD FOR EFFICIENT STATISTICAL TIMING ANALYSIS OF CYCLE TIME INDEPENDENT TESTS - A system performing selected timing comparisons in a digital electronic design includes propagating from signal sources to timing comparisons of one or multiple signal labels. The signal label includes signal source identifiers and signal path cycle adjust information. Timing comparisons are determined in which signal label values at each input of the timing comparison are required to compute the selected timing comparisons. The propagation back from the timing comparisons are needed signal labels, followed by the propagation and computing timing data from the signal source applied to the propagated signal labels corresponding to the required signal labels. | 03-24-2016 |
| 20160085895 | SYSTEM AND METHOD FOR EFFICIENT STATISTICAL TIMING ANALYSIS OF CYCLE TIME INDEPENDENT TESTS - A computer program product for performing selected timing comparisons in a digital electronic design includes propagating from signal sources to timing comparisons of one or multiple signal labels. The signal label includes signal source identifiers and signal path cycle adjust information. Timing comparisons are determined in which signal label values at each input of the timing comparison are required to compute the selected timing comparisons. The propagation back from the timing comparisons are needed signal labels, followed by the propagation and computing timing data from the signal source applied to the propagated signal labels corresponding to the required signal labels. | 03-24-2016 |
| 20160098504 | EFFICIENT POWER ANALYSIS - Embodiments relate to the emulation of circuits, and tracking states of signals in an emulated circuit for performing power analysis. A host system incorporates power analysis logic into a design under test (DUT). An emulator emulates the DUT along with the incorporated power analysis logic. Based on the power analysis logic, during a power analysis clock cycle, the emulator selects a signal from a plurality of signals of the DUT. The emulator determines whether a state event is detected for the selected signal. If the state event is detected, a state count is updated for the selected signal that indicates a number of state events detected for the selected signal during emulation of the DUT. If the state count reaches a threshold number based on the update, the emulator transmits a count update signal to the host system indicating that the state count reached the threshold number. | 04-07-2016 |
| 20160110487 | IDENTIFYING NOISE COUPLINGS IN INTEGRATED CIRCUIT - A method for determining the sensitivity of an analog output node of a mixed-signal module on a system on a chip (SoC) to noise coupling on the analog input nodes of the mixed-signal module includes (i) selecting an IP block for testing, (ii) selecting the output node, (iii) compiling a list of input nodes for testing, (iv) for each input node of the list, providing excitation signals at different frequencies, (v) for each provided excitation signal, determining the output node's noise sensitivity, and (vi) if any individual and/or cumulative noise sensitivity result exceeds a preset threshold, then modifying the SoC design to take corrective action. | 04-21-2016 |
| 20160125105 | Automatic Generation of Properties to Assist Hardware Emulation - Analysis of a first verification test suite automatically generates properties that may be directly used in a subsequent verification test suite. For example, an IP module may be verified by executing a software simulation test suite. The resulting data is accessed and analyzed to detect a set of properties of the software simulation test suite. A set of emulator-synthesizable properties are selected from the set of detected properties. The emulator-synthesizable properties are suitable for incorporation in a hardware emulation test suite used to test the SoC. | 05-05-2016 |
| 20160125106 | Chip-Scale Electrothermal Analysis - Various aspects of the disclosed technology relate to techniques of determining an across-chip distribution of temperature generated by on-chip devices. Effective thermal conductance and effective thermal capacity for each region of a plurality of regions of a layout design are first extracted. The effective thermal conductance for a region in a metal layer is determined based at least on density information of metal interconnect lines within the region and has components associated with directions of the metal interconnect lines. A thermal circuit is then constructed based on the effective thermal conductance, the effective thermal capacity and heat information of thermal nodes. The heat information of thermal nodes is determined based on an electrical simulation on the integrated circuit associated with the layout design. A thermal simulation is then performed on the thermal circuit to determine temperature information of the thermal nodes. | 05-05-2016 |
| 20160125122 | MEASURE OF ANALYSIS PERFORMED IN PROPERTY CHECKING - The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N. | 05-05-2016 |
| 20160147931 | PROGRAMMABLE CAD SYSTEM SUITED FOR PREVENTING INTERFERENCE BETWEEN COMPONENT AND CHASSIS, AND METHOD THEREOF - A programmable CAD system suited for preventing interference between components and a chassis, and a method thereof are provided. The method comprises the following steps of: automatically obtaining a protruding length of a pin tail of a component outwardly protruded from a circuit board, by a first arithmetic unit; obtaining a distance, between a chassis and a surface of the circuit board corresponding to a location where the component is disposed, from a component information unit, obtaining an interference value according to the protruding length and the distance, by a second arithmetic unit; and determining whether the interference value is greater than zero, by a determine unit. If the interference value is greater than zero, the component is determined to be interfering with the chassis; and if not, the component is determined not to be interfering with the chassis. | 05-26-2016 |
| 20160162625 | Mapping Intermediate Material Properties To Target Properties To Screen Materials - A system for evaluating candidate materials for fabrication of integrated circuits includes a data processor coupled to a memory. Roughly described, the data processor is configured to: calculate and write to a first database, for each of a plurality of candidate materials, values for each property in a set of intermediate properties; calculate and write to a second database, values for a selected target property for various combinations of values for the intermediate properties and values describing candidate environments; and for a particular candidate material and a particular environment in combination, determine values for the intermediate properties for the candidate material by reference to the first database, and determine the value of the target property for the candidate material by querying the second database with, in combination, (1) the determined intermediate property values of the candidate material and (2) a value or values describing the particular environment. | 06-09-2016 |
| 20160171135 | SYSTEM AND METHOD FOR MODULAR SIMULATION OF SPIN TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY DEVICES | 06-16-2016 |
| 20160180009 | IMPLEMENTING ENHANCED PERFORMANCE DYNAMIC EVALUATION CIRCUIT BY COMBINING PRECHARGE AND DELAYED KEEPER | 06-23-2016 |
| 20160203246 | THERMAL SIMULATION DEVICE AND METHOD FOR INTEGRATED CIRCUITS | 07-14-2016 |
| 20160203255 | Integrated Circuit Topologies for Discrete Circuits | 07-14-2016 |
| 20160253446 | SYSTEM AND METHOD FOR HIGH-SPEED SERIAL LINK DESIGN | 09-01-2016 |
| 20160253448 | CIRCUIT BOARD DESIGN SYSTEM, CIRCUIT BOARD DESIGN METHOD AND PROGRAM RECORDING MEDIUM | 09-01-2016 |
| 20190146031 | SYNTHESIS FOR RANDOM TESTABILITY USING UNREACHABLE STATES IN INTEGRATED CIRCUITS | 05-16-2019 |
| 20220138385 | INTEGRATED CIRCUIT DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT - A method executed at least partially by a processor includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group among the plurality of groups has a dominant feature among a plurality of features of the plurality of paths. The dominant features of the plurality of groups are different from each other. The method further includes testing at least one path in a group among the plurality of groups. The method also includes, in response to the testing indicating that the at least one path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram. | 05-05-2022 |
