| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 716135000 | For area | 29 |
| 20100299649 | NOVEL OPTIMIZATION FOR CIRCUIT DESIGN - Methods for optimizing design parameters of a circuit are disclosed. In one aspect, an optimization problem includes one or more performance specifications that represent an exponent of a design parameter to be optimized. Various parameters of passive and active circuit devices may be efficiently and accurately optimized as a result. In another aspect, linear performance specifications are included for accurately calculating voltages. In yet other aspects of the invention, three special types of convex optimization problems are disclosed for enabling the above use of exponents of design parameters which provide efficient and accurate calculations of a virtually unlimited array of circuit parameters and performance characteristics. | 11-25-2010 |
| 20110185334 | ZONE-BASED LEAKAGE POWER OPTIMIZATION - A leakage power optimization system optimizes leakage power of a circuit design which includes a set of logic gates. The system selects a leakage-power-reducing transformation for a logic gate, and determines a zone around the logic gate. This zone includes logic gates within a first predetermined number of levels in the logic gate's fan-out, the logic gate's fan-in, and a second predetermined number of levels in the logic gate's fan-in's fan-out. The system propagates arrival times within the zone to obtain updated slack values at endpoints of the zone. Then, in response to determining that the updated slack values at the endpoints of the zone do not degrade one or more circuit timing metrics, the system applies the leakage-power-reducing transformation to the logic gate. | 07-28-2011 |
| 20110202898 | Contour Alignment For Model Calibration - Techniques for model calibration and alignment of measurement contours of printed layout features with simulation contours obtained with a model are disclosed. With various implementations of the invention, contour point errors are determined. Based on the contour point errors and a cost function, values of alignment parameters may be determined. The values of alignment parameters may be used to realign the measurement contours for model calibration. The alignment may be conducted concurrently with model calibration. | 08-18-2011 |
| 20110225562 | COMPACT MODEL METHODOLOGY FOR PC LANDING PAD LITHOGRAPHIC ROUNDING IMPACT ON DEVICE PERFORMANCE - A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance. Then, transistor model parameter values in a transistor compact model are updated for the transistor device to include deltaW adder values to be added to a built-in deltaW value. A netlist used in a device simulation may then include the deltaW adder values to quantify the influence of the lithographic rounding effect of the landing pad feature. | 09-15-2011 |
| 20110239182 | AUTOMATIC CIRCUIT DESIGN TECHNIQUE - A set of pareto optimal solutions that are non-dominated solutions in a solution specification space for respective items in requirement specification is extracted with a combination of a circuit configuration including a specific function and a process constraint condition. Furthermore, pareto optimal solutions are extracted for all combinations of the circuit configuration and the process constraint condition, and pareto optimal solutions are extracted for the respective process constraint conditions. When such extracted data is distributed to designers, it is possible to reduce time to generate the pareto optimal solutions, and the designers can design the optimum circuit having a desired function by using such extracted data. | 09-29-2011 |
| 20120017194 | METHOD FOR FAST ESTIMATION OF LITHOGRAPHIC BINDING PATTERNS IN AN INTEGRATED CIRCUIT LAYOUT - The present invention provides a lithographic difficulty metric that is a function of an energy ratio factor that includes a ratio of hard-to-print energy to easy-to-print energy of the diffraction orders along an angular coordinate θ | 01-19-2012 |
| 20120110542 | METHOD TO SCALE DOWN IC LAYOUT - A method scales down an integrated circuit layout structure without substantially jeopardizing electronic characteristics of devices. First, a conductive line set includes a first conductive line and a second conductive line respectively passing through a first region and a second region. Second, a sizing-down operation is performed so that the first conductive line and the second conductive line respectively have a first region scaled-down line width, a first region scaled-down space and a first region scaled-down pitch in the first region as well as selectively have a second region original line width, a second region scaled-down space and a second region scaled-down pitch in the second region. The first region scaled-down line width and the second region original line width are substantially different from each other. | 05-03-2012 |
| 20120297355 | WHITESPACE CREATION AND PRESERVATION IN CIRCUIT DESIGN - A method, system, and computer program product for whitespace creation and preservation in the design of an integrated circuit (IC) are provided in the illustrative embodiments. A first estimate is formed by estimating an amount of whitespace that is needed to reduce a congestion value of a congested area of the design to a threshold value. A set of virtual filler cells is added to the congested area, wherein adding the set of virtual filler cells does not add actual whitespace cells to the congested area but reduces the congested area by at least the first estimate. A virtual filler cell in the set of virtual filler cells is replaced with a corresponding real filler cell. A determination is made whether the design has improved. A final placement solution is created when the design has not improved. | 11-22-2012 |
| 20140007037 | ESTIMATING OPTIMAL GATE SIZES BY USING NUMERICAL DELAY MODELS | 01-02-2014 |
| 20140033162 | DETERMINING OPTIMAL GATE SIZES BY USING A NUMERICAL SOLVER - Systems and techniques are described for optimizing a circuit design by using a numerical solver. The gates sizes are optimized by modeling a set of gate optimization problems and solving the set of gate optimization problems by using a numerical solver. Modeling each gate optimization problem can include selecting a portion of the circuit design that includes a driver gate that drives one or more inputs of each gate in a set of gates, and modeling a gate optimization problem for the portion of the circuit design based on circuit information for the portion of the circuit design. A differentiable objective function for delay can be created using numerical models for the delays in the circuit. In some embodiments, gradients of the differentiable objective function can be computed to enable the use of a conjugate-gradient-based numerical solver. | 01-30-2014 |
| 20140033163 | MODELING GATE SIZE RANGE IN A NUMERICAL GATE SIZING FRAMEWORK - Systems and techniques are described for optimizing a circuit design by using a numerical solver. The gates sizes are optimized by modeling a set of gate optimization problems and solving the set of gate optimization problems by using a numerical solver. The optimization can be performed iteratively, wherein in each iteration a gate optimization problem can be modeled for the portion of the circuit design based on circuit information for the portion of the circuit design. An objective function can be created, wherein the objective function includes at least one penalty function that imposes a lower and/or upper bound on at least one variable that is being optimized. In some embodiments, gradients of the objective function (which includes the penalty function) can be computed to enable the use of a conjugate-gradient-based numerical solver. | 01-30-2014 |
| 20140059510 | Sizing Method for Stand-alone Photovoltaic System - A sizing method for a stand-alone photovoltaic system is provided. The stand-alone photovoltaic system includes photovoltaic plates and batteries. The sizing method includes steps of obtaining climate data in a site during a period of time, calculating Tc | 02-27-2014 |
| 20140096103 | SYSTEM FOR OPTIMIZING NUMBER OF DIES PRODUCED ON A WAFER - A system for optimizing the number of dies that can be fabricated on a wafer uses a die number optimization (DNO) routine to determine a maximum number of dies for a target die area (TDA), and generate an initial result list of die shapes that have the maximum number of dies for the TDA. Optionally, a die size optimization (DSO) routine can be executed to determine a list of die shapes having a maximum die area corresponding to the maximum number of dies, a first list of optimized die shapes having a maximum area utilization (AU) for a decreased TDA, and/or a second list of optimized die shapes having a minimum AU for an increased TDA. A candidate list (CL) of the various die shapes can be generated, and entries from the CL automatically selected and/or displayed to indicate proposed wafer layouts. | 04-03-2014 |
| 20140123095 | MODELING MULTI-PATTERNING VARIABILITY WITH STATISTICAL TIMING - Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively. | 05-01-2014 |
| 20140201698 | AREA EFFICIENT POWER SWITCH - A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell. | 07-17-2014 |
| 20140208286 | SYSTEM AND METHOD FOR DESIGNING VIA OF PRINTED CIRCUIT BOARD - A via design method includes doing a simulation according to input data to obtain the impedance of the via of the reference printed circuit board (PCB). An optimal via model is determined according to a group of input data. Simulating is performed according to the thickness of a PCB to-be-designed and the optimal via model data, to obtain the impedance of a via of a PCB to be designed. The number of the anti-pads of the via of the PCB to be designed is recorded when the difference between the impedance of the via of the PCB to be designed and the impedance of the via model of the reference PCB does not fall within a preset range. An interval between each two adjacent anti-pads of the via of the PCB to designed is determined according to the recorded number and the thickness of the PCB to be designed. | 07-24-2014 |
| 20140331198 | METHOD FOR DESIGNING A PHYSICAL LAYOUT OF A PHOTOVOLTAIC SYSTEM - A method for creating a physical layout of a photovoltaic system in a specified field is provided where the photovoltaic system is specified by a plurality of technical properties. The method includes reading out more than 20 pre-calculated, completed layouts for the photovoltaic system from a memory; presenting the completed layouts in a graphical presentation wherein each of the completed layouts is represented by at least one partial amount of the plurality of technical properties; modifying value ranges of the presented technical properties, in order to present a modified number of completed layouts in a comparable manner; and selecting an optimized layout that has been optimized with regard to the presented properties from the modified number of completed layouts. Thereby a photovoltaic system having a high nominal power can be established in the best possible manner. The physical layout of the entire photovoltaic system is adapted to the specified field. | 11-06-2014 |
| 20140365988 | NETWORK RECONFIGURATION IN A DATA CONVERTER FOR IMPROVED ELECTRICAL CHARACTERISTICS - A process of optimizing a resistor-2 resistor (R-2R) digital-to-analog converter (DAC) by partial resistor network reconfiguration is disclosed. The method includes analyzing a circuit to determine whether any specifications are outside predetermined limits. The method further includes determining one or more addresses that cause the circuit to be outside of the predetermined limits. The method further includes defining logic to detect address information and control function to alter the circuit to improve the specifications. The method further includes installing the control function into the circuit to improve the specifications. | 12-11-2014 |
| 20150033201 | SYSTEMS AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURES - Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining raw measurement data for a wafer of semiconductor material from a metrology tool and adjusting a measurement model utilized by a metrology tool based at least in part on the raw measurement data and a value for a design parameter. The wafer has that value for the design parameter and an attribute of the semiconductor device structure fabricated thereon, wherein the measurement model is utilized by the metrology tool to convert the raw measurement data to a measurement value for the attribute. | 01-29-2015 |
| 20150040095 | Method of Improving Timing Critical Cells For Physical Design In The Presence Of Local Placement Congestion - Optimizing circuits having a congested placement with a timing critical placement map includes identifying critical circuit components in the placement map and determining failing circuit components in the placement map; determining “non-critical” circuit components safe to be moved; removing selected non critical from the placement map; and optimizing the critical circuit components in a new partial placement image of said map; and reinserting the “non-critical” circuit components back into said placement image. The optimization is performed by circuit transformation operating in congested regions of the placement image enabling cell insertion and modifications that increase cell size. | 02-05-2015 |
| 20150046896 | CAPACITOR ARRANGEMENT ASSISTING METHOD AND CAPACITOR ARRANGEMENT ASSISTING DEVICE - A capacitor arrangement assisting method wherein data entered by a user, such as the width w of a power supply wiring, the thickness h of a dielectric between the power supply wiring and a ground plane, the ESL | 02-12-2015 |
| 20150052494 | POWER RAIL LAYOUT FOR DENSE STANDARD CELL LIBRARY - A method includes electrically connecting a plurality of cells of a standard cell library to a power rail. A contact area is deposited to connect a first active area and a second active area of a cell of a plurality cells. The first area and the second area are located on opposite sides of the rail and electrically connected to different drains. The contact area is electrically connected to the power rail using a via. The contact area is masked to remove a portion of the contact area to electrically separate the first active are from the second active area. | 02-19-2015 |
| 20150106779 | METHODOLOGY FOR PATTERN DENSITY OPTIMIZATION - The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more low-pattern-density areas of the IC design are identified having a pattern density that results in a processing failure. The low-pattern-density areas are a subset of the IC design. The pattern density is adjusted within the low-pattern-density area by adding one or more dummy shapes within the low-pattern-density areas. A data preparation process is then performed on the IC design to modify shapes of the one or more dummy shapes within the low-pattern-density areas. By introducing dummy shapes into a local area, rather than into an entire integrated chip design, the demands of the subsequent data preparation process are reduced. | 04-16-2015 |
| 20150143324 | Semiconductor Device Design Methods and Conductive Bump Pattern Enhancement Methods - Semiconductor device design methods and conductive bump pattern enhancement methods are disclosed. In some embodiments, a method of designing a semiconductor device includes designing a conductive bump pattern design, and implementing a conductive bump pattern enhancement algorithm on the conductive bump pattern design to create an enhanced conductive bump pattern design. A routing pattern is designed based on the enhanced conductive bump pattern design. A design rule checking (DRC) procedure is performed on the routing pattern. | 05-21-2015 |
| 20150363531 | OPTIMIZATION OF INTEGRATED CIRCUIT PHYSICAL DESIGN - According to one embodiment of the present invention, a method for optimizing an integrated circuit design is provided. The method may include identifying one or more nets crossing a boundary between a parent block, having parent logic, and a child block, having child logic. The method may include inserting interior buffers on the nets inside of the child block and exterior buffers on the nets outside of the child block and inside of the parent block, wherein the interior buffers and the exterior buffers define a buffer pair for each of the nets. The method may further include determining a first placement for the parent logic and a second placement for the child logic, such that the buffers of the buffer pair for each net are placed substantially near to one another. The method may further include determining pin locations for the child block based on the second placement. | 12-17-2015 |
| 20160026747 | Method for Determining a Sequence for Drilling Holes According to a Pattern using Global and Local Optimization - A method determines a sequence for drilling holes in a workpiece according to a pattern by first partitioning the holes in the pattern into packets. A global sequence of the packets is determined by solving a global traveling salesman problem (TSP), and a local sequence of the holes in each packet is determined by solving a local TSP for each packet. Then, the local sequences of the holes are joined according to the global sequence of the packets to determine a complete sequence for drilling the holes. | 01-28-2016 |
| 20160140283 | METHODS AND SYSTEMS FOR DETERMINING A PHOTOVOLTAIC SYSTEM LAYOUT - A computer-implemented method for determining a system layout of a photovoltaic (PV) system is implemented by a design automation computer system in communication with a memory. The method includes receiving a first selection of a system table, receiving a layout mode designation, identifying a system orientation, identifying a system spacing, receiving a layout detail designation, and applying a layout algorithm based on the first selection of a system table, the layout mode designation, the layout mode designation, the system orientation, the system spacing and the layout detail designation. | 05-19-2016 |
| 20160179995 | Transistor Plasma Charging Eliminator | 06-23-2016 |
| 20160378888 | MODELING TRANSISTOR PERFORMANCE CONSIDERING NON-UNIFORM LOCAL LAYOUT EFFECTS - In a system and method, a design layout defines a transistor, a local layout effect (LLE)-inducing feature and shapes, including a non-uniform shape, that illustrate separation between the channel region and LLE-inducing feature. Layout information for the non-uniform shape, including minimum and maximum distances between the channel region and LLE-inducing feature, is extracted. Based on this layout information, a first width of a first portion of the non-uniform shape, which is associated with the maximum distance, and a second width of a second portion of the non-uniform shape, which is associated with the minimum distance, are derived and used to calculate the non-uniform shape's contribution to the value of a model parameter adjuster. The value of the model parameter adjuster is then calculated based on a sum of contributions from all shapes and used to generate a compact model for modeling a performance attribute of the transistor within the IC. | 12-29-2016 |
