| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 716134000 | For timing | 49 |
| 20110035717 | Design Optimization for Circuit Migration - An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist. | 02-10-2011 |
| 20110041114 | CIRCUIT DESIGN SUPPORT APPARATUS, CIRCUIT DESIGN SUPPORT METHOD, AND CIRCUIT DESIGN SUPPORT PROGRAM - A circuit design support apparatus for supporting design of a semiconductor integrated circuit includes an upper limit path delay determining unit that sorts circuit paths included in the semiconductor integrated circuit by probability distributions for the delay values of the circuit paths, selects a worst path having a largest delay value in the circuit paths, and determines a maximum delay value as an upper limit path delay value that does not affect an operational timing of the semiconductor integrated circuit, a cell size optimization processor that replaces cells by modifying their cell sizes on the basis of the upper limit path delay value, and a critical path determining unit that determines critical paths that are capable of affecting the upper limit path delay value if the cell size optimization processor replaces cells included in the circuit paths. | 02-17-2011 |
| 20110099531 | Statistical delay and noise calculation considering cell and interconnect variations - The electrical circuit timing method provides accurate nominal delay together with the delay sensitivities with respect to different circuit elements (e.g., cells, interconnects, etc.) and variational parameters (e.g., process variations; environmental variations). All the sensitivity computations are based on closed-form formulas; as a consequence, the method provides rapidly and at low cost high accuracy and high numerical stability. | 04-28-2011 |
| 20110107291 | DESIGN SYSTEM AND METHOD THAT, DURING TIMING ANALYSIS, COMPENSATES FOR REGIONAL TIMING VARIATIONS - Disclosed are embodiments that allow for compensation of regional timing variations during timing analysis and, optionally, allow for optimize placement of critical paths, as a function of such regional timing variations. Based on an initial placement of devices for an integrated circuit chip, regional variations in one or more physical conditions that impact device timing (e.g., polysilicon perimeter density, average distance of devices to a well edge, average reflectivity) are mapped. Then, using a table that associates different derating factors with different levels of the physical condition(s), derating factors are assigned to different regions on the map. Next, a timing analysis is performed such that, for each region, delay of any path within that region is derated by the assigned derating factor. The map information can also be used when establishing a final placement of the devices on the integrated circuit chip in order to optimize placement of critical paths. | 05-05-2011 |
| 20110138348 | HIERARCHICAL PRESENTATION TECHNIQUES FOR A DESIGN TOOL - A design tool hierarchically presents information about a design with nested blocks. For example, the design tool presents scheduling information for the design in a hierarchical Gantt chart. The scheduling information includes hierarchical design schedule blocks which accurately depict the timing and scheduling of the nested blocks of the design. Each of the hierarchical design schedule blocks includes control steps numbered relative to the block. The scheduling information also includes a hierarchical list of scheduled operations for the design. The hierarchical list emphasizes which operations are associated with which nested blocks. The scheduling information further includes pseudo-operation icons that are easily differentiated from real operation icons in the hierarchical Gantt chart. | 06-09-2011 |
| 20110138349 | Automated Digital Circuit Design Tool That Reduces or Eliminates Adverse Timing Constraints Due To An Inherent Clock Signal Skew, and Applications Thereof - The present invention provides an automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof In an embodiment, an automated design tool according to the invention generates a clocking system that includes a clock signal generator, control logic, enable logic, and at least one clock gater. The clock signal generator generates a clock signal that is distributed to various logic blocks of the digital circuit using a buffered clock tree. The enable logic receives input values from the control logic and provides a control signal to the clock gater. When enabled, the clock gater allows a clock signal to pass through to multiple registers. An early clock signal is provided to register(s) in the control logic, which allows for an increased clock frequency while still meeting timing constraints. | 06-09-2011 |
| 20110252393 | AUTOMATIC GENERATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CIRCUITS - Individual mode timing constraints associated with a set of netlists are combined into merged mode timing constraints. An initial merged mode constraint is generated by combining timing constraints from individual modes. The initial merged mode includes the union of all timing constraints from individual modes that add timing relationships and the intersection of all timing constraints from the individual modes that remove timing relationships. Extraneous timing relationships are identified in the merged mode and eliminated by introducing timing constraints in the merged mode. Equivalence between the merged mode and the individual modes is verified by comparing timing relationships in the merged mode with timing relationships in the individual modes. The merged mode is considered equivalent to the individual modes if every timing relationship present in an individual mode is present in the merged mode and every timing relationship present in the merged mode is present in any of individual modes. | 10-13-2011 |
| 20110258591 | METHOD AND APPARATUS TO OPTIMIZE ADAPTIVE RADIO-FREQUENCY SYSTEMS - A performance optimizing circuit is provided for a signal processing system which is parameterized by a set of coefficients that vary the operational characteristics of the signal processing system. The performance optimizing circuit receives as input a reference signal and an output signal of the signal processing system. The performance optimizing circuit may include (a) a cost computation circuit that receives the reference signal and the output signal and provides as output a cost signal representing a cost function computed using a set of current values for the set of coefficients, the output signal and the reference signal; and (b) a cost optimizer circuit that, at each of a plurality of successive time intervals, evaluates one or more values of the cost signal in the cost computation circuit and provides to the signal processing system a new set of values for the set of coefficients. The cost optimizer circuit implements two or more of the random search, parabolic interpolation and hill climbing techniques. | 10-20-2011 |
| 20120030642 | HYPER-CONCURRENT MULTI-SCENARIO OPTIMIZATION - Some embodiments of the present invention provide techniques and systems for performing aggressive and dynamic scenario reduction during different phases of optimization, e.g., during delay, area, leakage and DRC (design rule check) optimization. Specifically, essential scenarios at gates and timing end-points can be identified and then used during the dynamic scenario reduction process. In some embodiments, margin values associated with various constraints can be used to determine the set of essential scenarios to account for constrained objects that are near critical in addition to the constrained objects that are the worst violators. In some embodiments, at any point during the optimization process, only the set of essential scenarios are kept active, thereby substantially reducing runtime and memory requirements without compromising on the quality of results. | 02-02-2012 |
| 20120102447 | System and Method for Optimizing Logic Timing - In an embodiment, a system for optimizing a logic circuit is disclosed. The system is configured to identify an input of a logic circuit cell that violates a timing condition. The input of the logic circuit is coupled to a plurality of logic paths having at least one level of logic. The system is also configured to identify a last node along one of the plurality logic path that violates the timing condition, and insert a buffer at least one node before the last node along the one of the plurality of logic paths that violates the timing condition. The buffer also has a delay optimized to fix the timing condition. | 04-26-2012 |
| 20120102448 | Systems, Methods, and Programs for Leakage Power and Timing Optimization in Integrated Circuit Designs - A method, system and program for reducing or optimizing leakage power consumption in an integrated circuit produced in accordance with an integrated circuit model. A fast corner timing database and configurable timing constraints are used in conjunction with hold cell logic to identify a set of cells that should not be modified. A leakage optimization procedure is responsive to a slow corner timing database and timing constraints for a slow corner. The procedure is configurable and includes the repair of register transition violations. The procedure is performed on a select number of paths before an adjusted timing slack value is determined and cells are addressed in response to the number of failing timing paths associated with a cell. Some embodiments generate information in a router compatible format that identifies a desired modification to the top-level integrated circuit design. | 04-26-2012 |
| 20120110541 | CONSTRAINT OPTIMIZATION OF SUB-NET LEVEL ROUTING IN ASIC DESIGN - Functionality can be implemented for optimizing connection constraints in an integrated circuit design. A target timing path associated with a first of a plurality of sub-connections of the integrated circuit is determined. A timing probability value and a route probability value associated with the first of the plurality of sub-connections is determined based, at least in part, on the target timing path associated with the first of the plurality of sub-connections. The timing probability value indicates a probability that timing closure is satisfied on the target timing path. The route probability value indicates a probability that a physical routing track on the target timing path associated with the first of the plurality of sub-connections resolves congestion. A current connection constraint associated with the first of the plurality of sub-connections is modified in accordance with a connection constraint model to which the first of the plurality of sub-connections corresponds. | 05-03-2012 |
| 20120124542 | Method and System for Optimizing a Device With Current Source Models - A method for optimizing a circuit includes at least a first branch and a second branch includes defining an objective function using a shape of waveforms measured at a timing point in each branch, and optimizing the objective function to minimize a variance of clock skew of the first branch and the second branch across different process voltage temperature values. | 05-17-2012 |
| 20120124543 | FLIP-FLOP LIBRARY DEVELOPMENT FOR HIGH FREQUENCY DESIGNS BUILT IN AN ASIC FLOW - A method, computer program storage device and system are provided for determination and selection of optimized circuit components. The method includes performing a timing analysis on at least a portion of an electronic circuit and determining a path in the at least a portion of an electronic circuit, where the path comprises at least one storage element and an operational attribute associated with the path. The method also includes determining an optimized storage element adapted to utilize the operational attribute. The system includes a processing device and at least one of a synthesis tool, a timing tool or a place and route tool communicatively connected to the processing device. The synthesis tool, the timing tool and the place and route tool are adapted to process or analyze an electrical circuit. The system also includes a gate library communicatively connected to the at least one of a synthesis tool, a timing tool and a place r route tool, as well as a substitution unit communicatively connected to at least one of the at least one of a synthesis tool, a timing tool or a place and route tool or the gate library. The substitution unit is adapted to substitute an optimized storage element for a storage element in the electrical circuit. | 05-17-2012 |
| 20120174053 | TEMPORALLY-ASSISTED RESOURCE SHARING IN ELECTRONIC SYSTEMS - Methods and apparatuses to optimize integrated circuits by identifying functional modules in the circuit having similar functionality that can share circuit resources and producing a modified description of the circuit where the similar functional modules are folded onto common circuit resources and time-multiplexed using an original system clock or a fast clock. | 07-05-2012 |
| 20120198410 | PREDICTION OF DYNAMIC CURRENT WAVEFORM AND SPECTRUM IN A SEMICONDUCTOR DEVICE - A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing and power consumption characteristics. In one embodiment, timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less. | 08-02-2012 |
| 20120221995 | SYSTEM AND METHOD FOR EMPLOYING SIGNOFF-QUALITY TIMING ANALYSIS INFORMATION CONCURRENTLY IN MULTIPLE SCENARIOS TO REDUCE DYNAMIC POWER IN AN ELECTRONIC CIRCUIT AND AN APPARATUS INCORPORATING THE SAME - A dynamic power recovery system and method are disclosed herein. Additionally, an EDA tool and apparatus configured to perform dynamic power recovery are disclosed. In one embodiment, the system includes: (1) a power recovery module configured to carry out an instance of an initial power recovery process in each of multiple scenarios concurrently, the initial power recovery process including making first conditional downsizing of cells in at least one path in a circuit design with lower dynamic power cells and estimating a delay and a slack of the at least one path based on the first conditional downsizings and (2) a speed recovery module associated with the power recovery module and configured to carry out a speed recovery process in each of the multiple scenarios concurrently, the speed recovery process including determining whether the first conditional downsizings cause a timing violation with respect to the at least one path and making second conditional upsizings with higher dynamic power cells until the timing violation is removed. | 08-30-2012 |
| 20120221996 | SYSTEM AND METHOD FOR DISTRIBUTION ANALYSIS OF STACKED-DIE INTEGRATED CIRCUITS - Systems and methods for distribution analysis of a stacked-die integrated circuit (IC) are described. The stacked-die integrated circuit includes a primary die, and clock load information for the primary die of the IC is determined. Additionally, a clock load model may be created using the clock load information for the primary die. Clock load information for a second die that is coupled to the primary die may also be determined. The clock load information for the second die may be incorporated into the clock load model to create an enhanced clock load model of the stacked-die IC, which may then be analyzed as if a single-die IC. | 08-30-2012 |
| 20130091483 | AUTOMATIC FLOW OF MEGACELL GENERATION - A method and system optimizes or improves an electronic design by analyzing various signal paths in the electronic design and selecting certain critical paths, for example, failed-timing paths, to optimize. The optimizing method extracts the cascaded logic gates to create a megacell representing the function of the critical path, compare test parameters of the megacell with the critical path, and incorporate the megacell into the electronic design if the test parameters improve by an optimizing constraint. | 04-11-2013 |
| 20130145336 | PROGRESSIVE CIRCUIT EVALUATION FOR CIRCUIT OPTIMIZATION - Systems and techniques for optimizing a circuit design are described. Some embodiments reduce the number of gates in the library (e.g., by dynamically pruning the library) which are considered for optimization. Some embodiments create a linear delay model, and use the linear delay model instead of a non-linear delay model to substantially reduce the amount of computation required to check whether or not a particular replacement gate improves one or more metrics of the circuit design. Some embodiments determine an order for processing the gates in the library or for processing input pins of a gate to facilitate early rejection of a candidate gate in the library of gates. In some embodiments, the evaluation of the impact of a candidate gate transformation is done progressively and level-by-level only up to the point where the gate transformation degrades one or more metrics. | 06-06-2013 |
| 20130145337 | DELTA-SLACK PROPAGATION FOR CIRCUIT OPTIMIZATION - Systems and techniques for optimizing a circuit design are described. When a selected gate is transformed during optimization, it causes a slack value at a pin of the transformed gate to change. The change in the slack value, called the delta-slack, is then propagated through a transitive fanin cone and a transitive fanout cone of the transformed gate to compute the new slack values at all the affected pins of the design. Some embodiments update slack values without propagating arrival and required times, and also without repeatedly evaluating timing arcs to compute gate delays. The updated slack values can be used to compute timing metrics. The timing metrics can be used to decide whether or not to commit the gate transformation to the circuit design. | 06-06-2013 |
| 20130145338 | MODELING TRANSITION EFFECTS FOR CIRCUIT OPTIMIZATION - Systems and techniques are described for determining a transition-effect model for a timing arc of a library cell. A transition-effect model can be determined for each library cell that is used during an optimization process. The transition-effect models enable an optimization system to estimate the impact of a change in the transition at an output of a driver gate on the delays of downstream gates without requiring to propagate the change in the transition to the downstream gates. Once determined, the transition-effect models can be used to compute one or more transition-induced penalties during circuit optimization. An optimization system can then use the one or more transition-induced penalties to determine whether or not to accept an optimizing transformation, or to discretize a solution obtained from a numerical solver. | 06-06-2013 |
| 20130145339 | EFFICIENT TIMING CALCULATIONS IN NUMERICAL SEQUENTIAL CELL SIZING AND INCREMENTAL SLACK MARGIN PROPAGATION - Techniques and systems are described for improving the efficiency of timing calculations in numerical sequential cell sizing and for improving the efficiency of incremental slack margin propagation. Some embodiments cache timing-related information associated with a source driver that drives an input of a sequential cell that is being sized, and/or timing-related information for each output of the sequential cell that is being sized. The cached timing-related information for the source driver can be reused when sizing a different sequential cell. The cached timing-related information for the outputs of the sequential cell can be reused when evaluating alternatives for replacing the sequential cell. Some embodiments incrementally propagate slack margins in a lazy fashion (i.e., only when it is necessary to do so for correctness or accuracy reasons) while sizing gates in the circuit design in a reverse-levelized processing order. | 06-06-2013 |
| 20130152036 | OPTIMIZATION OF LIBRARY SLEW RATIO BASED CIRCUIT - Disclosed is a technique for providing minimal sequential overhead in a flip-flop circuit. Equalization of setup times is achieved in one embodiment. In addition, delays in clock to Q can be equalized for both rising data transitions and falling data transitions. Large setup times are not required since optimization techniques equalize setup times for both rising and falling data transitions. | 06-13-2013 |
| 20130159958 | EQUATION BASED TRANSIENT CIRCUIT OPTIMIZATION - Circuit simulation can be performed on digital, analog, and mixed signal types of circuitry. Phases of operation are identified for a circuit and transient behavior is analyzed. Multiple time points are identified and the circuit is replicated for those time points with evaluation of the circuitry performed at those various time points. Simultaneous optimization is performed across the time points. Transistors and other devices can have their lengths, widths, and number of fingers optimized. Simulation can include determining Kirchhoff current law equations for various nodes within the circuit. Equations describing device operation can include non-convex signomial equations and convex polynomial equations. | 06-20-2013 |
| 20130174115 | MODELING OF CELL DELAY CHANGE FOR ELECTRONIC DESIGN AUTOMATION - An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage V | 07-04-2013 |
| 20130179854 | DESIGN APPARATUS, METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, AND NON-TRANSITORY MEDIUM STORING PROGRAM FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a design apparatus includes a voltage drop analyzer, an improvement calculator, first and second cell replacing modules, and an outputting module. The voltage drop analyzer specifies a peak voltage drop point based on a cell library and design data. The cell library includes information on first and cell groups. The first cell replacing module changes the design data. The improvement calculator calculates a timing improvement. The second cell replacing module extracts at least one cell from second cell group in a target device corresponding to the design data changed by the first cell replacing module as a replacement candidate cell, based on the timing improvement, and changes the design data changed by the first cell replacing module. The outputting module outputs the design data changed by the second cell replacing module. | 07-11-2013 |
| 20130185692 | METHOD OF DESIGNING A SYSTEM-ON-CHIP INCLUDING A TAPLESS STANDARD CELL, DESIGNING SYSTEM AND SYSTEM-ON-CHIP - In a method of designing a system-on-chip including a tapless standard cell to which body biasing is applied, a slow corner timing parameter is adjusted to increase a slow corner of an operating speed distribution for the system-on-chip by reflecting forward body biasing, and a fast corner timing parameter is adjusted to decrease a fast corner of the operating speed distribution for the system-on-chip by reflecting reverse body biasing. The system-on-chip including the tapless standard cell is implemented based on the adjusted slow corner timing parameter corresponding to the increased slow corner and the adjusted fast corner timing parameter corresponding to the decreased fast corner. The slow corner timing parameter corresponds to a lowest value of an operating speed design window of the system-on-chip, and, the fast corner timing parameter corresponds to a highest value of the operating speed design window of the system-on-chip. | 07-18-2013 |
| 20140033161 | ACCURATE APPROXIMATION OF THE OBJECTIVE FUNCTION FOR SOLVING THE GATE-SIZING PROBLEM USING A NUMERICAL SOLVER - Systems and techniques are described for optimizing a circuit design by using a numerical solver. Some embodiments construct a set of lower bound expressions for a parameter that is used in an approximation of an objective function. Next, the embodiments evaluate the set of lower bound expressions to obtain a set of lower bound values. The embodiments then determine a maximum lower bound value from the set of lower bound values. Next, while solving a gate sizing problem using the numerical solver, the embodiments evaluate the approximate objective function and the partial derivatives of the approximate objective function by using the maximum lower bound value of the parameter. The maximum lower bound value of this parameter determines the accuracy of the approximation of the objective function. | 01-30-2014 |
| 20140040851 | OPTIMIZING A CIRCUIT DESIGN FOR DELAY USING LOAD-AND-SLEW-INDEPENDENT NUMERICAL DELAY MODELS - Systems and techniques are described for optimizing a circuit design. Specifically, gate sizes in the circuit design are optimized by iteratively performing a set of operations that include, but are not limited to: selecting a portion of the circuit design (e.g., according to a reverse-levelized processing order), selecting an input-to-output arc of a driver gate in the portion of the circuit design, selecting gates in the portion of the circuit design for optimization, modeling a gate optimization problem based on the selected input-to-output arc of the driver gate and the selected gates, solving the gate optimization problem to obtain a solution using one or more solvers, and discretizing the solution. Discretizing the solution involves identifying library cells that exactly or closely match the gate sizes specified in the solution. These library cells can then be used to model other gate optimization problems in the current or subsequent iterations. | 02-06-2014 |
| 20140137070 | Advanced Array Local Clock Buffer Base Block Circuit - A clock stretcher mechanism is provided for shifting a rising edge of a negative active global clock signal beyond a rising edge of a feedback path signal. A negative active global clock signal and a clock chopper signal are received in a base block. First base block circuitry modifies the clock chopper signal in order to form the feedback path signal. Second base block circuitry shifts the rising edge of the negative active global clock signal beyond the rising edge of the feedback path signal using a delay negative active global clock signal. | 05-15-2014 |
| 20140143748 | SEMICONDUCTOR TIMING IMPROVEMENT - Approaches are provided for improving timing of new and existing semiconductor products. Specifically, a method is provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to set starting across chip variation assumptions using design rules. The programming instructions are further operable to design a test chip and/or product chip using the starting across chip variation assumptions to close timing of the design. The programming instructions are further operable to place devices in the test chip and/or product chip. The programming instructions are further operable to compare performance of the devices within the test chip and/or the product chip to the starting across chip variation assumptions. The programming instructions are further operable to adjust the starting across chip variation assumptions based on the measured performance of the test chip and/or the product chip. | 05-22-2014 |
| 20140165022 | RELATIVE TIMING ARCHITECTURE - Technology for generating a relative timing architecture using a relative timed module is disclosed. In an example, an electronic design automation (EDA) tool enabled for clocked tool flows can include computer circuitry configured to: Generate a hardware description language (HDL) integrated circuit (IC) architecture using the relative timed module; map a relative timing constraint on to a relative timed instance of the relative timed module; and generate a timing target for each relative timing constraint. | 06-12-2014 |
| 20140181779 | TIMING BOTTLENECK ANALYSIS ACROSS PIPELINES TO GUIDE OPTIMIZATION WITH USEFUL SKEW - Techniques and systems for guiding circuit optimization are described. Some embodiments compute a set of aggregate slacks for a set of chains of logic paths in a circuit design. Each chain of logic paths starts from a primary input or a sequential circuit element that only launches a signal but does not capture a signal and ends at a primary output or a sequential circuit element that only captures a signal but does not launch a signal. Next, the embodiments guide circuit optimization of the circuit design based on the set of aggregate slacks. | 06-26-2014 |
| 20140189633 | SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN SUPPORTING APPARATUS, METHOD, AND PROGRAM - A latency adjusting part calculates a necessary delay based on the number of FFs that are required to be inserted between respective modules through high level synthesis of a behavioral description. An input FF stage number acquiring part extracts a pin having an input that receives an FF, and acquires the number of stages of input FFs of FF reception. A latency re-adjusting part obtains an optimum delay based on the above-mentioned necessary delay and input delay. A former-stage module analyzing part detects, based on the above-mentioned synthetic log or HDL, a state having a minimum total number of FFs. An FF insertion optimizing synthesis part subjects an entire circuit to high level synthesis again based on the above-mentioned optimum delay and an FF inserting position obtained based on the state having the minimum number of FFs, to thereby obtain optimized HDL. | 07-03-2014 |
| 20140189634 | PRIORI CORNER AND MODE REDUCTION - Systems and techniques are described for performing a priori corner and mode reduction. Some embodiments create a synthetic corner in which (1) a cell delay for each library cell in a set of library cells corresponds to a maximum delay over multiple temperature corners, and/or (2) a cell delay for each library cell in a set of library cells corresponds to a maximum delay over multiple parasitic corners. Some embodiments can identifying, for a given corner, a portion of the circuit design that is common across multiple modes, and then replace the multiple modes with a single mode for optimizing and verifying timing constraints of the portion of the circuit design that is common across the multiple modes. The circuit design can then be optimized over the reduced set of modes and/or corners. | 07-03-2014 |
| 20140245251 | Design Optimization for Circuit Migration - An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist. | 08-28-2014 |
| 20140258964 | AUTOMATIC SYNTHESIS OF COMPLEX CLOCK SYSTEMS - A global optimization method to synthesize and balance the clock systems in a multimode, multi-corner, and multi-domain design environment is described. The method builds a graph representation for a clock network. The method determines an optimal clock network balancing solution for the clock network by applying linear programming to the graph. To apply linear programming to the graph, the method generates a set of constraints for the graph and determines a proper insertion delay for each edge of the graph by solving for a minimal skew based on the set of constraints. The method implements the optimal clock network balancing solution. | 09-11-2014 |
| 20140351783 | CHARACTERIZING TSV STRUCTURES IN A SEMICONDUCTOR CHIP STACK - A first signal is transmitted through a first path. A computing device determines a signal propagation time of the first signal. The computing device transmits a second signal through a second path, wherein the second path includes the second signal traversing across at least one interconnecting structure. The computing device determines a signal propagation time of the second signal. The computing device determines a propagation time difference between the signal propagation time of the first signal and the signal propagation time of the second signal. The computing device adjusts a clock based on the determined propagation time difference. | 11-27-2014 |
| 20140351784 | LAYOUT MODIFICATION METHOD AND SYSTEM - A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout. | 11-27-2014 |
| 20150040094 | SEQUENTIAL DELAY ANALYSIS BY PLACEMENT ENGINES - Some embodiments provide a method of designing an integrated circuit (IC). The design is expressed as a graph that includes several nodes that represent several IC components. The nodes include a first set of nodes that represent a set of clocked elements. The method creates a second set of nodes by removing all nodes in the first set from the nodes that represent the IC components. The method identifies a set of edges that connect two nodes in the second set without encompassing a third node in the second set. The method assigns an event time to each node in the second set. The method assigns a cost function based on the event times of the nodes connected by each edge and the number of nodes in the first set encompassed by each edge. The method optimizes the cost function and places the components based on the cost function optimization. | 02-05-2015 |
| 20150302124 | Designing Photonic Switching Systems Utilizing Equalized Drivers - Designing a photonics switching system is provided. A photonic switch diode is designed to attain each performance metric in a plurality of performance metrics associated with a photonic switching system based on a weighted value corresponding to each of the plurality of performance metrics. A switch driver circuit is selected from a plurality of switch driver circuits for the photonic switching system. It is determined whether each performance metric associated with the photonic switching system meets or exceeds a threshold value corresponding to each of the plurality of performance metrics based on the designed photonic switch diode and the selected switch driver circuit. In response to determining that each performance metric associated with the photonic switching system meets or exceeds the threshold value corresponding to each of the performance metrics, the photonic switching system is designed using the designed photonic switch diode and the selected switch driver circuit. | 10-22-2015 |
| 20150324512 | SEQUENTIAL TIMING USING LEVEL-SENSITIVE CLOCKED ELEMENTS TO OPTIMIZE IC PERFORMANCE - A method of optimizing timing performance of an IC design expressed as a graph that includes several nodes representing IC components is provided. The method identifies several paths in the graph. Each path starts from a timed source node and ends to a timed target node. Each path includes several clocked elements and several computational elements. The method optimizes the timing performance of the IC design by skewing clock signals to one or more clocked elements in a set of paths to satisfy timing constraints. The method identifies a path that includes a set of edge-triggered clocked elements and does not satisfy the set of timing constraints. The method replaces each edge-triggered clocked element in the identified path with a level-sensitive clocked element and optimizes the timing performance of the IC design by skewing clock signals one or more clocked element in the identified path. | 11-12-2015 |
| 20150324514 | OPTIMIZING IC PERFORMANCE USING SEQUENTIAL TIMING - A method of optimizing timing performance of an IC design is provided. The IC design is expressed as a graph that includes several nodes that represent IC components. The method identifies a path in the graph that starts from a timed source node and ends at a timed target node. The path has several clocked elements and several computational elements. The method optimizes the timing performance of the IC design by skewing clock signals to a set of clocked elements without changing the position of any clocked element relative to the position of the computational elements in the path. The clock signal of at least one clocked element is skewed by more than a period of the clock signal. The method implements the IC design by using the optimized IC design. | 11-12-2015 |
| 20150331981 | Timing Verification of an Integrated Circuit - This disclosure describes a design tool that verifies timing of an integrated circuit design by partitioning the integrated circuit design's gate-level netlist into target cell partition netlists and performs transistor-level circuit simulation on each target cell partition netlist. The design tool performs a back tracing procedure on each target sequential cell to define the target cell partition netlists. The design tool then identifies timing modes that enable valid logical paths through the target cell partition netlists from source sequential cells to the target sequential cells. In turn, the design tool performs transistor-level circuit simulation (e.g., SPICE simulations) on each target cell partition netlist to check for timing violations based upon the timing modes. In one embodiment, the design tool includes clock tree delay information, power supply variations, or routing parasitic information in the simulations to achieve improved timing analysis accuracy compared with traditional static timing analysis or timing optimization. | 11-19-2015 |
| 20150347655 | APPARATUS FOR AND A METHOD OF MAKING A HIERARCHICAL INTEGRATED CIRCUIT DESIGN OF AN INTEGRATED CIRCUIT DESIGN, A COMPUTER PROGRAM PRODUCT AND A NON-TRANSITORY TANGIBLE COMPUTER READABLE STORAGE MEDIUM - An apparatus for and a method of making a hierarchical integrated circuit design of an integrated circuit design, a computer program product and a non-transitory tangible computer readable storage medium are provided. The apparatus comprises an input for receiving an hierarchical integrated circuit design, a selector for selecting a candidate output pin, a cloner for adapting the hierarchical integrated circuit design, a re-connector for adapting the hierarchical integrated circuit design, and an output for outputting the adapted hierarchical circuit design. Optionally, the apparatus comprises a timing improver. The apparatus selects a candidate output pin of an IP block that is a node on at least two timing paths that have contradictory timing violations. The candidate output pin is cloned and at least one of the timings paths is connected to the cloned output pin for one of the instances of the IP block. | 12-03-2015 |
| 20150347669 | ALTERATION OF A SIGNAL VALUE FOR AN FPGA AT RUNTIME - A method for changing a signal value of an FPGA at runtime, including the steps of loading an FPGA hardware configuration with at least one signal value onto the FPGA, running the FPGA hardware configuration on the FPGA, setting the signal value for transfer to the FPGA, determining writeback data from the signal value, writing the writeback data as status data to a configuration memory of the FPGA, and transferring the status data from the configuration memory to the functional level of the FPGA. A method is also provided for performing an FPGA build, including the steps of creating an FPGA hardware configuration with a plurality of signal values, arranging signal values in adjacent areas of the FPGA hardware configuration, ascertaining memory locations of a configuration memory for status data of the plurality of signal values on the basis of the FPGA hardware configuration, and creating a list containing signal values. | 12-03-2015 |
| 20150379175 | IC DESIGN SYNTHESIS USING SLACK DIAGRAMS - An updated integrated circuit (IC) design is generated by applying a histogram-based algorithm to an invalid, current IC design. The histogram-based algorithm includes worst negative slack (WNS) optimization followed by total negative slack (TNS) optimization. WNS optimization uses the slack histogram for the current IC design to generate an invalid, but improved, intermediate IC design. TNS optimization uses the slack histogram of the intermediate IC design to generate the updated IC design. | 12-31-2015 |
| 20160171147 | MANAGING VIRTUAL BOUNDARIES TO ENABLE LOCK-FREE CONCURRENT REGION OPTIMIZATION OF AN INTEGRATED CIRCUIT | 06-16-2016 |
