| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 716133000 | For power | 53 |
| 20100281453 | SYSTEM AND METHOD FOR INCLUDING PROTECTIVE VOLTAGE SWITCHABLE DIELECTRIC MATERIAL IN THE DESIGN OR SIMULATION OF SUBSTRATE DEVICES - A substrate device is designed by identifying one or more criteria for handling of a transient electrical event on the substrate device. The one or more criteria may be based at least in part on an input provided from a designer. From the one or more criteria, one or more characteristics may be determined for integrating VSD material as a layer within or on at least a portion of the substrate device. The layer of VSD material may be positioned to protect one or more components of the substrate from the transient electrical condition. | 11-04-2010 |
| 20100281454 | SYSTEM AND METHOD FOR INCLUDING PROTECTIVE VOLTAGE SWITCHABLE DIELECTRIC MATERIAL IN THE DESIGN OR SIMULATION OF SUBSTRATE DEVICES - A substrate device is designed by identifying one or more criteria for handling of a transient electrical event on the substrate device. The one or more criteria may be based at least in part on an input provided from a designer. From the one or more criteria, one or more characteristics may be determined for integrating VSD material as a layer within or on at least a portion of the substrate device. The layer of VSD material may be positioned to protect one or more components of the substrate from the transient electrical condition. | 11-04-2010 |
| 20110023003 | Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits - A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC. | 01-27-2011 |
| 20110138347 | SYSTEM AND METHOD FOR DESIGNING INTEGRATED CIRCUITS THAT EMPLOY ADAPTIVE VOLTAGE SCALING OPTIMIZATION - A design process optimization system and method for designing a circuit, which may be an integrated circuit (IC) employing adaptive voltage and scaling optimization (AVSO). In one embodiment, the system includes: (1) a process-voltage-temperature (PVT) libraries database configured to contain PVT libraries of PVT characterizations of devices of cells from which the circuit is to be constructed and (2) a PVT library selector coupled to the PVT libraries database and configured to receive a selection indicating a supplemental objective and respond to the selection by selecting one of the PVT libraries from the PVT libraries database, a timing signoff tool later employing at most two corners from the one of the PVT libraries to perform a timing signoff with respect to the circuit. | 06-09-2011 |
| 20110173585 | BATTERY CHARACTERISTIC EVALUATOR - There is provided a battery characteristic evaluator configured to identify a circuit constant of an equivalent circuit model based on a current-voltage characteristic of a battery. The battery characteristic evaluator includes: a current waveform divider configured to divide a certain current waveform into a plurality of step functions with a plurality of infinitesimal time intervals and output the step functions; and a circuit constant optimizing unit configured to calculate the optimized circuit constant of the equivalent circuit model, based on the step functions, a measured voltage value, and equivalent circuit model data. | 07-14-2011 |
| 20110185331 | Reducing Voltage Drops in Power Networks Using Unused Spaces in Integrated Circuits - A method of designing an integrated circuit includes providing an integrated circuit design including a power network. A voltage drop mitigation system is provided, which includes a power strap enhancer configured to automatically find a source node and a terminal node in the power network. A redundant strap for the power network using the voltage drop mitigation system is added, wherein the redundant strap interconnects the source node and the terminal node. After the step of adding the redundant strap, dummy patterns may be added. | 07-28-2011 |
| 20110185332 | MODEL BASED SIMULATION AND OPTIMIZATION METHODOLOGY FOR DESIGN CHECKING - A method, apparatus and program product are provided for simulating a circuit. A plurality of elements of the circuit is represented by device models including pass/fail criteria. A circuit simulation program is executed on a hardware implemented processor where the circuit simulation program is configured to obtain simulation results from the device models in response to applied parameters. The circuit simulation program identifies a failure of one or more of the plurality of elements of the circuit based on the pass/fail criteria of the device models. The circuit simulation program is further configured to output the failures during simulation of the one or more of the plurality of elements that are identified in response to the applied parameters. | 07-28-2011 |
| 20110185333 | GLOBAL LEAKAGE POWER OPTIMIZATION - Some embodiments provide techniques and systems for optimizing a circuit design's global leakage power. During operation, the system can determine leakage potentials for logic gates in the circuit design, such that a logic gate's leakage potential indicates an amount or degree by which the logic gate's leakage power is decreasable. The system can then determine a processing order for processing the logic gates based at least on the leakage potentials. Next, the system can optimize the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order. | 07-28-2011 |
| 20110209113 | Methods and Apparatuses for Thermal Analysis Based Circuit Design - Methods and apparatuses for circuit design to reduce power usage, such as reducing temperature dependent power usage, and/or to improve timing, such as reducing temperature dependent delay or transition time. At least one embodiment of the present invention reduces the power dissipation and improves the timing of an integrated circuit to optimize the design. A thermal analysis is used to determine the temperature dependent power dissipation of a circuit and the temperature distribution of the circuit resulting from dissipating the heat created by the temperature dependent power dissipation. Then, the components of the design are selectively transformed to reduce the power dissipation and to improve timing based on the temperature solution. The transformation may include placement changes and netlist changes, such as the change of transistor threshold voltages for cells or for blocks of the circuit chip. | 08-25-2011 |
| 20110258590 | SOFTWARE CONTROLLED TRANSISTOR BODY BIAS - Software controlled transistor body bias. A target frequency is accessed. Using software, transistor body-biasing values are determined for the target frequency in order to enhance a characteristic of a circuit. The bodies of the transistors are biased based on the body-biasing values, wherein the characteristic is enhanced. | 10-20-2011 |
| 20110276938 | POWER SUPPLY OPTIMIZATION FOR ELECTRICAL CIRCUITS DESIGNED OVER THE INTERNET - A method may include receiving an input from an optimization control that indicates a value along a scale, wherein the value is indicative of a design tradeoff between at least optimization for a first parameter of an electrical design and an optimization for a second parameter of the electrical design, wherein the value places an emphasis on the first parameter and an emphasis on the second parameter such that when the value on the scale is closer to the first parameter a larger emphasis is placed on the first parameter of the electrical design and when the value on the scale is closer to the second parameter a larger emphasis is placed on the second parameter of the electrical design. The method may further include choosing components for the electrical design based on the value indicated using the optimization control, the emphases affecting the components selected for the electrical design. | 11-10-2011 |
| 20120023473 | GRANULAR CHANNEL WIDTH FOR POWER OPTIMIZATION - A storage medium recording a cell library having one or more cells that may be readable by a computer and may be used by the computer to design an integrated circuit. The one or more cells may have a physical dimension parameter and a channel width parameter. The physical dimension parameter may be a footprint of the one or more cells. The channel width parameter may have a minimum driver size and a maximum driver size. The channel width parameter may define a range within which a tool varies the channel width between the maximum driver size and the minimum driver size during a design flow of the integrated circuit based upon one or more power criteria without changing the footprint. | 01-26-2012 |
| 20120096423 | METHOD FOR DESIGNING LED DRIVER CIRCUIT - A method for designing an LED driver circuit is disclosed, wherein the LED driver circuit serves to drive an LED circuit. The method includes the steps of: providing an LED driver circuit; calculating a design voltage and a design current; designing an actual driving voltage; designing a voltage output end voltage; and designing an actual driving current. The LED driver circuit includes a power source IC and a current-limiting resistor. The current-limiting resistor is electrically connected between a voltage output end and a voltage-regulating end of the power source IC. The actual driving current is designed by calculating the actual driving voltage and the voltage output end voltage according to the design voltage and by calculating the resistance value of the current-limiting resistor according to the design current. With the disclosed method, the design of an LED driver circuit capable of a stable and constant current can be rapidly completed. | 04-19-2012 |
| 20120144362 | METHOD AND DATA PROCESSING SYSTEM TO OPTIMIZE PERFORMANCE OF AN ELECTRIC CIRCUIT DESIGN, DATA PROCESSING PROGRAM AND COMPUTER PROGRAM PRODUCT - A method to optimize performance of an electric circuit design is disclosed. The method comprises providing for each circuit element of the electric circuit design available design parameter options; transforming the electric circuit design and the design parameter options into a linear programming model; determining a solution for the linear programming model; and based on the solution generating a list of circuit elements which design parameters need to be changed to a different option to achieve performance optimization. | 06-07-2012 |
| 20120216168 | GATE CONFIGURATION DETERMINATION AND SELECTION FROM STANDARD CELL LIBRARY - A method comprises determining gate configuration from a standard cell library for optimizing behavior of a logic gate in an electronic circuit to be resized. The determining includes defining variables for the logic gate to be resized and defining nets influenced by the logic gate to be resized. The determining includes determining constraints relative to other logic gates in the electronic circuit affected by the logic gate to be resized and formulating objective function to be solved by the electronic circuit. The determining includes solving the objective function using a linear programming solver based on the defined variables and the determined constraints. The determining includes outputting solving of the objective function obtained by linear programming solver for further processing. The gate configuration is selected from the standard cell library for optimizing behavior of the logic gate to be resized based on solving of the objective function. | 08-23-2012 |
| 20120290999 | Optimized Semiconductor Packaging in a Three-Dimensional Stack - A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer. | 11-15-2012 |
| 20120304144 | Power Mesh Managing Method - The invention discloses a power mesh managing method utilized in an integrated circuit. The integrated circuit includes a standard cell and a standard-cell power supplying mesh corresponding to a first direction. The power mesh managing method includes: defining a power supplying network including a first plurality of power meshes growing along the first direction and a second plurality of power meshes growing along a second direction, and defining an assistant connecting network on a third metal layer, wherein the assistant connecting network includes a plurality of assistant connecting lines growing along the second direction, the first plurality of power meshes are formed on a first metal layer, the second plurality of power meshes on a second metal layer, the third metal layer is below the first metal layer, and the second metal layer is above the first metal layer. | 11-29-2012 |
| 20120324413 | SEMICONDUCTOR MEMORY - A method includes simulating a first design of a semiconductor memory that includes at least one device disposed between and coupled to a memory bit cell and to a power supply line, determining if at least one simulated operational value of the semiconductor memory is above a threshold value, and adjusting at least one of a size of the device or a type of the device if the at least one simulated operational value is below the threshold value. The memory bit cell is disposed in a column including a plurality of bit cells. The size or type of the device is repeatedly adjusted and the design of the semiconductor memory is repeatedly simulated until the at least one simulated operational value is at or above the threshold value. | 12-20-2012 |
| 20130007690 | ELECTRONIC DEVICE AND SIMULATION METHOD FOR CHECKING PRINTED CIRCUIT BOARD POWER LOSS - An electronic device reads a layout file of a printed circuit board (PCB) to be manufactured from a storage device, obtains length information and section area information of copper cladding distributed on power source areas and ground trace areas in each of one or more layers of the PCB to be manufactured by analyzing the layout file, and calculates power loss in each of the one or more layers according to the length information, the section area information, a resistance value of the copper cladding, and preset parameters of a power supply module and an integrated circuit (IC) load to be located on the PCB. In response to a determination that the power loss in the layer exceeds a preset range, the electronic device indicates the locations of the power source areas and the ground trace areas of a layer in the PCB layout file which need to be redesigned. | 01-03-2013 |
| 20130007691 | MATCHING SYSTEMS WITH POWER AND THERMAL DOMAINS - A method for matching systems with power and thermal domains is provided in the illustrative embodiments. A subset of the set of systems is sorted according to size to form a sorted list of systems. The smallest remaining system in the sorted list of systems is selected. The smallest remaining system is allocated to a domain responsive to a determination that the domain can service the smallest remaining system. A system from a second subset is allocated to a plurality of domains such that the plurality of domains includes a smallest number of domains from the set of domains. | 01-03-2013 |
| 20130074030 | METHOD, COMPUTER PROGRAM AND COMPUTING SYSTEM FOR OPTIMIZING AN ARCHITECTURAL MODEL OF A MICROPROCESSOR - A computer program for optimizing an architectural model of a microprocessor by configuring elements of the instruction set as nodes of the graph. The architectural model of a microprocessor represents an instruction set of the microprocessor. Determination is made whether nodes with identical bit position and value encoding are in the graph. If nodes with the identical bit position and value encoding are present, a path from a source node to a target node is separated into a common node for each node in the graph. The common node is reused to optimize common paths from the graph and the source node is directly connected to the common node in the graph using a forward edge. A back-edge is added from the common node to the source node through the target node and the above steps are recursively repeated until all nodes of the graph are processed. | 03-21-2013 |
| 20130080990 | METHOD OF REDUCING POWER LEAKAGE OF INTEGRATED CIRCUIT - A method and system for performing power leakage reduction for an integrated circuit (IC) in a Virtual Multi-mode Multi-corner set up. Multiple view of the IC design data are analyzed in parallel to determine which low threshold voltage cells (LTVC) may be replaced with high threshold voltage cells (HVTC). A second analysis is performed that combines the analyses of each of the analyzed views and the IC design data is updated, where all of the LTVCs having positive slack time in all of the plurality of views are replaced with HTVCs. | 03-28-2013 |
| 20130104097 | PROGRAMMATIC AUTO-CONVERGENT METHOD FOR "PHYSICAL LAYOUT POWER HOT-SPOT" RISK AWARE ASIP ARCHITECTURE CUSTOMIZATION FOR PERFORMANCE OPTIMIZATION - Systems and methods are disclosed to automatically method to manage power in a custom integrated circuit (IC) design with a code profile by receiving an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operations or activities over a plurality of processing blocks to reduce hot spots; applying sub-region weight distributions to estimate power hot-spot locations; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. | 04-25-2013 |
| 20130111426 | PROGRAMMATIC AUTO-CONVERGENT METHOD FOR PHYSICAL DESIGN FLOORPLAN AWARE RE-TARGETABLE TOOL SUITE GENERATION (COMPILER-IN-THE-LOOP) FOR SIMULTANEOUS INSTRUCTION LEVEL (SOFTWARE) POWER OPTIMIZATION AND ARCHITECTURE LEVEL PERFORMANCE OPTIMIZATION FOR ASIP DESIGN | 05-02-2013 |
| 20130125081 | Automated Circuit Design Using Active Set Solving Process - A method is described that involves solving a family of equations for a circuit being designed over a subset of operational scenarios, thereby producing numeric values for design parameters of the circuit. The family of equations is enhanced with the numeric values are solved over a second subset of the operational scenarios. A design for the circuit that includes the numeric values is produced. | 05-16-2013 |
| 20130145335 | Hardware Synthesis Using Thermally Aware Scheduling And Binding - Technologies are generally described for hardware synthesis using thermally aware scheduling and binding. Multiple versions of a hardware design may be generated, each having variations of schedule and binding results. The scheduling and binding may be performed such that thermal profiles of the multiple versions have thermal peaks that are distant between the versions. The increased physical distance between the thermal peaks of the versions can give the versions unique thermal characteristics. A schedule of rotation between the multiple versions of the design may be constructed such that the thermal profile of the integrated circuit balances out during operation. A linear programming framework may be used to analyze the multiple designs and construct a thermally aware rotation scheduling and binding. For example, the K most efficient versions may be selected and then durations for operating each version within a rotation may be determined. | 06-06-2013 |
| 20130212550 | Thermal Relief Automation - An approach is provided in which a dynamic thermal relief generator retrieves a circuit board file that identifies power plane thru pin locations and a power plane layer. The dynamic thermal relief generator selects one of the power plane thru pin locations and identifies one or more electrical properties corresponding to a component assigned to the selected power plane thru pin location. As such, the dynamic thermal relief generator computes a conductive material exclusion amount based upon the identified electrical properties, which indicates an amount of area to exclude conductive material on the selected power plane layer. In turn, the dynamic thermal relief generator creates a thermal relief pattern based upon the computed conductive material exclusion amount that identifies conductive material voids on the selected power plane layer to exclude the substantially conductive material. | 08-15-2013 |
| 20130212551 | POWER SUPPLY CIRCUIT DESIGN SYSTEM AND POWER SUPPLY CIRCUIT DESIGN METHOD - A power supply circuit design system according to an exemplary aspect of the invention includes: a power supply voltage fluctuation deriving means for deriving a power supply voltage fluctuation characteristic as a voltage fluctuation characteristic in a semiconductor integrated circuit on the basis of design information about a power supply circuit for connecting the semiconductor integrated circuit and other components mounted on a substrate; a determination reference database including a power supply voltage fluctuation condition as a condition for which the power supply voltage fluctuation characteristic is allowed in the power supply circuit, and a change indicator for at least one of a circuit structure and operation of the semiconductor integrated circuit; a power supply voltage fluctuation determination means for comparing the power supply voltage fluctuation characteristic and the power supply voltage fluctuation condition, and determining whether the power supply voltage fluctuation characteristic satisfies the power supply voltage fluctuation condition; and a circuit structure changing means for changing at least one of the structure and the operation of the semiconductor integrated circuit in accordance with the change indicator if the power supply voltage fluctuation characteristic does not satisfy the power supply voltage fluctuation condition, and outputting design information about the changed semiconductor integrated circuit to the power supply voltage fluctuation deriving means; wherein the change indicator does not entail a change in size of the semiconductor integrated circuit. | 08-15-2013 |
| 20130254734 | Standard Cells having transistors annotated for gate-length biasing - A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device. | 09-26-2013 |
| 20130311965 | APPARATUS AND METHOD FOR OPTIMIZED POWER CELL SYNTHESIZER - Apparatus for providing semiconductor device with an analysis module to receive device information, a G-function processor producing an ordered relationship representation corresponding to an optimization parameter specification, and a power cell optimizer to produce an optimization parameter from the ordered relationship representation. A method for designing a semiconductor device includes receiving an optimization target specification; receiving an optimization parameter specification corresponding to an optimization parameter; receiving a the target parameter; receiving a G-function corresponding to an ordered relationship representation; optimizing the optimization parameter specification as a function of the predetermined G-function; and producing at least one optimized geometric layout parameter (GLP) by the optimizing, wherein the at least one GLP corresponds to an optimized power cell. | 11-21-2013 |
| 20130326459 | POWER/PERFORMANCE OPTIMIZATION THROUGH TEMPERATURE/VOLTAGE CONTROL - A method of optimizing power and timing for an integrated circuit (IC) chip, identifies a plurality of valid temperature and voltage combinations that allow integrated circuit chips produced according to the integrated circuit chip design to operate within average power consumption goals and timing delay goals. Such a method selects temperature cut points from the valid temperature and voltage combinations for each of the integrated circuit chips, calculates a power consumption amount of each of the temperature cut points, and adjusts the temperature cut points based on the power consumption amount until the temperature cut points achieve the average power consumption goals. Next, this method tests each of the integrated circuit chips, and records the temperature cut points in the memory of the integrated circuit chips. | 12-05-2013 |
| 20130326460 | POWER AND TIMING OPTIMIZATION FOR AN INTEGRATED CIRCUIT BY VOLTAGE MODIFICATION ACROSS VARIOUS RANGES OF TEMPERATURES - A method of optimizing power and timing for an integrated circuit (IC) chip, which uses an IC technology that exhibits temperature inversion, by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges. A high voltage is selected that meets a closed timing analysis across a full temperature range to meet a timing performance and a low voltage is selected to meet the timing performance and the power performance across a lower temperature range to a temperature cut point in the higher temperature range. The IC chip is turned on at the high voltage and the high voltage is lowered to the low voltage when the temperature cut point is exceeded to meet the power performance while maintaining the timing performance. | 12-05-2013 |
| 20140013293 | HIERARCHICAL POWER MAP FOR LOW POWER DESIGN - Power information associated with an IC design is displayed graphically and hierarchically using a power map, thereby providing an intuitive way for describing the power distribution among various power domains of the IC and parent-child relationships within the power domains. Each power domain is associated with a power control for controlling the power domain. The status of the power control for each power domain is displayed on the power map. The power map may include a token to set and display current operating mode of the IC design to enable the IC design to be debugged under different operating modes. | 01-09-2014 |
| 20140013294 | METHOD FOR RANKING PATHS FOR POWER OPTIMIZATION OF AN INTEGRATED CIRCUIT DESIGN AND CORRESPONDING COMPUTER PROGRAM PRODUCT - The invention pertains to a method for ranking paths for power optimization of an integrated circuit design, comprising identifying a plurality of paths of the integrated circuit design, each path comprising one or more instances of electronic devices providing an instance power estimate for each instance in the identified paths providing, for each identified path, at least one weighted power estimate based on the instance power estimates for instances in the path, and providing a ranking of the paths based on the least one weighted power estimate. The invention also pertains to a corresponding computer program product. | 01-09-2014 |
| 20140013295 | METHOD TO AUTOMATICALLY ADD POWER LINE IN CHANNEL BETWEEN MACROS - A method includes detecting channels between macros in an integrated circuit. Each channel is associated with a region between two macros such that a shortest distance of the region satisfies a threshold value. The method also includes automatically adding at least one power line within at least one channel to satisfy a power integrity issue within the at least one channel. The power integrity issue is satisfied when two power lines having opposite polarity are coupled to provide power to a device within the at least one channel. | 01-09-2014 |
| 20140033160 | SOFTWARE CONTROLLED TRANSISTOR BODY BIAS - Software controlled transistor body bias. A target frequency is accessed. Using software, transistor body-biasing values are determined for the target frequency in order to enhance a characteristic of a circuit. The bodies of the transistors are biased based on the body-biasing values, wherein the characteristic is enhanced. | 01-30-2014 |
| 20140053124 | THERMAL ANALYSIS BASED CIRCUIT DESIGN - Methods and apparatuses for circuit design to reduce power usage, such as reducing temperature dependent power usage, and/or to improve timing, such as reducing temperature dependent delay or transition time. At least one embodiment of the method implemented on a data processing system for circuit design, the method comprises determining for a first design of a circuit a first temperature solution and a first power dissipation solution, the first power dissipation solution and the first temperature solution being interdependent, and transforming the first design of the circuit into a second design of the circuit using the first temperature solution to reduce leakage power of the circuit under one or more design constraints. | 02-20-2014 |
| 20140082580 | CURRENT-AWARE FLOORPLANNING TO OVERCOME CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS - A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack. | 03-20-2014 |
| 20140096102 | SYSTEM AND METHOD FOR ACROSS-CHIP THERMAL AND POWER MANAGEMENT IN STACKED IC DESIGNS - A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, inputting a power profile in a computer processor, generating a transient temperature profile based on the 3D-IC model, identifying a potential thermal violation at a corresponding operating time interval and a corresponding location of a plurality of points of the 3D-IC design, and outputting data representing the potential thermal violation. The 3D-IC model represents a 3D-IC design comprising a plurality of elements in a stack configuration. The power profile is applied to the plurality of elements of the 3D-IC design as a function of an operating time. The transient temperature profile includes temperatures at a plurality of points of the 3D-IC design as a function of an operating time. | 04-03-2014 |
| 20140165021 | SYSTEM AND METHODS FOR DYNAMIC MANAGEMENT OF HARDWARE RESOURCES - A dynamically reconfigurable framework manages processing applications in order to meet time-varying constraints to select an optimal hardware architecture. The optimal architecture satisfies time-varying constraints including for example, supplied power, required performance, accuracy levels, available bandwidth, and quality of output such as image reconstruction. The process of determining an optimal solution is defined in terms of multi-objective optimization using Pareto-optimal realizations. | 06-12-2014 |
| 20140195999 | METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT - A method of designing a semiconductor integrated circuit, includes inserting, between a power supply voltage and a ground voltage, at least two types of capacitor cells which have a different ratio, the ratio being between an inverse number of a capacitance value of a capacitative element and a resistance value of an equivalent series resistance, such that an impedance between the power supply voltage and the ground voltage in a resonance frequency according to capacitances of the at least two types of capacitor cells and an external inductance, and an impedance between the power supply voltage and the ground voltage in a target frequency, are near respective desired values or less than or equal to the respective desired values. | 07-10-2014 |
| 20140223404 | Gate-Length Biasing for Digital Circuit Optimization - Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology that changes a nominal gate-length of a transistor to a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length. | 08-07-2014 |
| 20140245250 | SETTING SWITCH SIZE AND TRANSITION PATTERN IN A RESONANT CLOCK DISTRIBUTION SYSTEM - Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit. | 08-28-2014 |
| 20140282347 | SYSTEM AND METHOD FOR STRENGTHENING OF A CIRCUIT ELEMENT TO REDUCE AN INTEGRATED CIRCUIT'S POWER CONSUMPTION - A system and method enable strengthening of flip-Flops (FFs) in an integrated circuit (IC) for the purpose of reducing power consumption. This is achieved by using stability condition (STC) and observability don't-care (ODC) techniques. Strengthening enable is defined as ensuring that a FF later in the fan-out is enabled only when a FF earlier in the fan-out is driving a signal to that later FF. In an embodiment the fan-in of a FF is traversed and the STC or ODC is determined for the FF. Dependent on the determination a STC controller or an ODC controller is added to control the FF's enable signal. In an embodiment the power savings is checked and a controller is added only if there is a reduction in overall power consumption resulting from the addition of the controller. | 09-18-2014 |
| 20150040093 | ROBUST NUMERICAL OPTIMIZATION FOR OPTIMIZING DELAY, AREA, AND LEAKAGE POWER - Systems and techniques are described for performing numerical delay, area, and leakage power optimization on a circuit design. During operation, an embodiment can iteratively perform at least the following set of operations in a loop, wherein in each iteration a current threshold voltage value is progressively decreased: (a) perform numerical delay optimization on the circuit design using a numerical delay model that is generated using gates in a technology library whose threshold voltages are equal to the current threshold voltage; (b) perform a total negative slack based buffering optimization on the circuit design; and (c) perform a worst negative slack touchup optimization on the circuit design that uses gates whose threshold voltages are greater than or equal to the current threshold voltage. Next, the embodiment can perform combined area and leakage power optimization on the circuit design. The embodiment can then perform multiple iterations of worst negative slack touchup optimization. | 02-05-2015 |
| 20150113497 | LOW-LOSS TUNABLE RADIO FREQUENCY FILTER - A method of constructing an RF filter comprises designing an RF filter that includes a plurality of resonant elements disposed, a plurality of non-resonant elements coupling the resonant elements together to form a stop band having a plurality of transmission zeroes corresponding to respective frequencies of the resonant elements, and a sub-band between the transmission zeroes. The non-resonant elements comprise a variable non-resonant element for selectively introducing a reflection zero within the stop band to create a pass band in the sub-band. The method further comprises changing the order in which the resonant elements are disposed along the signal transmission path to create a plurality of filter solutions, computing a performance parameter for each of the filter solutions, comparing the performance parameters to each other, selecting one of the filter solutions based on the comparison of the computed performance parameters, and constructing the RF filter using the selected filter solution. | 04-23-2015 |
| 20150121329 | METHOD AND SYSTEM FOR DESIGNING FIN-FET SEMICONDUCTOR DEVICE - A method includes providing a first layout of a semiconductor device comprising a plurality of cells representing circuit elements, and providing a cell library comprising a plurality of cells in a processor. The circuit elements comprise a plurality of fin field effect transistors (Fin-FETs). Each of the plurality of cells in the cell library is displayed with a respectively different marker indicating a respective fin height. The method further includes generating a second layout for the semiconductor device to be fabricated, by placing or replacing at least one cell from the cell library in a respective location in the first layout. The at least one cell from the cell library comprises a Fin-FET with a respective fin height different from an adjacent Fin-FET in the second layout. | 04-30-2015 |
| 20150356222 | SYSTEM AND METHOD FOR REDUCING POWER OF A CIRCUIT USING CRITICAL SIGNAL ANALYSIS - A system and methods provide for an analysis of at least a portion of an integrated circuit (IC) that comprises a plurality of modules, for the purpose of identifying signals that can be indicative of the activity of the modules. By analyzing the activity of these signal immediately before and immediately after each module going from non-idle to idle and from idle to non-idle respectively, it is possible to determine which signals provide an indication that the module should be shut down. If the module can be shut down in idle state, then these input signals may be used as control signals for this purpose. By reporting to a designer the role of such signals a simple design change for detecting the activity and controlling the module, can save on power consumption, in ways not previously detected by the designer. | 12-10-2015 |
| 20150370943 | YIELD OPTIMIZATION OF PROCESSOR WITH GRAPHENE-BASED TRANSISTORS - Techniques described herein generally include methods and systems related to the selection of a combination of graphene and non-graphene transistors in an IC design. To reduce the increase in leakage energy caused by graphene transistors, selected non-graphene transistors may be replaced with graphene transistors in the IC design while other non-graphene transistors may be retained in the IC design. To limit the number of graphene transistors in the IC design, graphene transistors may replace non-graphene transistors primarily at locations in the IC design where significant delay benefit can be realized. | 12-24-2015 |
| 20160063149 | DESIGN TOOL APPARATUS, METHOD AND COMPUTER PROGRAM FOR DESIGNING AN INTEGRATED CIRCUIT - An integrated circuit design tool apparatus includes a processing resource configured to support a circuit simulator, a circuit sensitivity optimiser and a circuit sensitivity calculator. The circuit sensitivity optimiser is adapted to communicate to the circuit simulator a first dynamic list of selected devices of the circuit; and a second dynamic list of selected process parameters associated with the selected devices of the first dynamic list. The circuit simulator is configured to communicate to the circuit sensitivity calculator, a performance metrics of the circuit in response thereto. The circuit sensitivity calculator is configured to determine one sensitivity coefficient for each device of the first dynamic list in response thereto. The circuit sensitivity calculator is further configured to determine and communicate to the circuit sensitivity optimiser a variance of the performance metrics and also adapted to gradually determine whether or not to further communicate with the circuit simulator. | 03-03-2016 |
| 20160070845 | CRITICAL REGION IDENTIFICATION - A method and system to identify a region of a design block of an integrated circuit for redesign are described. The method includes dividing the design block into grids, each of the grids including a corresponding number of logic elements. The method also includes filtering each of the grids based on a specified criteria, the filtering including determining a number (B) of the corresponding logic elements among a total number (A) of the logic elements in each grid that meet the specified criteria. The region is a set of two or more of the grids based on a result of the filtering. | 03-10-2016 |
| 20160070849 | CRITICAL REGION IDENTIFICATION - A method and system to identify a region of a design block of an integrated circuit for redesign are described. The method includes dividing the design block into grids, each of the grids including a corresponding number of logic elements. The method also includes filtering each of the grids based on a specified criteria, the filtering including determining a number (B) of the corresponding logic elements among a total number (A) of the logic elements in each grid that meet the specified criteria. The region is a set of two or more of the grids based on a result of the filtering. | 03-10-2016 |
| 20160378898 | REDUCING THE LOAD ON THE BITLINES OF A ROM BITCELL ARRAY - Systems, apparatuses, and methods for reducing the load on the bitlines of a ROM bitcell array are described. The connections between nets of a ROM bitcell array may be assigned based on their programmed values using a traditional approach. Then, a plurality of optimizations may be performed on the assignment of nets to reduce the load on the bitlines of the array. A first optimization may swap the connections between ground and bitline for the nets of a given column responsive to detecting that the number of connections to the corresponding bitline is greater than the number of connections to ground for the given column. A second optimization may remove the connection of a net to a bitline if three consecutive nets of a given column are connected to the bitline. | 12-29-2016 |
