| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 716131000 | With partitioning | 17 |
| 20110055791 | METHOD AND APPARATUS FOR PERFORMING ROUTING OPTIMIZATION DURING CIRCUIT DESIGN - One embodiment of the present invention provides a system that concurrently optimizes multiple routing objectives during routing of an integrated circuit (IC) chip design. During operation, the system starts by receiving a routing solution for the IC chip design and a set of routing objectives. The system then partitions the IC chip design into a set of partitions. Next, for each partition in the set of partitions, the system optimizes the routing solution by, iteratively: (1) analyzing the routing solution to determine weights for the set of routing objectives; (2) constructing a cost function based on the weights for the set of routing objectives; and (3) modifying the routing solution within the partition to attempt to optimize the cost function. | 03-03-2011 |
| 20110055792 | Method and Apparatus for Circuit Partitioning and Trace Assignment in Circuit Design - Methods and apparatuses for incremental circuit partitioning and incremental trace assignment. In one embodiment of the present invention, a cost function based on both the partitioning solution and the trace assignment solution is used for the partitioning of a circuit; in reducing the cost function, blocks of circuits are moved among partitions and the trace assignment are updated accordingly to evaluate the cost function. In one embodiment, the traces and nets are grouped according to the partitions they connect for trace assignment. In one embodiment, a flow diagram is constructed for assigning nets to traces; and, maximum flow algorithms are used. In one embodiment, a flow diagram includes feedthrough solutions, in which flow conservation is not preserved at certain nodes. In one embodiment, integer linear programming techniques are used for assigning nets to traces. In one embodiment, a distribution of nets, which defines the numbers of blocks that each net has in each partition, is computed and maintained for efficient determination of the number of nets in net groups. | 03-03-2011 |
| 20110225561 | COMPUTER PRODUCT, APPARATUS, AND METHOD FOR SUPPORTING DESIGN - A non-transitory computer-readable recording medium storing a design supporting program causes a computer to perform: acquiring non-complying line lengths of a plurality of wiring paths; drawing for each of the wiring paths a wiring pattern connecting a transmission origin and a transmission destination based on a line length and a wiring route of the wiring path; and controlling the drawing to draw a line for each of the wiring paths, the line being divided into a first line amounting to a non-complying line length acquired at the acquiring and a second line being a wiring pass less the non-complying line length. | 09-15-2011 |
| 20120137264 | MULTIPLE LEVEL SPINE ROUTING - Multiple level spine routing is disclosed. In some embodiments, in response to receiving a specification of a net comprising a set of pins, a first wire for routing the net is generated, the set of pins comprising the net is partitioned into one or more groups based at least in part on a cost function, a second wire that connects to the first wire is generated for each group of the net, and a third wire that connects each pin to the second wire of its group is generated for each pin of each group of the net. | 05-31-2012 |
| 20120137265 | MULTIPLE LEVEL SPINE ROUTING - Multiple level spine routing is disclosed. In some embodiments, in response to receiving a specification of a plurality of nets and a specification of a set of routing tracks available for main spines, a main spine routing track is assigned to each of the plurality of nets based at least in part on a cost function and main spine wires are generated on the assigned main spine routing tracks for each of the plurality of nets. | 05-31-2012 |
| 20120151431 | GENERATION OF INDEPENDENT LOGICAL AND PHYSICAL HIERARCHY - A logically hierarchical netlist may be split along physical partition boundaries while retaining information on the logical hierarchy. Nets can be driven to higher levels of hierarchy in order to maintain connectivity and enable the original logical function. A mapping of nets can be created. During the design process merging of physical partitions may result in a new logically hierarchical netlist which retains the hierarchy of the original logically hierarchical netlist. The lowest common hierarchical ancestor (LCA) is identified and then the appropriate cells and nets are included during the merging process. | 06-14-2012 |
| 20130152035 | SYSTEM AND PROCESS FOR AUTOMATIC CLOCK ROUTING IN AN APPLICATION SPECIFIC INTEGRATED CIRCUIT - Embodiments of the claimed subject matter are directed to methods and a system that use a standardized grid of clock buffers to automatically route clocks according to a uniform clock grid throughout an ASIC of a non-uniform arrangement of non-uniformly sized logic partitions. According to one embodiment, clock sources and sinks are mapped to grid point locations and a novel grid routing process is performed to link them together. A clock routing macro is assigned to a corresponding partition and associated with the corresponding partition or logic unit according to a partition hierarchy. The underlying routing structure and resources of a clock routing macro are automatically renamed to correspond to the local partition in a script or schedule of programmed instructions, or a routing map. The position of blockages within a partition may also be detected and alternate routes for traversing the blockage may be preemptively determined as well. | 06-13-2013 |
| 20130167102 | ADAPTIVE PATTERNING FOR PANELIZED PACKAGING - An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units. | 06-27-2013 |
| 20130318491 | Method and Apparatus for Performing Parallel Routing Using A Multi-Threaded Routing Procedure - A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box. | 11-28-2013 |
| 20140026110 | GENERATING AND SELECTING BIT-STACK CANDIDATES FROM A GRAPH USING DYNAMIC PROGRAMMING - Bit stacks of an integrated circuit design are identified in a netlist by analyzing cell clusters. Candidate bit stacks are generated for each cluster using cone tracing, and wirelength costs are calculated for the candidate bit stacks based on the cells' locations from a previous (e.g., global) placement. The bit stack partition having a minimum total wirelength cost is selected for the final bit stacks. The invention can find K bit stacks in a cell cluster having N input cells and M output cells, where K, N and M are all different. The method is advantageously made timing aware by weighting connections between cells using weights based on timing information. Once the final bit stacks have been identified, the information can be included in the netlist and passed to a datapath placer for optimized placement. | 01-23-2014 |
| 20140033157 | Multiple Level Spine Routing - A computer implemented method for routing a net includes generating, using one or more computer systems, a first wire associated with the net in accordance with data associated with the net including a multitude of pins and partitioning, using the one or more computer systems, the multitude of pins into at least a first group of pins in accordance with a first cost function. The method further includes connecting, using the one or more computer systems, a second wire associated with the first group of pins to the first wire, and connecting, using the one or more computer systems, a third wire from a pin of the first group of pins to the second wire. | 01-30-2014 |
| 20140033158 | Multiple Level Spine Routing - A computer implemented method for routing a net includes selecting, using one or more computer systems, a first spine routing track from a first multitude of routing tracks in accordance with a first cost function, and further in accordance with data associated with the net and the first multitude of routing tracks. The method further includes generating, using one or more computer systems, a first spine wire on the selected first spine routing track. | 01-30-2014 |
| 20140215428 | DOUBLE PATTERNING TECHNOLOGY (DPT) LAYOUT ROUTING - One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues. | 07-31-2014 |
| 20140223403 | Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure - A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box. | 08-07-2014 |
| 20150100938 | SPINE ROUTING WITH MULTIPLE MAIN SPINES - A computer implemented method of routing a net of an electronic circuit is disclosed. The net connects a plurality of pins of the electronic circuit. The method includes selecting, using one or more computer systems, first and second main spine routing tracks for respective first and second groups of pins of the net. The method also includes generating, using one or more computer systems, a first main spine wire on the selected first main spine routing track and a second main spine wire on the selected second main spine routing track. A router configured to perform the method is also disclosed. | 04-09-2015 |
| 20150317426 | DATA PATH SYSTEM ON CHIP DESIGN METHODOLOGY - Integrated circuit (IC) technology design may include binning data paths of an IC device of a current technology node to bins based on a performance of each of the data paths. Each of the plurality of bins is mapped to a representative circuit unit data path configured according to a predetermined set of electrical and/or physical parameters. The representative circuit unit data paths are calibrated according to updated electrical and/or physical parameters to increase the performance of the representative circuit unit data paths to improve the performance of the IC device in an advanced technology node. | 11-05-2015 |
| 20160188777 | INTEGRATED CIRCUIT LAYOUT WIRING FOR MULTI-CORE CHIPS - An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections. | 06-30-2016 |
