Class / Patent application number | Description | Number of patent applications / Date published |
716130000 | Detailed | 36 |
20100325600 | ROUTING NETS OVER CIRCUIT BLOCKS IN A HIERARCHICAL CIRCUIT DESIGN - Some embodiments of the present invention provide a system that routes nets over circuit blocks in a hierarchical circuit design. During operation, the system can receive a set of circuit blocks. At least some terminals of the circuit blocks may be desired to be electrically linked together using a net which is expected to be routed over one or more circuit blocks. The system may divide an area associated with a block (e.g., an area in a metal layer which is situated above the block) into a set of tiles. Next, the system may assign costs to at least some of the tiles in the set of tiles. The system can then use the costs during routing. Note that using the costs of the tiles during routing makes it more likely that buffers can be used wherever required to meet slew and timing requirements. | 12-23-2010 |
20110041111 | METHOD AND APPARATUS FOR GENERATING A MEMORY-EFFICIENT REPRESENTATION OF ROUTING DATA - Some embodiments provide a system for generating a memory-efficient representation of a sequence of electrically connected routing shapes. The memory-efficient representation represents the sequence of electrically connected routing shapes using a sequence of points, such that two consecutive points represent a routing shape. At least some of the points can be represented using a compact representation, thereby reducing the memory required for storing the sequence of points. A full representation specifies a point's location using the point's two-dimensional coordinates, and a compact representation specifies a point's location using one of the point's two-dimensional coordinates and an orientation indicator which indicates the routing shape's orientation. The missing coordinate in a compact representation can be determined from the preceding points. The system can represent a via that joins two routing shapes by assigning different metal layers to the points associated with the two routing shapes. | 02-17-2011 |
20110041112 | METHOD AND APPARATUS FOR GENERATING A CENTERLINE CONNECTIVITY REPRESENTATION - Some embodiments provide a system for generating a centerline connectivity representation for a set of routing shapes. During operation, the system can represent the set of routing shapes using a set of centerlines with endcap extensions. Note that an intersection between two centerlines represents an electrical connection between the two routing shapes associated with the two centerlines. Next, the system can detect two routing shapes which overlap, but whose centerlines do not intersect. The system can then create a virtual shape whose centerline intersects with the centerlines of the two routing shapes. In some embodiments, the system can modify a dimension of at least one of the two routing shapes. Next, the system can create a new routing shape which overlaps with the two routing shapes, and create virtual shapes which connect the centerline of the new shape with the centerlines of the two routing shapes. | 02-17-2011 |
20110041113 | DESIGN SUPPORT PROGRAM, DESIGN SUPPORT SYSTEM, AND DESIGN SUPPORT METHOD - A design support program executed by a computer includes operations of: locating at least one via hole for coupling target wiring in a first layer in circuit information to wiring in a second layer being different form the first layer; calculating an area of the target wiring based on a length and a width of the target wiring; setting a division condition based on the area and a number of the via hole; dividing the target wiring into divided wirings at a position other than a position where the via hole is provided based on the division condition; generating connection information indicating a connection relationship between the divided wirings and limitation information for coupling the divided wirings via a wiring in a third layer being different from the first layer; and outputting the connection information, the limitation information and circuit information obtained after dividing. | 02-17-2011 |
20110055788 | METHOD AND APPARATUS FOR ROUTING USING A DYNAMIC GRID - One embodiment of the present invention provides a system that routes connections in an integrated circuit (IC) chip design. The system includes a representation mechanism which is configured to represent routing resources in the IC chip design as a 3-dimensional (3D) grid. This 3D grid further includes: static grid lines which do not change while the system routes the connections; and dynamic grid lines which are created for routing a connection that includes pins which are not located on a static grid line. Note that the dynamic grid lines can be removed after the connection is routed. The system also includes a search engine which is configured to search for a path in the 3D grid between a first set of vertices and a second set of vertices. | 03-03-2011 |
20110055789 | MULTI-THREADED TRACK ASSIGNMENT - Some embodiments provide techniques and systems for routing nets in a circuit design in parallel. During operation, the system can receive a first set of partitions for a circuit design, wherein each partition in the first set of partitions extends across the circuit design along a first direction. Next, the system can perform, in parallel, track assignment in the first direction on non-overlapping partitions in the first set of partitions. The system can then receive a second set of partitions for the circuit design, wherein each partition in the second set of partitions extends across the circuit design along a second direction which is different from the first direction. Next, the system can perform, in parallel, track assignment in the second direction on non-overlapping partitions in the second set of partitions. In some embodiments, each track assignment process being performed in parallel performs track assignment on a different net. | 03-03-2011 |
20110055790 | MULTI-THREADED DETAILED ROUTING - Some embodiments provide techniques and systems for routing nets in a circuit design in parallel. During operation, the system can receive a set of partitions for a circuit design, wherein each partition has zero or more overlapping partitions along four directions, e.g., up, down, left, and right. Next, the system can perform, in parallel, detailed routing on non-overlapping partitions in the set of partitions, wherein detailed routing is performed on a partition after detailed routing is completed on adjacent or overlapping partitions that located along two perpendicular directions. In some embodiments, each detailed routing thread that is executing in parallel performs detailed routing on a different net. | 03-03-2011 |
20110154283 | Shaping Ports in Integrated Circuit Design - A mechanism is provided for performing a detailed routing of a net joining ports in an integrated circuit. Extended port regions are created for the ports of the net of the integrated circuit, the extended port regions being shaped in such a way as to guarantee routing access to the ports. A wire corresponding to the net is then placed and the extended port regions of the ports are trimmed, thus identifying essential port regions required for connecting the wire to the ports and dispensable port regions not required for connecting the wire to the ports. The wiring resources are then updated by releasing the dispensable port regions so that the dispensable port regions no longer constitute parts of the ports. | 06-23-2011 |
20110185329 | GENERATING AND USING ROUTE FIX GUIDANCE - Some embodiments of the present invention provide systems for generating and using a route fix guidance for fixing design rule violations. A route fix guidance includes information that enables a router to locally modify a routing solution to fix one or more design rule violations. A route fix guidance can include a set of two or more metal avoidance areas, wherein avoiding any one of the set of two or more metal avoidance areas during routing fixes the design rule violation. Additionally, a route fix guidance can specify a set of rectangles to remove from a routing solution, and a set of rectangles to insert into or add to a routing solution. Further, the route fix guidance can include information for moving one or more vias to new locations in the routing solution. The route fix guidance can specify a sequence in which the local modifications are to be made. | 07-28-2011 |
20110185330 | METAL WIRING STRUCTURE FOR INTEGRATION WITH THROUGH SUBSTRATE VIAS - An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams. | 07-28-2011 |
20110214100 | INTEGRATED CIRCUIT DEVICES AND METHODS AND APPARATUSES FOR DESIGNING INTEGRATED CIRCUIT DEVICES - Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment of the present invention, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed. | 09-01-2011 |
20110231810 | SUPPORT COMPUTER PRODUCT, APPARATUS, AND METHOD - A computer-readable, non-transitory medium stores therein a design support program that causes a computer executing tentative wiring processing between a first terminal group and a second terminal group in a tentative wiring area to execute a process. The process includes detecting unwired nets occurring in the tentative wiring area consequent to the tentative wiring processing; updating the tentative wiring area by expanding the tentative wiring area according to the number of unwired nets, if any unwired nets are detected at the detecting; controlling to execute the tentative wiring processing and the subsequent detecting with respect to the tentative wiring area updated at the updating; and determining the tentative wiring area to be a wiring area if no unwired nets are detected at the detecting. | 09-22-2011 |
20110239181 | WIRING DESIGN METHOD AND COMPUTER-READABLE MEDIUM - In one embodiment, a wiring design method is disclosed. In the wiring design method, schematic wiring is performed on a substrate, and the substrate includes a first wiring layer with first-direction wiring lines and a second wiring layer with second-direction wiring lines; the substrate is divided into a plurality of tiles; the first wiring layer is divided into partial wiring regions with first-direction wiring lines, the second wiring layer is divided into partial wiring regions with second-direction wiring lines, and each partial wiring region corresponds to the tiles; and when the first-direction wiring lines in the tile overflow, the partial wiring region with second-direction wiring lines corresponding to the tile is changed to the partial wiring region with first-direction wiring lines. | 09-29-2011 |
20120072881 | DESIGN APPARATUS, METHOD FOR HAVING COMPUTER DESIGN SEMICONDUCTOR INTEGRATED CIRCUIT, AND NON-TRANSITORY COMPUTER-READABLE MEDIUM - According to one embodiment, a design apparatus includes an extractor, a regression equation generator and an output module. The extractor extracts a critical part from a net list of a semiconductor integrated circuit. The critical part has a delay value greater than a delay threshold. The regression equation generator generates a regression equation to reproduce the delay value of the critical part using a regression algorithm. The output module outputs the regression equation. | 03-22-2012 |
20120110539 | Automatically Routing Nets with Variable Spacing - A technique will automatically route interconnect of an integrated circuit and adjust spacing between tracks or interconnect in order to improve performance or reduce electromigration effects. By increasing spacing between certain tracks or moving tracks, performance can improve because a track will be more noise immunity from nearby tracks on the same layer or on different layers. The automatic router will adjust spacing between tracks depending on one or more factors. These factors may include current associated with a track, width of a track, capacitance, inductance, and electromigration. In a specific implementation, the technique uses a shape-based approach where a grid is not used. The technique may further vary the width of the tracks. | 05-03-2012 |
20120167032 | COMPUTER PROGRAM AND METHOD FOR GENERATING WIRE ROUTING PATTERN - A computer program generates a wire routing pattern that connects one driver with a plurality of receivers. The overlapping length of each vector pair, which consists of any two vectors headed from the driver to the receivers, is calculated. One vector pair that has the greatest overlapping length is selected. For the selected vector pair, three kinds of common nodes are created, each of which is used to make a common path part of the way to the receivers, to generate three kinds of renewed vector patterns. The operations are repeated and plural candidate routing patters are acquired. One candidate routing pattern having the smallest total wiring length is selected as the optimum routing pattern. If there exist plural patterns that have the same smallest total wiring length, one pattern can be selected that has the smallest one of the greatest D-R path lengths. | 06-28-2012 |
20120180018 | Increasing Dielectric Strength by Optimizing Dummy Metal Distribution - A method includes providing a wafer representation including a metal layer and a plurality of bump pads over the metal layer, wherein the metal layer includes directly-under-bump-pad regions. A solid metal pattern is inserted into the metal layer, wherein the solid metal pattern includes first parts in the directly-under-bump-pad regions and second parts outside the directly-under-bump-pad regions. Portions of the second parts of the solid metal pattern are removed, wherein substantially no portions of the first parts of the solid metal pattern are removed. The remaining portions of the solid metal pattern not removed during the step of removing form dummy metal patterns. The dummy metal patterns and the plurality of bump pads are implemented in a semiconductor wafer. | 07-12-2012 |
20120192139 | INTEGRATED STRUCTURES OF HIGH PERFORMANCE ACTIVE DEVICES AND PASSIVE DEVICES - Integrated structures having high performance CMOS active devices mounted on passive devices are provided. The structure includes an integrated passive device chip having a plurality of through wafer vias, mounted to a ground plane. The structure further includes at least one CMOS device mounted on the integrated passive device chip using flip chip technology and being grounded to the ground plane through the through wafer vias of the integrated passive device chip. | 07-26-2012 |
20120221994 | Wire Routing Using Virtual Landing Pads - Systems and methods for wire routing using virtual landing pads (VLPs) are described. In an embodiment, a method includes routing a wiring path between an output of a first circuit component and a VLP that represents an input of a second circuit component. For example, the VLP may have an area larger than the area of a physical pin of the second circuit component. The method may also include identifying a connection point on the VLP that is separated from an actual terminal of the second circuit, and completing the path between the connection point and the actual terminal. In some embodiments, the output of the first circuit component may also be represented by its own VLP. As such, systems and methods described herein may allow a circuit designer to perform routing procedures in a complex, highly integrated circuit, while reducing the circuit's overall capacitance and associated power consumption. | 08-30-2012 |
20120240094 | WIRING DESIGN SUPPORT DEVICE AND WIRING DESIGN SUPPORTING METHOD - A device includes a definition unit which defines a directional graph having a grid point as a node and a line connecting adjacent grid points as a branch, a generation unit which sets a branch connecting a grid pointing a wiring prohibited area in the branches of the directional graph to the capacity of “0”, and which sets another branch to the capacity of “1”, and which connects the starting point or the end point to each grid point of the wiring terminal indicated by wiring information, thereby generating a flow network, a search unit which searches the flow network for a path of a flow having the maximum amount of flow from the starting point to the end point, and a determination unit which determines a wiring path connecting the grid point indicated by the wiring information according to the search result of the path. | 09-20-2012 |
20120272203 | METHOD FOR COMPUTING IO REDISTRIBUTION ROUTING - A method of determining signal routing in an integrated circuit includes providing first coordinates of an input/output cell and second coordinates of an input/output pad to a parametric routing module. The parametric routing module receives at least one wire path parameter. The parametric routing module uses the at least one connection path parameter to determine a physical dimension of a wire path between the first coordinates and the second coordinates. | 10-25-2012 |
20130086546 | WIRING SUPPORT METHOD AND APPARATUS - A disclosed method includes: accepting designation of a condition of grouping plural signal lines to be wired from a user; and switching and carrying out a grouping of the plural signal lines into plural groups based on the designated condition and a disposition pattern of start terminals and end terminals of the plural signal lines. The condition may be designated from a first requirement, a second requirement and a third requirement that includes the first requirement and the second requirement and in which a priority is set to the first requirement or the second requirement. | 04-04-2013 |
20130159957 | METHOD, STRUCTURE, AND DESIGN STRUCTURE FOR A THROUGH-SILICON-VIA WILKINSON POWER DIVIDER - A method, structure, and design structure for a through-silicon-via Wilkinson power divider. A method includes: forming an input on a first side of a substrate; forming a first leg comprising a first through-silicon-via formed in the substrate, wherein the first leg electrically connects the input and a first output; forming a second leg comprising a second through-silicon-via formed in the substrate, wherein the second leg electrically connects the input and a second output, and forming a resistor electrically connected between the first output and the second output. | 06-20-2013 |
20130232461 | DESIGN SUPPORTING DEVICE, DESIGN SUPPORT METHOD AND COMPUTER-READABLE RECORDING MEDIUM - A design supporting device includes a calculator that calculates an estimated value of a width, shifted by etching, of a wiring arranged in each of partial regions formed by dividing a layout region of a circuit to be designed on basis of a density of the wiring of the partial region, a length of a circumference of the wiring and a distance between the partial region and another partial region affecting the partial region, and uses the calculated estimated value to recalculate the density of the wiring of the partial regions, and a changer that changes the density of the wiring on basis of relationships between a recalculated density of the wiring and a preset threshold for the density. | 09-05-2013 |
20140068543 | METHOD TO ENHANCE DOUBLE PATTERNING ROUTING EFFICIENCY - A method for enabling jogging functionality in circuit designs utilizing DPT without the need for difficult to implement tools such as stitch-aware routing tools is disclosed. Embodiments include: displaying a user interface for generating an IC having a plurality of masks for a single layer; causing, at least in part, a presentation in the user interface of a cell placement of the IC that includes a filler cell; and designating a portion of the filler cell as a routing zone, the routing zone being configured such that routes placed in the routing zone are decomposable with other routes placed outside the filler cell. | 03-06-2014 |
20140189632 | MULTIPLE-INSTANTIATED-MODULE (MIM) AWARE PIN ASSIGNMENT - Systems and techniques for multiple-instantiated-module (MIM)-aware pin assignment are described. An aggregate cost function can be determined, wherein the aggregate cost function is aggregated across all instances of an MIM for placing a pin at a particular location on the boundary of the MIM. The aggregate cost function can then be used by a pin assignment engine to place the pin in the MIM. A pin assignment engine can place one pin at a time, or place multiple pins at a time by trying to optimize the aggregate cost over multiple pins. Some embodiments can propagate pin-alignment constraints through one or more instances of one or more MIMs in the circuit design layout, and then perform pin assignment while observing the pin-alignment constraints. In some embodiments, pin assignment can be performed on MIMs in decreasing order of the number of pin-alignment constraints that are imposed on the MIMs. | 07-03-2014 |
20140195998 | Automatic Generation of Wire Tag Lists for a Metal Stack - Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design. | 07-10-2014 |
20140201696 | SUPPORT APPARATUS AND DESIGN SUPPORT METHOD - A receiving unit receives specification of two parts to be connected by wirings and the number of wirings connecting the two parts. A generating unit generates a schematic route connecting the two parts on a substrate with a width in accordance with the number of wirings received by the receiving unit. A derivation unit derives the number of arrangeable wirings by checking interference whether the schematic route generated by the generating unit is capable of being arranged on the substrate. | 07-17-2014 |
20140325467 | MULTIPLE-INSTANTIATED-MODULE (MIM) AWARE PIN ASSIGNMENT - Systems and techniques for multiple-instantiated-module (MIM)-aware pin assignment are described. An aggregate cost function can be determined, wherein the aggregate cost function is aggregated across all instances of an MIM for placing a pin at a particular location on the boundary of the MIM. The aggregate cost function can then be used by a pin assignment engine to place the pin in the MIM. A pin assignment engine can place one pin at a time, or place multiple pins at a time by trying to optimize the aggregate cost over multiple pins. Some embodiments can propagate pin-alignment constraints through one or more instances of one or more MIMs in the circuit design layout, and then perform pin assignment while observing the pin-alignment constraints. In some embodiments, pin assignment can be performed on MIMs in decreasing order of the number of pin-alignment constraints that are imposed on the MIMs. | 10-30-2014 |
20150067633 | COLOR-INSENSITIVE RULES FOR ROUTING STRUCTURES - Methodologies and an apparatus enabling a generation of color undeterminable polygons in IC designs are disclosed. Embodiments include: determining a plurality of first routes extending horizontally in an IC design, each of the plurality of first routes being placed on one of a plurality of equally spaced vertical positions of the IC design; determining whether a second route overlaps one of the vertical positions of the plurality of equally spaced vertical positions; and selecting a design rule for the second route based on the determination of whether the second route overlaps. | 03-05-2015 |
20150100937 | IMPLEMENTING ENHANCED NET ROUTING CONGESTION RESOLUTION OF NON-RECTANGULAR OR RECTANGULAR HIERARCHICAL MACROS - A method, system and computer program product are provided for implementing enhanced net routing for congestion resolution of non-rectangular or rectangular hierarchical macro designs of an integrated circuit chip. Congested macro nets near a macro boundary are identified. Wiring channels are reserved outside the macro boundary, allowing congested macro nets to be routed outside the physical boundary of the macro while still being logically contained within the macro. | 04-09-2015 |
20150106778 | SYSTEM FOR DESIGNING NETWORK ON CHIP INTERCONNECT ARRANGEMENTS - A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone. | 04-16-2015 |
20150331990 | SEMICONDUCTOR ARRANGEMENT FORMATION - A method of forming a semiconductor arrangement is provided. The semiconductor arrangement includes an interconnection arrangement comprising a first connection between a driver and a receiver. At least one buffer is disposed along the first connection to reduce delay associated with the interconnection arrangement. However, buffers increase power consumption, and thus a determination is made as to whether a buffer is unnecessary. A buffer is determined to be unnecessary where removal of the buffer does not violate a timing constraint regarding an amount of time a signal takes to go from the driver to the receiver. If a buffer is determined to be unnecessary, the buffer is removed to reduce power consumption. | 11-19-2015 |
20150347661 | CONGESTION AWARE LAYER PROMOTION - Embodiments relate to managing layer promotion of interconnects in the routing phase of integrated circuit design. An aspect includes reducing the set of candidate interconnects for layer promotion based on resource availability. A method of managing includes identifying a set of candidate interconnects for the layer promotion, scoring and sorting the set of candidate interconnects according to a respective score, thereby establishing a respective rank, and assessing routing demand and resource availability based on promoting the set of candidate interconnects. The method also includes managing the set of candidate interconnects based on the respective rank and the assessing, the assessing and the managing being done iteratively and the managing including, in at least one iteration, generating a second set of candidate interconnects based on reducing the set of candidate interconnects. | 12-03-2015 |
20150370953 | VIA PLACEMENT WITHIN AN INTEGRATED CIRCUIT - An integrated circuit layout | 12-24-2015 |
20160070842 | INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS - A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC. | 03-10-2016 |