| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 716127000 | Power (voltage islands) | 19 |
| 20110113398 | Method and System for Providing Secondary Power Pins in Integrated Circuit Design - An integrated circuit (IC) design with multiple metal layers containing cells requiring secondary power supply. After placing the cells and stripes of a primary power/ground grid in metal layers of the IC design, specific cells are provided with secondary power stripes in a first metal layer. The secondary power stripes are designed in such a way that each secondary power/ground stripe exhibits a full overlap with a stripe of a corresponding primary power/ground grid in a different metal layer. Subsequently, signals from the IC design are routed, and power vias between the primary power/ground grid stripes and the secondary power/ground stripes are generated. | 05-12-2011 |
| 20110239180 | METHOD AND APPARATUS FOR LAYING OUT POWER WIRING OF SEMICONDUCTOR - An aspect of the present invention is a method for laying out a power wiring of a semiconductor device. The method includes: modeling the power wiring as an analysis model including a plurality of nodes and a plurality of element resistors provided between the plurality of nodes neighboring each other; obtaining voltage values of the plurality of nodes by a circuit simulation; searching a path of a current flowing into a node of the plurality of nodes when an IR drop violation exists in the voltage values, the node having a maximum value of the IR drop violation; selecting a bottleneck element resistor from among the plurality of element resistors included in the path; and changing a resistance value of the bottleneck element resistor | 09-29-2011 |
| 20110246959 | METHOD, SYSTEM, AND DESIGN STRUCTURE FOR MAKING VOLTAGE ENVIRONMENT CONSISTENT FOR REUSED SUB MODULES IN CHIP DESIGN - The present invention discloses a method, system, and design structure for making voltage environment consistent for reused sub modules in chip design, wherein each reused sub module is connected to a power grid of the chip through power connection points on a power ring of the sub module, the method including: adjusting numbers and locations of power connection points of a plurality of reused sub modules, such that the numbers of the power connection points and locations of the corresponding power connection points are identical for the plurality of reused sub modules; adjusting power wires of the plurality of reused sub modules on the power grid which are connected the power connection points, such that voltages at the corresponding power connection points are consistent for the plurality of reused sub modules. The present invention may reduce timing variation of reused sub modules in chip design and finally achieve an objective of reducing design complexity and work load and shortening the design period. | 10-06-2011 |
| 20120084745 | Design Method for Non-Shrinkable IP Integration - A method of designing integrated circuits includes providing a design of an integrated circuit at a first scale, wherein the integrated circuit includes a shrinkable circuit including a first intellectual property (IP); and a non-shrinkable circuit including a second IP having a hierarchical structure. A marker layer is formed to cover the non-shrinkable circuit, wherein the shrinkable circuit is not covered by the marker layer. The electrical performance of the non-shrinkable circuit is simulated using a simulation tool, wherein the simulated non-shrinkable circuit is at a second scale smaller than the first scale. | 04-05-2012 |
| 20120198408 | SYSTEM AND METHOD FOR AUTOMATIC EXTRACTION OF POWER INTENT FROM CUSTOM ANALOG/CUSTOM DIGITAL/MIXED SIGNAL SCHEMATIC DESIGNS - A method of producing a hierarchical power information structure for a circuit design, the method comprising traversing a circuit design hierarchy from a top design level to a bottom design level to identify any intermediate design levels, associating identified power nets with ground nets to produce one or more power domains, producing one or more power domains using the identified power nets and ground nets, identifying an instance of one or more special cells that are associated with a power related property and creating constructs for the special cells in the hierarchical power information structure, generating power rules for the intermediate level design using the special cell constructs, mapping higher design level power domains to lower design level power domains within the intermediate design level, and storing the power domains and power rules as power intent within an information structure associated with a schematic for the intermediate level design. | 08-02-2012 |
| 20120204141 | Noise Coupling Reduction and Impedance Discontinuity Control in High-Speed Ceramic Modules - A method reduces coupling noise and controls impedance discontinuity in ceramic packages by: providing at least one reference mesh layer; providing a plurality of signal trace layers, with each signal layer having one or more signal lines and the reference mesh layer being adjacent to one or more of the signal layers; disposing a plurality of vias through the at least one reference mesh layer, with each via providing a voltage (Vdd) power connection or a ground (Gnd) connection; selectively placing via-connected coplanar-type shield (VCS) lines relative to the signal lines, with a first VCS line extended along a first side of a first signal line and a second VCS line extended along a second, opposing side of said first signal line. Each of the VCS lines interconnect with and extend past one or more vias located within a directional path along which the VCS lines extends. | 08-09-2012 |
| 20120216166 | LAYOUT METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT AND PROGRAM THEREFOR - A power domain is automatically generated. | 08-23-2012 |
| 20120290996 | Supplying Power to Integrated Circuits Using a Grid Matrix Formed of Through-Silicon Vias - An integrated circuit structure includes a chip including a substrate and a power distribution network. The power distribution network includes a plurality of power through-silicon vias (TSVs) penetrating the substrate, wherein the plurality of power TSVs forms a grid; and a plurality of metal lines in a bottom metallization layer (M | 11-15-2012 |
| 20130074029 | Method To Ensure Double Patterning Technology Compliance In Standard Cells - An integrated circuit with standard cells with top and bottom metal-1 and metal-2 power rails and with lateral standard cell borders that lie between an outermost vertical dummy poly lead from one standard cell and an adjacent standard cell. A DPT compatible standard cell design rule set. A method of forming an integrated circuit with standard cells constructed using a DPT compatible standard cell design rule set. A method of forming DPT compatible standard cells. | 03-21-2013 |
| 20130132922 | CAPACITOR ARRANGEMENT ASSISTING METHOD AND CAPACITOR ARRANGEMENT ASSISTING DEVICE - A capacitor arrangement assisting method wherein data entered by a user, such as the width w of a power supply wiring, the thickness h of a dielectric between the power supply wiring and a ground plane, the ESL | 05-23-2013 |
| 20130205273 | POWER SUPPLY WIRING DESIGN SUPPORT METHOD, POWER SUPPLY WIRING DESIGN SUPPORT APPARATUS, POWER SUPPLY WIRING DESIGN SUPPORT PROGRAM AND RECORDING MEDIUM - A power supply wiring design support method of an embodiment includes: receiving input of information about multiple elements formed on a semiconductor chip and circuit information about the semiconductor chip; calculating a voltage drop of power supply voltage in each of areas into which the semiconductor chip is virtually divided based on a grid indicated by XY coordinates; and calculating a voltage drop gradient from the voltage drop of the area and voltage drops of adjacent areas. | 08-08-2013 |
| 20140068542 | Systems and Methods for Designing and Making Integrated Circuits with Consideration of Wiring Demand Ratio - A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described. | 03-06-2014 |
| 20140089884 | DESIGN SUPPORT METHOD AND APPARATUS - A disclosed design support method includes: dividing an circuit element that is included in a circuit to be designed and is provided on a path that connects between memory circuits into plural circuit elements, based on information concerning circuit elements that can be divided into circuit elements; tracing the path from the memory circuits; and during the tracing, setting a new power supply voltage that is lowed by a predetermined voltage from a voltage, which was set immediately before, to a traced circuit element, which is provided on the path and satisfies a predetermined condition concerning a predetermined lower limit voltage of the traced circuit element. | 03-27-2014 |
| 20140149959 | METHOD FOR DESIGNING AN ARRAY OF ORGANIC PHOTODETECTOR OR PHOTOEMITTER ELEMENTS - A method for making a matrix device including a matrix of photodetecting or photoemitting elements, the method including designing operations for: a) identifying, from at least one topology of the matrix device, one or more spurious conducting closed circuits; b) selecting at least one photodetecting or photoemitting element of the matrix device belonging to at least one of the spurious conducting closed circuits identified, the at least one element selected being made inactive. | 05-29-2014 |
| 20140189629 | PATTERN-BASED POWER-AND-GROUND (PG) ROUTING AND VIA CREATION - Systems and techniques for pattern-based power-and-ground (PG) routing and via rule based via creation are described. A pattern for routing PG wires can be received. Next, an instantiation strategy may be received, wherein the instantiation strategy specifies an area of an integrated circuit (IC) design layout where PG wires based on the pattern are to be instantiated and specifies one or more net identifiers that are to be assigned to the instantiated PG wires. The PG wires can be instantiated in the IC design layout based on the pattern and the instantiation strategy. Additionally, a set of via rules can be received, wherein each via rule specifies a type of via that is to be instantiated at an intersection between two PG wires that are in two different metal layers. Next, one or more vias can be instantiated in the IC design layout based on the set of via rules. | 07-03-2014 |
| 20140310671 | Electrical Measurement Based Circuit Wiring Layout Modification Method and System - The capacitance or inductance of electrical circuits is adjusted by measuring inductance or capacitance values of passive components fabricated on a first substrate, storing individual associations between the passive components and the respective measured values of the passive components, and determining electrical connections for the passive components based on the stored individual associations between the passive components and the respective measured values of the passive components. A corresponding system includes a tester operable to measure inductance or capacitance values of the passive components fabricated on the first substrate, a storage system operable to store the individual associations between the passive components and the respective measured values of the passive components, and a processing circuit operable to determine the electrical connections for the passive components based on the stored individual associations between the passive components and the respective measured values of the passive components. | 10-16-2014 |
| 20150012902 | Automatic mapping method for a distribution network based on logical layout - The invention provides an automatic mapping method for a distribution network based on logical layout, comprising (1) pretreating a model of the distribution network model by analyzing it, and partitioning and striping the distribution network model to generate a plurality of partial models; (2) analyzing an automatic mapping algorithm to be utilized by comparing a distribution network graph obtained by the algorithm with the distribution network model, to find out a basis for purposefully improving the partial models or the whole distribution network model; (3) achieving automatic layout of the partial models or the whole distribution network model on the basis of analysis of the automatic mapping algorithm to be utilized by combining with one or more of the force-directed layout algorithm, hybrid layout algorithm, dynamic interactive layout algorithm and an improved grid routing algorithm in order to generate the distribution network graph; and (4) analyzing and treating the automatic layout to achieve the generation of the distribution network graph with a desired practical effect. In the method of the invention, the automatic mapping of a distribution network is achieved on the basis of the distribution network by combining multiple mapping algorithms, thus the layout of the automatically generated distribution network graph is beautiful, clear and reasonable. | 01-08-2015 |
| 20150379184 | LAYOUT METHOD FOR PRINTED CIRCUIT BOARD - A printed circuit board (PCB) is provided. The PCB has a specific routing module, having a first chip, a memory chip, and a plurality of traces designed for interconnection between the first chip and the memory chip according to a routing configuration between the first chip and the memory chip. The memory chip is a dynamic random access memory (DRAM) with a memory type, the specific routing module is obtained from a module group comprising a plurality of routing modules according to a plurality of PCB parameters, and module group is obtained from a database according to the memory type of the DRAM. | 12-31-2015 |
| 20160085900 | Activity-Driven Capacitance Reduction to Reduce Dynamic Power Consumption in an Integrated Circuit - In an embodiment, a methodology for designing an integrated circuit that attempts to improve power efficiency is provided. The methodology includes simulating the design under one or more power stimuli, where the power stimuli are known to cause high power consumption (e.g. in previous designs of the integrated circuit, the power stimuli may have caused power consumption). A set of nets within the integrated circuit may be identified that have the highest activity in the simulation (e.g. the highest amount of switching). The methodology may include providing data to the routing tool that is to route the nets in the integrated circuit. The data may indicate constraints for the set of nets, to help reduce dynamic power on these nets. Power efficiency of the integrated circuit may be improved if the routing tool is able to honor the constraints. | 03-24-2016 |
