Class / Patent application number | Description | Number of patent applications / Date published |
716116000 | Mapping circuit design to programmable logic devices (PLDs) | 23 |
20110320996 | DELAY LIBRARY GENERATION SYSTEM - A delay library generation apparatus ( | 12-29-2011 |
20120151429 | MULTISTAGE, HYBRID SYNTHESIS PROCESSING FACILITATING INTEGRATED CIRCUIT LAYOUT - Multistage synthesis of hardware function operation descriptions is provided, which facilitates placement of logic cells in an integrated circuit design layout, and includes: parsing hardware function operation descriptions of a circuit to identify multiple instantiations of a type of logic function; performing, without shape restriction, a first synthesis on each logic function type identified as having multiple instantiations and producing an irregular-shaped logic unit layout for that logic function type; establishing an irregular-shaped blocking mask corresponding to a respective irregular-shaped logic unit layout produced by the first synthesis; creating a partial circuit layout by placing each irregular-shaped blocking mask multiple times corresponding to the multiple instantiations of the respective logic function type; and performing, employing the partial circuit layout, a second synthesis on the balance of the hardware function operation descriptions of the circuit outside the multiple instantiations of the logic function type. | 06-14-2012 |
20120210288 | METHOD AND APPARATUS FOR INTERFACING MULTIPLE DIES WITH MAPPING FOR SOURCE IDENTIFIER ALLOCATION - A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to allocate to the received transaction a local source identity information as source identity information, the local source identity information comprising one of a set of reusable local source identity information. This ensures the order of transactions tagged with a same original source identity and target and allows transactions tagged with different source identifiers to be processed out of order. | 08-16-2012 |
20120304141 | Power Mesh for Multiple Frequency Operation of Semiconductor Products - A semiconductor platform for implementing multiple-frequency operations includes multiple physical resources comprising embedded functions and a configurable transistor fabric. The transistor fabric includes at least first and second portions, the first portion being programmable to instantiate a first function having higher frequency operations than the second portion. The platform further includes multiple logical resources corresponding to the physical resources of the semiconductor platform and a configurable power mesh to support multiple frequency operations configurable from the transistor fabric. The power mesh includes at least first and second configurable grids. The first configurable grid is operable at a different frequency than the second configurable grid. The power mesh is modifiable, as a function of a desired performance of a customer's requirements, in a vicinity of the first portion of the configurable transistor fabric to support the first function having higher frequency operations. | 11-29-2012 |
20130097569 | MODULAR ROUTING FABRIC USING SWITCHING NETWORKS - A routing fabric using multiple levels of switching networks along with associated routing matrices to allow for better interconnection or routing path among logic modules or routing modules compared with those in the conventional designs. The resulting routing fabric can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc. | 04-18-2013 |
20150324509 | PARTITION BASED DESIGN IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES - Various techniques are provided to generate designs for programmable logic devices (PLDs). In one example, a computer-implemented method includes selectively grouping a first plurality of logic components for a first design into a plurality of partitions. The method also includes selectively merging at least a subset of the partitions of the first design. The method also includes converting each partition into a corresponding first physical implementation for a PLD. The method also includes comparing the first plurality of logic components to a second plurality of logic components for a second design to identify changed and unchanged partitions. The method also includes converting each changed partition into a corresponding second physical implementation for the PLD. The method also includes combining the first physical implementations for the unchanged partitions, with the second physical implementations for the changed partitions. | 11-12-2015 |
20160125115 | GENERATING AN ELECTROMAGNETIC PARAMETERIZED CELL FOR AN INTEGRATED CIRCUIT DESIGN - An electromagnetic parameterized cell (EM Pcell) is generated for a local environment of an integrated circuit (IC) design for an electronic design flow. A set of parasitics extracted netlists is developed from a set of Pcell layouts and an external EM environment. The parasitics extracted netlists are simulated to provide a set of performance metrics. When a symbolic view of the EM Pcell is displayed to a designer during a subsequent schematic phase of the design flow, the performance metrics are accessed from a design library, to increase accuracy of parameter value selection for the EM Pcell without a parasitics extraction of the physical layout and generation of a parasitics extracted netlist. | 05-05-2016 |
716117000 | Configuring PLDs (including data file, bitstream generation, etc.) | 16 |
20100318954 | MANAGING AND CONTROLLING THE USE OF HARDWARE RESOURCES ON INTEGRATED CIRCUITS - Disclosed herein are representative embodiments of methods and apparatus for managing and allocating hardware resources during RTL synthesis. For example, in one exemplary method disclosed herein, an RTL description of a circuit to be implemented in a target architecture is received. The target architecture of this embodiment comprises a fixed number of hardware resources in a class of hardware resources. One or more operator instances are determined from the RTL description received, where at least some of the operator instances are implementable by the hardware resources in the class of hardware resources. In this embodiment, and prior to initially synthesizing the RTL description into a gate-level netlist, assignment information indicative of how the operator instances are to be implemented using the hardware resources in the class of hardware resources is automatically determined. A graphical user interface is also provided that allows a user to view and modify the assignment information. | 12-16-2010 |
20100325598 | SINGLE EVENT TRANSIENT MITIGATION AND MEASUREMENT IN INTEGRATED CIRCUITS - A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements. | 12-23-2010 |
20110126164 | SEMICONDUCTOR INTEGRATED CIRCUIT, PROGRAM TRANSFORMATION APPARATUS, AND MAPPING APPARATUS - A mapping apparatus maps, on a semiconductor integrated circuit, a circuit function described in a circuit description, the semiconductor integrated circuit having a plurality of reconfigurable cores arranged separately from one another and having a logic reconfiguration function. A first group of register circuits are formed between at least two reconfigurable cores included in the plurality of reconfigurable cores and temporarily hold an output from one of the reconfigurable cores and transferring the output to another one of the reconfigurable cores. The mapping apparatus includes a divider that divides the circuit function into a plurality of circuit function blocks, an eliminator that eliminates a register from between the plurality of circuit function blocks and a synthesis executer that executes logic synthesis on each of the plurality of circuit function blocks from between which the register has been eliminated. A placing and routing unit places and routes, on each of the reconfigurable cores, each of the plurality of circuit function blocks on which the logic synthesis has been executed. | 05-26-2011 |
20110161906 | SIGNAL CONVERSION FACILITY AND METHOD FOR CREATING PROGRAMMING FOR A SIGNAL CONVERSION FACILITY - A signal converter device has a programmable logic circuit, wherein a number of binary input signals are being transmitted from the outside of the signal converter unit. The programmable logic circuit is programmed by a programming in such a way, as to detect binary output signals from a number of logic functions. The output signals are output by the signal converter device to the outside. The logic functions are designed in such a manner, that the output signals are determined exclusively by logic associations of the input signals. The output signals are at least partially transmitted to drives. Programming is in such a way, that for at least two drives, output signals to be emitted to the drives are determined uniformly. | 06-30-2011 |
20130007687 | METHOD AND SYSTEM FOR PARTIAL RECONFIGURATION SIMULATION - Disclosed is a method of simulating partial reconfiguration of a programmable logic device (PLD). A wrapper module is incorporated into a logic description that may be implemented in a PLD. The wrapper module represents a first logic design. In response to receiving a parameter, the wrapper module changes to represent a second logic design. According to various embodiments, the logic description is a simulatable source file. The simulatable source file is a source file that is used by a simulation program to simulate partial reconfiguration of the logic design. The wrapper module of the simulatable source file receives a run-time parameter. In various embodiments, the logic description is a synthesizable source file. The synthesizable source file is a source file that is used by a synthesis tool to compile the source file into hardware. The wrapper module of the synthesizable source receives a compile-time parameter. | 01-03-2013 |
20130139122 | Method of, and Apparatus for, Data Path Optimisation in Parallel Pipelined Hardware - A method of generating a hardware design for a pipelined parallel stream processor, by defining a hardware processing operation; specifying at least one propagation rule; defining a graph representing the processing operation in the time domain, comprising at least one data path to be implemented as a hardware design and a plurality of parallel branches; each data path having: at least one data path input, output, and discrete object corresponding to a hardware element; each discrete object comprises an input for receiving an input variable, an operator for executing a function on said input variable, and an output variable; optimizing each output from each discrete object in dependence upon the propagation rule to produce an optimised graph; and utilizing the optimised graph to define an optimised hardware design for implementation in said pipelined parallel stream processor. | 05-30-2013 |
20130239082 | PROGRAMMABLE MICROFLUIDIC SYSTEMS AND RELATED METHODS - A microfluidic device is programmable so that a single microarchitecture design can run many assays. Specifically, the programmable microfluidic device includes an execution method to facilitate translating from a programming language to a set of requests that are specified for the device. In addition, the microfluidic device includes a contamination mitigation method that includes a conflict list to mitigate contamination effects within the microfluidic device. | 09-12-2013 |
20140109031 | CONFIGURATION OF SELECTED MODULES OF A HARDWARE BLOCK WITHIN A PROGRAMMABLE LOGIC DEVICE - Various techniques are provided to configure embedded hardware resources of a programmable logic device (PLD). In one example, a method includes receiving configuration information for a plurality of hardware modules of an embedded hardware block of a PLD. The configuration information is received from a user of a computer system external to the PLD. The method also includes generating a plurality of models of the hardware block. The method also includes merging the generated models into a combined model of the hardware block. The combined model includes the configuration information received for the hardware modules of the hardware block. Related systems and additional techniques are also provided. | 04-17-2014 |
20140137064 | RECONFIGURABLE LOGIC FABRICS FOR INTEGRATED CIRCUITS AND SYSTEMS AND METHODS FOR CONFIGURING RECONFIGURABLE LOGIC FABRICS - In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics. | 05-15-2014 |
20140215424 | DYNAMIC RECONFIGURATION OF PROGRAMMABLE HARDWARE - Technologies related to dynamic reconfiguration of programmable hardware are generally described. In some examples, coprocessor regions in programmable hardware such as a Field Programmable Gate Array (FPGA) may be dynamically assigned to transition the FPGA from a starting arrangement of coprocessor regions to an efficient arrangement. A placement algorithm may be executed to determine the efficient arrangement, and a path finding algorithm may be executed to determine path finding operations leading from the starting arrangement to the efficient arrangement. The path finding operations may be performed to implement the transition. | 07-31-2014 |
20140245246 | CONFIGURING A PROGRAMMABLE LOGIC DEVICE USING A CONFIGURATION BIT STREAM WITHOUT PHANTOM BITS - Techniques and mechanisms generate a configuration bit stream to load into a circuit such as a Programmable Logic Device (PLD). A configuration bit stream may have a reduced size if “phantom bits” not corresponding to configuration elements are removed. However, the PLD may need a full-sized and properly ordered configuration bit stream in order to be properly configured. Techniques and mechanisms are described for selectively adding a “padding bit” to compensate for the missing phantom bits. | 08-28-2014 |
20140351780 | SYSTEM AND METHOD FOR CONFIGURING A CHANNEL - A system and method are provided for configuring a plurality of pin resources. The method includes identifying a plurality of pin resources of a primary application specific integrated circuit (ASIC) device and configuring the plurality of pin resources based on a pin distribution between a first interface and a second interface, where the first interface provides a first communication path between the primary ASIC device and a first device, and the second interface provides a second communication path between the primary ASIC device and a second device. | 11-27-2014 |
20150106776 | TECHNIQUES FOR GENERATING MICROCONTROLLER CONFIGURATION INFORMATION - A method and apparatus for configuring a programmable device, wherein a user may select from pre-defined user modules to select a configuration and corresponding function, representations of which are each displayed to the user, and instructions, based on the selected module, are automatically generated and used by the programmable device to implement the selected configuration and corresponding function. | 04-16-2015 |
20150135155 | Design Support Device, Semiconductor Device, and Non-Transitory Computer Readable Medium - According to an embodiment, a semiconductor device switches circuit forms and circuit configurations of a plurality of analog functional circuits by rearranging a command execution order according to the command execution order set in advance irrespectively of a command execution order specified by a user and executing the commands. | 05-14-2015 |
20160034625 | Network Architectures for Boundary-Less Hierarchical Interconnects - Systems and methods for implementing boundary-less hierarchical networks including methods of generating such networks in accordance with embodiments of the invention are disclosed. In one embodiment, a hierarchical network in an integrated circuit that includes a plurality of computing elements, where the plurality of computing elements have M outputs and N inputs, and a plurality of switches arranged into stages of switches wherein the plurality of computing elements are connected to switches in a first stage, the switches in the first stage are connected to the plurality of computing elements and switches in a second stage, where the switches in the second stage are connected to the switches in the first stage, at least M+1 adjacent computing elements can connect to at least two nearest neighboring computing elements via a stage 1 switch, and every computing element can connect with every other computing element within the hierarchical network. | 02-04-2016 |
20220138390 | INFORMATION PROCESSING APPARATUS AND NON-TRANSITORY COMPUTER READABLE MEDIUM - An information processing apparatus includes a processor connected to a programmable logic circuit and configured to: acquire a software module indicating first processing and start the first processing; reconfigure a hardware module in the programmable logic circuit, the hardware module indicating second processing included in the first processing; and, if reconfiguration of the hardware module is completed before the first processing is completed, supply intermediate data generated by the first processing to the hardware module and cause the programmable logic circuit to start to execute the second processing. | 05-05-2022 |