Entries |
Document | Title | Date |
20110055625 | NONVOLATILE MEMORY DEVICE AND MEMORY CONTROLLER - The memory controller writes and reads data in and from a nonvolatile memory. The nonvolatile memory has a plurality of memory cell blocks, each memory cell block includes a plurality of multi-level cells each capable of storing m-bit data (m is a natural number of two or more), a first page to a m-th page are allocated to the respective m bits of the multi-level cell, the memory controller sequentially writes the data to the memory cells from the first page in ascending order, and comprises a backup unit, and when a write command is received from the outside of the memory controller, in a case where a data write destination of the data in the nonvolatile memory is a n-th (n is a natural number of two to m) page of the multi-level cell, and data is already written in the first to (n-1)th pages, the backup unit copies the already written data to a nonvolatile storable backup region. | 03-03-2011 |
20110066880 | APPARATUS AND METHOD FOR COMPENSATING FOR SYSTEM MEMORY ERROR - A method to compensate for a system memory error, including determining whether there is an error in the system memory using a system memory error compensation program; initializing system memory error compensation values during reboot if an error is detected in the system memory; sequentially changing the initialized system memory error compensation values to determine system memory error compensation values that reduce system memory error; and storing the determined system memory error compensation values in a basic input/output system (BIOS) memory. | 03-17-2011 |
20110099417 | Memory Device and Method for Repairing a Semiconductor Memory - A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row. The block repair device stores a block repair configuration that determines the dimensions (e.g., the number of rows and columns spanned) of a repair block. Routing circuitry is configured by the stored block repair configuration to output some row and column address bits from received row and column addresses in a selected ratio. Comparison circuitry compares the row and column address bits output by the routing circuitry with the address of the defective cell that defines the repair block. When a match occurs, the comparison circuitry implements a block repair by activating the redundant row and by causing data to be written to or read from the activated redundant row instead of the primary array. | 04-28-2011 |
20110179306 | Data Read Method for Flash Memory - The invention provides a data read method. In one embodiment, a flash memory comprises a plurality of pages, and predetermined information is written into each of the pages of the flash memory. First, a target address of the flash memory is read according to a source read voltage to obtain source data and a source error correction code. When error bits of the source data cannot be corrected according to the source error correction code, the predetermined information corresponding to the source data is read from the flash memory according to the source read voltage to obtain correction information. The source data and the source error correction code are then amended according to the difference between the predetermined information and the correction information to obtain an amended data and an amended error correction code. Error bits of the amended data are then corrected according to the amended error correction code. | 07-21-2011 |
20110185223 | Target Operating System and File System Agnostic Bare-Metal Restore - A system, method, and computer program product for performing a bare-metal restore, the system including a target storage device, and a target computer configured to boot independent of the target storage device, expose the target storage device to a restoring computer after the target computer has booted, and act as a conduit for the restoring computer to perform a bare-metal restore of backup data onto the target storage device, and the method including booting a target computer independent of a target storage device, exposing the target storage device to a restoring computer after the target computer has booted, and causing the target computer to act as a conduit for the restoring computer to perform a bare-metal restore of backup data onto the target storage device. | 07-28-2011 |
20110185224 | FLASH STORAGE DEVICE AND DATA PROTECTION METHOD THEREOF - A flash storage device comprises: a memory module, for storing data; a control unit, electrically connected to the memory module, for accessing the data in the memory module; and a detecting unit, electrically connected to the control unit, for passing a temperature detecting result to the control unit, and the control unit determining whether a data protection operation is activated according to the temperature detecting result. | 07-28-2011 |
20110185225 | MEMORY SYSTEM WITH NONVOLATILE SEMICONDUCTOR MEMORY - A memory system includes a nonvolatile semiconductor memory and a controller. The memory has a plurality memory blocks each including memory cells capable of holding data. The data in each of the memory blocks is erased simultaneously. The data is written simultaneously in pages in each of the memory blocks. Each of the pages is a set of a plurality of memory cells. The controller transfers write data and a first row address to the memory and issues a change instruction for the transferred first row address and a second row address differing from the first row address. The memory writes the write data into the memory cells corresponding to the first row address when the change instruction has not been issued, and writes the write data into the memory cells corresponding to the second row address when the change instruction has been issued. | 07-28-2011 |
20110202789 | PROCESSOR-MEMORY UNIT FOR USE IN SYSTEM-IN-PACKAGE AND SYSTEM-IN-MODULE DEVICES - An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols. | 08-18-2011 |
20110264948 | DISK STORAGE APPARATUS AND METHOD FOR RECOVERING DATA - According to one embodiment, a disk storage apparatus includes a write module, an operation module, and a controller. The write module is configured to write data, in units of blocks, in a designated write area of a disk. The operation module is configured to perform an exclusive OR operation on the blocks of data. The controller is configured to control the write module, causing the write module to write, in a designated block, recovery data that is a result of the exclusive OR operation on all data blocks written in the designated write area. | 10-27-2011 |
20110283136 | MEMORY ERRORS - The present invention provides a method of protecting against errors in a boot memory, the method comprising initiating booting of a processor by executing primary boot code from a primary boot memory, and based on the execution of the primary boot code: accessing a data structure comprising a plurality of redundant portions of boot information stored on a secondary boot memory; performing an error check on a plurality of the portions to determine whether those portions contain errors and, based on the error checks, to identify a valid portion; and booting the processor using the valid portion of boot information. | 11-17-2011 |
20110296235 | MEMORY DEVICE - According to one embodiment, a memory device includes a semiconductor memory and a controller that controls the semiconductor memory. The controller includes a first command issuing module, second command issuing module, error correction module and control module. The first command issuing module is configured to issue a read command to the semiconductor memory. The second command issuing module is configured to issue a first command instructing a process that does not involve reading data from the semiconductor memory independently from the first command issuing module to the semiconductor memory. The error correction module is configured to correct an error contained in data supplied from the semiconductor memory. The control module is configured to control the error correction module, first command issuing module and second command issuing module. | 12-01-2011 |
20120023363 | PROTOCOL INCLUDING A COMMAND-SPECIFIED TIMING REFERENCE SIGNAL - Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device. | 01-26-2012 |
20120089866 | DISASTER RECOVERY PRODUCTION TAKEOVER - Various embodiments for disaster recovery (DR) production takeover in a computing environment by a processor device are provided. If, for a designated storage system operable in the computing environment, a takeover operation may be executed, and a DR storage system has validly replaced the designated storage system using a replacement process, a withdrawal of a DR mode of operation is performed, and ownership of at least one storage device operable in the computing environment is transferred to the DR storage system. The replacement process authorizes the DR storage system to transfer the ownership while withdrawn from the DR mode of operation. | 04-12-2012 |
20120159239 | DATA MANIPULATION OF POWER FAIL - Disclosed is a power isolation and backup system. When a power fail condition is detected, temporary storage is flushed to an SDRAM. After the flush, interfaces are halted, and power is removed from most of the chip except the SDRAM subsystem. The SDRAM subsystem copies data from an SDRAM to a flash memory. On the way, the data may be encrypted, and/or a data integrity signature calculated. To restore data, the SDRAM subsystem copies data from the flash memory to the SDRAM. On the way, the data being restored may be decrypted, and/or a data integrity signature checked. | 06-21-2012 |
20120173920 | MEMORY SYSTEM AND METHOD OF OPERATING THE SAME - A method of operating a memory system includes classifying numbers of total error bits into a plurality of ranges, assigning a plurality of data to the plurality of ranges, respectively, counting a number of detected error bits for a memory cell block, and storing a selected one of the plurality of data in at least one spare cell when the number of the detected error bits is within one of the ranges that corresponds to the selected data. | 07-05-2012 |
20120198272 | Priority Based Exception Mechanism for Multi-Level Cache Controller - This invention is an exception priority arbitration unit which prioritizes memory access permission fault and data exception signals according to a fixed hierarchy if received during a same cycle. A CPU memory access permission fault is prioritized above a DMA memory access permission fault of a direct memory access permission fault. Any memory access permission fault is prioritized above a data exception signal. A non-correctable data exception signal is prioritized above a correctable data exception signal. | 08-02-2012 |
20120226934 | MISSION CRITICAL NAND FLASH - A flash controller reliably stores data in NAND FLASH by encoding data using an encoding algorithm, and storing that data across multiple pages of the memory. In one embodiment, true data is accepted by the controller, and the controller in turn creates coded data that is the bit-for-bit complement of the true data. The true data and the coded data are then written to the NAND FLASH on a page by page basis. A property of the coding techniques used is that, in at least some cases, detected errors can be corrected. | 09-06-2012 |
20120233497 | DATA STORAGE APPARATUS, CACHE CONTROL APPARATUS AND METHOD FOR CONTROLLING CACHE MEMORY - According to one embodiment, a cache control apparatus includes an error detecting and correcting module and a controller. The error detecting and correcting module is configured to detect errors in the data read from a cache memory and to correct the errors. The controller is configured to control the supply of power to the cache memory if the error detecting and correcting module is unable to correct errors and if the errors are hard errors. | 09-13-2012 |
20120278651 | Remapping data with pointer - Embodiments herein relate to a method for remapping data. In an embodiment, it is determined if a first memory block is faulty. A pointer is stored to the first memory block and a pointer flag of the first memory block is set when the first memory block is faulty. Data previously stored at the first memory block is written to a second memory block, where the pointer points to a location of the second memory block. | 11-01-2012 |
20120297242 | IMAGE PROCESSING APPARATUS AND METHOD FOR CONTROLLING IMAGE PROCESSING APPARATUS - An image processing apparatus includes an image processing unit configured to perform image processing, a storage unit configured to be capable of storing an application program installed in the image processing apparatus, a first determination unit configured to determine whether the application program had ever been installed in the image processing apparatus, and a control unit configured to selectively control the image processing unit to be operable and control the image processing unit not to operate according to the determination by the first determination unit if an error has occurred in the storage unit. | 11-22-2012 |
20120304000 | RESTORING STORAGE DEVICES BASED ON FLASH MEMORIES AND RELATED CIRCUIT, SYSTEM, AND METHOD - A restoring operation of a storage device based on a flash memory. In an embodiment, a storage device emulates a logical memory space (including a plurality of logical blocks each one having a plurality of logical sectors), which is mapped on a physical memory space of the flash memory (including a plurality of physical blocks each one having a plurality of physical sectors for storing different versions of the logical sectors). A method may detect a plurality of conflicting physical blocks for a corrupted logical block and determines a plurality of validity indexes. One or more of the conflicting physical blocks are selected according to the validity indexes. The selected conflicting physical blocks are then associated with the corrupted logical block. At the end, each one of the non-selected conflicting physical blocks is discarded. | 11-29-2012 |
20120311379 | CONTROL OF INTERRUPT GENERATION FOR CACHE - A data processing device includes a cache having a plurality of cache lines. Each cache line has a lockout state that indicates whether an error has been detected for data accessed at the cache line. The lockout state of a cache line is indicated by a set of one or more lockout bits associate with the cache line. When a cache line is in a locked-out state, the cache line is not used by the cache. Accordingly, a locked-out cache line is not employed by the cache to satisfy a cache accesses, and is not used to store data retrieved from memory in response to a cache miss. In response to determining the detected error likely did not result from a hardware failure or other persistent condition, memory error management software can reset the lockout state of the cache line. | 12-06-2012 |
20120324276 | INTELLIGENT BIT RECOVERY FOR FLASH MEMORY - A method and system intelligent bit recovery is provided. The intelligent bit recovery determines which bits are toggling, and examines a subset of the potential bit patterns to determine which in the subset of potential bit patterns is valid. The subset is a fraction of the potential bit patterns, and is based on an understanding of the flash memory and the problems that may cause the toggling bits. The intelligent bit recovery may analyze at least one aspect of the flash memory to identify which problem is potentially causing the toggling bits, and to select the subset of potential bit patterns as solutions for the determined problem. Or, the intelligent bit recovery selects potential bit patterns for multiple potential problems. In either way, the subset of potential bit patterns examined by the intelligent bit recovery is a small fraction of the entire set of potential bit patterns. | 12-20-2012 |
20120324277 | SYSTEM AND METHOD FOR DETECTING COPYBACK PROGRAMMING PROBLEMS - Methods and systems are disclosed herein for detecting problems related to copyback programming. After the copyback data is read into the internal flash buffer, a part of the copyback data stored in the internal flash buffer (such as spare data) is analyzed to determine whether there are any errors in a part of the copyback data read. The analysis may be used by the flash memory in one or more ways related to the current copyback operation, subsequent copyback operations, subsequent treatment of the data in the current copyback operation, and subsequent treatment of the section in memory associated with the source page. | 12-20-2012 |
20130073897 | HANDLING UNCLEAN SHUTDOWNS FOR A SYSTEM HAVING NON-VOLATILE MEMORY - Systems and methods are disclosed for handling unclean shutdowns for a system having non-volatile memory (“NVM”). In some embodiments, the system can leverage from information obtained from index pages in order to efficiently reconstruct logical-to-physical mappings after an unclean shutdown event. In other embodiments, the system can reconstruct logical-to-physical mappings by leveraging from context information stored in a NVM. In further embodiments, context information can be used in conjunction with index pages to reconstruct logical-to-physical mappings after an unclean shutdown. | 03-21-2013 |
20130086416 | AUTOMATIC DISK POWER-CYCLE - According to the presently disclosed subject matter there is provided, inter alia, a system and method which enable to identify, in a storage-system, malfunctioning disks, and in response, to activate a power-cycle process only for the specific failing disks, in order to bring these disks into proper operational mode. During the power-cycle process of a failing disk, other disks, which are not failing, remain operative and available. | 04-04-2013 |
20130117602 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING REDUNDANCY CELLS - In one embodiment, the memory device includes a memory cell array having at least a first memory cell group, a second memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, the second memory cell group includes a plurality of second memory cells associated with a second data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. A data line selection circuit is configured to provide a data path between an input/output node and one of the first data line, the second data and the redundancy data line. | 05-09-2013 |
20130151889 | DISK-FREE RECOVERY OF XA TRANSACTIONS FOR IN-MEMORY DATA GRIDS - A data grid node that is hosted by a computing system receives a request to prepare transaction operations for a multi-operational transaction for a commit. The transaction operations are associated with other data grid nodes in the data grid. The data grid node stores transaction state data for the multi-operational transaction in local memory associated with the data grid node and identifies other data grid nodes in the data grid that manage the data pertaining to the transaction operations for the multi-operational transaction. The data grid node sends the transaction state data to the other data grid nodes and the other data grid nodes store the transaction state data in local memory associated with the corresponding data grid node. | 06-13-2013 |
20130185589 | MIRRORING DISK DRIVE SECTORS - A recoverable error associated with a first disk drive sector is determined. Data of the first disk drive sector is duplicated to a mirrored sector in response to the recoverable error. The first disk drive sector continues to be used to store the data after the recoverable error is determined. | 07-18-2013 |
20130238927 | METHOD OF OPERATING A STORAGE DEVICE - A device power is supplied for running a storage device. When a device error occurs, a recovery operation is performed on the storage device. When the recovery operation fails, the device power is reset in a compatibility verification operation and the recovery operation is performed again on the storage device. | 09-12-2013 |
20130254591 | METHOD AND DEVICE FOR ENHANCING THE RELIABILITY OF A MULTIPROCESSOR SYSTEM BY HYBRID CHECKPOINTING - The present invention relates to a method and a device for enhancing the reliability of a system comprising a plurality of processors and a memory. The method comprises a step of grouping processes into a plurality of groups and a step of saving, individually for each group of processes, data stored in the memory which can be used by at least one of the processes belonging to said group, so as to restore an error-free global state of the system following an error occurring in a processor executing one of the processes belonging to said group without having to restore the entire memory. | 09-26-2013 |
20130268802 | MEMORY SYSTEM AND WIRELESS COMMUNICATION METHOD BY MEMORY SYSTEM - An aspect of the present embodiment, there is provided a memory system including a nonvolatile memory area, a first interface be connected to a first host device, a second interface connected to a second host device, and a controller controlling the first interface such that the first device is configured to prohibit to write data into the nonvolatile memory area on a basis of a command provided from the second host device before the second host device writes data into the nonvolatile memory area through the second interface, wherein the first interface notices an error to the first host device when the first device writes data into the nonvolatile memory area, and the second host device transmits data from an portion not to be written in the nonvolatile memory area to the first host. | 10-10-2013 |
20130268803 | METHOD FOR OPERATING MEMORY CONTROLLER AND DEVICES HAVING THE SAME - A memory controller and an operating method of the memory controller are provided. The operating method includes: performing error correction on data, including a plurality of chunks, in a unit of a chunk; determining if a coefficient of each term of which a degree is equal to or greater than a degree of a reference-degree term, in an error location polynomial for a last chunk among the plurality of chunks, is all zero; and controlling an output time of an error-corrected first chunk based on a result of the determining. | 10-10-2013 |
20130318391 | METHODS FOR MANAGING FAILURE OF A SOLID STATE DEVICE IN A CACHING STORAGE - Techniques for managing caching use of a solid state device are disclosed. In some embodiments, the techniques may be realized as a method for managing caching use of a solid state device. Management of the caching use may include receiving, at a host device, notification of failure of a solid state device. In response to the notification a cache mode may be set to uncached. In uncached mode input/output (I/O) requests may be directed to uncached storage (e.g., disk). | 11-28-2013 |
20130318392 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD - An information processing apparatus includes a memory, and a processor that executes a process in the memory. The process includes detecting a sign of a fault of a storage device that prohibits write access to a storage area of the storage device and permits read access to the storage area during a fault, and storing a copy of data to be written to the storage device as first copy data in the memory when the sign of a fault is detected. | 11-28-2013 |
20130339784 | ERROR RECOVERY IN REDUNDANT STORAGE SYSTEMS - Embodiments relate to providing error recovery in a storage system that utilizes data redundancy. An aspect of the invention includes monitoring plurality of storage devices of the storage system and determining that one of the plurality of storage devices has failed based on the monitoring. Another aspect of includes suspending data reads and writes to the failed storage device and determining that the failed storage device is recoverable. Based on determining that the failed storage device is recoverable, initiating a rebuilding recovery process of the failed storage device based on determining that the failed storage device is recoverable and restoring data reads and writes to the failed storage device upon completion of the rebuilding recovery process. | 12-19-2013 |
20140047265 | ENHANCED STORAGE OF METADATA UTILIZING IMPROVED ERROR DETECTION AND CORRECTION IN COMPUTER MEMORY - A novel ECC scheme is disclosed that offers an error protection level that is at least the same as (if not better than) that of the conventional ECC scheme without negatively impacting latency and design complexity. Embodiments of the present disclosure utilize an ECC scheme which leaves up to extra 2B for metadata storage by changing the error detection and correction process flow. The scheme adopts an early error detection mechanism, and tailors the need for subsequent error correction based on the results of the early detection. | 02-13-2014 |
20140059376 | RECOVERING A VOLUME TABLE AND DATA SETS FROM A CORRUPTED VOLUME - Provided are a computer program product, system, and method for recovering a volume table and data sets from a corrupted volume. Data corruption is detected in a volume having data sets. A volume table having information on the data sets allocated in the volume is diagnosed. A backup volume table comprising a most recent valid backup of the volume table is accessed from a backup of the volume in response to determining that the diagnosed volume table is not valid. Content from the backup volume table is processed to bring to a current state in a recovery volume table for a recovery volume. The data sets in the volume are processed to determine whether they are valid. The valid data sets are moved to the recovery volume. A data recovery operation is initiated for the data sets determined not to be valid. | 02-27-2014 |
20140068322 | IIMPLEMENTING DRAM COMMAND TIMING ADJUSTMENTS TO ALLEVIATE DRAM FAILURES - A method, system and computer program product are provided for implementing command timing adjustments to alleviate Dynamic Random Access Memory (DRAM) failures in a computer system. A predefined DRAM failure is detected. Responsive to the detected failure, a set of timers is adjusted for controlling predetermined timings used to access the DRAM. Responsive to the failure being resolved by the adjusted set of timers, checking for a predetermined level of performance is performed. | 03-06-2014 |
20140108856 | Real-Time Trigger Sequence Checker - A system, and in particular a system operating in real-time, may have its operation rely on a particular sequence of trigger signals, hardware or software, for proper operation. A trigger sequence checker provides a way to monitor in real-time predetermined sequences of triggers and is configured to generate an error signal upon detection of a faulty operation or sequence. Rules for sequences of triggers are stored in memory and are used by the trigger sequence checker to verify one or more sequences of triggers received as an input to the checker. A plurality of triggers may be handled by the checker. In one embodiment the checker is configurable to be set in a learning mode to capture triggers rules. | 04-17-2014 |
20140115381 | MULTI-LEVEL RUN-LENGTH LIMITED FINITE STATE MACHINE WITH MULTI-PENALTY - Techniques are described for constructing maximum transition run (MTR) modulation code based upon a multi-level (ML) run-length limited (RLL) finite state machine (FSM) that implements different sets of penalties. A processor is configured to receive information from a hard disk drive (HDD) via a read channel and recover data from the HDD using MTR modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct an MTR modulation code to mimic the optimized Markov source based upon an FSM having a limited transition run length and a multi-level periodic structure. The FSM provides at least two different sets of penalties in a period. | 04-24-2014 |
20140115382 | Scheduling Workloads Based on Detected Hardware Errors - Scheduling workloads based on detected hardware errors is provided. In response to determining that a hardware error is detected, it is determined whether the hardware error is a cache error. In response to determining that the hardware error is a cache error, it is determined whether execution of a workload on a processor is changing contents of a cache associated with the cache error more than a threshold value. In response to determining that the execution of the workload on the processor is changing the contents of the cache associated with the cache error more than the threshold value, it is determined whether the cache associated with the cache error is private to a core in the processor. In response to determining that the cache associated with the cache error is private to a core, the execution of the workload is scheduled on a different core of the processor. | 04-24-2014 |
20140122922 | METHODS AND STRUCTURE TO ASSURE DATA INTEGRITY IN A STORAGE DEVICE CACHE IN THE PRESENCE OF INTERMITTENT FAILURES OF CACHE MEMORY SUBSYSTEM - Methods and structure for enabling re-training of a DDR memory controller in a storage device without loss of data in the DDR memory devices of the cache memory in response to detecting failure of the memory subsystem during operation of the storage device. In response to detecting a failure of the memory subsystem, the memory controller is reset without resetting the memory devices. The memory controller is then re-trained for operation with the memory device. During the re-training, self-refresh mode of the memory devices is disabled and manual refresh is performed by a processor of the storage device to thereby retain any user data in the memory device. | 05-01-2014 |
20140129874 | REDUNDANCY SCHEMES FOR NON-VOLATILE MEMORY USING PARITY ZONES HAVING NEW AND OLD PARITY BLOCKS - A method includes, in a non-volatile memory that includes multiple memory blocks, defining a redundancy zone that includes at least an old parity block, a new parity block and multiple active blocks of which one block is defined as an open block. Data is stored in the redundancy zone and the stored data is protected, such that new input data is stored in the open block, redundancy information for the active blocks including the open block is stored in the new parity block, and the redundancy information for the active blocks excluding the open block is stored in the old parity block. Upon filling the open block and the new parity block, an alternative block is assigned to serve as the open block and the new parity block is assigned to serve as the old parity block. | 05-08-2014 |
20140136883 | READ DISTURB EFFECT DETERMINATION - An apparatus comprising a non-volatile memory and a controller. The controller is coupled to the non-volatile memory and configured to (i) accumulate a read disturb count for a first region of the non-volatile memory, (ii) accumulate error statistics for a second region of the non-volatile memory, (iii) determine, based upon both the read disturb count and the error statistics, whether the first region has reached a read disturb limit, and (iv) in response to determining that the first region has reached the read disturb limit, relocate at least some data of the first region. | 05-15-2014 |
20140136884 | READ DISTURB HANDLING FOR NON-VOLATILE SOLID STATE MEDIA - Described embodiments track a read disturb limit of a solid-state media coupled to a media controller. The media controller receives a read operation from a host device. In response to the received read operation, the media controller determines one or more associated regions of the solid-state media accessed by the read operation and reads the associated regions to provide read data to the host device. Based on a probability value corresponding to each of the associated regions, the media controller selectively increments a read count of each of the associated regions. Based upon each read count, the media controller determines whether each region has reached a read disturb limit. If a given region has reached the read disturb limit, the media controller relocates data of the given region to a free region of the solid-state media. Otherwise, the media controller maintains the data in the given region. | 05-15-2014 |
20140149787 | METHOD AND SYSTEM FOR COPYBACK COMPLETION WITH A FAILED DRIVE - Disclosed is a method and system for saving the copybacked data in a drive and continuing to rebuild on the same drive where the copy back was in progress when the online drive, where the copy back is not initiated, fails. | 05-29-2014 |
20140157044 | IMPLEMENTING DRAM FAILURE SCENARIOS MITIGATION BY USING BUFFER TECHNIQUES DELAYING USAGE OF RAS FEATURES IN COMPUTER SYSTEMS - A method, system and computer program product are provided for implementing dynamic random access memory (DRAM) failure scenarios mitigation using buffer techniques delaying usage of RAS features in computer systems. A buffer is provided with a memory controller. Physical address data read/write failures are analyzed. Responsive to identifying predefined failure types for physical address data read/write failures, the buffer is used to selectively store and retrieve data. | 06-05-2014 |
20140164820 | MANAGING ERRORS IN A DRAM BY WEAK CELL ENCODING - This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data. | 06-12-2014 |
20140164821 | Techniques For Encoding and Decoding Using a Combinatorial Number System - A data storage system includes a memory circuit having memory cells and a control circuit. The control circuit is operable to receive data bits provided for storage in the memory cells. A subset of the memory cells have predetermined stuck-at faults. The control circuit is operable to compute a binomial coefficient for each of the predetermined stuck-at faults based on a bit position of a corresponding one of the predetermined stuck-at faults within the memory cells. The control circuit is operable to add together the binomial coefficients to generate an encoded number using a combinatorial number system. The control circuit is operable to generate a first set of redundant bits that indicate the encoded number. The first set of redundant bits are used to decode bits read from the memory cells to regenerate the data bits. | 06-12-2014 |
20140164822 | HOST COMPUTER AND METHOD FOR MANAGING SAS EXPANDERS OF SAS EXPANDER STORAGE SYSTEM - In a method for managing serial attached small computer system interface (SAS) expanders using a host computer, the host computer connects to an SAS expander storage system through a redundant array of independent disks (RAID) card. The SAS expander storage system includes a first switch device, a first SAS expander, a second SAS expander, a second switch, a flash memory, and hard disk drives. The method controls the first switch device to switch the RAID card from the first SAS expander to the second SAS expander when the first SAS expander fails to function, controls the second switch device to switch the flash memory from the first SAS expander to the second SAS expander, and controls the first switch device to connect each of the hard disk drives to the second SAS expander. | 06-12-2014 |
20140164823 | Memory Disturbance Recovery Mechanism - Components of a memory system, such as a memory controller and memory device, which detect accumulated memory read disturbances and correct such disturbances before they reach a level that causes errors. The memory device includes a memory array and a disturbance control circuit. The memory array includes a plurality of memory rows. Each memory row is associated with a disturbance warning circuit having a state that corresponds to an accumulated disturbance in the memory row. The disturbance control circuit determines, responsive to an activation of a memory row of the plurality of memory rows specified by a row access command, whether the disturbance condition is present in the memory row based on the state of the disturbance warning circuit associated with the memory row. If a disturbance condition is present, the disturbance control circuit causes a recovery operation to be performed on the memory row to reduce the accumulated disturbances. | 06-12-2014 |
20140181575 | DATA ERROR DETECTION AND CORRECTION USING HASH VALUES - The subject disclosure is directed towards a data storage service that uses hash values, such as substantially collision-free hash values, to maintain data integrity. These hash values are persisted in the form of mappings corresponding to data blocks in one or more data stores. If a data error is detected, these mappings allow the data storage service to search the one or more data stores for data blocks having matching hash values. If a data block is found that corresponds to a hash value for a corrupted or lost data block, the data storage service uses that data block to repair the corrupted or lost data block. | 06-26-2014 |
20140189420 | MEMORY SYSTEM - A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus. | 07-03-2014 |
20140201566 | AUTOMATIC COMPUTER STORAGE MEDIUM DIAGNOSTICS - An approach to providing diagnostics of data storage medium units may be performed automatically without interruption to system operations. Upon receipt of one or more error messages occurring on a first data storage medium unit, data content from the first data storage medium unit may be copied to a second data storage medium unit. A system may operate using the second data storage medium unit while the first data storage medium unit is diagnosed for possible disk failure. | 07-17-2014 |
20140245061 | Fault Repair Apparatus, Fault Repair Method and Storage Medium Storing Fault Repair Program - Disclosed is a fault repair apparatus capable of reducing time which fault repair processing needs. | 08-28-2014 |
20140281682 | Systems and Methods for Performing Defect Detection and Data Recovery in a Memory System - Systems and methods for performing defect detection and data recovery within a memory system are disclosed. A controller of a memory system may receive a command to write data in a memory of the memory system; determine a physical location of the memory that is associated with the data write; write data associated with the data write to the physical location; and store the physical location of the memory that is associated with the data write in a Tag cache. The controller may further identify a data keep cache of a plurality of data keep caches that is associated with the data write based on the physical location of the memory that is associated with the data write; update an XOR sum based on the data of the data write; and store the updated XOR sum in the identified data keep cache. | 09-18-2014 |
20140281683 | FLASH MEMORY TECHNIQUES FOR RECOVERING FROM WRITE INTERRUPT RESULTING FROM VOLTAGE FAULT - Techniques, related to a flash memory device having a non-volatile memory array (NVM), for recovering from a write interrupt resulting from host-supplied memory voltage fault are disclosed. A memory controller is configured to control a response to an occurrence of the write-interrupt, the response including writing to the NVM, after the memory voltage is verified as being within an acceptable range, one or more of a safe copy of a portion of a first sector of upper-page data and a safe copy of a portion of a second sector of lower-page data, and terminating the write interrupt. Terminating the write-interrupt may include receiving new data from the host while avoiding sending an error message to the host. | 09-18-2014 |
20140281684 | Data Storage Devices Based on Supplementation - New data storage devices and techniques are provided. In some aspects of the invention, a new remote supplementation based media and system are provided. A local file and control system comprises a data density distribution that varies depending on Media Depth. A remote supplementation source and control system are also provided in a common network with the local control system. The local control system reports local file attributes, authorization and factors impacting media depth in real time, and the supplementation control system delivers permanent and streaming data corrections, supplementation and format updates to the local control system. In additional aspects of the invention, a patterned reference media device aids in building the local data density distribution. In some embodiments, the 3D arrangement, or other attributes, of structural storage device elements may serve as the patterned reference device. | 09-18-2014 |
20140281685 | PROBABILITY-BASED REMEDIAL ACTION FOR READ DISTURB EFFECTS - A method may be performed in a data storage device that includes a memory including a three-dimensional (3D) memory and a controller, in response to a request to read data from the memory. The data is located within a first word line of the memory. The method includes accessing the data from the first word line and determining, based on a probability threshold, whether to perform a remedial action with respect to a second word line. | 09-18-2014 |
20140298087 | HARD DISK DATA RECOVERY METHOD, APPARATUS, AND SYSTEM - This invention discloses a hard disk data recovery method, apparatus, and system. The method includes: recording a logical block address corresponding to erroneous data if an error is discovered when data is read from the hard disk; performing a recovery operation for data at a first physical block address corresponding to the logical block address according to a preset algorithm to obtain recovered data; and sending an instruction of writing the recovered data into the logical block address to the hard disk so that the hard disk writes the recovered data into the logical block address according to the instruction, where the logical block address corresponds to a remapped second physical block address. Therefore, the method repairs an erroneous sector or a bad block of the hard disk quickly and improves efficiency of repairing the erroneous sector of the hard disk or the bad block of the hard disk. | 10-02-2014 |
20140304546 | SYSTEM AND METHOD FOR RECOVERING FROM A CONFIGURATION ERROR - A system and method for recovering from a configuration error are disclosed. A Basic Input Output System (BIOS) configures a memory associated with a node of an information handling system and enables a progress monitoring process during configuration of the memory. The memory is disabled if the BIOS determines that a configuration error occurred and a memory reference code associated with the memory is modified in order to prevent a reset of the information handling system. | 10-09-2014 |
20140317443 | METHOD AND APPARATUS FOR TESTING A STORAGE SYSTEM - A method and a system for testing a storage system to which is applied a command or a sequence of commands. The storage system has a storage medium and a controller, and each command results in an outcome, and the method comprises: storing in a dataset; information related to the command and/or the sequence of commands including for each command: an address of the storage system the command is applied to, and an outcome of the command. When a sequence of commands is applied, the information stored in the dataset includes an outcome of the sequence of commands. This method further comprises selecting one or more commands from the dataset to be subsequently replayed when the outcome of the at least one command indicates an error. | 10-23-2014 |
20140351627 | STORAGE DEVICE WITH ERROR RECOVERY INDICATION - Methods, apparatus and computer program products implement embodiments of the present invention that enable a controller of a storage device having storage media to perform one or more error recovery operations on the storage media, and to convey, while performing the one or more error recovery operations, a message indicating a status of the one or more error recovery operations to a host processor in communication with the storage device. Storage devices implementing embodiments of the present invention include hard disk drives and solid state disk drives. | 11-27-2014 |
20140351628 | INFORMATION PROCESSING DEVICE, CONTROL CIRCUIT, COMPUTER-READABLE RECORDING MEDIUM FOR CONTROL PROGRAM, AND CONTROL METHOD - An information processing device includes: a storage device that has a plurality of storage areas; a detection unit that carries out error detection from read data out of the storage area belonging to the storage device; a readout unit that, in a case that the detection unit detects an error, identifies an area where error occurrence is estimated including a storage area in which the data where the error is detected is written and carries out readout of data individually from each storage area in the identified area; and a movement unit that, in a case of detecting an error from the data read out by the readout unit, moves the data to another storage area. | 11-27-2014 |
20140359345 | DATA STORAGE DEVICE AND ERROR CORRECTION METHOD THEREOF - The present invention provides a data storage device including a flash memory and a controller. The controller is configured to perform a first read operation to read a first page corresponding to a first word line of the flash memory according to a read command of a host, and perform a distribution-adjustment procedure when data read by the first read operation cannot be recovered by coding, wherein the controller is further configured to perform an adjustable read operation to read a second page corresponding to a second word line of the flash memory in the distribution-adjustment procedure. | 12-04-2014 |
20140359346 | DATA STORAGE DEVICE AND ERROR CORRECTION METHOD THEREOF - The present invention provides a data storage device including a flash memory and a controller. The flash memory is capable of operating in a SLC mode and a non-SLC mode. The controller is configured to perform a first read operation to read a page corresponding to a first word line of the flash memory in the SLC mode according to a read command of a host, and perform an adjustable read operation when data read by the first read operation cannot be recovered by coding, wherein the controller is further configured to enable the flash memory to operate in the non-SLC mode in the adjustable read operation, and write logic 1 into a most-significant-bit page corresponding to the first word line in the non-SLC mode to adjust voltage distribution of the first page. | 12-04-2014 |
20140365816 | SYSTEM AND METHOD FOR ASSIGNING MEMORY RESERVED FOR HIGH AVAILABILITY FAILOVER TO VIRTUAL MACHINES - Techniques for assigning memory reserved for high availability (HA) failover to virtual machines in high availability (HA) enabled clusters are described. In one embodiment, the memory reserved for HA failover is determined in each host computing system of the HA cluster. Further, the memory reserved for HA failover is assigned to one or more virtual machines in the HA cluster as input/output (I/O) cache memory at a first level. | 12-11-2014 |
20150019904 | DATA PROCESSING SYSTEM AND OPERATING METHOD THEREOF - Provided is an operating method of a data processing system which includes a data storage device and a host device. The operating method includes reading data at the data storage device based on a request from the host device, and performing an error correction code (ECC) decoding operation on the read data, and performing an additional ECC decoding operation at the host device when the ECC decoding operation performed by the data storage device fails. | 01-15-2015 |
20150019905 | STALE DATA DETECTION IN MARKED CHANNEL FOR SCRUB - Embodiments relate to stale data detection in a marked channel for a scrub. An aspect includes bringing the marked channel online, wherein the computer comprises a plurality of memory channels comprising the marked channel and a remaining plurality of unmarked channels. Another aspect includes performing a scrub read of an address in the plurality of memory channels. Another aspect includes determining whether data returned by the scrub read from the marked channel is valid or stale based on data returned from the unmarked channels by the scrub read. Another aspect includes based on determining that the data returned by the scrub read from the marked channel is valid, not performing a scrub writeback to the marked channel. Another aspect includes based on determining that the data returned by the scrub read from the marked channel is stale, performing a scrub writeback of corrected data to the marked channel. | 01-15-2015 |
20150026509 | STORAGE DEVICE HAVING A DATA STREAM CONVERTER - According to one embodiment, a storage device has a plurality of memory modules and a memory controller. The memory controller has a first unit configured to receive data to be stored in the memory modules from a host device as a write data stream and transmit data read from the memory modules to the host device as a read data stream, a second unit having a plurality of subunits, each of which is configured to write data in one of the memory modules corresponding to the subunit and read data from one of the memory modules corresponding to the subunit, and a data stream converter configured to parallelize the write data stream into a plurality of data blocks each of which is to be stored in one of the memory modules and to serialize a plurality of data blocks read from the memory modules into the read data stream. | 01-22-2015 |
20150026510 | DYNAMIC BUFFER SIZE SWITCHING FOR BURST ERRORS ENCOUNTERED WHILE READING A MAGNETIC TAPE - In one embodiment, a system for dynamically allocating a ring buffer includes a processor and logic integrated with and/or executable by the processor, the logic being configured to divide a ring buffer into a first portion and a second portion after detecting an error condition in data read from a data storage medium, wherein the first portion is allocated for processing normal read and/or write requests, and wherein the second portion is allocated for processing error recovery procedure (ERP) requests. In another embodiment, a method for dynamically allocating a ring buffer includes dividing a ring buffer into a first portion and a second portion after detecting an error condition in data read from a data storage medium, wherein the first portion is allocated for processing normal read and/or write requests, and wherein the second portion is allocated for processing ERP requests. | 01-22-2015 |
20150033064 | SELF-IDENTIFYING MEMORY ERRORS - A memory region can durably self-identify as being faulty when read. Information that would have been assigned to the faulty memory region can be assigned to another of that sized region in memory using a replacement encoding technique. For phase change memory, at least two fault states can be provided for durably self-identifying a faulty memory region; one state at a highest resistance range and the other state at a lowest resistance range. Replacement cells can be used to shift or assign data when a self-identifying memory fault is present. A memory controller and memory module, alone or in combination may manage replacement cell use and facilitate driving a newly discovered faulty cell to a fault state if the faulty cell is not already at the fault state. | 01-29-2015 |
20150033065 | SOLID STATE DRIVE EMERGENCY PRE-BOOT APPLICATION PROVIDING EXPANDED DATA RECOVERY FUNCTION - An apparatus includes a non-volatile memory and a controller. The non-volatile memory includes a user area and a non-user area. The user area is generally enabled to store and retrieve data in a logical block address space of a host. The non-user area stores a failure-specific recovery routine. The controller may be communicatively coupled to the non-volatile memory. The controller is generally enabled, when operationally coupled to the host, (i) to respond to host commands to read and to write data into the user area of the non-volatile memory and (ii) upon detection of a predefined failure of a controller boot process, to respond to host read requests by returning the failure-specific recovery routine stored in the non-user area of the non-volatile memory. | 01-29-2015 |
20150046747 | TORN WRITE MITIGATION - Torn write mitigation circuitry determines if a write operation to memory is in progress at or about a time of power loss. In response to the write operation being in progress at or about the time of the power loss, the torn write mitigation circuitry causes torn write data and metadata to be stored to a non-volatile cache. The torn write data comprise data left in a degraded or uncorrectable state as a result of the loss of power. The metadata describe the torn write data. | 02-12-2015 |
20150095692 | PROCESS CONTROL SYSTEMS AND METHODS - Process control system and methods are disclosed. An example method includes operating a first cluster including first virtual machines and first servers and operating a second cluster including second virtual machines and second servers. The example method also includes storing first data from the first virtual machines at a first data store of the first cluster and storing a replica of the first data at a second data store of the second cluster. The example method also includes storing second data from the second virtual machines at the second data store and storing a replica of the second data at the first data store and identifying a failure of the first cluster. The method also includes, in response to the failure, restarting the first virtual machines using the second servers and the replica of the first data at the second data store. | 04-02-2015 |
20150113318 | Systems and Methods for Soft Data Utilization in a Solid State Memory System - Systems and methods relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. | 04-23-2015 |
20150121127 | WATCHPOINT SUPPORT SYSTEM FOR FUNCTIONAL SIMULATOR - A functional simulator with watchpoint support includes a CPU having a first-level DMI cache, a watchpoint manager having a second-level DMI cache, an interconnect module, and a memory controller. The simulator is operated by a front-end tool. Watchpoints corresponding to a predetermined memory addresses are set by the front-end tool and stored as a watchpoint address list in the watchpoint manager. When a memory access request is received by the first-level DMI cache, after a failure to complete the memory access request, the CPU transmits the request to the watchpoint manager. The watchpoint manager searches for a memory address associated with the memory access request in the watchpoint address list. If a match is found, the watchpoint manager generates a watchpoint hit signal and notifies the front-end tool. | 04-30-2015 |
20150121128 | SYSTEMS AND METHODS FOR RETRIEVING DATA - Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as NAND flash. For example, disclosed techniques can be embodied in a device driver of an operating system. Errors are tracked during read operations. If sufficient errors are observed during read operations, the block is then retired when it is requested to be erased or a page of the block is to be written. One embodiment is a technique to recover data from uncorrectable errors. For example, a read mode can be changed to a more reliable read mode to attempt to recover data. One embodiment further returns data from the memory device regardless of whether the data was correctable by decoding of error correction code data or not. | 04-30-2015 |
20150149816 | MULTI-STAGE CODEWORD DETECTOR - A multi-stage codeword detector for detecting codewords from read signals received from a multi-level memory device, includes a first detection stage configured for a coarse detection of a first codeword from a received read signal; a second detection stage configured for a fine detection of a second codeword from the received read signal; and a deciding entity configured to decide on using the second detection stage for the received read signal in dependence on a reliability indicator indicating a certain reliability level of the received read signal. | 05-28-2015 |
20150149817 | MANAGING NON-VOLATILE MEDIA - Apparatuses, systems, and methods are disclosed to manage non-volatile media. A method includes determining a configuration parameter for a set of storage cells of a non-volatile recording medium. A method includes reading data from a set of storage cells using a determined configuration parameter. A method includes adjusting a configuration parameter based on read data. | 05-28-2015 |
20150293824 | PROCESSING A TARGET MEMORY - A method is suggested for processing a target memory, the method comprising the steps of (i) checking the target memory subsequent to an erase operation directed to the target memory; and (ii) replacing the target memory with a spare memory in case a defect is detected. | 10-15-2015 |
20150309900 | INFORMATION PROCESSING APPARATUS AND CONTROL METHOD OF INFORMATION PROCESSING APPARATUS - An information processing apparatus including a removable storage device for storing data includes a control unit that determines whether communication is possible with the storage device and, if communication with the storage device is determined not to be possible, prohibit data from being written to the storage device. When the information processing apparatus is started up, the control unit again determines whether communication is possible with the storage device to which the control unit prohibits data writing and permits data writing to the storage device if communication with the storage device is determined to be possible. | 10-29-2015 |
20150317198 | ONBOARD ELECTRONIC CONTROL UNIT - Provided is an onboard electronic control unit. A CPU regularly performs a memory check and, if a determination has been made that there is an error in the memory content, writes the number of times an error has been determined to an error count storage unit, and resets itself. Immediately after the CPU has been reset and before the first memory check is performed, an error determination unit determines whether or not the error count stored in the error count storage unit is at least an error determination threshold. If the error count is at least the error determination threshold, an error response unit causes the CPU to execute a specific error response program, out of the programs in the memory. | 11-05-2015 |
20150317201 | STORAGE DEVICE WITH ERROR RECOVERY INDICATION - Various embodiments are provided that enable a controller of a storage device having storage media to perform one or more error recovery operations on the storage media, and to convey, while performing the one or more error recovery operations, a message indicating a status of the one or more error recovery operations to a host processor in communication with the storage device. Storage devices implementing embodiments of the present invention include hard disk drives and solid state disk drives comprising a disk head having a magnetoresistive (MR) element configured to read and write data to and from the storage media, and coupled to an analog/digital (A/D) converter, and the error recovery operations are selected from a list of changing an automatic gain control of the A/D converter, positioning the disk head off-track in order to read the data, and adjusting a bias value of the MR element. | 11-05-2015 |
20150324264 | USING SPARE CAPACITY IN SOLID STATE DRIVES - An SSD has a plurality of dies, with each die having a storage capacity. The storage capacity of each die is divided into a primary capacity and a spare capacity. A primary die has a maximum primary capacity, and a sum of the spare capacities of the remaining dies is greater than the maximum primary capacity. Data stored on the SSD is distributed among the primary capacities of the dies. When a failure of a first die is detected, data stored on the failed first die is migrated to the spare capacity of at least one of the remaining dies. | 11-12-2015 |
20150324282 | SOLID-STATE MEMORY CORRUPTION MITIGATION - Systems and methods are disclosed for programming data in a non-volatile memory array are disclosed. Certain embodiments provide a non-volatile solid-state memory array and a controller configured to receive write data from a host device, program the write data to a first block of the memory array in a lower-page-only (LPO) programming mode, and perform a data consolidation operation on the first block, wherein said performing garbage collection comprises programming at least a portion of the write data to a second block not in LPO programming mode. | 11-12-2015 |
20150339201 | MICROCONTROLLER AND ELECTRONIC CONTROL DEVICE USING THE SAME - The present invention provides a microcontroller which can continue operation even at the time of a failure without making a memory redundant to suppress increase in chip area. The microcontroller includes three or more processors executing the same process in parallel and a storage device. The storage device includes a memory mat having a storage region which is not redundant, an address selection part, a data output part, and a failure recovery part. The address selection part selects a storage region in the memory mat on the basis of three or more addresses issued at the time of an access by the processors. The data output part reads data from the storage region in the memory mat selected by the address selection part. The failure recovery part corrects or masks a failure of predetermined number or less which occurs in the memory mat, the address selection part, and the data output part. | 11-26-2015 |
20150347247 | READ/WRITE CACHE DEVICE AND METHOD PERSISTENT IN THE EVENT OF A POWER FAILURE - A read/write cache device and method persistent in the event of a power failure are disclosed herein. The read/write cache device includes a meta-information part, a recency/frequency (RF) table part, a mapping table part, and a log area. The meta-information part provides information about whether metadata has integrity and information about the version of metadata stored in two metadata regions. The RF table part provides information about the recency and frequency of each of low-speed segments of a plurality of high-speed and low-speed segments and information about whether each of the low-speed segments is cached, in order to maintain the consistency of the metadata. The mapping table part provides information about a low-speed segment that is cached to each of the high-speed segments. The log area provides changed caching information that is not applied into the mapping table part. | 12-03-2015 |
20150355985 | RECOVERY CONSUMER FRAMEWORK - A recovery consumer framework provides for execution of recovery actions by one or more recovery consumers to enable efficient recovery of information (e.g., data and metadata) in a storage system after a failure event (e.g., a power failure). The recovery consumer framework permits concurrent execution of recovery actions so as to reduce recovery time (i.e., duration) for the storage system. The recovery consumer framework may coordinate (e.g., notify) the recovery consumers to serialize execution of the recovery actions by those recovery consumers having a dependency while allowing concurrent execution between recovery consumers having no dependency relationship. Each recovery consumer may register with the framework to associate a dependency on one or more of the other recovery consumers. The dependency association may be represented as a directed graph where each vertex of the graph represents a recovery consumer and each directed edge of the graph represents a dependency. The framework may traverse (i.e., walk) the framework graph and for each vertex encountered, notify the associated recovery consumer to initiate its respective recovery actions. | 12-10-2015 |
20150355986 | COOPERATIVE MEMORY ERROR DETECTION AND REPAIR - Some embodiments include apparatuses and methods having a memory structure included in a memory device and a control unit included in the memory device. The control unit can provide information obtained from the memory structure during a memory operation to a host device (e.g., a processor) in response to a command from the host device. If the control unit receives a notification from the host device indicating that the host device has detected an error in the information obtained from the memory structure, then a repair unit included in the memory device performs a memory repair operation to repair a portion in the memory structure. | 12-10-2015 |
20150363257 | RESISTIVE MEMORY DEVICE AND OPERATING METHOD - Provided are a resistive memory device and an operating method for the resistive memory device. The operating method includes detecting a write cycle, determining whether or not to perform a recovery operation by comparing the detected write cycle with a first reference value, and upon determining to perform the recovery operation, performing the recovery operation on target memory cells of the memory cell array. | 12-17-2015 |
20150363264 | CELL-TO-CELL PROGRAM INTERFERENCE AWARE DATA RECOVERY WHEN ECC FAILS WITH AN OPTIMUM READ REFERENCE VOLTAGE - An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory may comprise a plurality of memory modules each having a size less than a total size of the memory. The controller may be configured to recover data stored in the memory determined to exceed a maximum number of errors after performing a first read operation using a first read reference voltage. The controller may perform a second read operation using a second read reference voltage. The controller may identify a victim cell having a threshold voltage in a region between the first read reference voltage and the second read reference voltage. The controller may perform a third read operation on aggressor cells of the victim cell. The controller may perform a fourth read operation using the first read reference voltage with bit-fixed values on the victim cell based on a type of interference from the aggressor cells. | 12-17-2015 |
20160004587 | METHOD, APPARATUS AND SYSTEM FOR HANDLING DATA ERROR EVENTS WITH A MEMORY CONTROLLER - Techniques and mechanisms for providing error detection and correction for a platform comprising a memory including one or more spare memory segments. In an embodiment, a memory controller performs first scrubbing operations including detection for errors in a plurality of currently active memory segments. Additional patrol scrubbing is performed for one or more memory segments while the memory segments are each available for activation as a replacement memory segment. In another embodiment, a first handler process (but not a second handler process) is signaled if an uncorrectable error event is detected based on the active segment scrubbing, whereas the second handler process (but not the first handler process) is signaled if an uncorrectable error event is detected based on the spare segment scrubbing. Of the first handler process and the second handler process, only signaling of the first handler process results in a crash event of the platform. | 01-07-2016 |
20160034226 | DATA STORAGE DEVICE, METHOD OF STORING DATA, AND ON-VEHICLE CONTROL APPARATUS - A memory having a plurality of storage blocks, and a memory control unit, are included, and each of the storage blocks is partitioned into a management data area and an actual data area. The management data area stores therein writing-in-progress management data indicating that writing of actual data has started, validity management data indicating that the writing of the actual data has been completed, and pre-erasure management data indicating that stored actual data have been brought into an erasable state. The memory control unit determines, based on a storage state of the management data, the storage block storing therein the latest data. | 02-04-2016 |
20160055051 | MANAGING STORAGE PROTECTION FAULTS - Management of storage used by pageable guests of a computing environment is facilitated. A query instruction is provided that details information regarding the storage location indicated in the query. It specifies whether the storage location, if protected, is protected by host-level protection or guest-level protection. | 02-25-2016 |
20160062819 | METHOD FOR REPAIRING DEFECTIVE MEMORY CELLS IN SEMICONDUCTOR MEMORY DEVICE - Provided is a method for repairing one or more defective memory cells of a semiconductor memory device by a system management interrupt and a basic input/output system service routine. In the method, when an error has occurred in data read from the semiconductor memory device, the system management interrupt is generated to invoke the basic input/output system service routine. During execution of the basic input/output system service routine, a repair task is performed to one or more defective memory cells causing a read error in the semiconductor memory device using spare memory cells. | 03-03-2016 |
20160085613 | METHOD TO REDUCE READ ERROR RATE FOR SEMICONDUCTOR RESISTIVE MEMORY - A method for operating a memory device includes performing a single read operation that includes additional one or more combinations of read and/or write cycles, and performing a single write operation that includes additional one or more combinations of read and/or write cycles. For example, a method for auto-correcting errors in a memory device having plurality of memory cells includes performing a first read operation of the memory cell to obtain a first read data value, performing a first write operation to the memory cell to write a second data value, which is a complement of the first data value, into the memory cell, performing a second read operation of the memory cell to obtain a third data value, and performing a second write operation to the memory cell to write a fourth data value, which is a complement of the third data value, to the memory cell. | 03-24-2016 |
20160103730 | NON-VOLATILE MEMORY DEVICES AND CONTROLLERS - For single-level cell flash memories and multi-level cell flash memories, different operations can be performed according to their stability when an abnormal status is terminated. Specifically, for the multi-level cell flash memories, when the abnormal status is terminated, a now physical block is used to proceed with write operation, and the previous physical block(s) would not be written any more. On the contrary, for the single-level cell flash memories, when the abnormal status is terminated, the controller needs to perform corresponding operations on the last physical page of the previous physical block(s). | 04-14-2016 |
20160103733 | REDUCING ERROR CORRECTION LATENCY IN A DATA STORAGE SYSTEM HAVING LOSSY STORAGE MEDIA - In at least one embodiment, a read operation in a data storage system having lossy storage media includes fetching target data of the read operation from a lossy storage device into a buffer, transferring the target data from the buffer to an external controller external to the lossy storage device via a communication bus, performing error location processing on the target data during the transferring of the target data, communicating error location information regarding at least one error location to error repair logic via the communication bus, the error repair logic repairing the at least one error in the target data using the error location information, and the external controller causing the target data as repaired to be transmitted toward a destination. By deserializing the suboperations comprising the read operation, read latency can be reduced. | 04-14-2016 |
20160117216 | TEMPERATURE RELATED ERROR MANAGEMENT - Apparatuses and methods for temperature related error management are described. One or more apparatuses for temperature related error management can include an array of memory cells and a write temperature indicator appended to at least one predetermined number of bytes of the stored data in the array of memory cells. The apparatuses can include a controller configured to determine a numerical temperature difference between the write temperature indicator and a read temperature indicator and determine, from stored operations, an error management operation for the stored data based, at least in part, on comparison of the numerical temperature difference to a temperature difference threshold. | 04-28-2016 |
20160124804 | NONVOLATILE MEMORY SYSTEM AND DATA RECOVERY METHOD THEREOF - A nonvolatile memory system includes a nonvolatile memory device including a distribution table suitable for storing recovery read level intervals that are set by being changed through multiple stages according to a distribution value of threshold voltage levels of a plurality of memory cells, measured at a reference read level, is changed through the multiple stages; and a memory controller suitable for reading measurement data from the memory cells by additionally using a measurement read level, searching for a difference value between the normal data and the measurement data from the multiple stages of distribution values stored in the distribution table, and recovering the normal data based on a recovery read level interval corresponding to a searched distribution value, when an error occurs in normal data read from the memory cells by using the reference read level. | 05-05-2016 |
20160124805 | NONVOLATILE MEMORY SYSTEM AND DATA RECOVERY METHOD THEREOF - A nonvolatile memory system includes a nonvolatile memory device including a plurality of memory cells; and a memory controller suitable for recovering normal data based on a recovery read level interval when an error occurs in the normal data read from the memory cells by using a reference read level, wherein the memory controller generates N distribution measurement values by measuring distribution values of threshold voltage levels of the memory cells at N respective distribution read levels, which have a preset read level interval with the reference read level serving as a center, and determines the recovery read level interval through calculating variations of the N distribution measurement values by using a linear equation, where ‘N’ is a natural number equal to or larger than 2. | 05-05-2016 |
20160132384 | DATA READING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT - A data reading method, a memory storage device and a memory controlling circuit unit are provided. The method includes: receiving a first read command; setting a plurality of first read events in a multi trigger queue (MTQ) according to the first read command, wherein the first read events include a general read event and at least one cache read event; sending a first read command sequence according to at least one of the first read events and receiving first data from a rewritable non-volatile memory module; and if a decoding for the first data fails, resetting the MTQ, and sending at least one second read command sequence according to at least one second read event in the reset MTQ, wherein the at least one second read event includes at least one of the at least one cache reading event. | 05-12-2016 |
20160132410 | KERNEL STATE AND USER STATE DATA EXCHANGE METHOD FOR DISASTER RECOVERY OF VIRTUAL CONTAINER SYSTEM - The present invention relates to a kernel state and user state data exchange method for disaster recovery of a virtual container system. In one disaster recovery backup of a virtual container, data needs to be exchanged between a kernel state and a user state. The file system operation of the kernel state needs to be transmitted to a user state program for processing firstly, and the processing result is returned to the kernel state and then transmitted to an original application program. Low recovery speed of a data block is mainly caused by the need of multiple times of switching between the kernel state and the user state, and the communication efficiency of the kernel state and the user state is low. In the present invention, all recovery operations are completed by the user state by virtue of a FUSE. A FUSE file system is realized firstly, one of files therein is mapped to the /DEV/LOOP device, then the LOOP device is used as a shadow device of a disk to be recovered, and a virtual container manager enables a virtual container with the LOOP device. The access to the original hard disk is intercepted in the FUSE file system, and then the FUSE file system communicates with the server, so that efficient on-demand recovery of data is realized. | 05-12-2016 |
20160132412 | PERFORMANCE OPTIMIZATION OF READ FUNCTIONS IN A MEMORY SYSTEM - According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that minors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table. | 05-12-2016 |
20160139837 | ERROR RECOVERY IN A DATA PROCESSING SYSTEM WHICH IMPLEMENTS PARTIAL WRITES - A data processing system includes a command buffer and control circuitry. The command buffer is configured to store pending write requests to a memory in which each pending write request has corresponding write data. The control circuitry is configured to select a pending write request from an entry of the command buffer and send the selected write request to the memory. The selected write request is a partial write request having first write data stored in the entry. Sending the selected write request includes performing a read-modify-write (RMW), wherein the control circuitry is configured to, after a read operation of the RMW, update the pending write request in the entry from a partial write request to a full write request. | 05-19-2016 |
20160179608 | REMOVING READ DISTURB SIGNATURES FOR MEMORY ANALYTICS | 06-23-2016 |
20160179632 | MEMORY FAULT SUPPRESSION VIA RE-EXECUTION AND HARDWARE FSM | 06-23-2016 |
20160188402 | PROCESSING DEVICE WITH SELF-SCRUBBING LOGIC - An apparatus includes a processing unit including a configuration memory and self-scrubber logic coupled to read the configuration memory to detect compromised data stored in the configuration memory. The apparatus also includes a watchdog unit external to the processing unit and coupled to the self-scrubber logic to detect a failure in the self-scrubber logic. The watchdog unit is coupled to the processing unit to selectively reset the processing unit in response to detecting the failure in the self-scrubber logic. The apparatus also includes an external memory external to the processing unit and coupled to send configuration data to the configuration memory in response to a data feed signal outputted by the self-scrubber logic. | 06-30-2016 |
20220137836 | STORAGE DEVICE AND METHOD OF OPERATING THE SAME - The present technology relates to an electronic device. The storage device according to the present technology may include a memory device and a memory controller. The memory device may include a plurality of memory blocks. The memory controller may control the memory device to perform a recovery operation for a first sudden power off on a target block on which a program operation is stopped due to the first sudden power off among the plurality of memory blocks, and perform a program operation of storing lock data including information indicating completion of the recovery operation for the first sudden power off in a page next to a page on which the recovery operation is completed in the target block. | 05-05-2022 |