| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 714400500 | Bus network (e.g., PCI, AGP, etc.) | 24 |
| 20110093739 | FAULT MANAGEMENT FOR A COMMUNICATION BUS - A differential communication bus comprising a master module and a plurality of slave modules connected to at least first and second conductors whereby to communicate between the master and slave modules. The master module comprises a driver for applying first and second voltages respectively to the first and second conductors and for sourcing and sinking currents in the first and second conductors. The driver controls a difference between the first and second voltages and a common mode value of the first and second voltages. The driver includes first sourcing and sinking current limiters and second sourcing and sinking current limiters for limiting the currents in the first and second conductors. The master module is selectively responsive to a fault condition triggering simultaneous activation of the first and second sourcing current limiters or of the first and second sinking current limiters to disable the driver. | 04-21-2011 |
| 20110145629 | FLEXIBLE BUS ARCHITECTURE FOR MONITORING AND CONTROL OF BATTERY PACK - The present invention provides a control system which is used for a stacked battery of a plurality of battery packs. Each battery pack has a plurality of battery cells coupled in series. The control system is capable of reconfiguring communication among the battery packs in the stacked battery, and comprises a plurality of processors, a plurality of controllers, and a monitoring unit. The processors are coupled to the battery packs. Two adjacent processors among the processors are able to communicate with each other though a first bus. The controllers are coupled to the battery packs. Two adjacent controllers among the controllers are able to communicate with each other through a second bus. The processors are capable of communicating with the controllers through a third bus. The monitoring unit is used for monitoring communications among the plurality of processors and communications among the plurality of controllers. The monitoring unit is capable of detecting communication problems on the first bus and/or the second bus. The monitoring unit further is capable of reconfiguring communication paths among the plurality of processors and communication path among the plurality of controllers. | 06-16-2011 |
| 20110252272 | FALLOVER POLICY MANAGEMENT IN HIGH AVAILABILITY SYSTEMS - The method determines whether a particular node of a high availability cluster is functioning properly or is a failed node. The method dumps node process state information as a dump data for the failed or crashed node in a shared storage area of the high availability cluster. A high availability cluster manager identifies the dump data that corresponds to the failed node as the most recent dump data for that failed node. The high availability cluster manager interrogates the dump data using kernel debugger services to identify a process trace and thereby identify the crash-causing application for the failed node. The method determines if the dump data includes a process match for the failed node process. The high availability cluster manager may initiate a crash-causing application notification to administrators or other entities of the high availability cluster. The method provides relocation and restoration capability of applications from the failed node to a fallover node and returns those application resources to the user and other entities using the high availability cluster. | 10-13-2011 |
| 20120036390 | REDUNDANCY CONFIGURATION OF MAIN UNIT - A single main unit manages information on hardware resources and the like of all main units connected to a network in an integrated fashion. A slot management module, a slot control module, and a physical slot/managed slot comparison table are provided between an input/output control module and a slot interface subordinate thereto. The input/output control module accesses the slot interface by using virtual slot identification information. The slot management module refers to the physical slot/managed slot comparison table, converts the virtual slot identification information into physical slot identification information, and accesses a slot control module corresponding to the physical slot identification information obtained by the conversion, thereby realizing a physical access of the input/output control module to the slot interface. | 02-09-2012 |
| 20120144230 | CABLE REDUNDANCY AND FAILOVER FOR MULTI-LANE PCI EXPRESS IO INTERCONNECTIONS - Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting a failure in the first link, at a PCIE bridge end, the first set of lanes is swapped with a second set of lanes of the first PCIE bridge for exchanging a second set of bussed bits between the first PCIE bridge and the first IO device over a second link using the second set of lanes, the second link connecting a second PCIE bridge with a second IO device. In response to detecting the failure in the first link, at an IO device end, the first set of lanes is switched with the second set of lanes for exchanging the second set of bussed bits between the first PCIE bridge and the first IO device over the second link using the second set of lanes | 06-07-2012 |
| 20120144231 | ARRANGEMENTS DETECTING RESET PCI EXPRESS BUS IN PCI EXPRESS PATH, AND DISABLING USE OF PCI EXPRESS DEVICE - A root port connection functioning as a PCI express bridge, and having a PCI express path constituting a PCI express tree having a PCI express device or switch; when detecting a failure on a PCI express path, a PCI express device or switch transmits a failure signal; the root port transmits an SMI responsive to the failure signal; the CPU executes the BIOS responsive to the SMI; the BIOS collects a log of the PCI express path where failure is detected, analyzes the collected log to judge failure type, and upon a fatal failure on the PCI express path, resets the PCI express tree downstream of the root port that received the failure signal, and upon a non-fatal failure on the PCI express path, resets the PCI express device in which the failure occurred; and the CPU closes the reset PCI express device by executing the device driver. | 06-07-2012 |
| 20120151247 | Dynamic Fault Detection and Repair in a Data Communications Mechanism - A communications link of multiple parallel communications lines includes at least one redundant line. In a first aspect, the lines are periodically recalibrated one at a time while the others carry functional data. If a fault is detected, the faulty line is disabled and the remaining previously calibrated lines transmit functional data. In a second aspect, impending line malfunction is detected from anomalies during calibration. In a third aspect, line malfunction is detected from receiver circuit output by determining a logical lane upon which each detected error occurs, and by mapping the logical lane to a physical line currently carrying the logical lane data. | 06-14-2012 |
| 20120233495 | CONTROL DEVICE, INPUT/OUTPUT DEVICE, CONNECTION SWITCH DEVICE AND METHOD FOR AN AIRCRAFT CONTROL SYSTEM - Methods and apparatus are described for an aircraft network that permits an automatic configuring and/or repairing of the network. | 09-13-2012 |
| 20120246510 | INFORMATION PROCESSING APPARATUS, CONTROL DEVICE, AND ABNORMAL UNIT DETERMINATION METHOD - An information processing apparatus determines an abnormal unit by: determining whether or not there is an abnormal point in access to a slave unit by a first master unit that controls a plurality of slave units connected by a serial bus; requesting a second master unit having redundancy with the first master unit to access a specific slave unit when the abnormal point is determined to exist in access to the specific slave unit in the determining; and determining a unit having an abnormality by use of an access result relating to the abnormal point determined to have an abnormality in the determining and an access result indicating a result of the request made in the requesting. | 09-27-2012 |
| 20130080825 | CABLE REDUNDANCY AND FAILOVER FOR MULTI-LANE PCI EXPRESS IO INTERCONNECTIONS - Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting a failure in the first link, at a PCIE bridge end, the first set of lanes is swapped with a second set of lanes of the first PCIE bridge for exchanging a second set of bussed bits between the first PCIE bridge and the first IO device over a second link using the second set of lanes, the second link connecting a second PCIE bridge with a second IO device. In response to detecting the failure in the first link, at an IO device end, the first set of lanes is switched with the second set of lanes for exchanging the second set of bussed bits between the first PCIE bridge and the first IO device over the second link using the second set of lanes. | 03-28-2013 |
| 20130159761 | Parallel Data Communications Mechanism Having Reduced Power Continuously Calibrated Lines - A communications link includes multiple continuously calibrated parallel lines, wherein one or more lines are at least partially powered down while being continuously calibrated to reduce power consumption. In one aspect, at least N+1 lines (where N is the logical bus width) are periodically recalibrated, and at least one redundant line is powered down between calibrations. The redundant line could be either a true spare available for use as a replacement, or an extra line which carries functional data while other lines are being calibrated in turn. In another aspect, the logical bus width is variable, but does not exceed N | 06-20-2013 |
| 20130179722 | RING TOPOLOGY FOR COMPUTE DEVICES - Devices, systems and methods for providing a ring topology for physically connecting compute devices having PCIe bridges are disclosed. Each device, having an internal PCIe bus or other similar standard that natively support a tree structure, is connected in a ring to neighboring compute devices. Two physical links connecting each device to the ring are provided, enabling each device to communicate with all of the other devices on the ring, without requiring a server or main host to enumerate or control the flow of information between devices. If a failure occurs in the physical connection at any single point in the ring, there is still an alternate path to communicate with every device. Methods for performing data transfer between PCIe compute devices connected to the ring are also disclosed. | 07-11-2013 |
| 20130227338 | RECONFIGURING INTERRELATIONSHIPS BETWEEN COMPONENTS OF VIRTUAL COMPUTING NETWORKS - Embodiments of the present invention relate to an approach for reconfiguring interrelationships between components of virtual computing networks (e.g., a grid computing network, a local area network (LAN), a cloud computing network, etc.). In a typical embodiment, a set of information pertaining to a set of components associated with a virtual computing network is received in a computer memory medium or the like. Based on the set of information, a graphical representation (e.g., hierarchical tree) depicting the set of interrelationships between the set of components is generated. When a failure in the virtual computing network is detected, at least one of the set of interrelationships between the set of components is reconfigured based on the graphical representation and the set of rules to address the failure. | 08-29-2013 |
| 20130232376 | Managing A Storage Device Using A Hybrid Controller - Methods, apparatuses, and computer program products for managing a storage device using a hybrid controller are provided where the storage device comprises an internal peripheral component interconnect express (PCIe) interface to control solid state memory within the storage device. In particular embodiments, the storage device includes a first external interface configured to establish an external PCIe link and a second external interface configured to establish at least one of an external serial attached small computer system interface (SAS) link and an external serial advanced technology attachment (SATA) link. Embodiments include receiving from an external source, by the hybrid controller, a first command at the first external interface and a second command at the second external interface; and concurrently implementing, by the hybrid controller, the first command using a PCIe protocol and the second command using one of a SAS protocol and a SATA protocol. | 09-05-2013 |
| 20140281668 | ADAPTIVE CONTROL LOOP PROTECTION FOR FAST AND ROBUST RECOVERY FROM LOW-POWER STATES IN HIGH SPEED SERIAL I/O APPLICATIONS - Methods and apparatus related to adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applications are described. In some embodiments, a first bit pattern is detected, at a first agent, that indicates a speculative entry by a second agent into a low power consumption state and one or more control loops are frozen. A second bit pattern is detected (after entering the low power consumption state) that indicates exit from the low power consumption state by the second agent and the one or more control loops are unfrozen (e.g., in a specific order). Other embodiments are also claimed and/or disclosed. | 09-18-2014 |
| 20140298079 | Localized Fast Bulk Storage in a Multi-Node Computer System - A high performance computing (HPC) system includes computing blades having a first region that includes computing circuit boards having processors for performing a computation, and a second region that includes non-volatile memory for use in performing the computation. The regions are connected by a plurality of power connectors that convey power from the computing circuit boards to the memory, and a plurality of data connectors that convey data between the first and second regions. The power and data connectors are configured redundantly so that failure of a computing circuit board, a power connector, or a data connector does not interrupt the computation. A method of performing such a computation, and a computer program product implementing the method, are also disclosed. | 10-02-2014 |
| 20140372789 | IMPLEMENTING ENHANCED ERROR HANDLING OF A SHARED ADAPTER IN A VIRTUALIZED SYSTEM - A method, system and computer program product are provided for implementing enhanced error handling for a hardware I/O adapter, such as a Single Root Input/Output Virtualization (SRIOV) adapter, in a virtualized system. The hardware I/O adapter is partitioned into multiple endpoints, with each Partitionable Endpoint (PE) corresponding to a function, and there is an adapter PE associated with the entire adapter. The endpoints are managed both independently for actions limited in scope to a single function, and as a group for actions with the scope of the adapter. An error or failure of the adapter PE freezes the adapter PE and propagates to the VF PEs associated with the adapter, causing the VF PEs to be frozen. An adapter driver and VF device drivers are informed of the error, and start recovery. The hypervisor locks out the VF device drivers at key points enabling adapter recovery to successfully complete. | 12-18-2014 |
| 20150058658 | STORAGE APPARATUS AND METHOD FOR CONTROLLING STORAGE APPARATUS - Provided is a storage apparatus and a method for controlling the storage apparatus which are capable of achieving both enhancement of data transfer processing efficiency and enhancement of apparatus availability. A storage apparatus including a storage medium for providing an external apparatus with a data storage area has a processing unit including a plurality of processors and a shared memory for storing programs executed by the processors and is configured such that the processors receive data I/O requests and store the data I/O requests in the shared memory as storage medium control information for the storage medium. The storage medium controller executes data processing of writing or reading target data for the corresponding data I/O processing request to or from the storage medium on the basis of the storage medium control information transmitted from the external apparatus. The data transfer controller executes data transfer processing between the processing unit and the storage medium controller in accordance with a predetermined communication method. When the storage medium controller transmits a data transfer request to the data transfer controller and the data transfer controller transfers the data transfer request from the storage medium controller to the processing unit, the data transfer controller sends the storage medium controller data including predetermined error information stipulated for the communication method when determining that the processing unit does not execute the data transfer processing normally, and the storage medium controller determines that a failure has occurred to the processor which is the target of the data transfer request transmitted to the data transfer controller when receiving the predetermined error information. | 02-26-2015 |
| 20150089273 | COMPUTER SYSTEM, CONTROL METHOD FOR COMPUTER SYSTEM AND COUPLING MODULE - A control method comprising: a first step of detecting, by the server module, a failure in the first interface; a second step of executing, by the server module, given recovery processing when a failure is detected in the first interface; a third step of using, by the coupling module, the first end point to detect a failure in the first interface and output a failure notification; a fourth step of converting, by the coupling module, the failure notification into a notification of disconnection of the first interface, and transmitting the disconnection notification generated by the conversion to the storage module from the second end point; and a fifth step of disengaging, by the storage module, coupling to the server module when the disconnection notification is received from the coupling module. | 03-26-2015 |
| 20150127969 | SELECTIVELY COUPLING A PCI HOST BRIDGE TO MULTIPLE PCI COMMUNICATION PATHS - Instead of disabling PCI communication between system resources in a host computing device and I/O devices when a PCI Host Bridge (PHB) is reset, the host computing device may include a PCI communication path for maintaining communication between the system resources and the I/O devices. In one embodiment, the redundant PCI communication path includes a second PHB that is maintained in a standby state. The host may monitor the errors generated by a plurality of master PHBs and select a master PHB that satisfies an error threshold. The second PHB (i.e., a servant PHB) and the selected master PHB are synchronized, and the second PHB is coupled to the PCI communication path between the master PHB and a PCI switch. The master PHB can then be reset while the second PHB maintains PCI communication between the host and the I/O devices. | 05-07-2015 |
| 20150309892 | INTERCONNECT PATH FAILOVER - One or more techniques and/or systems are provided for interconnect failover between a primary storage controller and a secondary storage controller. The secondary storage controller may be configured as a backup or failover storage controller for the primary storage controller in the event the primary storage controller fails. Data and/or metadata describing the data (e.g., data and/or metadata stored within a write cache) may be mirrored from the primary storage controller to the secondary storage controller over one or more interconnect paths. Responsive to identifying a failover trigger for a failed interconnect path, the secondary storage controller is instructed to fence (e.g., block) I/O operations from the failed interconnect path. Streams of data and/or metadata that were affected by the failure may be instructed to transmit such data and/or metadata over one or more non-failed interconnect paths to the secondary storage controller during failover of the failed interconnect path. | 10-29-2015 |
| 20160034365 | INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING APPARATUS, REDUNDANCY PROVIDING METHOD, AND PROGRAM - In an information processing system including I/O cards provided with redundancy, the disclosed system and method realize a fail-over that enables improvement of the availability of the information processing apparatus. An information processing system constituting the information processing apparatus includes first and second I/O cards; a BIOS that performs a detection of a correctable failure of the first I/O card; a predictive monitoring unit that performs a predictive detection of a sign of an occurrence of a hardware failure of the first I/O card when a result of the detection of the correctable failure indicates an occurrence of the correctable failure; and an OS that disconnects the first I/O card and performs switching from the first I/O card to the second I/O card when a result of the predictive detection indicates an existence of the sign of the occurrence of the hardware failure of the first I/O card. | 02-04-2016 |
| 20160077934 | MANAGING VIOS FAILOVER IN A SINGLE STORAGE ADAPTER ENVIRONMENT - According to one exemplary embodiment, a method for VIOS failover in an environment with a physical storage adapter is provided. The method may include assigning the physical storage adapter to a first VIOS, wherein the physical storage adapter has I/O connectivity to at least one storage device. The method may include configuring a first I/O path between the first VIOS and a second VIOS. The method may include configuring a second I/O path from a client partition to the first VIOS, wherein the second I/O path is set as a primary I/O path. The method may include configuring a third I/O path from the client partition to the second VIOS. The method may include determining the first VIOS is inaccessible. The method may include unassigning the physical storage adapter from the first VIOS. The method may include assigning the physical storage adapter to the second VIOS. | 03-17-2016 |
| 20220138059 | STORAGE SYSTEM AND OPERATING METHOD THEREOF - A storage system includes a host including a host queue storing a plurality of commands and a storage device including a storage queue exchanging commands with the host through a first port or a second port, and storing the exchanged commands, wherein the storage device is configured to, when a communication error has occurred through the first port, transfer information about a command stored in the storage queue before the error occurrence to the host through the second port. | 05-05-2022 |
