| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 716020000 | Mesh generation | 21 |
| 20080209386 | METHOD FOR PREDICTING RESIST PATTERN SHAPE, COMPUTER READABLE MEDIUM STORING PROGRAM FOR PREDICTING RESIST PATTERN SHAPE, AND COMPUTER FOR PREDICTING RESIST PATTERN SHAPE - The contour shape of an aerial image formed on a resist by projecting a test pattern onto the resist via a projection optical system is computed. The shape of a resist pattern formed by the exposure using the test pattern and the development process is measured. A correction model indicating the relationship between the amount of characteristic of the contour shape and the amount of correction determined in accordance with the difference between the computed contour shape and the measured shape of the resist pattern is created. The contour shape of an aerial image formed on a resist by projecting an arbitrary pattern onto the resist via the projection optical system is computed. The shape of a resist pattern corresponding to the arbitrary pattern is predicted by correcting the computed contour shape of the aerial image, using the amount of correction given by the correction model in correspondence with the amount of characteristic of the contour shape. | 08-28-2008 |
| 20080244504 | Method and apparatus for determining mask layouts for a multiple patterning process - One embodiment provides a method for determining mask layouts. During operation, the system can receive a design intent. Next, the system can determine a set of critical edges in the design layout, and select a first edge and a second edge. The system can then determine a first trench and a second trench using the first edge and the second edge, respectively. Note that an edge of the first trench may substantially overlap with the first edge, and an edge of the second trench may substantially overlap with the second edge. Next, the system may assign the first trench and the second trench to the first mask layout and the second mask layout, respectively. The system can then increase the first trench and the second trench, thereby improving pattern fidelity. The resulting mask layouts may be used in a double patterning process. | 10-02-2008 |
| 20080276215 | Mask Pattern Designing Method Using Optical Proximity Correction in Optical Lithography, Designing Device, and Semiconductor Device Manufacturing Method Using the Same - A method for designing a mask pattern realizes shortening the ever-growing time for the OPC treatment, decreases the fabrication TAT of a semiconductor device and cuts cost. A method for fabricating a semiconductor device uses the mask pattern designed. This invention performs the OPC treatment in advance on a cell library constituting the basic configuration of a semiconductor circuit pattern and prepares a semiconductor chip using the cell library that has undergone the OPC treatment. The method for designing a mask pattern includes the steps of designing a cell library pattern by executing for each of the cell libraries a treatment for correcting proximity effect directed to correcting the change of shape taking place during the formation of a pattern by the exposure of a mask pattern, designing a mask pattern by laying out the cell libraries and changing the amount of correction of proximity effect applied to the cell libraries in consideration of the influence of the cell library patterns disposed peripherally. This treatment for correction is executed by the degree of influence exerted by surrounding patterns collected in advance and the genetic algorithm. | 11-06-2008 |
| 20080282218 | Method for Designing Mask - A method for designing a mask is disclosed. A chip region can be defined and reduced to form a parent dummy pattern. A mesh dummy pattern can be formed, and portions where the parent dummy pattern and the mesh dummy pattern overlap each other can be removed to form offspring dummy patterns. | 11-13-2008 |
| 20080320434 | PHOTOMASK MANAGEMENT METHOD AND PHOTOMASK WASH LIMIT GENERATING METHOD - A photomask is washed and at least one physical amount of transmittance and phase difference of the photomask, dimension of a pattern, height of the pattern and a sidewall shape of the pattern is measured. After this, the two-dimensional shape of a borderline pattern previously determined for the photomask is measured. Lithography tolerance is derived by performing a lithography simulation for the measured two-dimensional shape by use of the measured physical amount. Then, whether the photomask can be used or not is determined based on the derived lithography tolerance. | 12-25-2008 |
| 20090013304 | Physical-Resist Model Using Fast Sweeping - A method for determining a surface in a material is described. During this method, arrival times of a wavefront at a first depth in the material are calculated using an Eikonal equation. Note that the first depth is proximate to an outer surface of the material. Next, arrival times of the wavefront at a second depth in the material are calculated using the Eikonal equation and the calculated arrival times at the first depth. Then, the surface in the material is determined based on the calculated arrival times at the first depth, the calculated arrival times at the second depth, and a given time interval. Note that arrival times at a given depth in the material, which includes the first depth or the second depth, are calculated by directly determining a steady-state solution of the Eikonal equation. | 01-08-2009 |
| 20090037868 | AREA BASED OPTICAL PROXIMITY CORRECTION IN RASTER SCAN PRINTING - Methods and apparatus for correcting defects, such as rounded corners and line end shortening, in patterns formed via lithography are provided. Such defects are compensated for “post-rasterization” by manipulating the grayscale values of pixel maps. | 02-05-2009 |
| 20090044167 | PROCESS-MODEL GENERATION METHOD, COMPUTER PROGRAM PRODUCT, AND PATTERN CORRECTION METHOD - A process-model generation method according to an embodiment of the present invention comprises: forming a test pattern on a film to be processed by exposing a test mask having a mask pattern formed thereon; generating a plurality of process models having a different model parameter; performing a simulation of the mask pattern by using each of the process models to predict a plurality of model patterns; calculating a difference in dimension between the test pattern and each of the model patterns; extracting a model pattern in which the difference in dimension from the test pattern is within a scope of specification from the model patterns; and specifying the process model, which predicts the extracted model pattern, as the mask pattern. | 02-12-2009 |
| 20090070732 | Fracture Shot Count Reduction - Techniques are described for reducing the number of shots in a fractured layout design. Each polygon in a layout design is examined for “jogs.” For each identified jog, the surrounding region is examined to determine if there is an opposing jog or parallel edge that can be aligned with the identified jog. The surrounding region then is examined for any polygon features, such as edges or vertices, which might restrict or prevent the alignment of the identified jog with the opposing jog or edge. If the identified jog can be aligned with an opposing jog or edge without violating a specified alignment constraint, then those jogs are deemed an alignable jog pair. Next, one or more of the alignable jog pairs is selected for alignment. The alignable jog pairs may be selected for alignment based upon their impact on the size of the polygon when aligned. Once one or more of the alignable jog pairs have been selected, then the layout design data will be modified to align the selected jog pairs. | 03-12-2009 |
| 20090119635 | MASK PATTERN CORRECTION METHOD FOR MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Mask data is generated from a design layout by executing a mask data process including optical proximity correction. A pattern is formed on the major surface of a test semiconductor substrate by using a mask prepared from the mask data. The dimensional difference between the design layout and the pattern is measured. The design layout is corrected, at a portion with the dimensional difference of the design layout, by the magnitude of the dimensional difference in a direction in which the dimensions of the pattern equal those of the design layout, thereby generating a corrected design layout. Corrected mask data is generated from the corrected design layout by executing the mask data process including the optical proximity correction. A pattern is formed on the major surface of a semiconductor substrate by using a corrected mask prepared from the corrected mask data. | 05-07-2009 |
| 20090178018 | PRE-BIAS OPTICAL PROXIMITY CORRECTION - A pre-bias optical proximity correction (OPC) method allows faster convergence during OPC iterations, providing an initial set of conditions to edge fragments of a layout based on density conditions near the edge fragments. | 07-09-2009 |
| 20090193386 | SEMICONDUCTOR CELL FOR PHOTOMASK DATA VERIFICATION AND SEMICONDUCTOR CHIP - A semiconductor cell for photomask data verification is disclosed that is provided in a semiconductor chip having a semiconductor integrated circuit and used for verifying photomask data of the semiconductor chip obtained by performing arithmetic processing on layout data of the semiconductor integrated circuit. The semiconductor cell for photomask data verification has the photomask data obtained by performing the arithmetic processing on the layout data of the semiconductor integrated circuit and is electrically separated from the semiconductor integrated circuit. | 07-30-2009 |
| 20090199151 | ELECTRICALLY DRIVEN OPTICAL PROXIMITY CORRECTION - An approach that provides electrically driven optical proximity correction is described. In one embodiment, there is a method for performing an electrically driven optical proximity correction. In this embodiment, an integrated circuit mask layout representative of a plurality of layered shapes each defined by features and edges is received. A lithography simulation is run on the mask layout. An electrical characteristic is extracted from the output of the lithography simulation for each layer of the mask layout. A determination as to whether the extracted electrical characteristic is in conformance with a target electrical characteristic is made. Edges of the plurality of layered shapes in the mask layout are adjusted in response to determining that the extracted electrical characteristic for a layer in the mask layout fails to conform with the target electrical characteristic. | 08-06-2009 |
| 20090204936 | Method of Performing Proximity Correction - A method of performing proximity correction of a mask layout is used during the generation of a masking structure for performing a processing step. The masking structure includes at least one opening that is delimited by a sidewall and that exposes an area that is to be processed. The method includes the steps of a) determining a value representing a flux of particles to a target portion, wherein the target portion is at least one of the group of a portion of the sidewall and a portion of the uncovered area and wherein the particles are generated during the processing of the area; and b) determining a corrected mask layout dependent on the value determined in step a). | 08-13-2009 |
| 20100175041 | ADJUSTMENT OF MASK SHAPES FOR IMPROVING PRINTABILITY OF DENSE INTEGRATED CIRCUIT LAYOUT - Embodiments of the present invention provide a method for making mask shape adjustment The method includes creating a first mask shape; identifying one or more mask segments of the first mask shape as candidate mask segments of needing segment adjustment; applying an optical proximity correction (OPC) process to the first mask shape, the OPC process identifying at least one of the candidate mask segments as a constrained mask segment; applying a rotational adjustment to the constrained mask segment; and creating a second mask shape having the constrained mask segment being rotationally adjusted. A system and a machine-readable medium for performing the above method are also provided. | 07-08-2010 |
| 20100185999 | SHORT PATH CUSTOMIZED MASK CORRECTION - Embodiments of the present invention provide a method of performing photo-mask correction. The method includes identifying a hot-spot in a photo-mask that violates one or more predefined rules; creating a window area in the photo-mask that surrounds the hot spot; categorizing the window area; selecting a solution, from a library of pre-computed solutions, based on a category of the window area; and applying the solution to the hot spot. A service-oriented architecture (SOA) system that synchronizes the design to the process is also provided. | 07-22-2010 |
| 20100186000 | APPARATUS AND METHOD FOR SEGMENTING EDGES FOR OPTICAL PROXIMITY CORRECTION - An apparatus and method for modifying a mask data set includes calculating a derivative of a figure-of-merit, indicative of a data set defined by a plurality of polygon edges and then segmenting polygon edges in response to said step of calculating. | 07-22-2010 |
| 20100218160 | METHOD AND APPARATUS FOR DETERMINING A PROCESS MODEL THAT MODELS THE IMPACT OF A CAR/PEB ON THE RESIST PROFILE - An embodiment provides systems and techniques for determining a process model. During operation, the system may receive a first optical model which models a first optical system of a photolithography process. Next, the system may use the first optical model to determine a second optical model that models a second latent image that is formed by the first optical system at a second distance. The system may also use the first optical model to determine a third optical model that models a third latent image that is formed by the first optical system at a third distance. Next, the system may receive process data which is obtained by subjecting a test layout to the photolithography process. The system may then determine a process model using the first optical model, the second optical model, the third optical model, the test layout, and the process data. | 08-26-2010 |
| 20100251202 | Lithography Modelling And Applications - The manufacturing of integrated circuits relies on the use of lithography simulation to predict the image of the mask created on the wafer. Such predictions can be used for example to assess the quality of the images, verify the manufacturability of such images, perform using OPC necessary correction of the mask data to achieve images close to the targets, optimize the printing parameters such as the illumination source, or globally optimize the source and the mask to achieve better printability. This disclosure provides a technique based on the association of at least one kernel function per source region or source point. Each kernel function can be directly convoluted with a mask image to create a prediction of the wafer image. As the kernel functions are associated with the source, the source can be easily changed to create new models. The optical system can be fully described by computing the possible kernels for all possible source points and all possible numerical apertures. Therefore this technique is ideally suited for source-mask optimization as well as source-mask-numerical aperture optimization, and their associated applications. | 09-30-2010 |
| 20100269084 | Visibility and Transport Kernels for Variable Etch Bias Modeling of Optical Lithography - Kernels that model characteristics of the etching portion of an optical lithographic model are provided. In various implementations, a visibility density kernel is provided. The visibility density kernel approximates the area of the simulated substrate that is “visible” to the etchant. With various implementations, a transport kernel is provided. The transport kernel approximates the convective “movement” of etchant. | 10-21-2010 |
| 20100299646 | UNIFORMITY FOR SEMICONDUCTOR PATTERNING OPERATIONS - Systems and methods of semiconductor device optimization include a system and method to determine a dataset for a layer of the semiconductor device, where the operation includes receiving a dataset defining a plurality of original patterns of sacrificial material in a layer of a semiconductor device, wherein the original patterns of sacrificial material are used to define placement of spacer material to define patterning of circuit elements for the semiconductor device; determining densities of the plurality of original patterns of sacrificial material in areas across a portion of the layer of the semiconductor device; and augmenting the dataset to include an additional pattern of sacrificial material in an area of the layer having a density lower than a threshold density. | 11-25-2010 |
