Class / Patent application number | Description | Number of patent applications / Date published |
716018000 | Logical circuit synthesizer | 57 |
20080216042 | Method and Computer System for Otimizing the Signal Time Behavior of an Electronic Circuit Design - A method and program for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided. | 09-04-2008 |
20080216043 | Structure for Optimizing the Signal Time Behavior of an Electronic Circuit Design - A design structure for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit designed by an IC design house or other circuit design provider. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided. | 09-04-2008 |
20080216044 | METHOD, SYSTEM AND PROGRAM PRODUCT FOR SPECIFYING A CONFIGURATION FOR A DIGITAL SYSTEM UTILIZING DIAL BIASING WEIGHTS - In a method of data processing, a database defines a Dial entity and at least one instance of the Dial entity. Each instance of the Dial entity has an input having a plurality of different possible input values and one or more outputs, and each of the plurality of different possible input values has a different associated output value set for the one or more outputs. Each instance of the Dial entity determines a value of at least one of a plurality of configuration latches in a digital system separate from the database. The database also associates with the Dial entity at least one set of biasing weights that, when applied, determines a probability of each instance of the Dial entity having particular ones of the plurality of different possible input values. In response to a call to set the plurality of configuration latches, the database is accessed to apply the at least one set of biasing weights to select one of the plurality of different possible input values for the at least one instance of the Dial entity. The plurality of configuration latches in the digital system are set based upon the output value set for the one or more outputs of the at least one instance of the Dial entity. | 09-04-2008 |
20080222595 | METHOD OF ENGINEERING CHANGE TO SEMICONDUCTOR CIRCUIT EXECUTABLE IN COMPUTER SYSTEM - A method of engineering change to a semiconductor circuit includes: performing a first synthesis with optimization of a first HDL code to generate a first circuit; performing a first physical design of the first circuit to generate a post layout circuit; modifying the first HDL code to generate a second HDL code, and performing a second synthesis with optimization of the first and second HDL codes while forcibly preserving elements to generate a second circuit and a third circuit, respectively; performing an ECO cone-pair extraction operation of the second and third circuit to generate at least one ECO cone-pair; and obtaining an ECO logic and an element to be replaced according to the ECO cone-pair and the post layout circuit, and then replacing the element to be replaced in the post layout circuit with the ECO logic gate circuit, thereby modifying the post layout circuit into a post layout ECO circuit. | 09-11-2008 |
20080235648 | PROGRAM PRODUCT PROVIDING A CONFIGURATION SPECIFICATION LANGUAGE SUPPORTING ARBITRARY MAPPING FUNCTIONS FOR CONFIGURATION CONSTRUCTS - A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at least a portion of the digital design. In addition, a Dial is specified that defines a relationship between each of a plurality of input values and a respective one of a plurality of different output values. The HDL files also include a statement that instantiates an instance of the Dial in association with the configuration latch such that a one-to-one correspondence exists between a value contained within the configuration latch and an input value of the instance of the Dial. The HDL files further include a statement associating the Dial with a mapping function that applies a selected transformation to values read from or written to the instance of the Dial. | 09-25-2008 |
20080244501 | METHOD FOR READING INFORMATION FROM A HIERARCHICAL DESIGN - The present invention relates to a method for obtaining physical component information that is associated with hierarchical and non-hierarchical symbols as represented within a logical schematic diagram. The method comprises extracting logical design data of a hierarchical schematic from a primary software application, identifying a hierarchical symbol for analysis, and determining at least one physical component that is comprised within a schematic diagram that is represented by the identified hierarchical symbol. The method further comprises determining a schematic diagram page and path that is associated with the determined at least one physical component, determining schematic diagram children pages and paths that are associated with a common parent page and path of the at least one physical component, determining the schematic diagram parent page and path of the at least one physical component. | 10-02-2008 |
20080244502 | SYSTEM FOR AND METHOD OF SUPPORTING LOGIC DESIGN - A logic design support system which supports logic design using an HDL includes: RTL analysis means for receiving, as input, an RTL including a dedicated comment as a comment statement specifying expansion of a generate statement, detecting the dedicated comment from the input RTL, and retrieving a generate statement to be expanded; logic expansion means for expanding the generate statement retrieved by the RTL analysis means; and RTL output means for merging a portion not retrieved by the RTL analysis means from the input RTL with a portion expanded by the logic expansion means, and generating and outputting output RTL. | 10-02-2008 |
20080250379 | LOGIC CIRCUIT SYNTHESIS DEVICE - In a logic circuit synthesis device, a library of cell preliminarily stores a condition concerning a property that should be satisfied by the net having the property. The logic circuit synthesis device selects, from a list of nets, a net that has a predetermined property. the logic circuit synthesis device performs logic synthesis in accordance with the condition stored in the library, for the selected net. | 10-09-2008 |
20080250380 | Method of OPC Model Building, Information-Processing Apparatus, and Method of Determining Process Conditions of Semiconductor Device - A method capable of quantitatively evaluating two-dimensional patterns and a system to which the method is applied are provided. In the present invention, a reference coordinate system is set in order to convert pattern edge information (one-dimensional data) acquired by measurement using an existing critical dimension machine into coordinate data. Thus, a pattern is converted into coordinate information. Next, a function formula is determined from this coordinate information by approximate calculation and a pattern is represented by the mathematical expression y=f(x). Integrating y=f(x) in the reference coordinate used when calculating the coordinate data gives the area of the pattern, whereby it is possible to convert the coordinate data to two-dimensional data. | 10-09-2008 |
20080288911 | Method for localizing faulty hardware components and/or system errors within a production plant - There is described a method for localizing faulty hardware components and/or system errors within a production plant comprising several hardware components, with the production plant and the individual hardware components thereof being managed and/or configured by means of automation software and with the production plant being visualized and/or controlled by means of HMI software. Provision is made for identification data of the hardware components and/or groups of hardware components to be detected by the automation software and for information relating to the site to be assigned to the individual hardware components and/or groups of hardware components by means of the automation software and/or HMI software on the basis of identification data such that in the event of error messages as a result of faulty hardware components or in the event of system errors, a localization of the affected hardware component and/or group of hardware components is enabled within the production plant. | 11-20-2008 |
20080295058 | REPRESENTING BINARY CODE AS A CIRCUIT - A high level intermediate representation of a binary is generated. Circuit nodes from the high level intermediate representation are built, wherein a circuit node represents an operation in the high level intermediate representation. The circuit nodes are connecting using a flow analysis of the binary to build a circuit that represents the binary. | 11-27-2008 |
20090013301 | Hardware definition language generation for frame-based processing - A method generates hardware description language (HDL) code from a model having a plurality of components, including at least one component that processes frame-based input data. A selected preference is received for implementing the frame-based component. The generated HDL code includes a hardware implementation of the frame-based component that satisfies the selected preference. | 01-08-2009 |
20090019416 | CUSTOMIZABLE SYNTHESIS OF TUNABLE PARAMETERS FOR CODE GENERATION - An apparatus, method and/or computer readable media automatically generate hardware description language (HDL) code. A design environment is configured to receive a hardware design, the hardware design including a plurality of numerical parameters. A user interface (UI) accepts a designation of a first numerical parameter as a tunable numerical parameter. An HDL code generator detects the designation and instantiates a memory structure to store the first numerical parameter. The HDL code generator also configures an interface of a module of the hardware design to receive a value of the first numerical parameter, and instantiates one or more structures internal to the module to utilize the first numerical parameter. The HDL code generator also determines a second numerical parameter has not been designated as a tunable numerical parameter, in response, instantiates one or more structures to maintain the second numerical parameter as a hard-coded numerical parameter. | 01-15-2009 |
20090019417 | LOGIC SYNTHESIS APPARATUS - According to the present invention, there is provided an apparatus for executing logic synthesis for a module having a plurality of clock domains, having: an input unit which inputs circuit description data about a circuit function and a constraint in logic synthesis; a path selection unit which selects a path included in the module using a result obtained by analyzing the circuit description data; a recognition unit which recognizes a start point and an end point of the selected path and recognizes clock domains to which the start point and the end point belong; and a technology library setting unit which sets a technology library for the selected path in accordance with the clock domains to which the start point and the end point belong. | 01-15-2009 |
20090031276 | Design Apparatus, Design Method, and Program - A design apparatus, a design method, and a program, which enable the design of a small-scale circuit that is high in serviceability and quality are provided. Plural commands described at a behavior level are separated into control system behaviors that are behaviors concerning control and data system behaviors that are behaviors concerning data transfer, the data system behaviors for the commands are integrated into one or more behaviors, and both the control system behaviors for the commands and the behavior obtained by integrating the data system behaviors for the commands are subjected to high-level synthesis. | 01-29-2009 |
20090031277 | ARCHITECTURAL PHYSICAL SYNTHESIS - The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The synthesis transform is then made with accurate timing information from the placement, and the process is incrementally iterative toward the final timing enclosure of the design. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement, and the incremental improvements on placement made with knowledge of current circuit logic. | 01-29-2009 |
20090031278 | ARCHITECTURAL PHYSICAL SYNTHESIS - The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement, and the incremental improvements on placement made with knowledge of current circuit logic. According to another aspect, the present invention circuit design discloses incremental force directed placement transforms utilizing resource layers to address the heterogeneous resource distribution problem, where the force on an instance can be a weighted average of the forces from its resource layers based on the local congestion of those resources. In addition, incremental area removal method can be utilized to address resource utilization problem through a quality metric based on force directed placement transforms, such as a resource demand topological mapping. | 01-29-2009 |
20090064082 | METHOD FOR CUSTOM REGISTER CIRCUIT DESIGN - A computer program product stored on machine readable media is disclosed. The computer program product includes machine executable instructions for implementing a method of automatically creating a custom register circuit with a Computer Aided Design (CAD) application. The method includes obtaining parameters of the custom register circuit via a graphical user interface, executing one or more custom functions using the obtained parameters, and creating a cell comprising the custom register circuit. | 03-05-2009 |
20090083690 | SYSTEM FOR AND METHOD OF INTEGRATING TEST STRUCTURES INTO AN INTEGRATED CIRCUIT - A system and method for performing device-specific testing and acquiring parametric data on integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The testing system includes a device test structure integrated into an IC design which tests a set of dummy devices that are identical or nearly identical to a selected set of devices contained in the IC. The test structures are built from a device under test (DUT) library according to customer requirements and design requirements. The selected test structures are further prioritized and assigned to design elements within the design in order of priority. Placement algorithms use design, layout, and manufacturing requirements to place the selected test structures into the final layout of the design to be manufactured. | 03-26-2009 |
20090083691 | SYSTEMS AND TECHNIQUES FOR DEVELOPING HIGH-SPEED STANDARD CELL LIBRARIES - A method for providing a high-speed cell library is provided. The method can include, for example, selecting a set of commonly-occurring logic functions. The method can then include obtaining a netlist of area distributions for each of the set of functions. The netlist can be used to synthesize a set of cell libraries wherein an N-diffusion to P-diffusion area allowance is varied among the set of cell libraries. Thereafter, the method may also include comparing a time delay associated with each of the set of cell libraries with a time delay of a library benchmark delay. Based on the comparing, a delay number may be associated with each of the cell libraries. Finally, the cell libraries may be ranked based on the respective delay numbers associated with each of the cell libraries. | 03-26-2009 |
20090100398 | STRUCTURE FOR PERFORMING ITERATIVE SYNTHESIS OF AN INTEGRATED CIRCUIT DESIGN TO ATTAIN POWER CLOSURE - A design structure that performs iterative synthesis of an integrated circuit design to attain power closure is described. In one embodiment, the design structure is embodied in a computer readable medium and has the capability to initially synthesized an integrated circuit design to satisfy timing and power constraints. Results from the initial synthesis are fed back into the synthesis process where specific nodes in the circuit design are targeted to satisfy the timing and power constraints. Selected nodes in the circuit design are worked on in an iterative manner until it has been determined that all of selected nodes have undergone evaluation for satisfying timing and power constraints. Once all of the selected nodes have undergone evaluation for satisfying timing and power constraints, then a final netlist representing the circuit design is generated. | 04-16-2009 |
20090113375 | METHODS, MEDIA, AND MEANS FOR FORMING ASYNCHRONOUS LOGIC NETWORKS - Methods, media, and means for forming asynchronous logic networks are provided. In some embodiments, methods for forming an asynchronous logic network are provided. The methods include: receiving a logic network including vertices and signals, wherein the vertices include vertices with multiple output signals; determining a set of signals of the signals included in the logic network to be covered; selecting at least one vertex in the logic network to cover each signal in the set of signals; replacing the at least one selected vertex with a robust vertex; and replacing at least one non-selected vertex with a relaxed vertex. | 04-30-2009 |
20090132991 | PARTIAL ORDER REDUCTION FOR SCALABLE TESTING IN SYSTEM LEVEL DESIGN - A system and method for program testing includes, using a static analysis, determining dependency relations of enabled running processes in a program. The dependency relations are organized in a matrix to provide an interface for exploring the program. A reduced set of possible executions obtained by removal of redundant interleavings as determined with respect to the dependency relation, is explored on the program in a stateless exploration process that analyzes executed states and transitions to verify operation of the program. | 05-21-2009 |
20090138842 | BEHAVIORAL SYNTHESIS SYSTEM, BEHAVIORAL SYNTHESIS METHOD, AND BEHAVIORAL SYNTHESIS PROGRAM - A behavioral synthesis system has a scheduling unit and a mode control unit. The scheduling unit performs scheduling of a behavioral level description with reference to a resource quantity data indicating resource constraint and a resource delay data indicating delay times of respective resources. A single process described in the behavioral level description is divided into a plurality of description blocks, and a scheduling mode among a plurality of scheduling modes is designated with respect to each of the plurality of description block. The mode control unit refers to a mode designation code that indicates the designated scheduling mode and controls such that the scheduling unit performs the scheduling with respect to each description block in accordance with the designated scheduling mode indicated by the mode designation code. | 05-28-2009 |
20090144690 | SYSTEM AND METHOD FOR CONVERTING SOFTWARE TO A REGISTER TRANSFER (RTL) DESIGN - A method for converting a C-type programming language program to a hardware design, where the said program is an algorithmic representation of one or more processes. The C-type programming language program is compiled into a hardware description language (HDL) synthesizable design. The compiler categorizes variables as using either implicit memory or custom memory. Different accessor functions are used depending on which type of memory is used. The programming language may use ANSI C and the HDL may be Verilog Register Transfer Level (RTL). The hardware device generated from the HDL synthesizable design may be an Application-Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA). | 06-04-2009 |
20090158235 | SYNTHESIS OF ELECTRONIC CIRCUITS - The invention relates to a method of synthesising an electronic circuit for performing a function. The method comprises programming the function using a programming language by defining one or more terms, each term comprising one or more functional constants. Game semantics are applied to interpret the programmed function. Each term is interpreted as one or more strategies defined on moves. Each of the constants of the programmed function is associated with a sub-circuit. Each move is associated with at least one input or output port of the associated sub-circuit, and a move occurrence defined by a strategy produces a change of state of an associated port. The associated sub-circuits are combined to provide a synthesised circuit for performing the function. | 06-18-2009 |
20090164965 | Method and System for Building Binary Decision Diagrams Efficiently in a Structural Network Representation of a Digital Circuit - A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached. In response to determining that a union of first set and the second set of m-ary decision representations do not describe the logic function, the first and second size limits are increased, and the steps of building the first and second set are repeated. In response to determining that the union of the first set of m-ary decision representations and the second set of m-ary decision representations describe the logic function, the union is reported. | 06-25-2009 |
20090164966 | Method and System for Building Binary Decision Diagrams Efficiently in a Structural Network Representation of a Digital Circuit - A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached. In response to determining that a union of first set and the second set of m-ary decision representations do not describe the logic function, the first and second size limits are increased, and the steps of building the first and second set are repeated. In response to determining that the union of the first set of m-ary decision representations and the second set of m-ary decision representations describe the logic function, the union is reported. | 06-25-2009 |
20090164967 | HIGH-LEVEL SYNTHESIS APPARATUS, HIGH-LEVEL SYNTHESIS SYSTEM AND HIGH-LEVEL SYNTHESIS METHOD - A high-level synthesis apparatus for automatically generating a register transfer level (RTL) logic circuit from a behavioral description has a scheduling unit configured to perform data flow analysis and scheduling to generate a data flow graph showing an operation cycle of an operation from the behavioral description, a scheduling result inputting/outputting unit configured to extract a point to be allocated to a register from the data flow graph and output register information indicating the point, the scheduling result inputting/outputting unit being provided with dynamic analysis data that includes at least one of the number of times that data at the point has been substituted and the number of times that a value stored at the point has changed by a predetermined simulation, an allocating unit configured to consult dynamic analysis data and allocate circuit elements to the behavioral description, and an RTL description generating unit configured to generate the logic circuit based on the allocation of circuit elements by the allocating unit. | 06-25-2009 |
20090164968 | Method and System for Implementing Top Down Design and Verification of an Electronic Design - Disclosed is a method and system for performing design and verification using stepwise refinement techniques, which can also include or be referred to as “top-down” design verification. With the present stepwise refinement approach, the electronic design can be acted upon at different levels of abstraction, but with approximately the same level of resolution at each abstraction level. A strong relationship of consistency exists between the successive abstraction levels of the design. On account of this consistency, properties that are established or true at one level of the design remain true for all subsequent levels of abstraction of the design. The present approach also allows designers to more efficiently and accurately perform hardware/software co-design. For the co-design process, consistency between different levels of abstraction allows a designer to safely implement a systematic and concurrent divide-and-conquer approach to the hardware and/or software elements in a design. | 06-25-2009 |
20090172630 | AUTOMATED PROCESSOR GENERATION SYSTEM AND METHOD FOR DESIGNING A CONFIGURABLE PROCESSOR - A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification. | 07-02-2009 |
20090187875 | SYSTEM AND METHOD FOR CREATING A LOGICAL REPRESENTATION OF A FUNCTIONAL LOGIC SYSTEM FROM A PHYSICAL REPRESENTATION - A system and method for transforming a physical representation of a functional logic system or sub-system to a logical representation of the same functional logic system or sub-system. One embodiment provides a method comprising loading a physical hardware description language (HDL) representation of the system or creating a physical HDL representation from a physical schematic of the system, identifying the power nets and component blocks, identifying initial conditions on the power nets and component blocks, converting connector blocks to hierarchical IO logical HDL representations, converting appropriate component blocks to logical HDL representations, deleting component blocks appropriate for deletion, and converting resistor components to logical HDL representations. | 07-23-2009 |
20090217231 | INTEGRATED CIRCUIT DESIGN SUPPORT APPARATUS, INTEGRATED CIRCUIT DESIGN SUPPORT METHOD, INTEGRATED CIRCUIT DESIGN SUPPORT PROGRAM, AND RECORDING MEDIUM WITH SAID PROGRAM RECORDED THEREIN - Provided is an integrated circuit design support apparatus capable of estimating the optimal wiring length and wiring congestion at the stage of implementing a logical design of an integrated circuit, thereby preventing the do-over of the logical design or functional design caused by a wiring delay that is discovered at a packaging design stage, and shortening the time required for designing the integrated circuit. The present invention is able to accurately estimate the wiring length between the modules and the wiring congestion in the modules at the stage of implementing the logical design of the integrated circuit, and reflect the logical design result of the integrated circuit in the packaging design of the integrated circuit. | 08-27-2009 |
20090217232 | LOGIC SYNTHESIS OF MULTI-LEVEL DOMINO ASYNCHRONOUS PIPELINES - Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied. | 08-27-2009 |
20090235223 | PROGRAM GENERATION APPARATUS AND PROGRAM GENERATION METHOD - According to one embodiment, a software generation apparatus generates software for verifying a RTL description obtained by high-level synthesis of an operation description describing an LSI operation. The apparatus comprises a judgment function generation module configured to generate a judgment function based on a test program for verifying the operation description and an execution cycle number, the judgment function starting a process of determining whether the relationship between the input value and the output value is an expected relation when the number of times of receiving a pair of an input value and an output value from the test program exceeds the execution cycle number. | 09-17-2009 |
20090241084 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR EXPLOITING ORTHOGONAL CONTROL VECTORS IN TIMING DRIVEN SYSTEMS - Systems, methods and computer program products for exploiting orthogonal control vectors in timing driven systems. An exemplary embodiment includes running an initial logic synthesis run on the system, identifying critical inputs to a logic cone related to the run, identifying orthogonal vectors in the logic cone, adding vectors to the logic cone, obtaining logical solutions and selecting a solution from the logical solutions. | 09-24-2009 |
20090288058 | POWER AWARE ASYNCHRONOUS CIRCUITS - Techniques are described for converting netlists for synchronous circuits such as combinational modules, flip flops (or latches), and clock gating modules, to netlist of asynchronous modules. Processes including algorithms are described that bundle multiple modules in an enable domain, so that they are activated only if the incoming enable token to the enable domain has the UPDATE value. The modules can be clustered inside an enable domain, so that each cluster has a separate controller. The objective function of bundling and clustering can minimize power consumption with respect to a given cycle time. Exemplary embodiments can include a gated multilevel domino template. | 11-19-2009 |
20090288059 | CLUSTERING AND FANOUT OPTIMIZATIONS OF ASYNCHRONOUS CIRCUITS - Techniques are described for generating asynchronous circuits from any arbitrary HDL representation of a synchronous circuit by automatically clustering the synthesized gates into pipeline stages that are then slack-matched to meet performance goals while minimizing area. Automatic pipelining can be provided in which the throughput of the overall design is not limited to the clock frequency or the level of pipelining in the original RTL specification. The techniques are applicable to many asynchronous design styles. A model and infrastructure can be designed that guides clustering to avoid the introduction of deadlocks and achieve a target circuit performance. Slack matching models can be used to take advantage of fanout optimizations of buffer trees that improve the quality of the results. | 11-19-2009 |
20090293036 | HARDWARE DESCRIPTION LANGUAGE AND A SYSTEM AND METHODS FOR ELECTRONIC DESIGN - A Hardware Description Language (HDL) comprising of a plurality of object commands, a plurality of compile commands and a plurality of comment styles is used in methods of electronic circuit design. An object command in the HDL defines a logic object, which can be as simple as a piece of wire or as complex as a priority-encoded arbitrator with a variable number of requesters. A Register Transfer Level (RTL) design in the HDL can be translated into a set of generic gates and instantiated library modules for design verification and synthesis. The design can also be translated to a target hardware description language such as Verilog-HDL or VHDL to feed into a conventional design flow. | 11-26-2009 |
20100017776 | DESIGN PROGRAM, DESIGN APPARATUS, AND DESIGN METHOD FOR DYNAMIC RECONFIGURABLE CIRCUIT - A computer-readable recording medium that stores therein a computer program for designing a dynamic reconfigurable circuit in which a plurality of circuit configurations are implemented with a single circuit, the computer program enabling a computer to execute: acquiring a plurality of contexts having connection information between operation devices and network modules, wherein the operation devices and network modules are disposed in clusters, and connection information among the network modules; calculating a cluster count of the clusters and an operation device count for each operation device type of the operation devices in each cluster based on the acquired plurality of contexts; generating a circuit configuration for each context in which disposition of the operation devices in each cluster and connection of the network modules are made to satisfy the calculated cluster count and operation device count; and outputting the generated circuit configuration. | 01-21-2010 |
20100017777 | Method and apparatus for synthesizing a hardware system from a software - A method and an apparatus take software source code to synthesize a hardware platform for running the software. The method determines which processor is suitable for running the code and meeting the performance parameters determined by the user. The method also determines which hardware devices are accessed by software. If the hardware target is a semiconductor chip, the invention selects the appropriate IP and creates an HDL description of the chip. If the hardware target is a printed circuit board, the invention creates a schematic or netlist that includes the appropriate microprocessor, the various semiconductor chips, and the necessary interconnections. | 01-21-2010 |
20100042965 | Method and System for Scalable Reduction in Registers With Sat-Based Resubstitution - A method, system, and computer program product for reducing the size of a logic network design, prior to verification of the logic network design. The method includes eliminating registers to reduce the size of the logic network design; thereby, increasing the speed and functionality of the verification process, and decreasing the size of the logic network design. The system identifies one or more compatible resubstitutions of a selected register, wherein the compatible resubstitution expresses the selected register as one or more pre-existing registers of fixed initial state. The resubstitutions are refined utilizing design invariants. When one more resubstitutions are preformed, the system eliminates the selected registers to reduce the size of the logic network design. As a result of the resubstitution process, a logic network design of reduced size is generated. | 02-18-2010 |
20100042966 | MULTIPLEXER IMPLEMENTATION - Disclosed is a method of improving a synthesized circuit design comprising searching the synthesized circuit design for a first instance of a first pattern of gates. The first instance is removed from the synthesized circuit design. The first instance is replaced with a non-synthesized cell. A method of altering a multiplexer implementation comprises receiving a netlist that describes a synthesized logic circuit design. Parsing the netlist to detect a first instance of a first pattern of gates that implements a first multiplexer. The first instance is replaced in the netlist with a technology implementation of the first multiplexer. | 02-18-2010 |
20100050148 | METHOD AND SYSTEM FOR AUTOMATED SCHEMATIC DIAGRAM CONVERSION TO SUPPORT SEMICONDUCTOR BODY BIAS DESIGNS - A computer implemented method and system for converting schematic diagrams. The method includes accessing a first set of schematic diagrams, wherein the schematic diagrams represent an integrated circuit design to be realized in physical form. A plurality of a first type of circuit elements in the firs set are converted into a second type of circuit elements. The conversion is implemented in accordance with a set of conversion rules. A second set of schematic diagrams representing the integrated circuit design and including the second type of circuit elements are then output. | 02-25-2010 |
20100058277 | Method and system for organizing data generated by electronic design automation tools - A method and system for organizing a plurality of files generated by an Electronic Design and Automation (EDA) tool into composite objects is disclosed. The system provides a plurality of rules, which may be configured for various EDA tools. These rules may be configured for any EDA tool by specifying various parameters such as filename patterns, file formats, directory name patterns, and the like. Using these rules which are configured for an EDA tool, the files that form a part of the design objects are identified and packaged in the form of composite objects. | 03-04-2010 |
20100058278 | METHOD AND APPARATUS FOR AUTOMATED SYNTHESIS OF MULTI-CHANNEL CIRCUITS - Methods and apparatuses to automatically generate time multiplexed multi-channel circuits from single-channel circuits. At least one embodiment of the present invention automatically and efficiently synthesize multi-channel hardware for time-multiplexed resource sharing by automatically generating a time multiplexed design of multi-channel circuits from the design of a single-channel circuit. Channel specific elements of the single-channel design (e.g., registers and memories) are replaced with corresponding elements of N-times more capacity for pipelining the signal processing for multiple channels. | 03-04-2010 |
20100070943 | Development method for integrated circuits, program storage medium for storing the development method for integrated circuits, and concurrent development system, development program, and development method of ASIC and programmable logic device - A method for developing integrated circuits includes generating a core (logic core) in an HDL format readable by a logic synthesis tool, from an ASIC core (logic core) made of ports of blocks and port connection information, creating a temporary chip design from chip terminal information to generate a terminal in the temporary chip design, generating a design identical to that created, as a cell within the design created, connecting a design port with a cell port, wherein a name of the design port is identical to a name of the cell port, inserting an I/O buffer, depending on the device technology, into a net between the ports connected, replacing the cell by the core (logic core) created to gerate a netlist, and expanding a hierarchy of the design, being the top hierarchy. | 03-18-2010 |
20100083209 | BEHAVIORAL SYNTHESIS APPARATUS, BEHAVIORAL SYNTHESIS METHOD, AND COMPUTER READABLE RECORDING MEDIUM - A behavioral synthesis apparatus includes a acquisition unit, a scheduling unit and a generation unit. The acquisition unit acquires a behavioral level description describing an operation of a semiconductor integrated circuit. The scheduling unit separates the acquired behavioral level description into N stage descriptions, and makes a schedule in such a way that input/output operations and computations among the N stage descriptions are pipelined. The generation unit generates a register transfer level description based on the N stage descriptions and a result of scheduling performed by the scheduling unit in such a way as to form stage circuits respectively corresponding to the N stage descriptions and a state control circuit which controls possible 2N−1 stage control states of the semiconductor integrated circuit. The generation unit generates the register transfer level description in such a way as to inhibit the operation of a stage circuit which need not be operated. | 04-01-2010 |
20100138805 | Method and System for Building Binary Decision Diagrams Efficiently in a Structural Network Representation of a Digital Circuit - A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached. In response to determining that a union of first set and the second set of m-ary decision representations do not describe the logic function, the first and second size limits are increased, and the steps of building the first and second set are repeated. In response to determining that the union of the first set of m-ary decision representations and the second set of m-ary decision representations describe the logic function, the union is reported. | 06-03-2010 |
20100146474 | Method and System for Building Binary Decision Diagrams Efficiently in a Structural Network Representation of a Digital Circuit - A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached. In response to determining that a union of first set and the second set of m-ary decision representations do not describe the logic function, the first and second size limits are increased, and the steps of building the first and second set are repeated. In response to determining that the union of the first set of m-ary decision representations and the second set of m-ary decision representations describe the logic function, the union is reported. | 06-10-2010 |
20100153898 | MODEL BUILD IN THE PRESENCE OF A NON-BINDING REFERENCE - One or more hardware description language (HDL) files describe a plurality of hierarchically arranged design entities defining a digital design to be simulated and a plurality of configuration entities not belonging to the digital design that logically control settings of a plurality of configuration latches in the digital design. The HDL file(s) are compiled to obtain a simulation executable model of the digital design and an associated configuration database. The compiling includes parsing a configuration statement that specifies an association between an instance of a configuration entity and a specified configuration latch, determining whether or not the specified configuration latch is described in the HDL file(s), and if not, creating an indication in the configuration database that the instance of the configuration latch had a specified association to a configuration latch to which it failed to bind. | 06-17-2010 |
20100153899 | METHODS AND APPARATUSES FOR DESIGNING LOGIC USING ARITHMETIC FLEXIBILITY - Methods and apparatuses for designing logic are described. In one embodiment, a method includes determining a directive which specifies a format for data in a data processing operation and creating a representation of logic to perform the data processing operation, wherein the creating uses the directive as a minimum format, rather than an exact or required format, for at least a portion of the representation of logic. Other methods are disclosed, and systems and machine readable media are also disclosed. | 06-17-2010 |
20100153900 | AUTOMATED CIRCUIT DESIGN PROCESS FOR GENERATION OF STABILITY CONSTRAINTS FOR GENERICALLY DEFINED ELECTRONIC SYSTEM WITH FEEDBACK - A method is described that involves accepting a description of an electronic system having feedback. The method further includes expressing a real root of the electronic system's transfer function and expressing a real part of a complex root of the electronic system's transfer function. The method further includes expressing a time parameter as a maximum of the real root and the real part of a complex root. The method further involves expressing a settling time of the electronic system with the time parameter and using the settling time to automatically generate a design for the electronic system. | 06-17-2010 |
20100192118 | METHOD OF AND CIRCUIT FOR IMPLEMENTING A FILTER IN AN INTEGRATED CIRCUIT - According to an embodiment of the invention, a method of configuring a filter in a circuit to be implemented in an integrated circuit is disclosed. The method comprises receiving a high level design of the circuit; identifying a filter in the high level design; analyzing coefficients of the filter; and transforming the filter of the high level design to a filter using a processing block of the circuit configured to accommodate a common coefficient, wherein the processing block is coupled to receive taps associated with the common coefficient. A computer program product and a circuit for configuring a filter in a circuit to be implemented in an integrated circuit are also disclosed. | 07-29-2010 |
20100205576 | SYSTEM AND METHOD FOR APERTURE BASED LAYOUT DATA ANALYSIS TO ACHIEVE NEIGHBORHOOD AWARENESS - Embodiments of the invention provide system and methods for EDA tools. Specifically, some embodiments of the invention provide an input infrastructure for EDA tools that gathers pertinent information surrounding an input cursor's present locality (or neighborhood) and then analyzes the pertinent information in view of an issued command to automatically determine suitable targets or subsequent operations that a user of the EDA tool may want to select next. | 08-12-2010 |
20100229144 | SYSTEM AND METHOD FOR BEHAVIORAL SYNTHESIS - An operation synthesis system includes an operation synthesizing section configured to perform operation synthesis of an operation description to generate a data path graph corresponding to the operation description, wherein the data path graph contains an input terminal configured to input an input data and an operating unit configured to perform an operation on the input data; and a gating circuit inserting section configured to insert a gating circuit between the input terminal and the operating unit. The gating circuit blocks off transmission of the input data from the input terminal to the operating unit when the operating unit does not need the input data, and transmits the input data from the input terminal to the operating unit only when the operating unit needs the input data. | 09-09-2010 |
20100251201 | INTERACTIVE SIMPLIFICATION OF SCHEMATIC DIAGRAM OF INTEGRATED CIRCUIT DESIGN - The interactive grouping tool offers the flexibility to simplify the schematic diagram of an integrated circuit (IC) design by grouping circuit elements that are not specified to be of interest into entities of any size. Circuit elements of various types and functionalities, including ports and pins, can be combined together into the same entity without modifying the underlying design logic and connectivity. By grouping and hiding the unnecessary details, the tool reduces clutter in a schematic diagram and greatly eases the process of traversing, debugging, and analyzing the schematic diagram. Users can choose to dynamically group the circuit elements on the schematic diagram without going through any compilation or synthesis process. Users can also choose to revert any of the entities back to the original schematic diagram with the ungrouping operation. For specific or batch manipulation of the schematic diagram, the tool provides a scripting interface for users to enter commands. The content of selected entities can be changed by using the drag-and-drop technique for certain operations including moving nodes into, removing nodes from, and adding nodes into an entity. | 09-30-2010 |