| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 716011000 | Layout editor (e.g., updating) | 69 |
| 20080201679 | DESIGN AID APPARATUS, COMPUTER-READABLE RECORDING MEDIUM IN WHICH DESIGN AID PROGRAM IS STORED, AND INTERACTIVE DESIGN AID APPARATUS - Logical design of a circuit or a printed board including a number of components is carried out with improved flexibility in determination of the positions and the number of logical terminals of a symbol in order to easily create a logical circuit diagram high invisibility due to absence of deficiency such as interconnections crossing. The design aid apparatus includes a terminal information retaining section for retaining terminal information pieces; a tentative symbol determining section for determining a tentative symbol, for each component, having tentative logical terminals; a tentative symbol arranging section for arranging the determined tentative symbol; and a symbol determining section for determining the tentative symbol to be the symbol representing each component by, for the component, allocating each retained terminal information piece to one of the tentative logical terminals of the arranged tentative symbol. | 08-21-2008 |
| 20080209382 | STITCHED IC CHIP LAYOUT DESIGN STRUCTURE - Stitched integrated circuit (IC) chip layout design structures are disclosed. In one embodiment, a design structure embodied in a machine readable medium used in a design process includes: an integrated circuit (IC) chip exceeding a size of a photolithography tool field, the IC chip layout including: a plurality of stitched regions including at least one redundant stitched region or at least one unique stitched region; and for each stitched region: a boundary identification identifying a boundary of the stitched region at which stitching occurs. | 08-28-2008 |
| 20080222589 | Protecting Trade Secrets During the Design and Configuration of an Integrated Circuit Semiconductor Design - A system and method for facilitating the design process of an integrated circuits (IC) is described. The system and method utilizes a plurality of repositories, rules engines and design and verification tools to analyze the workload and automatically produce a hardened GDSII description or other representation of the IC. Synthesizable RTL is securely maintained on a server in a data center while providing designers graphical access to customizable IP block by way of a network portal. | 09-11-2008 |
| 20080229267 | Method and System for Developing Post-Layout Electronic Data Automation (Eda) Applications - A method and system for processing geometrical layout design data to manufacture an electronic circuit is provided. The method includes extracting the geometrical layout design data from one or more data-format files. The method further includes segregating the geometrical layout design data extracted from one or more data-format files into each of a structural data, a spatial data, and a raw-geometry data. Thereafter, one or more predefined operations are performed on one or more of the structural data, the spatial data, and the raw-geometry data. | 09-18-2008 |
| 20080235645 | Method and apparatus for detecting lithographic hotspots - Method for detecting hotspots in a circuit layout includes constructing a layout graph having nodes, corner edges and proximity edges from the circuit layout, converting the layout graph to a corresponding dual graph, and iteratively selecting edges and nodes having weights greater than a predetermined threshold value at each iteration as hotspots. | 09-25-2008 |
| 20080244493 | PATTERN BASED ELABORATION OF HIERARCHICAL L3GO DESIGNS - A system, method and program product that utilizes flat pattern based L3GO elaboration in a hierarchical environment to create a nested conventional layout. A system is provide for processing a glyph layout to generate shapes for use in a VLSI (very large scale integrated circuit) design process, including: a hierarchical pattern search system that matches patterns from a pattern library to a set of glyph data, wherein the patterns have dependencies that cross hierarchical design boundaries; and a target shape generation system that selects patterns from a set of matching patterns and generates associated shapes. | 10-02-2008 |
| 20080301613 | DESIGNING WIRING HARNESSES - A method of designing a wiring harness using a wiring harness design tool can include allowing a first user to access and edit a first wiring harness design component in a wiring harness design workspace, allowing a second user to access and edit a second wiring harness design component in the wiring harness design workspace at least during a portion of the time that the first user is allowed to access and edit the first wiring harness design component, and displaying the first and second wiring harness design components to the first and second users during at least a portion of the time that access is allowed to the first and second users. | 12-04-2008 |
| 20080301614 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR SPARE CIRCUITRY DISTRIBUTION - A method, system, and computer program product for spare circuitry distribution in an integrated circuit design are provided. The method includes receiving design data for the integrated circuit design. The design data includes descriptions of spare circuitry and physical area available for circuitry placement. The method further includes determining target placement locations for the spare circuitry, where the target placement locations create a balanced distribution of the spare circuitry throughout the physical area available for circuitry placement. The method also includes shifting the location of the spare circuitry from each target placement location towards a nearest clock block within the integrated circuit design, resulting in an updated integrated circuit design. The method additionally includes outputting the updated integrated circuit design. | 12-04-2008 |
| 20080307381 | IC LAYOUT PARSING FOR MULTIPLE MASKS - A method for separating features in a target layout into different mask layouts for use in a photolithographic process. Features of a target layer are searched for features having a predefined shape. In one embodiment, portions of the feature having the predefined shape divided into two or more sub-features and at least one sub-feature are not considered when separating the features into two or more mask layouts. In another embodiment, features having a predefined shape are cut to form two or more sub-features and all features and sub-features are considered when separating the features of the target layout into the two or more mask layouts. | 12-11-2008 |
| 20080313592 | MASK LAYOUT EDITOR SHAPE QUERY - A computer program product stored on machine readable media includes machine executable instructions for display a layout of a circuit design, the product including instructions for displaying a layout of a circuit design, the product including instructions for: receiving query input including location information; querying a design layout for object information associated with the location information; and reporting the object information. A system is also provided. | 12-18-2008 |
| 20080320429 | CIRCUIT LAYOUT TOOL DIMMING FEATURE - A computer program product stored on machine readable media including machine executable instructions for display a layout of a circuit design, includes instructions for: receiving designation of at least one design segment from a user; receiving designation of a degree of intensity for at least one of highlighting and dimming the design segments and on a display screen, highlighting the designated design segments and dimming remaining segments on the display. A system is also provided. | 12-25-2008 |
| 20080320430 | Spare Gate Array Cell Distribution Analysis - A method for determining gate array distribution includes steps or acts of: randomly placing a plurality of test boxes in a logic circuit layout; counting the number of fill cells in each of the plurality of test boxes; recording the count; grouping the plurality of test boxes into two groups: a first group with local clock buffers and a second group without local clock buffers; determining the fill cell percentage of each of the plurality of test boxes; and flagging the test boxes with a poor distribution of gate array cells. | 12-25-2008 |
| 20090007046 | Layout Method for Vertical Power Transistors Having a Variable Channel Width - The invention relates to a simulation and/or layout process for vertical power transistors as DMOS or IGBT with variable channel width and variable gate drain capacity which can be drawn and/or designed by the designer with the respectively desired parameters of channel width and gate drain capacity and the parameters of volume resistance and circuit speed, which are correlated therewith, and whose electrical parameters can be described as a function of the geometrical gate electrode design. Here, both discrete and integrated vertical transistors may be concerned. | 01-01-2009 |
| 20090013298 | Offset Fill - Techniques are described for increasing the density of structures in a layout circuit design, while reducing undesired total interconnect capacitance that might otherwise be created by the increase in structure density. Data representing a pattern of fill structures is added to the fill regions of the design for one of the layers. Data representing a pattern of fill structures then is added to the fill regions of the design for another of the layers adjacent to the first layer. In the design for the second conductive layer, however, the pattern of fill structures is offset from the pattern of fill structures added to the design for the first layer in a direction substantially parallel to the layers. The offset may be selected to minimize or otherwise reduce the amount of overlap between the fill structures along a direction substantially perpendicular to the layers, thereby reducing the total interconnect capacitance associated with the layers. | 01-08-2009 |
| 20090019414 | HIGH TOLERANCE TCR BALANCED HIGH CURRENT RESISTOR FOR RF CMOS AND RF SIGE BICMOS APPLICATIONS AND CADENCED BASED HIERARCHICAL PARAMETERIZED CELL DESIGN KIT WITH TUNABLE TCR AND ESD RESISTOR BALLASTING FEATURE - A resistor device structure and method of manufacture therefore, wherein the resistor device structure invention includes a plurality of alternating conductive film and insulative film layers, at least two of the conductive film layers being electrically connected in parallel to provide for high current flow through the resistor device at high frequencies with increased temperature and mechanical stability. The alternating conductive film and insulative film layers may be of a planar or non-planar geometric spatial orientation. The alternating conductive film and insulative film layers may include lateral and vertical portions designed to enable a uniform current density flow within the structure itself through a self-ballasting effect within the physical resistor. A computer aided design tool with graphical and schematic features is provided to enable generation of hierarchical parameterized cells for a resistor element with the ability to provide customization, personalization and tunability of TCR, TCR matching, and high current and ESD robustness. | 01-15-2009 |
| 20090024975 | SYSTEMS, METHODS AND COMPUTER PRODUCTS FOR TRAVERSING DESIGN HIERARCHY USING A SCROLL MECHANISM - A method and an apparatus are disclosed for the display of hierarchical navigation in the automated design of integrated circuits under test. A user, using a computer, assigns a head pointer assignment and a tail pointer assignment, which form a definition of a viewable scope of at least one hierarchical level of design from a plurality of hierarchical levels of design. These head pointer and tail pointer assignments are stored in a repository of the computer to set the definition of the viewable scope of the at least one hierarchical level of design. After being set, the viewable scope of the at least one hierarchical level of design is displayed on a computer display device, where the viewable scope of the at least one hierarchical level of design can be traversed by moving a scrolling mechanism up and down in the viewable scope of the at least one hierarchical level of design. | 01-22-2009 |
| 20090031272 | CIRCUIT BOARD DESIGN TOOL AND METHODS - A design tool for printed circuit boards displays a graphical representation of a printed circuit board layout through a graphical user interface (GUI). Comments for particular components of the printed circuit board layout can be entered through the graphical user interface. The comments are stored in a data file associated with the printed circuit board layout. Comments can be entered and viewed by multiple users in real time. Comments can be displayed through the graphical user interface in proximity to the component associated with the comment, thereby improving the efficiency with which designers can review and implement suggested changes to the PCB layout | 01-29-2009 |
| 20090031273 | METHOD FOR STACKED PATTERN DESIGN OF PRINTED CIRCUIT BOARD AND SYSTEM THEREOF - A method for designing stacked pattern of PCB utilizing genetic algorithm and the system thereof are disclosed. The method comprises the following steps: First of all, information data of stacked pattern is inputted into operational interface of the software; Next, initial solution sets of stacked pattern are generated; Then, duplications of the initial solution sets of stacked pattern are generated according to a fitness function; Afterward, crossover of the duplications of stacked pattern are performed at random; Then, mutations are executed by a probability at random; Finally, identification is performed to check if the solution approaches the standard of demand and the result of stacked pattern is shown; otherwise, operational step jumps to duplicate step and repeats above steps until satisfying solution is obtained. The most suitable way for package can be arranged out through making especially mathematical calculations by the system efficiently. | 01-29-2009 |
| 20090037863 | Integration of Pre-Defined Functionality and a Graphical Program in a Circuit - System and method for designing a circuit. At least one graphical program comprising a plurality of interconnected nodes that visually indicate functionality of the graphical program is selected in response to user input. At least one pre-defined hardware configuration program (HCP) is selected from a plurality of pre-defined HCPs in response to user input, where the selected at least one pre-defined HCP specifies a fixed functionality, including interface functionality for communicating with the at least one graphical program when implemented on the circuit. At least a portion of a netlist is generated based on the at least one graphical program and the at least one selected pre-defined HCP, where the netlist is usable to configure a circuit, wherein a first portion of the circuit implements the functionality of the graphical program and a second portion of the circuit implements the fixed functionality. | 02-05-2009 |
| 20090037864 | Methods for Designing Semiconductor Device with Dynamic Array Section - A method is provided for designing a semiconductor chip having one or more functionally interfaced dynamic array sections. A virtual grate is laid out for conductive features used to define a gate electrode level of a dynamic array section. The virtual grate is defined by a framework of parallel lines defined at a substantially constant pitch. One or more conductive features are arranged along every line of the virtual grate. For each line of the virtual grate, a gap is defined between proximate ends of each pair of adjacent conductive features which are arranged along a common line of the virtual grate. Each gap is defined to maintain a substantially consistent separation between proximate ends of conductive features. Each conductive feature is defined to be devoid of a substantial change in direction, such that the conductive features remain substantially aligned to the framework of parallel lines of the virtual grate. | 02-05-2009 |
| 20090055790 | DESIGN STRUCTURE FOR ON CHIP SHIELDING STRUCTURE FOR INTEGRATED CIRCUITS OR DEVICES ON A SUBSTRATE - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure comprises: a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate and at least one feed through capacitor and one transmission line associated with the conductive structure and providing the power supply and signals to the circuit or circuit device respectively. The design structure also comprises a shielding structure surrounding a circuit or a circuit device arranged on a substrate and at least one feed through capacitor or a transmission line arranged on a side of the shielding structure. | 02-26-2009 |
| 20090064075 | SYSTEMS, METHODS AND COMPUTER PRODUCTS FOR SCHEMATIC EDITOR MULIT-WINDOW ENHANCEMENT OF HIERARCHICAL INTEGRATED CIRCUIT DESIGN - A method and apparatus for displaying hierarchical navigation and editing a plurality of hierarchical levels of design of an integrated circuit includes opening a main editor screen, displaying a viewable scope of hierarchical levels of design in the main editor screen and using a computer to assign a side window adjacent to the main editor screen. The side-window displays information about schematics previously viewed including thumbnail views of most recently viewed levels of the plurality of hierarchical levels of design. Using the computer input device, the user scrolls through the main editor screen into a hierarchical level of design. The side window is populated with a schematic that was last viewed and a thumbnail view of the hierarchical level of design is surrounded by a highlighted border, enabling the user to view schematic elements underneath the hierarchical level of design and to see the thumbnail view of the top-level schematic. | 03-05-2009 |
| 20090064076 | SYSTEMS, METHODS AND COMPUTER PRODUCTS FOR TRAVERSING SCHEMATIC HIERARCHY USING A SCROLLING MECHANISM - A method and a system for displaying hierarchical navigating, debugging and editing of selected hierarchical levels of design of a plurality of hierarchical levels of design in graphical hierarchical design applications, by assigning, from a schematic of the integrated circuit, a viewable scope of a block element desired for traversing. Opening the viewable scope of the block element, by using a mouse scrolling device to cause a cursor to highlight and roll in a downward direction over the highlighted block element, while holding down a predefined keyboard key. Then closing the viewable scope of the block element, by causing the cursor to be positioned in an empty area of the schematic, while holding down an other predefined keyboard key and rolling the mouse scrolling device in an upward direction. | 03-05-2009 |
| 20090064077 | LAYOUT VERSUS SCHEMATIC ERROR SYSTEM AND METHOD - According to various embodiments of the invention, systems and methods for presenting Layout Versus Schematic (LVS) errors within a layout using a visual circuit representation of the design and highlighting is provided. One embodiment includes overlaying the layout circuit representation on the schematic circuit representation with highlighting that indicates the LVS errors. The method of such an embodiment compares a layout netlist against a schematic netlist in order to identify the layout-versus-schematic errors, generates a graphical representation of the layout netlist and a graphical representation of the schematic netlist, displays an overlay of the graphical representation of the layout netlist with the graphical representation of the schematic netlist and then, highlights the identified layout-versus-schematic errors that are present. | 03-05-2009 |
| 20090064078 | Method of designing a semiconductor integrated circuit having a dummy area and the semiconductor integrated circuit thereof - An exemplary semiconductor integrated circuit is formed on a surface of a semiconductor chip includes a circuit region and a dummy region on the surface of the semiconductor chip. The circuit region includes a plurality of circuit patterns, which form circuit elements of the semiconductor integrated circuit, in a plurality of pattern layers. The dummy region includes a plurality of character dummies, which do not contribute to an operation of the semiconductor integrated circuit. The character dummies have a fixed shape and dimension, and arranged in a character pattern layer selected from the plurality of pattern layers with a fixed pitch. The dummy region further includes an identification sign formed by connecting selected ones of the character dummies chosen from the plurality of the character dummies. | 03-05-2009 |
| 20090070723 | METHOD FOR GENERATING A SCAN CHAIN IN A CUSTOM ELECTRONIC CIRCUIT DESIGN - The present invention relates to a method for generating a scan chain in a custom electronic circuit design with a plurality of storage elements. Said method comprises the steps of providing a schematic, propagating all scan inputs and all scan outputs of the storage elements to a top level of the design hierarchy, and declaring each scan input and each scan output on the top level as primary input and primary output, respectively. Said method comprises further the steps of adjusting a layout of the custom circuit according to the schematic, building up the scan chain according to a predetermined algorithm, and annotating the scan chain back into the schematic. | 03-12-2009 |
| 20090070724 | INFORMATION PROCESSING DEVICE, METHOD OF CREATING POWER SUPPLY SYSTEM TREE AND PROGRAM OF THE SAME - According to one embodiment, an information processing device includes a registration section for registering terminals of a symbol diagrams to a library by associating a relationship of connections of each of a devices, an extraction section for extracting a hierarchical structure of a power supply system and the symbol diagrams, a connection section for connecting the terminals of the symbol diagrams on the basis of the extracted hierarchical structure of the power supply system and the registered relationship of connections of the symbol diagrams, and a creation section for creating a schematic diagram of a hierarchical structure by connecting the terminals of the symbol diagrams on the basis of the extracted hierarchical structure of the power supply system and the registered relationship of connections of the symbol diagrams. | 03-12-2009 |
| 20090077518 | DERIVED LEVEL RECOGNITION IN A LAYOUT EDITOR - A computer program product stored on machine readable media includes machine executable instructions for displaying a layout of a circuit design, the product including instructions for: over a plurality of layers within a design, identifying at least one of a derived level and a device defined within the plurality; and displaying the at least one derived level and device to a user. | 03-19-2009 |
| 20090077519 | Displacement Aware Optical Proximity Correction For Microcircuit Layout Designs - Techniques for adjusting edge segments within a layout design such that fewer iterations of an optical proximity correction process are required for covergence are provided. With various implementations, multiple iterations of an optical proximity correction process are performed on a portion of a layout design. The final displacement of various edge segments within a layout design may be employed to adjust the displacement of like edge segments within the same or alternate layout design, such that the optical proximity correction process may converge upon a suitable solution in fewer iterations. | 03-19-2009 |
| 20090083688 | METHOD AND APPARATUS FOR GENERATING A LAYOUT FOR A TRANSISTOR - A system that generates a layout for a transistor is presented. During operation, the system receives a transistor library which includes operating characteristics of fabricated transistors correlated to transistor gate shapes. The system also receives one or more desired operating characteristics for the transistor. Next, the system determines a transistor gate shape for the transistor based on the transistor library so that a fabricated transistor with the transistor gate shape substantially achieves the one or more desired operating characteristics. The system then generates the layout for the transistor which includes the transistor gate shape. | 03-26-2009 |
| 20090089733 | METHOD FOR AUTOMATICALLY PRODUCING LAYOUT INFORMATION - A method of automatically producing layout information includes receiving first layout information of an integrated circuit; when receiving the first layout information, activating an automated process mechanism to stores the first layout information into a reference database; reading the first layout information from the reference database by the automated process mechanism; and analyzing the first layout information to obtain second layout information by the automated process mechanism. In an exemplary embodiment, the method of the present invention further includes validating accuracy of the first layout information according to the second layout information. | 04-02-2009 |
| 20090089734 | METHOD FOR FASTER IDENTIFICATION OF AVAILABLE REFERENCE DESIGNATORS IN A DESIGN AUTOMATION SYSTEM - A method, system, and computer program product for a faster identification of available reference designators (ARDs) in a design automation system. An ARD utility detects a selection of one or more selected component types for placement on a circuit schematic. A list containing one or more unavailable reference designators (URDs) is sorted through to identify one or more ARDs from the list of URDs. A list of ARDs is then generated, from which a pre-determined portion of ARDs are reserved. The reserved list of ARDs is then outputted for selection by a user. | 04-02-2009 |
| 20090113369 | REGISTRY FOR ELECTRONIC DESIGN AUTOMATION OF INTEGRATED CIRCUITS - A method for registering constraints for EDA (Electronic Design Automation) of an IC (Integrated circuit) includes: associating a constraint with values for constraint identification that identify the constraint in an IC design; associating the constraint with values for constraint relationships that relate the constraint to at least one EDA application; saving the constraint identification values and the constraint relationship values in a constraint registry element; and providing an interface to a user for accessing values of the constraint registry element. | 04-30-2009 |
| 20090113370 | Layout designing method for semiconductor device and layout design supporting apparatus for the same - In a layout designing method of a semiconductor device, a first standard cell with a first well and a second standard cell with a second well are arranged. The first well and the second well are applied with different voltages, respectively. An empty cell is arranged in an area that a distance from the first well falls within a first distance. The second standard cell is moved such that the empty cell does not overlap with the empty cell, when the empty cell overlaps with the second well. | 04-30-2009 |
| 20090119633 | CAD APPARATUS AND PROGRAM USED IN THE SAME - A CAD apparatus is comprised of: input unit | 05-07-2009 |
| 20090132986 | CIRCUIT DESIGN ASSISTING APPARATUS, METHOD, AND PROGRAM - A circuit design assisting apparatus for assisting a layout tool in designing an integrated circuit that includes a circuit module having plural cells achieving a prescribed function. A cell connection information acquiring device is provided to acquire cell connection information that specifies connection counterparts to the plural cells and is used when auto layout is executed by the layout tool. A terminal designating device is provided to designate a terminal of the circuit module. A terminal connection information generation device is provided to generate terminal connection information that specifies connecting counterparts to the terminal. A buffer circuit addition determining device is provided to determine one of if a buffer circuit is additionally connected between the terminal and the counterpart and if the buffer circuit already connected to the terminal is replaced in accordance with the terminal connection information. | 05-21-2009 |
| 20090132987 | Method and system for the modular design and layout of integrated circuits - An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end application, each of the modular tiles being configured to perform a predetermined function and constructed to have approximately the same length and width dimensions. The modular tiles are used to form the IC in a standard IC fabrication process. In many implementations, physical layout of the IC does not include the step of routing. Capabilities also include configuring the modular tiles to have programmable performance parameters and configuring the modular tiles to cooperate usefully with one another based on a programmable parameter. | 05-21-2009 |
| 20090150847 | Logic circuit delay optimization - A method for modifying a logic circuit layout to optimize circuit propagation delays for improved circuit operation is presented. The layout includes multiple logic gates connected by conductive segments. An initial layout of a physical electronic logic circuit having the plurality of logic gates is input. A respective size is determined for each of the logic gates in accordance with the initial layout and a circuit propagation delay criterion. The circuit propagation delay criterion is a joint function of properties of at least some of the logic gates and at least some of the conductive segments. A modified logic circuit layout is output. The modified logic circuit layout includes a layout of the logic gates arranged in accordance with the initial layout, where each of the logic gates is modified according to the respective determined size, thereby to obtain a modification of the logic circuit layout incorporating an optimized circuit propagation delay. | 06-11-2009 |
| 20090164961 | Design Structure for a System For Controlling Access to Addressable Integrated Circuits - A design structure for a circuitry access system for controlling access to addressable circuit elements of an integrated circuit. The circuitry access system includes a first storage element having a first listing of unique identifiers each identifier representing one of the addressable circuit elements. A selector distinguishes a first subset of unique identifiers from the first listing. A second storage element receives and stores the first subset in an arrangement that does not include an indication of the absence of any unique identifier of the first thing that is not included in the first subset. An output of second storage element allows a user of the integrated circuit to access one or more of the addressable circuit elements corresponding to the first subset of unique identifiers. | 06-25-2009 |
| 20090164962 | Method of Reducing Crosstalk Induced Noise in Circuitry Designs - A method of reducing crosstalk induced noise in a physical circuit wiring design constructs a spatial vector for each interconnect wire segment in the physical circuit wiring design. The method compares the spatial vectors of said physical circuit wiring design and identifies any of the spatial vectors that are parallel to each other and have opposite directions. The method may identify all drivers and receivers in the physical circuit wiring design, and trace each interconnect line, starting with its driver, to determine a routed length from the driver to each segment break point of the interconnect line. The method may construct the spatial vector by defining an origin in the physical circuit wiring design. The method determines a starting point and an ending point of the spatial vector with respect to the origin. The starting point of the spatial vector is the break point of the interconnect wire segment closer to the driver. The ending point of the spatial vector is the break point of the interconnect wire segment farther from the driver. The method may define a Cartesian coordinate system with respect to the origin. The Cartesian coordinate system may be orthogonal with the interconnect wire segments of the physical circuit wiring design. The method may define one or more geometry windows in the physical circuit wiring design and compare the spatial vectors in each geometry window. | 06-25-2009 |
| 20090172626 | METHOD AND SYSTEM FOR VISUAL IMPLEMENTATION OF LAYOUT STRUCTURES FOR AN INTEGRATED CIRCUIT - The present approach is directed to an improved method, system, and computer program product for visually presenting layout options for generating an electronic design. The visual presentation could be employed to display a set of layout choices when correcting errors or rules violations identified in the design. Alternatively, the visual presentation could be employed to display layout choices during the initial design entry phase for the electronic design. | 07-02-2009 |
| 20090172627 | Design Structure for a Clock System for a Plurality of Functional Blocks - A design structure for a clock system for a plurality of functional blocks designed using a method of reducing peak power that utilizes connectivity and/or timing information among a plurality of design partitions of an integrated circuit system to create a clock system that reduces peak power consumption across the system. The method used to create the design structure includes sorting the design partitions according to a connectivity model, a timing model, or both, and assigning interleaved clock signals as a function of the design partition ordering. The clock system is created as a function of the interleaved clock signals. | 07-02-2009 |
| 20090183133 | TOOL AND METHOD TO GRAPHICALLY CORRELATE PROCESS AND TEST DATA WITH SPECIFIC CHIPS ON A WAFER - A tool and method is provided to graphically correlate process and test data with specific chips on a multi-project wafer. The tool and method is configured and implemented to select certain sites and export these sites to an industry standard map that can be used in a variety of chip picking or test tools. In one embodiment, the method includes importing a wafer floor plan with chips of different design parameters and importing manufacturing logistical information of the chips. The method further includes graphically rendering each chip on the wafer to scale within a unit cell using the imported wafer floor plan and the manufacturing logistical information. | 07-16-2009 |
| 20090183134 | DESIGN STRUCTURE FOR IDENTIFYING AND IMPLEMENTING FLEXIBLE LOGIC BLOCK LOGIC FOR EASY ENGINEERING CHANGES - A design structure for identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. | 07-16-2009 |
| 20090187871 | Hierarchical Compression For Metal One Logic Layer - A method of increasing hierarchy compression of a metal | 07-23-2009 |
| 20090199147 | LAYOUT DATA REDUCTION FOR USE WITH ELECTRONIC DESIGN AUTOMATION TOOLS - A system and method which stores a three dimensional physical representation of an electrical circuit such as an integrated circuit design uses a database having a plurality of files to store active trace data and inactive feature data (layout data). The data from each file can be cross mapped with schematic data. A netlist or some other correlation method can be used to correlate the data from each of the individual files such that the leads of the layout data are correlated to leads from a schematic to maintain compatibility between the netlist and the layout data. Segmenting data into individual files decreases load times while correlating data with the netlist ensures electrical data is valid and suitable for characterization and optimization of the layout data. Various other embodiments are also described. | 08-06-2009 |
| 20090199148 | Pattern-producing method for semiconductor device - Disclosed is a method of producing a pattern for a semiconductor device, comprising extracting part of a pattern layout, perturbing a pattern included in the part of the pattern layout to generate a perturbation pattern, correcting the perturbation pattern, predicting a first pattern, to be formed on a wafer, from the corrected perturbation pattern, acquiring a first difference between the perturbation pattern and the first pattern, and storing information concerning the perturbation pattern including information concerning the first difference. | 08-06-2009 |
| 20090210845 | COMPUTER PROGRAM PRODUCT, APPARATUS, AND METHOD FOR INSERTING COMPONENTS IN A HIERARCHICAL CHIP DESIGN - Components are inserted into a cell-based current chin design with multiple levels of nested hierarchy. A selection of components having various silicon densities to insert into the current chip design is received. The components are inserted into the current chip design such that the components do not touch or overlap existing circuits or silicon shapes in the current chip design. The components are inserted such that components having highest silicon densities are placed further away from the existing circuits or silicon shapes than components having lower silicon densities. | 08-20-2009 |
| 20090210846 | I/O PLANNING WITH LOCK AND INSERTION FEATURES - A method of operation for an input/output assignment tool is disclosed. The method generally includes the steps of (A) generating a graphic presentation to a user displaying (i) a circuit icon having a plurality of pin icons and (ii) a plurality of signal icons, (B) moving a first of the signal icons within the graphic presentation to a first of the pin icons in response to a move command from the user and (C) indicating an acceptance of an association between the first signal icon and the first pin icon in response to the association passing a rule. | 08-20-2009 |
| 20090300570 | INTERACTIVE HIERARCHICAL ANALOG LAYOUT SYNTHESIS FOR INTEGRATED CIRCUITS - In one embodiment of the invention, a method of synthesizing a layout of an integrated circuit chip including analog circuitry is disclosed. The method includes receiving a circuit netlist of an integrated circuit chip including analog circuitry; representing and manipulating a hierarchical analog circuit layout including device placement and net routing in response to the circuit netlist, the hierarchical analog circuit layout including a plurality of levels of layout hierarchy; and passing layout information from one level of the layout hierarchy to an adjacent level of the layout hierarchy to synthesize the layout of the integrated circuit chip. In response to user preference directives, methods and apparatus are disclosed to perform re-synthesis of analog circuit layouts in another embodiment of the invention. | 12-03-2009 |
| 20090319976 | METHOD AND SYSTEM PERFORMING CIRCUIT DESIGN PREDICTIONS - Disclosed is a method, system, and computer program product for performing predictions for an electronic design. Embodiments of the invention allow the ability to efficiently update the model predictions at a later time once previously incomplete blocks are completed. Predictions can be efficiently updated after block designs are updated (e.g. after correcting problems detected from model predictions). | 12-24-2009 |
| 20090327988 | METHODS, SYSTEMS AND COMPUTER PROGRAM PRODUCTS FOR LAYOUT DEVICE MATCHING DRIVEN BY A SCHEMATIC EDITOR - Systems and computer program products for layout device matching driven by a schematic editor. Exemplary embodiments include identifying a master device in a circuit layout having at least transistors, the master device having property values including at least one of topology, name and device-type, identifying a cloned device linked to the master device, automatically propagating the property values to the cloned device, making changes to a design layout of the master device, including a change to the properties, and automatically propagating the changes to the design layout and the change to the properties of the master device to the cloned device. | 12-31-2009 |
| 20100005438 | PROCESSING METHOD. PROCESSING EQUIPMENT, PROGRAM AND COMPUTER-READABLE STORAGE MEDIUM - Designing operation efficiency is improved by automatically transmitting and receiving circuit-related information and layout-related information required for designing each printed board between printed boards, for designing a plurality of printed boards at the same time. In an electric information processing method in a CAD system, the printed boards are designed at the same time by transmitting and receiving the circuit design information relating to the printed boards and the layout design information relating to the printed boards between the circuits and layouts relating to the printed boards. | 01-07-2010 |
| 20100011334 | METHOD AND SYSTEM FOR DESIGNING A PROBE CARD - A method and system for designing a probe card from data provided by prospective customers via the Internet is provided. Design specifications are entered into the system by prospective customers and compiled into a database. The collective feasibility of each set of design specifications is determined by an automated computer system and communicated to the prospective customer. If feasible, additional software enables prospective customers to create verification packages according to their respective design specifications. These verification packages further consist of drawing files visually describing the final design and verification files confirming wafer bonding pad data. Verification packages are reviewed and forwarded to an applications engineer after customer approval. An interactive simulation of probe card performance is also provided. Data on probe card performance is incorporated into an overall modeling exercise, which includes not only the probe card, but data on the device(s) under test and wafer, as well as data on automated test equipment. | 01-14-2010 |
| 20100115486 | ASSIST FEATURE PLACEMENT BASED ON A FOCUS-SENSITIVE COST-COVARIANCE FIELD - One embodiment of the present invention provides a system that determines an assist feature placement within a post-optical proximity correction (post-OPC) mask layout. During operation, the system receives a set of target patterns which represent a set of polygons in a pre-OPC mask layout. The system then constructs a focus-sensitive cost function based on the target patterns, wherein the focus-sensitive cost function represents an amount of movement of post-OPC contours of the target patterns in response to changes in focus condition of the lithography system. Note that the contours of the target patterns substantially coincide with the edges of set of the polygons. Next, the system computes a cost-covariance field (CCF field) based on the focus-sensitive cost function, wherein the CCF field is a two-dimensional (2D) map representing changes to the focus-sensitive cost function due to an addition of a pattern at a given location within the post-OPC mask layout. Finally, the system generates assist features for the post-OPC mask layout based on the CCF field. | 05-06-2010 |
| 20100162194 | Method for Selectively Enlarging Via and Contact Sizes - A method and system for improving the yield of integrated devices is invented by adaptively selecting contact and via sizes. According to this invention, the drawn size of via holes in a design layout is selected based on its neighboring layout geometries. The invention comprises identifying the minimal space required for placing a via; analyzing available free space for potential via size increase; identifying the proximity configuration of the via with other vias on the via layer; selecting an appropriate via size based on the free space and proximity configuration to create an improved design layout; and fabricate the new layout with model based proximity correction such that vias of a plurality of sizes are reproduced on silicon within predetermined tolerances. | 06-24-2010 |
| 20100180248 | ELECTRIC INFORMATION PROCESSING METHOD IN CAD SYSTEM, DEVICE THEREOF, PROGRAM, AND COMPUTER READABLE STORAGE MEDIUM - It is possible to improve workability of a design work by handling electric information between one object and other objects associated with the object. A plurality of objects are inputted and electric information is inputted to the objects. Among the objects, mutually connected objects are virtually made into a single object. According to electric information in each of the objects, i.e., the virtually unified single object and the other objects excluding the virtually unified single object, objects having the common electric information are connected by straight lines. According to the straight lines, a figure connecting the objects is inputted. A condition for connecting the objects in the figure is inputted. According to the condition, circuit parts are built and signal information is set in a terminal of the circuit parts. | 07-15-2010 |
| 20100199249 | Programmable analog tile placement tool - A programmable analog tile integrated circuit placement tool allows a user to manipulate a graphical representation of a first power management integrated circuit (PMIC) tile with respect to a graphical representation of a second PMIC tile in a proposed Multi-Tile Power Management Integrated Circuit (MTPMIC). The novel PMIC tiles have pre-defined physical structures including a bus portion and a memory structure for storing configuration information for configuring the tile. When appropriately placed in a MTPMIC, the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. A remote user with minimal training in analog circuit design may command the placement of individual tiles in a proposed MTPMIC layout. Upon receiving a user response indicating satisfaction with the placement of PMIC tiles, the tool quickly and automatically generates physical layout data suitable for fabrication of the MTPMIC. | 08-05-2010 |
| 20100199250 | Analog tile selection, placement, configuration and programming tool - An Analog Tile Selection, Placement, Configuration and Programming (ATSPCP) tool communicates a power management characteristic query over a network. The query is displayed to a user on a webpage. The query is a solicitation for desired characteristics of a Power Management Integrated Circuit (PMIC). After receiving user requirements in a response to the query, the tool selects a number of power management integrated circuit tiles having pre-defined physical structures. The pre-defined structure of each tile includes a bus portion and a memory structure for storing configuring information for the tile. When combined in a Multi-Tile Power Management Integrated Circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC that meets the user requirements. The ATSPCP tool combines the physical layout data of each selected PMIC tile to form composite physical layout data for the overall MTPMIC. | 08-05-2010 |
| 20100199251 | Heuristic Routing For Electronic Device Layout Designs - Various implementations of the invention provide a method for dynamically determining a layer bias. In various implementations, the layer bias may be employed to determine placement locations for a trace within an electrical device layout design. The trace providing for the electrical connection of components or pins within the layout design. With various implementations of the invention, a layer within the layout design is partitioned into regions, selected regions having a bias. As events or alterations to the layout design occur, the corresponding bias for the selected regions is updated to reflect any changes in bias occurring due to the event or alteration. With other implementations of the invention, processes, machines, or manufactures are provided that dynamically determine a layer bias. The dynamically determined layer bias may be incorporated into a layer bias heuristic employed by for example, an automated trace routing tool. | 08-05-2010 |
| 20100205575 | Methods, Systems, and Computer-Program Products for Item Selection and Positioning Suitable for High-Altitude and Context Sensitive Editing of Electrical Circuits - Disclosed are methods, systems, computer program products for editing electrical circuits that facilitate and speed the layout of electrical circuits. Embodiments disclosed herein provide high-altitude editing capabilities to the user that enable the user to more easily select circuit items in congested layouts and schematic diagrams, and modify and arrange circuit items with respect to one another in congested layouts and schematic diagrams. Additional embodiments disclosed herein are directed to enabling EDA commands and the like to have context sensitivity, neighborhood awareness, and/or an ability to anticipate intentions of the user. | 08-12-2010 |
| 20100218156 | SYSTEM AND METHOD FOR COMPRESSED POST-OPC DATA - According to various embodiments of the invention, systems and methods for system and methods for compressed post-OPC data created during the design and manufacturing of integrated circuits. In one embodiment of the invention, the method begins by generating a post-OPC layout from a circuit layout during the design phase of a circuit. This post-OPC layout is generated by way of an OPC process. Next, a set of differences between the post-OPC layout and the circuit layout are calculated and a dataset containing these differences are generated In some embodiments the dataset is generated during the OPC process. | 08-26-2010 |
| 20100223587 | EFFICIENT CHIP ROUTING METHOD AND APPARATUS FOR INTEGRATED CIRCUIT BLOCKS WITH MULTIPLE CONNECTIONS - Methods and apparatuses are disclosed for improving the speed of chip routing for integrated circuit blocks with multiple connections. In some embodiments, the method may include creating a layout abstract for a first block and a second block of the integrated circuit, where the first and second blocks are coupled together via a plurality of connections. The method may further include determining whether the number of connections in the plurality exceeds a threshold, and in the event that the number of connections exceeds the predetermined threshold, representing a first subset of the plurality as a first logical connection. | 09-02-2010 |
| 20100229143 | DETECTION AND REMOVAL OF HAZARDS DURING OPTIMIZATION OF LOGIC CIRCUITS - A method of generating a hazard-free representation of a logic circuit that can leverage the powerful and mature synchronous-circuit CAD synthesis tools. In a representative embodiment of the method, an initial representation of a specified asynchronous logic circuit is synthesized using one of such CAD tools. The initial representation is then analyzed to identify hazardous transitions and modified, e.g., by iteratively inserting additional logic aimed at preventing the identified hazardous transitions from producing glitches, until a hazard-free representation of the specified asynchronous logic circuit is produced. | 09-09-2010 |
| 20100235801 | METHOD AND APPARATUS FOR ACCELERATING PROJECT START AND TAPE-OUT - Some embodiments of the present invention provide systems and techniques that accelerate project start and tape-out. During operation, a system can receive a set of technology files and a set of libraries. Next, the system can identify deficiencies in the set of technology files and the set of libraries. The system can then construct update utilities that when executed by a computer system cause the computer system to fix the deficiencies in the technology files and the set of libraries. Further, a system can receive a set of checks that are performed by a foundry. Next, the system can construct tape-out scripts that when executed by a computer cause the computer to perform the set of checks on the circuit design. The update utilities and the tape-out scripts can then be provided to a customer with an electronic design automation software to accelerate project start and tape-out. | 09-16-2010 |
| 20100251198 | METHOD FOR EXTRACTING INFORMATION FOR A CIRCUIT DESIGN - The present disclosure is directed to a method for extracting information for a circuit design. The method may utilize an incremental extraction process for extracting information for a portion of the circuit design. Extracted results of this portion may be merged with a previously extracted result to obtain an integrated result that is equivalent to that of extracting the entire circuit design. The incremental extraction process may identify a set of changed shapes, a set of affected shapes, and a set of involved shapes for extraction. The method may also divide the circuit design into a plurality of regions, wherein two or more regions may be processed in parallel. | 09-30-2010 |
| 20100269082 | SYSTEMS AND METHODS FOR LITHOGRAPHY-AWARE FLOORPLANNING - The present invention is directed towards designing integrated circuit and provides systems and methods for lithography-aware floorplanning. According to one embodiment of the invention, a method for circuit floorplanning is provided. The method comprises generating a floorplan through a floorplanner, performing a lithography-analysis within the floorplanner on at least a portion of the floorplan, and generating one or more violations that result from the lithography-analysis. Some embodiment, in addition to viewing a floorplan, further comprise of modifying the floorplan. Furthermore, some embodiments provide a method that further comprises fixing the violations that result from the lithography analysis. | 10-21-2010 |
| 20100269083 | Method of Employing Slew Dependent Pin Capacitances to Capture Interconnect Parasitics During Timing Abstraction of VLSI Circuits - A method for converting interconnect parasitics of an interconnect network into slew dependent pin capacitances utilizes charge matching between predetermined voltage thresholds. During timing abstraction of a macro, parasitics of interconnects connected to the primary inputs are represented as slew dependent pin capacitances in an abstract model being created. Interconnect model order reduction is employed to speed the process. The generated abstract is subsequently used in place of each occurrence of the macro during chip level hierarchical static timing analysis, leading to an enhanced accuracy of the timing analysis of the logic components driving the abstracts. | 10-21-2010 |
| 20100275173 | Model For a Hardware Device-Independent Method of Defining Embedded Firmware for Programmable Systems - A processing device programming system automatically provides a user interface comprising a selectable list of one or more processing devices based on a system level solution, automatically generates an embedded programmable system solution from the system level solution and a processing device selected from the selectable list of one or more processing devices, and automatically programs the processing device according to the embedded programmable system solution. | 10-28-2010 |
