| Entries |
| Document | Title | Date |
|---|
| 20080209378 | METHOD AND SYSTEM FOR PROTOTYPING ELECTRONIC DEVICES WITH MULTI-CONFIGURATION CHIP CARRIERS - A solution for prototyping electronic devices is proposed. The solution uses a carrier which allows mounting the desired components with different configurations. In order to achieve this result, for some of these components, such as discrete capacitors, the carrier includes more contacts than the corresponding terminals. In this way, each capacitor may be mounted in multiple positions (such as a working one based on the manufacturing standards, an advanced one with gaps between the components below the corresponding safety margins, and as control one with larger gaps). As a result, it is possible to assemble different prototypes by using a single type of carrier, thereby substantially reducing the cost of the process. | 08-28-2008 |
| 20080209379 | Method of designing semiconductor integrated circuit, design device, and CAD program - A semiconductor integrated circuit design device capable of carrying out design by evaluating a crosstalk between blocks has been disclosed. The integrated circuit design device is adapted to design a semiconductor integrated circuit having a plurality of blocks and comprises a virtual noise source setting PORTION that sets a virtual noise source at a neighboring boundary with a neighboring block of each block, a block design PORTION that carries out design of each block while taking into consideration influence from the virtual noise source, and an assembly design PORTION that assembles the plurality of the designed hierarchical blocks. | 08-28-2008 |
| 20080209380 | DEVICE AND METHOD FOR HIGH-LEVEL SYNTHESIS - A high-level synthesis unit creates a first register transfer level circuit from an operation level description. A circuit creating unit creates a second register transfer level circuit based on circuit information for creating an additional circuit to be added to the first register transfer level circuit. A circuit connecting unit connects the first register transfer level circuit with the second register transfer level circuit, based on connecting information describing a connecting relation between a signal in the first register transfer level circuit and a signal in the second register transfer level circuit. | 08-28-2008 |
| 20080209381 | SHALLOW TRENCH ISOLATION DUMMY PATTERN AND LAYOUT METHOD USING THE SAME - A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed. | 08-28-2008 |
| 20080216040 | Incremental Relative Slack Timing Force Model - Simultaneous Dynamical Integration modeling techniques are applied to global placement of elements of integrated circuits as described by netlists specifying interconnection of morphable-devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through a continuous location space in continuous time, and is used to derive placements of the morphable-devices having one-to-one correspondences with the nodes. Nodes under the influence of net attractive forces, computed based on the interconnections between the morphable devices, tend to coalesce into well-organized topologies. Nodes are also affected by spreading forces determined by density fields that are developed based on local spatial node populations. | 09-04-2008 |
| 20080216041 | Integrated circuit simulation method considering stress effects - Provided is an integrated circuit (IC) simulation method which can predict the operation and performance of an IC considering stress effects that affect the characteristics of unit devices included in the IC. The method includes drawing out a first net list of unit devices included in a designed IC; preparing a layout of the designed IC; extracting a stress parameter from the layout of the designed IC; and drawing out a second net list of the first net list and the stress parameter. | 09-04-2008 |
| 20080222588 | Method and program for designing semiconductor device - A method of designing a semiconductor device is provided. According to the method, a group of cells that is a target of clock distribution is placed. After the group of cells is placed, a plurality of clock driver cells for driving the clock are placed such that each clock driver cell is prohibited from overlapping with a prohibited region of a predetermined size surrounding another clock driver cell. | 09-11-2008 |
| 20080235644 | Semiconductor integrated circuit with multi-cut via and automated layout method for the same - A semiconductor integrated circuit according to an embodiment of the invention includes a single-cut via | 09-25-2008 |
| 20080244491 | Generic methodology to support chip level integration of IP core instance constraints in integrated circuits - A method and apparatus are provided for generating and using timing constraints templates for IP cores that can be instantiated in an integrated circuit design. The templates include a plurality of timing constraint statements for inputs and outputs of the respective IP core. At least one of the statements includes a configurable variable, wherein the timing constraints template is configurable through the variable for each of a plurality of instances of the IP core in the integrated circuit design. | 10-02-2008 |
| 20080244492 | APPARATUS AND METHOD FOR DESIGNING SYSTEM, AND COMPUTER READABLE MEDIUM - There is provided with a designing apparatus, including: an input accepting unit configured to accept an input of design description which describes a design of a system that includes components and a plurality of channels each of which connects between components communicating with each other; component constraint description which describes constraints that should be met by respective components; channel constraint description which describes constraints that should be met by respective channels; a connection constraint description calculator configured to calculate connection constraint description which describes constraints that should be met between components connected by each channel: a specifying unit configured to specify communication medium or communication protocol to be used in the system; an overall constraint description calculator configured to calculate overall constraint description which describes constraints that should be met between all of the components. | 10-02-2008 |
| 20080250375 | Detailed Placer For Optimizing High Density Cell Placement In A Linear Runtime - A detailed placement process which optimizes cell placement with up to one hundred percent densities in a linear run time. The output from a conjugate-gradient coarse placement process is input to the detailed placement process. A dynamic programming technique is used to optimize cell placement by swapping cells between two or more rows. The search space is pruned beforehand. A greedy cleanup phase using an incremental row placer is used. Thereby, the detailed placement process handles congestion driven placements characterized by non-uniform densities expeditiously and efficiently. | 10-09-2008 |
| 20080263492 | 3-Dimensional Device Design Layout - A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area. | 10-23-2008 |
| 20080270965 | METHOD OF REDUCING PEAK POWER CONSUMPTION IN AN INTEGRATED CIRCUIT SYSTEM - A method that utilizes connectivity and/or timing information among a plurality of design partitions of an circuit system to create a clock system that reduces peak power consumption across the system. The method includes sorting the design partitions according to a connectivity model, a timing model, or both, and assigning interleaved clock signals as a function of the design partition ordering. The clock system is created as a function of the interleaved clock signals. | 10-30-2008 |
| 20080276212 | OPTIMIZING INTEGRATED CIRCUIT DESIGN THROUGH BALANCED COMBINATIONAL SLACK PLUS SEQUENTIAL SLACK - A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow. | 11-06-2008 |
| 20080282212 | SYSTEM AND METHOD ENABLING CIRCUIT TOPOLOGY RECOGNITION WITH AUTO-INTERACTIVE CONSTRAINT APPLICATION AND SMART CHECKING - A computer implemented method is provided for interactive application of constraints to sub-circuits in a circuit design stored in a computer readable medium, comprising: receiving from a first designer a selection of a sub-circuit; receiving from the first designer a constraint; producing an information structure in computer readable medium that associates a graph representing a topology of the selected sub-circuit with the received constraint; using the graph to identify sub-circuit instances in the circuit design having the same topology as the selected sub-circuit; receiving from a second designer a selection of the information structure; presenting to the second designer one or more of the identified sub-circuit instances and the received constraint; and receiving from the second designer instruction as to application of the received constraint to one or more of the presented sub-circuit instances. | 11-13-2008 |
| 20080301612 | Method and System for Placement of Electric Circuit Components in Integrated Circuit Design - The invention relates to a method and a system for placing electric circuits in integrated circuit chip design. Specifically, the invention encompasses performing a global placement step ( | 12-04-2008 |
| 20080307380 | Operational Cycle Assignment in a Configurable IC - Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. For at least a first set of operations that has a start operation and an end operation, the method assigns a particular operation in the first set to a first operational cycle based at least partially on the position of the particular operation with respect to the start and end operations. | 12-11-2008 |
| 20080313591 | SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING METHOD - An IC designing method includes planning placement of a first isolated-power supplied region operating between common ground and power bus lines during a normal operation, and second/third isolated-power supplied regions each operating between the common ground bus line and first/second isolated power lines and supplied with potentials different from the common power supply, planning placement of first electrostatic protection circuits connected between the common ground power bus lines and between the common ground bus line and the first/second isolated power lines, and second electrostatic protection circuits connected between the first/second isolated power lines and the common power bus lines, judging presence of a signal transmission between non-adjacent regions among the first to third isolated-power supplied regions, and amending the circuit to insert a buffer circuit powered by the common power bus line in a transmission path when the signal transmission is present. | 12-18-2008 |
| 20080320428 | Minimizing Effects of Interconnect Variations in Integrated Circuit Designs - Roughly described, method and apparatus for laying out an integrated circuit, in which a subject interconnect has predetermined values for a plurality of variables affecting propagation delay of the subject interconnect. The value of an adjustment one of the variables is adjusted to minimize exposure of the propagation delay of the interconnect to process variations causing variations in the value of a subject fabrication variable, and a revised layout is developed in dependence upon the adjusted value for the adjustment variable. In an embodiment, the adjustment is made in dependence upon a pre-calculated “interconnect optimization database” indicating combinations of values for the plurality of variables which have been pre-determined to minimize exposure of interconnect propagation delay to process variations affecting the subject variable. Different databases, or different entries in the same database, can be provided for minimizing exposure of interconnect propagation delay to process variations affecting each subject variable of interest. | 12-25-2008 |
| 20090007044 | Design support method and apparatus, and computer product - A design support apparatus includes an extracting unit that extracts a first cell from among plural cells in a target circuit; a detecting unit that detects a second cell arranged adjacent to the first cell; and a setting unit that sets a delay value of the first cell according to an arrangement pattern of the second cell. | 01-01-2009 |
| 20090007045 | METHOD OF DESIGNING A SEMICONDUCTOR DEVICE - Aiming at providing a method of designing a semiconductor device capable of producing a semiconductor device which expresses performances adapted to required performances, the present invention sets a plurality of suites of device parameters, containing parameters relevant to transistor characteristics (transistor parameters) and parameters relevant to interconnect characteristics (interconnect parameters) corresponded to the transistor characteristics, for a single CMOS generation, selecting, out of the plurality of suites, a suite matched to performances required for a semiconductor to be designed, and designing the semiconductor device. | 01-01-2009 |
| 20090013295 | METHOD FOR ARRANGING VIRTUAL PATTERNS - A method for arranging virtual patterns includes providing a semiconductor layout and a circuit pattern; setting a forbidden area of the circuit pattern according to a restriction condition; defining at least a virtual pattern arrangement area on a portion of the semiconductor layout which does not correspond to the forbidden area; and providing a virtual pattern array in the virtual pattern arrangement area. | 01-08-2009 |
| 20090013296 | Layout design method for a semiconductor integrated circuit - A method of designing a layout of a semiconductor integrated circuit having a hard macro includes acquiring a condition for permitting wirings with respect to a given region within the hardmacro, and searching a passing wiring that passes through the given region among the wirings that are arranged 6n the semiconductor integrated circuit. The method further includes allowing a normal passing wiring that satisfies the condition to pass through the hardmacro, and wiring a defaulting passing wiring that does not satisfy the condition so as to bypass the hard macro among the searched passing wirings. | 01-08-2009 |
| 20090013297 | CONTACT RESISTANCE AND CAPACITANCE FOR SEMICONDUCTOR DEVICES - A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are selected. The selected critical cells are altered with respect to contact resistance and/or contact capacitance. The map including the altered cells is provided as the design layout. | 01-08-2009 |
| 20090031270 | Design Method and System for Minimizing Blind Via Current Loops - A design method and system for minimizing blind via current loops provides for improvement of electrical interconnect structure design without requiring extensive electromagnetic analysis. Other vias in the vicinity of a blind via carrying a critical signal are checked for suitability to conduct return current corresponding to the critical signal that is disrupted by the transition from a layer between two metal planes to another layer. The distance to the return current via(s) is checked and the design is adjusted to reduce the distance if the distance is greater than a specified threshold. If the blind via transition is to an external layer, suitable vias connect the reference plane at the internal end of the blind via to an external terminal. If the transition is between internal layers, suitable vias are vias that connect the two reference planes surrounding the reference plane traversed by the blind via. | 01-29-2009 |
| 20090031271 | ROBUST DESIGN USING MANUFACTURABILITY MODELS - The present invention allows for a robust design using manufacturability models. A method, system and/or computer usable medium may be provided in an integrated circuit design to track sensitivity to a variation of process from wafer to wafer and/or fab to fab in order to assist the designers to anticipate the variations to improve the final yield of the products. | 01-29-2009 |
| 20090055789 | METHODS AND SYSTEMS FOR COMPUTER AIDED DESIGN OF 3D INTEGRATED CIRCUITS - Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed. | 02-26-2009 |
| 20090070722 | METHOD FOR GENERATING DEVICE MODEL OVERRIDES THROUGH THE USE OF ON-CHIP PARAMETRIC MEASUREMENT MACROS - A method generates area dependent design rules during semiconductor technology qualification by identifying the layout parametric variation in a semiconductor technology and establishing layout dependent design rules. This method applies the area dependent design rules to identify design sensitivity to area dependent design rules and to optimize semiconductor libraries and/or semiconductor products using an on-chip parametric monitor by designing processes for library elements, semiconductor design systems, and/or custom semiconductor products using the layout dependent design rules. | 03-12-2009 |
| 20090077517 | Semiconductor intergrated device and apparatus for designing the same - A semiconductor integrated device includes a plurality of power system circuit units, a first circuit unit | 03-19-2009 |
| 20090106725 | METHOD AND APPARATUS FOR COMPUTING DUMMY FEATURE DENSITY FOR CHEMICAL-MECHANICAL POLISHING - One embodiment of the present invention provides a system that computes dummy feature density for a CMP (Chemical-Mechanical Polishing) process. Note that the dummy feature density is used to add dummy features to a layout to reduce the post-CMP topography variation. During operation, the system discretizes a layout of an integrated circuit into a plurality of panels. Next, the system computes a feature density and a slack density for the plurality of panels. The system then computes a dummy feature density for the plurality of panels by, iteratively, (a) calculating an effective feature density for the plurality of panels using the feature density and a function that models the CMP process, (b) calculating a filling amount for a set of panels in the plurality of panels using a target feature density, the effective feature density, and the slack density, and (c) updating the feature density, the slack density, and the dummy feature density for the set of panels using the filling amount. In one embodiment of the present invention, the iterative process is guided by a variance-minimizing heuristic to efficiently select the set of panels and assign/remove dummy density to the set of panels to decrease the effective feature density variation. | 04-23-2009 |
| 20090113368 | FILLER CELLS FOR DESIGN OPTIMIZATION IN A PLACE-AND-ROUTE SYSTEM - A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell. | 04-30-2009 |
| 20090119632 | METHOD FOR SUPPORTING DETERMINATION OF DESIGN PROCESS ORDER - A system and method which support determination of a design process order. The system includes: a storage device that stores constraint data indicating a strength of a constraint that is given to a respective design process from a respective of the other design processes; a detection unit that accesses the storage device to detect, from the constraint data, a loop of relationships concerning a design process receiving a constraint from another design process; a selection unit that accesses the storage device to select, from the detected loop, a pair capable of canceling the loop when the pair is deleted and having a minimum total constraint strength; and an output unit that deletes the selected constraint pair from the constraint data and outputs data indicating a constraint that is to be satisfied by each design process. | 05-07-2009 |
| 20090132985 | Design structure for on-chip electromigration monitoring system - A design structure embodied in a machine readable medium used in a design process can include apparatus of a semiconductor chip operable to detect an increase in resistance of a monitored element of the semiconductor chip. The design structure can include, for example, a resistive voltage divider circuit operable to output a plurality of reference voltages having different values. A plurality of comparators in the semiconductor chip may be coupled to receive the reference voltages and a monitored voltage representative of a resistance of the monitored element. Each of the comparators may produce an output indicating whether the monitored voltage exceeds the reference voltages, so that the resistance value of the monitored element may be precisely determined. | 05-21-2009 |
| 20090144686 | METHOD AND APPARATUS FOR MONITORING MARGINAL LAYOUT DESIGN RULES - A method includes generating a layout for an integrated circuit device in accordance with a plurality of layout design rules. A plurality of metrology sites on the layout associated with at least one subset of the layout design rules is identified. A metrology tag associated with each of the metrology sites is generated. At least one metrology recipe for determining a characteristic of the integrated circuit device is generated based on the metrology tags. Metrology data is collected using the at least one metrology recipe. A selected layout design rule in the at least one subset is modified based on the metrology data. | 06-04-2009 |
| 20090144687 | Layout design method of semiconductor integrated circuit by using soft macro - A layout design method of a semiconductor integrated circuit to be formed in an integrated circuit (IC) chip is provided. The layout design method includes reading a netlist and a soft macro. The soft macro includes: relative position information describing relative positions of a plurality of relative arrangement position determined cells; and wiring information describing positions of arrangement position determined wiring lines arranged in corresponding to the plurality of relative position determined cells. The layout design method further includes: determining coordinates of the plurality of relative arrangement position determined cells in the IC chip based on the relative position information; determining wiring routes of the arrangement position determined wiring lines in the IC chip based on the coordinates and the wiring information; and determining an arrangement position of an arrangement position undetermined cell in the IC chip. The arrangement position undetermined cell is a cell of which arrangement position in the IC chip is undetermined in advance. | 06-04-2009 |
| 20090158231 | Design Structure for a Redundant Micro-Loop Structure for use in an Integrated Circuit Physical Design Process and Method of Forming the Same - A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via. | 06-18-2009 |
| 20090164959 | Layout design device and layout design method of semiconductor integrated circuit - A layout design device includes a calculation processing portion that calculates a degree of wire congestion of each layer based on a pre-wiring design data to form a desired wiring structure in each layer, a selection processing portion that selects one area from a plurality of areas as a selection area, and an adding processing portion that generates a post-addition design data by adding a design data which connects the power supply and ground including layer and the (n−1)th layer or the (n+1)th layer to the pre-wiring design data. A degree of wire congestion of the selection area of nth layer is lower than that of (n−1)th layer or (n+1)th layer, the selection processing portion selects a power supply and ground including layer which is a lower layer of the (n−1)th layer or an upper layer of the (n+1)th layer and has a power supply or a ground. A wiring process and a metal generating process are performed based on the post-addition design data. | 06-25-2009 |
| 20090164960 | SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN SYSTEM, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN METHOD, AND COMPUTER READABLE MEDIUM - A semiconductor integrated circuit design method has extracting connection-permitted patterns which are permitted to connect to each other in a layout pattern, disconnection-permitted patterns which exercise no effect on a circuit operation even when disconnected in the layout pattern, and a multicut via which suffices when connection is made to at least one via thereof in the layout pattern, by using a net list and a cell library; conducting LRC (Lithography Rule Check) processing on the layout pattern to which a correction pattern resulting from OPC (Optical Proximity Correction) processing is added, and detecting an error part; and judging the error part either as a false error when the error part is included in the connection-permitted patterns, the disconnection-permitted patterns, or the multicut via extracted, or as a true error when the error part is not included in the connection-permitted patterns, the disconnection-permitted patterns, or the multicut via extracted, and making a pattern correction to the error part when the error part is judged as the true error. | 06-25-2009 |
| 20090172625 | METHOD AND MECHANISM FOR PERFORMING CLEARANCE-BASED ZONING - A method and mechanism is disclosed for identifying spacing and clearance based rule violations in an IC design. Shadows are employed to identify spacing and clearance based rule violations. The shadow approach of is particularly useful to identify width-dependent spacing and clearance violations, while avoiding false positives that exist with alternate approaches. The embodiments can be used with any type, configuration, or shape of layout objects. | 07-02-2009 |
| 20090193378 | MODIFYING LAYOUT OF IC BASED ON FUNCTION OF INTERCONNECT AND RELATED CIRCUIT AND DESIGN STRUCTURE - Modifying a layout of an integrated circuit (IC) based on a function of an interconnect therein and a related circuit and design structure are disclosed. In one embodiment, a method includes identifying a function of an interconnect in the layout from data of the layout embodied in a computer readable medium; and modifying the layout to form another layout that accommodates the function of the interconnect. A design structure embodied in a machine readable medium used in a design process, according to one embodiment, may include a circuit including a high voltage interconnect positioned in a dielectric layer, the high voltage interconnect positioned such that no fill is above or below the high voltage interconnect. | 07-30-2009 |
| 20090199146 | SYSTEM AND METHOD FOR EFFICIENT AND OPTIMAL MINIMUM AREA RETIMING - A method for use in electronic design software efficiently and optimally produces minimized or reduced register flip flop area or number of registers/flip flops in a VLSI circuit design without changing circuit timing or functionality. The method dynamically generates constraints; maintains the generated constraints as a regular tree; and incrementally relocates registers/flip flops and/or the number of registers/flip flops in the circuit design. | 08-06-2009 |
| 20090204933 | SINGLE EVENT TRANSIENT MITIGATION AND MEASUREMENT IN INTEGRATED CIRCUITS - A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements. Provision is made for applying the method to logic designs implemented in programmable logic integrated circuit devices. | 08-13-2009 |
| 20090210843 | Method of Automating Creation of a Clock Control Distribution Network in an Integrated Circuit Floorplan - The process of laying out a floorplan for a clock control distribution network in an integrated chip design is simplified and the efficiency of a staging network created is improved. Rather than manually create the staging network in HDL or as a network description table while looking at a picture of the chip floorplan in a Cadence Viewer, an automated method which runs in the Cadence environment uses an algorithmic approach to the problem of maximizing the utilization of staging latches, eliminating unnecessary power and area usage. Efficiency is maximized by updating the Physical Layout directly with the staging solution arrived at by the algorithm. | 08-20-2009 |
| 20090210844 | SYSTEMS AND METHODS INVOLVING DESIGNING INTEGRATED CIRCUITS - A system comprising, a processor operative to, receive a first input designating a first net segment profile on a first level in an integrated circuit for shielding, determine whether the designated first net segment profile is in electrical communication with other net segment profiles, determine whether the net segment profiles are located in a different level than the first net segment profile, define a first shielding profile corresponding to the net segment profiles on the first level, define a second shielding profile corresponding to the net segment profiles on the second level, determine and removing segments of the first shielding profile and the second shielding profile contact features of the integrated circuit, determine and removing segments of the first shielding profile and the second shielding profile are non-continuous, define vias at the intersections of first shielding profile and the second shielding profile, and a processor operative to display the output. | 08-20-2009 |
| 20090217228 | METHOD OF MAKING AN INTEGRATED CIRCUIT USING PRE-DEFINED INTERCONNECT WIRING - A method for configuring an integrated circuit including configuring a plurality cells to form a cell library, wherein configuring each cell includes defining intracell wiring in at least one layer positioned above a substrate, the intracell wiring connecting to structures below the at least one layer and forming one or more terminals, and defining one or more candidate wires for at least one terminal to use as pre-defined intercell wiring for connection to the at least one terminal. The method further includes arranging selected cells from the cell library to form a desired layout of an integrated circuit, and routing intercell wiring so as to interconnect the selected cells to achieve a desired function of the integrated circuit including using only selected candidate wires for intercell wiring within borders of each of the selected cells. | 08-27-2009 |
| 20090222783 | INTEGRATED CIRCUIT (IC) DESIGN METHOD, SYSTEM AND PROGRAM PRODUCT - A method of integrated circuit (IC) design, an IC design system and computer program product therefore, e.g., for L3GO designs. Special case cells are cells that represent specialized, process dependent components and are provided as dual representation cells with an internal view and external view. The external view is high level abstract representation that includes access pins, boundary and possible blocking shapes/layers and optionally, parameterizations. Each external view includes cell to cell spacing rules and connecting and blocking/keepout rules for placement and routing. The internal cell or, internal view includes regular shapes forming cell components and defining cell construction details and are ground rule clean by construction or verified by simulation or hardware. | 09-03-2009 |
| 20090222784 | Design method estimating signal delay time with netlist in light of terminal line in macro, and program - A design method according to an aspect of the present invention includes laying out a plurality of functional blocks of a design circuit based on a first netlist, creating a second netlist by adding a first path information to the first netlist, the first path information corresponding to an inter-block line connecting between the functional blocks, creating a third netlist by adding a second path information to the second netlist, the second path information corresponding to an intra-block line connected to a terminal of each functional block from inside of each functional block, creating a fourth netlist that models a line resistance and a line capacitance of an inter-instance line which combines the first path information and the second path information included in the third netlist, and estimating a delay time from information based on the fourth netlist. | 09-03-2009 |
| 20090235220 | DATA PROCESSING DEVICE, BEHAVIORAL SYNTHESIS DEVICE, DATA PROCESSING METHOD, AND RECORDING MEDIUM - A behavioral synthesis unit generates an intermediate level description that describes a plurality of processes indicated by a behavioral level description and data passed over during the plurality of processes based oil a behavioral level description describing the behavior of an electronic circuit and synthesis constraint information constituting constraints to be satisfied while generating a register transfer level description based on the behavioral level description and the number and type of circuit configuration elements that can be described in the register transfer level description. The data flow path information analyzing unit acquires path information indicating a data path and at least one process executed on the path based on the intermediate level description. A synthesis constraint generating unit then generates new synthesis constraint information that improves prescribed circuit performance of the electronic circuit based on library information and path information. | 09-17-2009 |
| 20090249275 | METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT, RECORDING MEDIUM RECORDING DESIGN PROGRAM OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND DESIGN SUPPORT APPARATUS OF SEMICONDUCTOR INTEGRATED CIRCUIT - A design method of a semiconductor integrated circuit carried out by a computer, including: a DRC step of performing a design rule check (Design Rule Check) with reference to layout information on an internal wiring in a capacitor cell and layout information on a signal wiring in the semiconductor integrated circuit; an integration step of integrating layout information on the internal wiring into layout information on the signal wiring when being determined in the DRC step that there is an error; and an elimination step of eliminating an error portion in the internal wiring from the integrated layout information. | 10-01-2009 |
| 20090265676 | METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT - A method for designing a semiconductor integrated circuit, includes: disposing a plurality of cells in a cell layout region on the basis of a net list indicating connection relations of the plurality of cells to satisfy a setup timing condition; generating a plurality of power regions dividing the cell layout region into plurality; calculating a consumption current of each of the power regions by using a cell power file indicating a consumption current of each of the cells; adjusting layout positions of the temporarily disposed cells with reference to the consumption current of each of the power regions in a range that the setup timing condition is not violated; and optimizing hold timing of the cells after the position adjustment of the cells. | 10-22-2009 |
| 20090276748 | STITCHED CIRCUITRY REGION BOUNDARY INDENTIFICATION FOR STITCHED IC CHIP LAYOUT - Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip. | 11-05-2009 |
| 20090282381 | ELECTRONIC DESIGN AUTOMATION TOOL AND METHOD FOR OPTIMIZING THE PLACEMENT OF PROCESS MONITORS IN AN INTEGRATED CIRCUIT - An electronic design automation (EDA) tool for and method of optimizing a placement of process monitors (PMs) in an integrated circuit (IC). In one embodiment, the EDA tool includes: (1) a critical path/cell identifier configured to identify critical paths and critical cells in the IC, (2) a candidate PM position identifier coupled to the critical path/cell identifier and configured to identify a set of candidate positions for the PMs, (3) a cluster generator coupled to the critical path/cell identifier and configured to associate the critical cells to form clusters thereof and (4) a PM placement optimizer coupled to the candidate PM position identifier and the cluster generator and configured to place a PM within each of the clusters by selecting among the candidate positions. | 11-12-2009 |
| 20090288053 | METHODS OF CELL ASSOCIATION FOR AUTOMATED DISTANCE MANAGEMENT IN INTEGRATED CIRCUIT DESIGN - Associated methods and a computer program product are disclosed for modifying a design of an integrated circuit. Properties are assigned to cells in an integrated circuit design. The properties include a location constraint property and a timing constraint property. When a cell is moved and one or more properties are not in compliance, other cells are moved to restore the non-compliant properties to compliance. | 11-19-2009 |
| 20090288054 | Method and apparatus for hierarchical design of semiconductor integrated circuit - A hierarchical design apparatus | 11-19-2009 |
| 20090300568 | Bus interface design apparatus and bus interface design method - A design method of a bus interface that includes an I/F interposed between chips, includes determining a bus width of the bus interface between chips and a type of the bus interface, based on a physical constraint condition between the chips, and automatically generating a bus IP core that comprises a circuit configured in accordance with the determined bus width and the bus interface. | 12-03-2009 |
| 20090300569 | DESIGN METHOD AND ARCHITECTURE FOR POWER GATE SWITCH PLACEMENT - A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage references to the logic cells are routed to their associated switch cells. Because conventional standard cell design and placement techniques achieve only a placement density or utilization between 70-80% (i.e., unoccupied space constitutes between 20 to 30% of the available space in each row of logic cells), by placing the power gate cells in the unoccupied space, the method does not increase the silicon real estate requirement even though the power gate cells are introduced into the design. Optimization techniques may be applied to achieve proper sizing and distribution of power gate cells, so as to avoid a performance penalty due to the power gate cells. In one embodiment, fine-grained power gating is achieved by selectively providing non-power-gated logic cells among power-gated logic cells. | 12-03-2009 |
| 20090313595 | STRESS-MANAGED REVISION OF INTEGRATED CIRCUIT LAYOUTS - Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors. | 12-17-2009 |
| 20090319974 | User Selected Grid for Logically Representing an Electronic Circuit - A computer implemented method employs software on a system for generating a logical representation of an electronic circuit undergoing a design. A predetermined grid for the circuit being designed is selected through interaction with the user through a graphical user interface. An input file defines objects to be plotted to the grid, and is read into a computer system. Objection locations relative to the grid, and connections between objects are checked and adjustments made by moving objects as necessary to align with the grid and to ensure connections between the objects. A design file of the adjusted logical representation is written for use in completing a circuit design. | 12-24-2009 |
| 20090319975 | Method and system for the modular design and layout of integrated circuits - An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end application, each of the modular tiles being configured to perform a predetermined function and constructed to have approximately the same length and width dimensions. The modular tiles are used to form the IC in a standard IC fabrication process. In many implementations, physical layout of the IC does not include the step of routing. Capabilities also include configuring the modular tiles to have programmable performance parameters and configuring the modular tiles to cooperate usefully with one another based on a programmable parameter. | 12-24-2009 |
| 20090327987 | Timing operations in an IC with configurable circuits - Some embodiments provide a method that identifies a first physical design solution for positioning several configurable operations on several reconfigurable circuits of an integrated circuit (IC). The method identifies a second physical design solution for positioning the configurable operations on the configurable circuits. One of the identified physical design solutions has one reconfigurable circuit perform a particular configurable operation in at least two reconfiguration cycles while the other identified solution does not have one reconfigurable circuit perform the particular configurable operation in two reconfiguration cycles. The method costs the first and second physical design solutions. The method selects one of the two physical design solutions based on the costs. | 12-31-2009 |
| 20100005437 | METHODS AND SYSTEMS FOR COMPUTER AIDED DESIGN OF 3D INTEGRATED CIRCUITS - Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed. | 01-07-2010 |
| 20100011329 | Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors - A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. The restricted layout region includes a gate electrode level layout defined to include rectangular-shaped layout features placed to extend in only a first parallel direction. Some of the rectangular-shaped layout features form gate electrodes of respective PMOS transistor devices, and some of the rectangular-shaped layout features form gate electrodes of respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the restricted layout region of the semiconductor device. Additionally, the restricted layout region corresponds to an entire gate electrode level of a cell layout. | 01-14-2010 |
| 20100011330 | Semiconductor Device Layout Having Restricted Layout Region Including Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing with Corresponding Non-Symmetric Diffusion Regions - A restricted layout region in a layout of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes. The plurality of diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level layout. A gate electrode level layout is defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. | 01-14-2010 |
| 20100011331 | Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing with Corresponding Non-Symmetric Diffusion Regions - A restricted layout region includes a diffusion level layout including p-type and n-type diffusion region layout shapes separated by a central inactive region. The diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level layout. A gate electrode level layout is defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. The restricted layout region corresponds to an entire gate electrode level of a cell layout. | 01-14-2010 |
| 20100011332 | Semiconductor Device Layout Having Restricted Layout Region Including Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors - A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level layout is defined above the portion of the substrate to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. A number of PMOS transistor devices is equal to a number of NMOS transistor devices in the restricted layout region. | 01-14-2010 |
| 20100011333 | Semiconductor Device Layout Having Restricted Layout Region Including Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors - A restricted layout region includes a diffusion level layout including a number of diffusion region layout shapes to be formed within a substrate portion of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level layout is defined above the substrate portion to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. A total number of the PMOS transistor devices and the NMOS transistor devices in the restricted layout region of the semiconductor device is greater than or equal to eight. | 01-14-2010 |
| 20100023910 | METHOD OF PACKING-BASED MACRO PLACEMENT AND SEMICONDUCTOR CHIP USING THE SAME - A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format. | 01-28-2010 |
| 20100023911 | Layout of Cell of Semiconductor Device Having Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors - A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions. The cell layout also includes a gate electrode level layout defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. Linear-shaped layout features within the gate electrode level layout extend over one or more of the p-type and/or n-type diffusion regions to form PMOS and NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. | 01-28-2010 |
| 20100031217 | METHOD AND SYSTEM FOR FACILITATING FLOORPLANNING FOR 3D IC - One embodiment of the present invention provides a system for facilitating floorplanning for three-dimensional integrated circuits (3D ICs). During operation, the system receives a number of circuit blocks. The system places the blocks in at least one layer of a multi-layer die structure and sets an initial value of a time-varying parameter. The system then iteratively perturbs the block arrangement until the time-varying parameter reaches a pre-determined value. | 02-04-2010 |
| 20100031218 | System and Method for Automated Placement in Custom VLSI Circuit Design with Schematic-Driven Placement - A method for automatically generating an electronic circuit layout with placed circuit elements includes receiving a user provided schematic, the user provided schematic comprising a plurality of circuit elements, each circuit element comprising general parameters. The method associates a plurality of first placement parameters with each of the plurality of circuit elements. The method retrieves, from a design library, design parameters associated with at least one of the plurality of circuit elements. The method selects a subset of circuit elements and receives placement inputs. The method generates a first placed layout configuration comprising adjusted placement parameters, based on the received placement inputs, the first placement parameters, and the design parameters. The method assigns absolute placement coordinates for each of the plurality of circuit elements based on the first placed layout configuration. The method generates an electronic circuit layout with placed circuit elements based on the absolute placement coordinates. | 02-04-2010 |
| 20100031219 | APPARATUS, METHOD, AND PROGRAM FOR PREDICTING LAYOUT WIRING CONGESTION - A layout-wiring-congestion prediction apparatus. The layout-wiring-congestion prediction apparatus includes: a circuit-data providing section providing circuit data; a conversion processing section converting the provided circuit data into directed graph data; a node-placement-coordinate calculation processing section calculating individual node placement coordinates of the directed graph data produced by the conversion processing section; a node-placement-density calculation section calculating a node-placement density on the basis of the individual node placement coordinates calculated by the node-placement-coordinate calculation processing section; and a node-placement-density error determination processing section determining the node-placement density calculated by the node-placement-density calculation section to be an error if the node-placement density is higher than an error-determination threshold value. | 02-04-2010 |
| 20100042963 | Constrained Physical Design Tuning - Described is a constraint language and related technology by which complex constraints may be used in selecting configurations for use in physical database design tuning. The complex constraint (or constraints) is processed, e.g., in a search framework, to determine and output at least one configuration that meets the constraint, e.g., a best configuration found before a stopping condition is met. The search framework processes a current configuration into candidate configurations, including by searching for candidate configurations from a current configuration based upon a complex constraint, iteratively evaluating a search space until a stopping condition is satisfied, using transformation rules to generate new candidate configurations, and selecting a best candidate configuration. Transformation rules and pruning rules are applied to efficiently perform the search. Constraints may be specified as assertions that need to be satisfied, or as soft assertions that come close to satisfying the constraint. | 02-18-2010 |
| 20100058268 | LAYOUT DETERMINATION - A device includes a processor and a computer-readable medium including computer-readable instructions. Upon execution by the processor, the computer-readable instructions cause the device to receive a first request from a second device, where the first request is a layout request that includes an identification of a space. The computer-readable instructions also cause the device to provide a second request to a third device, where the second request includes the identification of the space. The computer-readable instructions also cause the device to receive one or more dimension corresponding to the space, and to provide the one or more dimension to the third device. The computer-readable instructions further cause the device to receive a generated layout from the third device, and to provide the generated layout to the second device. | 03-04-2010 |
| 20100058269 | Uniquification and Parent-Child Constructs for 1xN VLSI Design - Embodiments that create parent-child relationships for reuse of 1×N building blocks in a closed-loop 1×N system are disclosed. Some methods comprise generating a representation of an IC design, inserting a first 1×N building block into the representation, and creating an association between the first 1×N building block and a second 1×N building block. The association enables the first 1×N building block to inherit alterations of attributes of the second 1×N building block and enables unique alterations of attributes of the first 1×N building block which differ from the second 1×N building block. Further embodiments comprise an apparatus having an equivalency determiner to determine a logical equivalence between a two 1×N building blocks, an attribute creator that creates a set of attributes and enables one of the 1×N building blocks to inherit parent attributes and comprise child attributes. | 03-04-2010 |
| 20100064272 | System and method for supporting layout design of semiconductor integrated circuit - In a layout design method of a semiconductor integrated circuit, an IR drop data is calculated to indicate a voltage drop for every local area, and a virtual arrangement library is generated which stores data of a circuit cell to be arranged based on the IR drop data for every circuit module. A virtual arrangement net list is generated by converting the circuit cell contained in a net list into a virtual arrangement cell which is registered on the virtual arrangement library. The circuit module is automatically arranged based on the virtual arrangement net list; and the virtual arrangement cell contained in the automatically arranged circuit module is replaced with the circuit cell contained in the net list. | 03-11-2010 |
| 20100115483 | CROSSBAR STRUCTURE WITH MECHANISM FOR GENERATING CONSTANT OUTPUTS - Embodiments provide crossbar structures, and reconfigurable circuits that contain crossbar structures, that include n inputs and an output, where n is an integer, chains of transistors coupled to the n inputs and the output, a plurality of control signal elements—each coupled to one or more transistors of the plurality of chains of transistors to selectively couple said n inputs to the output—and an additional chain of transistors coupled to at least some of the plurality of control signal elements and the output to selectively couple a constant output voltage to the output. Other embodiments may be disclosed and claimed. | 05-06-2010 |
| 20100115484 | Standard cell placement - A method of generating a layout of an integrated circuit is provided, the method comprising the steps of: providing functional data representing circuit elements and connections between the circuit elements, providing a cell library defining a plurality of standard cells, each standard cell representing a potential component for forming the integrated circuit, providing compatibility information indicative of the compatibility of the boundaries of the standard cells, and generating a placement of standard cells in dependence on the functional data and the compatibility information to produce the layout such that no abutting cells have incompatible boundaries. | 05-06-2010 |
| 20100115485 | Circuit design device for conducting failure analysis facilitating design - A circuit design device decides placement of elements and interconnections included in a circuit, on the basis of connection information of the circuit. The circuit design device includes an equivalent fault class extracting unit, a weighting unit, and a placement deciding unit. The equivalent fault class extracting unit extracts one or more classes (hereinbelow referred to as “equivalent fault classes”) having, as members, interconnections (hereinbelow referred to as “equivalent fault interconnections”) which mutually cause an equivalent fault in the circuit. The weighting unit gives a greater weight to the equivalent fault class or the equivalent fault interconnections included in the equivalent fault class, as the number of the members in the equivalent fault class (hereinbelow referred to as the “number of equivalent fault interconnections”) increases. The placement deciding unit decides placement of the elements and the interconnections so that, among the equivalent classes, an equivalent fault class having a larger number of equivalent fault interconnections would have a lower probability of including a single stuck-at fault. | 05-06-2010 |
| 20100122229 | Apparatus and Method of Preventing Congestive Placement - An apparatus of preventing congestive placement is provided. The apparatus comprises a judging module, a pattern generating module, and a placement module. The judging module judges whether a circuit layout comprises a congestive region according to a judging rule. When a judgment result of the judging module is affirmative, the pattern generating module generates a redistribution pattern with a density distribution of blockages. The density distribution gradually decreases outward. The placement module regards the congestive region as the center redistributes the blockages and electronic cells according to the redistribution pattern. | 05-13-2010 |
| 20100125822 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODCUT FOR IMPLEMENTING INTERACTIVE CROSS-DOMAIN PACKAGE DRIVEN I/O PLANNING AND PLACEMENT OPTIMIZATION - Disclosed are a method, a system, and a computer program product for implementing interactive cross-domain package driven I/O planning and placement optimization of an electronic circuit design. In some embodiments, the method identifies an object on a first EDA tool session, determines a drop location for the first object based on a tentative location in the first EDA tool session, places the first object at the drop location, and adjusts the drop location via a second EDA tool session, performs placement or routing of a portion of the design. The method or the system further comprises placing a corresponding first object in the second EDA tool session, initiating the second EDA tool session object move in the first EDA tool session, determining whether a constraint is satisfied. | 05-20-2010 |
| 20100138802 | PRINTED BOARD DESIGN SYSTEM AND PRINTED BOARD DESIGN METHOD - A decoupling capacitor pin position information obtain unit calculates based on board design data of a printed board, position information indicating positions of decoupling capacitors on the printed board. A power supply plane position/shape information obtain unit calculates based on the board design data, position/shape information indicating a position and shape of a power supply plane of the printed board. A restriction condition input unit collects restriction conditions from an input device. A decoupling capacitor examination unit judges based on the position information, the position/shape information and the restriction conditions, whether or not arrangement of the decoupling capacitors is adequate. Therefore, a designer, while designing arrangement/wiring of the printed board, can check in real time whether or not the arrangement of the decoupling capacitors is adequate, and thus can design at higher speed a printed board in which arrangement of decoupling capacitors is adequate. | 06-03-2010 |
| 20100146469 | SYSTEM AND METHOD FOR SELECTING GATES IN A LOGIC BLOCK - For each of a plurality of interconnected gates forming one or more non-critical timing paths through a logic block, a gate size may be selected based on (i) a gate delay, (ii) a change in gate delay and gate power associated with downsizing the gate to a next available gate size, and (iii) signal arrival times at one or more inputs and outputs of the gate to minimize power consumed by the logic block while maintaining a specified cycle time. | 06-10-2010 |
| 20100146470 | METHOD AND SYSTEM FOR VOLTAGE FLUCTUATION AMOUNT CALCULATION - Method includes specifying a first relationship between power supply voltage in a semiconductor device and the maximum operable frequency of internal circuit upon fluctuation of the power supply voltage being detected by changing the power supply voltage in the semiconductor device and the operating frequency of the internal circuit, specifying second relationship between the maximum operable frequency of the internal circuit and the mounting manner of the decoupling capacitor upon the fluctuation of the power supply voltage being detected by changing the mounting manner of the decoupling capacitor and the operating frequency of the internal circuit, and calculating the fluctuation amount of the power supply voltage corresponding to the decoupling capacitor mounting manner based on the first relationship and the second relationship. | 06-10-2010 |
| 20100162193 | METHOD AND PROCESS FOR DESIGN OF INTEGRATED CIRCUITS USING REGULAR GEOMETRY PATTERNS TO OBTAIN GEOMETRICALLY CONSISTENT COMPONENT FEATURES - The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit. | 06-24-2010 |
| 20100185996 | SEMICONDUCTOR LAYOUT SCANNING METHOD AND SYSTEM - A method for scanning a semiconductor layout, the layout comprising objects with edges and corners, the method comprising identifying locally closest point pairs, identifying a proximity relation between two parallel edges where the parallel edges have at least one locally closest point pair in common and storing the proximity relation in a proximity relations table of a database together with a reference to the corresponding pair of edges. Locally closest point pairs are identified where the first edge and the second edge are not in contact with each other, a distance between the first point and the second point is the shortest distance between the first edge and the second edge, and a convex bounding area with the first point and the second point on its boundary contains no edge. | 07-22-2010 |
| 20100185997 | TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS - A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements. | 07-22-2010 |
| 20100199248 | Packaging design supporting device and packaging design supporting method for semiconductor integrated circuit and recording medium - A disclosed packaging design supporting device for a semiconductor integrated circuit includes a selection data acquisition unit inputting a change of the selected logic cell; a bulk fix data generation unit generating bulk fix data in which a bulk layer of the semiconductor substrate of the semiconductor integrated circuit has been fixed, arranging a design-change dummy logic cell in a region where no logic cell is arranged in the bulk layer, and generating a design-change logic cell by wiring the design-change dummy logic cell; and a selection cell move determination unit prohibiting the change with respect to the selected logic cell. | 08-05-2010 |
| 20100211923 | Design Structure for a Redundant Micro-Loop Structure for use in an Integrated Circuit Physical Design Process and Method of Forming the Same - A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via. | 08-19-2010 |
| 20100218155 | Automated Critical Area Allocation in a Physical Synthesized Hierarchical Design - A method, computer program product, and data processing system for efficiently performing automated placement of timing-critical unit-level cells in a hierarchical integrated circuit design is disclosed. In preparation for global optimization the entire unit at the cell level, macro-level cells are assigned a “placement force” that serves to limit the movement of the macro-level cells from their current position. Movement boundaries for each macro element are also defined, so as to keep the components in a given macro element in relative proximity to each other. | 08-26-2010 |
| 20100223586 | TECHNIQUES FOR PARALLEL BUFFER INSERTION - The present disclosure is directed to a method for determining a plurality of buffer insertion locations in a net for an integrated circuit design. The method may comprise calculating a plurality of resistive-capacitive (RC) influences in parallel, each RC influence corresponding to one of a plurality of buffering options available for a first sub-tree for the addition of a wire segment to the first sub-tree; updating the plurality of RC influences for the addition of a buffer for the first sub-tree, the buffer comprising one of a plurality of buffer types; and merging the first sub-tree with a second sub-tree in parallel by grouping the plurality of buffering options available for the first sub-tree and a plurality of buffering options available for the second sub-tree into a plurality of merging groups, and merging at least two groups of the plurality of merging groups in parallel. | 09-02-2010 |
| 20100229142 | LOW RC GLOBAL CLOCK DISTRIBUTION - A semiconductor die includes: a clock distribution network that distributes a clock signal within the die. The clock distribution network includes: a clock tree corresponding to one or more metal layers of the die, a plurality of clock spines corresponding to a metal layer of the die, a plurality of clock wings corresponding to a metal layer of the die, a plurality of clock grid drivers placed in one or more gaps of a floorplan corresponding to the semiconductor layer of the die, a clock grid placed in the one or more gaps of the floorplan, a plurality of buffers placed in a local gain buffer pair configuration wherein the local gain buffer pair connects the clock grid to a shorting bar, and a plurality of conductors that connect the shorting bar to a plurality of loads. | 09-09-2010 |
| 20100235800 | METHODS AND MECHANISMS FOR INSERTING METAL FILL DATA - A method for implementing virtual metal fill includes obtaining a layout record for a circuit design, and inserting metal fill data into the layout record based on one or more rules, wherein the metal fill data represents a consolidation of actual metal fill. A method for implementing virtual metal fill includes obtaining a layout record for a circuit design, and inserting metal fill data into the layout record, the metal fill data representing a virtual metal fill having a configuration that is different from a configuration of actual metal fill. | 09-16-2010 |
| 20100242009 | Method and Apparatus For Preventing Congestive Placement - A congestive placement preventing apparatus, applied in a logic circuit layout having 2 | 09-23-2010 |
| 20100287519 | METHOD AND SYSTEM FOR CONSTRUCTING A CUSTOMIZED LAYOUT FIGURE GROUP - A method and a system for constructing a customized layout figure group are disclosed. The method provides improved options for users to flexibly create a customized figure group design. During the layout process, the layout shape, the leaf device and the nest device with design parameters can be created with built-in figure groups, user's scripts and/or by capturing the user's existing layout. | 11-11-2010 |
| 20100306725 | APPARATUS AND METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, AND COMPUTER READABLE MEDIUM - An apparatus for designing a semiconductor integrated circuit according to an embodiment of the present invention includes an interface circuit information extracting unit configured to specify one or more transmitting registers and one or more receiving registers forming an interface that needs to be synchronized, an insertion point candidate specifying unit configured to specify a number of supply sources that is of a number of the transmitting registers serving as data supply sources, for each receiving register, and specify at least one insertion point candidate based on the number of supply sources, an insertion point specifying unit configured to specify a number of output destinations that is of a number of the receiving registers serving as data output destinations, for each transmitting register, and specify at least one insertion point based on the number of output destinations and the insertion point candidate, and a synchronization circuit inserting unit configured to insert a synchronization circuit in the insertion point, and generate synchronized circuit description data of the semiconductor integrated circuit in which the synchronization circuit is inserted in the insertion point. | 12-02-2010 |
| 20100306726 | CHAIN/LEAPFROG CIRCUIT TOPOLOGIES AND TOOLS FOR CARBON NANOTUBE / GRAPHENE NANORIBBON NANOELECTRONICS, PRINTED ELECTRONICS, POLYMER ELECTRONICS, AND THEIR CONFLUENCES - Software for designing and testing types of nanoelectronic circuits and larger scale electronics renderings is described. The software designs circuits comprising only a chain/leapfrog topology. The chain/leapfrog topology permits a wide range of circuits and circuit modules to be implemented on a common shared carbon nanotube, graphene nanoribbon, or strips of other types of semiconducting material, for example as rendered in traditional printed electronics and nanoscale printed electronics or as employing semiconducting polymers. In one approach a chain/leapfrog topology circuit design software tool accesses information in a library of chain/leapfrog circuits data, and creates descriptive data pertaining to a number of approaches to rendering electronics components using a library of component data. The chain/leapfrog circuits data library includes designs for a number of different types of chain/leapfrog circuit modules. The software provides for “IP cores,” “System-on-a-Nanotube,” and other related modular design approaches. | 12-02-2010 |
| 20100306727 | Method and design system for semiconductor integrated circuit - A layout region in which a wiring pattern and a special pattern are placed is divided into division regions. The minimum pitch for the special pattern is larger than the minimum pitch for the wiring pattern. With respect to each division region, the special pattern included in a predetermined region surrounding the each division region is extracted as a peripheral pattern, and a dummy pattern placement region included in the each division region is determined. The dummy pattern placement region is apart from at least one of boundaries between adjacent division regions. A dummy pattern is added in the dummy pattern placement region with avoiding a design rule error with the peripheral pattern existing around the each division region. Then, the plurality of division regions to which the dummy pattern is added are coupled with each other. | 12-02-2010 |
