| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 716009000 | Detailed placement (i.e., iterative improvement) | 57 |
| 20080216039 | Node Spreading via Artificial Density Enhancement to Reduce Routing Congestion - Simultaneous Dynamical Integration modeling techniques are applied to global placement of elements of integrated circuits as described by netlists specifying interconnection of morphable-devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through a continuous location space in continuous time, and is used to derive placements of the morphable-devices having one-to-one correspondences with the nodes. Nodes under the influence of net attractive forces, computed based on the interconnections between the morphable devices, tend to coalesce into well-organized topologies. Nodes are also affected by spreading forces determined by density fields that are developed based on local spatial node populations. | 09-04-2008 |
| 20080235643 | Method and system for reducing inter-layer capacitance in integrated circuits - The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer. In particular, dummy fill features on each layer may be placed in a checkerboard pattern to avoid overlaps. As such, the present invention may eliminate large overlap area of the dummy patterns on consecutive layers by utilizing intelligent dummy filling placement. | 09-25-2008 |
| 20080244490 | Sequence-pair creating apparatus and sequence-pair creating method - A sequence-pair creating apparatus includes a block placement storing unit that stores information of size of a block b | 10-02-2008 |
| 20080250374 | Method of Making an Integrated Circuit - A method is provided for making an integrated circuit. Cell representing a layout of a set of features, is divided into at least a first region and a second region. Optical Proximity Correction is carried out on at least the first region of cell. One or more instances of cell are located to define IC prior to carrying out final OPC optimisation on the second regions of each cell in the defined IC. | 10-09-2008 |
| 20080276211 | Method and apparatus for determining a process model using a 2-D-pattern detecting kernel - One embodiment provides a system for determining an improved process model that models one or more semiconductor manufacturing processes. During operation, the system can receive a first process model. Next, the system can receive a 2-D-pattern detecting kernel which can detect 2-D patterns. The system can then receive a second set of empirical data which is associated with 2-D patterns in a test layout. Next, the system can determine an improved process model using the first process model, the 2-D-pattern detecting kernel, the test layout, and the second set of empirical data. | 11-06-2008 |
| 20080288906 | Integrated system on module - An electronic product includes a circuit board, an integrated system on module, and an application-specific module. The integrated system on module and the application-specific module are integrated with the circuit board. A method of forming the circuit board is disclosed, as well as a method of forming the electronic product. | 11-20-2008 |
| 20080301611 | Selective Optical Proximity Layout Design Data Correction - After layout design data has been modified using an OPC process, a repair flow is initiated. This repair flow includes analyzing the modified data to identify any remaining or new potential print errors in the layout data. Regions then are formed around the identified potential print errors, and a subsequent OPC process is performed only on the data within these regions using a different set of process parameters from the process parameters employed by the initial OPC process. This repair flow is iteratively repeated, where a different set of process parameter values for the subsequent OPC process is used during each iteration. | 12-04-2008 |
| 20090007043 | Managing Integrated Circuit Stress Using Dummy Diffusion Regions - Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors. | 01-01-2009 |
| 20090019410 | PATH PLANNING DEVICE - A path generating device | 01-15-2009 |
| 20090019411 | Thermally Aware Design Modification - In a first variation, a thermally aware design automation suite integrates system-level thermal awareness into design of semiconductor chips, performing fine-grain thermal simulations of the chips based on thermal models and boundary conditions. The suite uses results of the simulations to modify thermally significant structures to achieve desired thermal variations across a chip, meet design assertions on selected portions of the chip, and verify overall performance and reliability of the chip over designated operating ranges and manufacturing variations. In a second variation, a discretization approach models chip temperature distributions using heuristics to adaptively grid space in three dimensions. Adaptive and locally variable grid spacing techniques are used to efficiently and accurately converge for steady state and/or transient temperature solutions. The modeling optionally reads a mesh initialization file specifying selected aspects and parameters associated with controlling use and behavior of the variable grid spacing techniques. | 01-15-2009 |
| 20090019412 | DESIGN METHOD AND DESIGN APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT - According to the present invention, timing information, connection information and physical information are received, and at the weighting determination step, the degree to which a cell can move is weighted. Then, at the movement range determination step, the movement enabled range of the cell is determined, and whether or not a cell placement area is available is decided. When it is decided that a cell placement area is available, the processing advances either to the cell movement area extension step or to the cell placement area acquisition step. Thereafter, an automatic, optimal placement process is performed for the cell. | 01-15-2009 |
| 20090019413 | System and method for automatic layout of integrated circuit - An automatic layout apparatus is provided with: a storage device storing a cell library containing therein cell library data; and a layout tool obtaining from the cell library the cell library data associated with cells to be placed as described in a netlist to perform automatic placement of the cells to be placed. The obtained cell library data include layout coordinates of diffusion layers within the cells to be placed. The layout tool determines positions of the cells to be placed, referring to the layout coordinates of the diffusion layers. | 01-15-2009 |
| 20090031269 | ANALYTICAL GLOBAL PLACEMENT FOR AN INTEGRATED CIRCUIT - A placer produces a global placement plan specifying positions of cell instances to be interconnected by nets within an integrated circuit (IC) by initially clusterizing cell instances to form a pyramidal hierarchy of blocks and generating an initial global placement plan specifying a position of each block at a highest level of the hierarchy. The placer then declusterizes the global placement plan by replacing the highest level blocks with their component blocks and then improves the routability of the global placement plan by iteratively moving specified block positions in directions and by distances dynamically determined by analyzing the global placement plan and an objective function having a total wirelength term and having a bin density term reflecting density of blocks in specified areas (bins) of the IC. The placer iteratively repeats the declusterization and routability improvement process until the global placement plan specifies positions of all blocks residing at the lowest level of the hierarchy, with weighting of the bin density term adjusted when necessary during each iteration of the routability improvement process to provide sufficient white space in each bin. The placer employs a look-ahead legalization technique to move low level blocks to legal positions during later iterations of the plan improvement process. | 01-29-2009 |
| 20090044163 | METHOD OF GENERATING A STANDARD CELL LAYOUT - A method of generating a standard cell layout includes analyzing a circuit of a standard cell layout and obtaining an analysis result, selecting a plurality of leaf cell layout according to the analysis result, and piecing together the leaf cell layouts to generate the standard cell layout. | 02-12-2009 |
| 20090044164 | Method for Placing Dummy Patterns in a Semiconductor Device Layout - Disclosed is a method for placing dummy patterns in a semiconductor device layout. More specifically, the method places the dummy patterns densely between main patterns in accordance with a sequence and configuration. The method includes placing vertical dummies having a greater length than width in a region other than main patterns to form a first layout, removing the vertical dummies within a first distance from the main patterns to form a second layout, placing horizontal dummies having a greater length than width in a vacant space of the second layout to form a third layout, and removing the horizontal dummies within a second distance from the main patterns in the third layout. The method prevents and/or inhibits pattern deformation. | 02-12-2009 |
| 20090049418 | Method for Radiation Tolerance by Automated Placement - A method of designing a layout of an integrated circuit for increased radiation tolerance by ensuring that any critical components (those deemed particularly sensitive to radiation-induced soft errors) are at spacings greater than a predetermined threshold based on particle migration within the silicon substrate. The method starts with an initial placement, identifies the objects for which radiation tolerance is desired, determines whether any of those objects and, if so, moves the relevant objects to increase the spacing. An exemplary threshold for contemporary CMOS device technologies is 5 μm. The objects can be moved by vertically and/or horizontally shifting away from a reference point of the integrated circuit. The critical objects may include triplicated (redundant) structures, clock control latches, or a reset bit. The method can be used in conjunction with other placement optimizations such as area, power and timing. | 02-19-2009 |
| 20090089732 | METHOD AND APPARATUS FOR PERFORMING DUMMY-FILL BY USING A SET OF DUMMY-FILL CELLS - An embodiment performs dummy fill in a design layout to achieve a target density that is within a narrow range of target densities. During operation, the system can receive a design layout that includes a region whose density is not within a desired range of target densities. Next, the system can receive a set of dummy-fill cells which can be used to place a dummy-fill array to fill an arbitrarily sized rectangle. The set of dummy-fill cells may contain assist features and optical proximity corrections which cause the dummy shapes to print properly regardless of the size of the dummy-fill array. The system may then determine a polygon in the design layout to fill with dummy-fill cells. Next, the system may fracture the polygon into a set of rectangles. The system may use the set of dummy-fill cells to place a dummy-fill array that fills a rectangle. | 04-02-2009 |
| 20090100397 | Buffer Placement with Respect to Data Flow Direction and Placement Area Geometry in Hierarchical VLS Designs - A method for identifying and modifying, in a VLSI hierarchical chip design, parent buffer placements which lead to wiring track inefficiencies with respect to data flow and the parent placement area geometry. Parent placement area is reviewed and a subset is categorized and distinguished as either horizontal slots or vertical slots. Buffer to buffer data flow is reviewed for cases where data flow direction is either Strongly horizontal or strongly vertical. Situations where buffer to buffer data flow is oriented in the same direction as the parent placement slots in which the buffers reside are reported, Additionally, an attempt is made to find a valid placement location for the buffers excluding parent placement areas oriented in the same direction as the data flow. | 04-16-2009 |
| 20090113367 | ANALOG IC PLACEMENT USING SYMMETRY-ISLANDS - A placement tool searches for an optimal placement for a plurality of device modules within an integrated circuit (IC) including symmetry groups formed by device modules that are to be symmetrically placed. The tool employs a hierarchical B*-tree (HB*-tree) representation of a trial placement wherein each symmetry group and each module not included in a symmetry group is represented by a separate node of the HB*-tree. Each symmetry group node maps to a symmetry island placement for the symmetry group satisfying all symmetry and other placement constraints on the symmetry group. The placement tool employs a simulated annealing technique to iteratively perturb the HB*-tree representation to produce a sequence of trial placements, and uses a cost function to evaluate the quality of each trial placement. | 04-30-2009 |
| 20090158230 | DETERMINING ALLOWABLE ANTENNA AREA AS FUNCTION OF TOTAL GATE INSULATOR AREA FOR SOI TECHNOLOGY - A method is disclosed of determining allowable antenna limits for semiconductor-on-insulator (SOI) technology. In one embodiment, the method may include: determining antenna area on a gate; determining antenna area on a source/drain; determining a total gate insulator area between gate and source/drain nets; and calculating allowable antenna area as a function of the total gate insulator area between the nets such that a larger total antenna area is allowed for larger total gate insulator area between the nets. | 06-18-2009 |
| 20090172623 | METHOD AND SYSTEM FOR IMPLEMENTING EFFICIENT LOCKING TO FACILITATE PARALLEL PROCESSING OF IC DESIGNS - Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking. | 07-02-2009 |
| 20090172624 | Method and System for Implementing Stacked Vias - The invention is directed to a method, computer program product and apparatus for a body of code to specify how database elements are combined to create a complex element, a database grouping is created that receives the content of the evaluation without introducing a level of hierarchy, and provides graphical user interface (GUI) to interactively manipulate the element. | 07-02-2009 |
| 20090187870 | PLACEMENT DRIVEN ROUTING - A method placing items routing wiring pursuant to integrated circuit specifications to create an integrated circuit design. Once the initially placed design is legalized, rather that just starting wiring routing, the method identifies books in the integrated circuit design which contain blocked items. The method allows the routing process to be paused temporarily, and for the items to be moved to a certain extent. This movement process is controlled (limited according to signal power output by the associated books) so that the timing of the integrated circuit design is not affected by any such “mid-routing” movement. If the books do not have any blocked items, the process continues to route wires between the items and the books. If at any point before or during the routing of the wires it is found that the books do have blocked items, the process pauses the routing of the wires and performs any number of different processes to solve the blocked item situation (unblock the blocked items). | 07-23-2009 |
| 20090193376 | CLOCK POWER MINIMIZATION WITH REGULAR PHYSICAL PLACEMENT OF CLOCK REPEATER COMPONENTS - Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance on the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally place clock components in a regular fashion so as to minimize clock power within a performance constraint. A rectangular grid is created and clock distribution structures are assigned to the grid intersection points. Latches are then located around the clock distribution structures to minimize an overall distance for connections between the latches and respective clock distribution structures. The horizontal and vertical pitches of the grid may be independently adjusted to achieve a more uniform spread of the clock distribution structures. | 07-30-2009 |
| 20090193377 | REGULAR LOCAL CLOCK BUFFER PLACEMENT AND LATCH CLUSTERING BY ITERATIVE OPTIMIZATION - Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance of the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally design a clock network by logically assigning clusters of the latches to respective clock distribution structures, placing clock pins at favored pin locations, and placing clock distribution structures directly underneath the clock pins. The clock distribution structures may be moved to favored distribution locations along the clock stripes, and new optimal clustering generated between the latches and the clock distribution structures. These three optimizations are preferably repeated iteratively to derive a local optimal solution for the clock network. | 07-30-2009 |
| 20090235219 | HIERARCHICAL ANALOG IC PLACEMENT SUBJECT TO SYMMETRY, MATCHING AND PROXIMITY CONSTRAINTS - A placement tool generates an optimal placement for a plurality of device modules within an analog integrated circuit (IC) subject to device matching, symmetry, and proximity constraints by first defining a multiple-level hierarchy of constraint groups, wherein each constraint group consists of elements that are subject to one of the placement constraints. Each element of each constraint group consists of either of one of the device modules or another one of the constraint groups residing at a lower level of the hierarchy. The tool then generates a hierarchical B*-tree representation of a trial placement for the IC including a separate node representing each constraint group of the hierarchy and a separate node for each of device module not included in any of the constraint groups. Each node representing a constraint group defines relative positions within the IC of each the device modules or lower level constraint groups forming the constraint group that are consistent with the placement constraint on the constraint group. The placement tool iteratively perturbs the hierarchical B*-tree to generate a sequence of trial placements for the IC design and then evaluates a cost function for each trial placement to select a best one of the trial placements as the optimal trial placement. | 09-17-2009 |
| 20090241083 | ROUTER-AIDED POST-PLACEMENT-AND-ROUTING-RETIMING - A method of minimising the longest delay path between two logic elements of a circuit placed on a reconfigurable device, each logic element being associated with a register and the reconfigurable device including logic elements and associated registers which are programmed to be transparent, the method includes the steps of determining a number of possible routing paths for connecting the two logic elements of the circuit through a specific register associated with one of the logic elements, including at least one path which passes through at least one register which is programmed to be transparent and selecting a routing path based on at least one routing path criterion including whether each routing path passes through a register which is programmed to be transparent. | 09-24-2009 |
| 20090249274 | INTEGRATED CIRCUIT DESIGN METHOD APPLIED TO A PLURALITY OF LIBRARY CELLS AND INTEGRATED CIRCUIT DESIGN SYSTEM THEREOF - A first library cell and a second library cell each includes a plurality of metal layers, and a metal track direction of the odd metal layers of the first library cell is perpendicular to that of the odd metal layers of the second library cell. An integrated circuit design method applied to these library cells includes the steps of rotating the second library cell to cause the metal track direction of the odd metal layers of the second library cell to be parallel to that of the odd metal layers of the first library cell, and placing the first library cell and the second library cell in an identical integrated circuit design. | 10-01-2009 |
| 20090259980 | Method and System for Concurrent Buffering and Layer Assignment in Integrated Circuit Layout - A method and system for concurrent buffering and layer assignment in integrated current layout. Buffers are inserted and metal interconnects or “wires” are sized for every net, which consists of one driver and one or more receivers, such that timing skew constraints can be met. Long nets are promoted to a higher level if the slew violation can be fixed only by a promotion of the net or if the “slack” gain available by this promotion is equal to or greater than a predesignated layer of promotion threshold. In response to determining these layer assignments, the method and system then systematically demotes nets that are not critical and which do not impact the circuit and electrical constraints in order to minimize the use of high layer wire resources. | 10-15-2009 |
| 20090259981 | Integrated Circuit With Areas Having Uniform Voltage Drop and Method Therefor - A method that determines the maximum number of logic cells that can be placed in a predetermined area on the base of an integrated circuit, and meet a voltage drop requirement. The method iteratively changes the logic cell spacing until the voltage drop requirement is made. This is done prior to the placement and extraction design phases as was done in previous methods. The predetermined area may be extrapolated across the base of the integrated circuit and meet the voltage drop requirements without the need to change the power grid, or to redo the placement and extraction phases. An integrated circuit designed according to the method, and an integrated circuit design system for using the method is also disclosed. | 10-15-2009 |
| 20090265675 | On Chip Local MOSFET Sizing - A method for reducing variation in a desired property between transistors in an integrated circuit that is fabricated with a given process. The process is characterized to form a mathematical model that associates changes in polysilicon density and active density in the integrate circuit with changes in gate length and gate width in the transistors, and associates changes in the gate length and the gate width to the desired property. The integrated circuit is laid out with space sufficient to adjust the gate length and the gate width of the transistors without violating design rules of the transistors. The integrated circuit is divided into portions, and for at least a given one of the portions of the integrated circuit, the polysilicon density and the active density of the given portion is measured. For at least one of the transistors in the given portion of the integrated circuit, at least one of the gate length and the gate width of the transistor is selectively adjusted according to the mathematical model, based on at least one of the polysilicon density and the active density of the given portion, to reduce variation in the desired property between the transistors in the integrated circuit. | 10-22-2009 |
| 20090271752 | Legalization of VLSI circuit placement with blockages using hierarchical row slicing - A hierarchical method of legalizing the placement of logic cells in the presence of blockages selectively classifies the blockages into at least two different sets based on size (large and small). Movable logic cells are relocated first among coarse regions between large blockages to remove overlaps among the cells and the large blockages without regard to small blockages (while satisfying capacity constraints of the coarse regions), and thereafter the movable logic cells are relocated among fine regions between small blockages to remove all cell overlaps (while satisfying capacity constraints of the fine regions). The coarse and fine regions may be horizontal slices of the placement region having a height corresponding to a single circuit row height of the design. Cells are relocated with minimal perturbation from the previous placement, preserving wirelength and timing optimizations. The legalization technique may utilize more than two levels of granularity with multiple relocation stages. | 10-29-2009 |
| 20090271753 | Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same - A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell. | 10-29-2009 |
| 20090282380 | METHOD OF LAYING OUT INTEGRATED CIRCUIT DESIGN BASED ON KNOWN POLYSILICON PERIMETER DENSITIES OF INDIVIDUAL CELLS - Disclosed is a method of laying out individual cells of an integrated circuit design, based at least in part on the known polysilicon perimeter densities of those cells. That is, the method embodiments use the knowledge of polysilicon perimeter density for known cells to drive placement of those cells on a chip (i.e., to drive floor-planning). The method embodiments can be used to achieve approximately uniform across-chip polysilicon perimeter density and, thereby to limit performance parameter variations between functional devices that are attributable to variations in polysilicon perimeter density. Alternatively, the method embodiments can be used to selectively control variations in the average polysilicon perimeter density of different regions of a chip and, thereby to selectively control certain performance parameter variations between functional devices located in those different regions. | 11-12-2009 |
| 20090307647 | LAYOUT DESIGN METHOD AND COMPUTER-READABLE MEDIUM - A layout design method includes extracting a plurality of pairs of complementary signals from signal lines connected between a plurality of circuit blocks, for every signal lines connected between the same circuit blocks, and routing the pairs by twisting each pair. | 12-10-2009 |
| 20090313594 | Relative Positioning of Circuit Elements in Circuit Design - Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed, routed, and optimized circuit design obeys relative positioning rules of a set of the circuit elements. Such relative positioning rules were created specifically for these circuit elements. | 12-17-2009 |
| 20090319973 | SPACER FILL STRUCTURE, METHOD AND DESIGN STRUCTURE FOR REDUCING DEVICE VARIATION - A design structure is provided for spacer fill structures and, more particularly, spacer fill structures, a method of manufacturing and a design structure for reducing device variation is provided. The structure includes a plurality of dummy fill shapes in different areas of a device which are configured such that gate perimeter to gate area ratio will result in a total perimeter density being uniform across a chip. | 12-24-2009 |
| 20100005436 | METHOD AND APPARATUS FOR CHARACTERIZING AN INTEGRATED CIRCUIT MANUFACTURING PROCESS - A system that characterizes an integrated circuit manufacturing process is presented. During operation, the system receives a layout which includes a plurality of test structures for semiconductor devices, wherein each test structure varies one or more design variables. The system then fabricates a plurality of wafers based on the layout, wherein each wafer in the plurality of wafers is fabricated using one of a plurality of process settings. Next, the system obtains performance characteristics for the plurality of test structures on the plurality of wafers. The system then generates a process model that is based on at least the effect that values for the one or more design variables and the plurality of process settings have on the performance characteristics of the plurality of test structures. | 01-07-2010 |
| 20100023909 | VOLTAGE FLUCTUATION ESTIMATING METHOD AND APPARATUS, SEMICONDUCTOR DEVICE OPERATION VERIFICATION APPARATUS, SEMICONDUCTOR DEVICE DESIGNING METHOD, PRINTED CIRCUIT BOARD DESIGNING METHOD, AND PROGRAM - A computer determines a first relationship between a maximum frequency of the semiconductor device and an internal power supply voltage of the semiconductor device. Then, the computer determines a second relationship between the maximum frequency and an amount of noise, based on a number of the input/output signal pins. In addition, the computer estimates a fluctuation of the internal power supply voltage corresponding to a amount of noise of the semiconductor device, based on the first relationship and the second relationship. Then, the computer performs a design change of the semiconductor device based on the estimated fluctuation. And the computer stores the changed design of the semiconductor device to a storage device. | 01-28-2010 |
| 20100031214 | Method and Apparatus for Proximate Placement of Sequential Cells - Various methods and apparatuses (such as computer readable media implementing the method) are described that relate to proximate placement of sequential cells of an integrated circuit netlist. For example, the preliminary placement is received; and based on the preliminary placement, a group of sequential cells is identified as being subject to improved power and/or timing upon subsequent placement. In another example, identification is received of a group of sequential cells subject to improved power and/or timing upon subsequent placement; and proximate placement is performed of the identified group of sequential cells. In yet another example, a proximate arrangement of a group of sequential cells is received; and if proximate placement fails, then the group of sequential cells is disbanded and placement is performed of the sequential cells of the disbanded group. | 02-04-2010 |
| 20100031215 | System and Method for Improved Placement in Custom VLSI Circuit Design with Schematic-Driven Placement - A method for generating an electronic circuit layout with placed circuit elements receives a user provided schematic, the user provided schematic comprising a plurality of circuit elements, each circuit element comprising general parameters. The method associates a plurality of first placement parameters with each of the plurality of circuit elements, wherein the first placement parameters comprise a cell horizontal position, a cell vertical stacking position, and a cell vertical adjacent spacing. The method retrieves, from a design library, design parameters associated with at least one of the plurality of circuit elements. The method assigns first absolute placement coordinates for each of the plurality of circuit elements based on the first placement parameters and the design parameters. The method defines and performs an adjustment operation on the placement parameters of a selected subset of circuit elements, generating adjusted placement parameters. The method assigns second absolute placement coordinates based on the first placement parameters, the design parameters, and the adjusted placement parameters and generates an electronic circuit layout with placed circuit elements based on the second absolute placement coordinates. | 02-04-2010 |
| 20100031216 | METHOD FOR LAYOUT OF RANDOM VIA ARRAYS IN THE PRESENCE OF STRONG PITCH RESTRICTIONS - Exemplary embodiments provide a method for laying out an integrated circuit (“IC”) design and the IC design layout. In one embodiment, the IC design layout can include a first feature placed on a first intersecting point of a grid. The placed first feature can define a local grid area. The local grid area can further include a plurality of local intersecting points having an outer perimeter spaced from any outermost local intersecting point in a spacing ranging from a length of a grid side to a length of a grid diagonal of a grid unit. A second feature can either be restrictively placed on any local intersecting point of the local grid area, or be randomly placed on any location outside the outer perimeter of the local grid area. | 02-04-2010 |
| 20100037196 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING INCREMENTAL PLACEMENT IN ELECTRONICS DESIGN - Disclosed are a method, system, and computer program product for implementing incremental placement for an electronic design while predicting and minimizing the perturbation impact arising from incremental placement of electronic components. In some embodiments, an initial placement of an electronic design is identified, the abstract flow is computed, the target locations of various electronic components to be placed are identified, the relative ordering of electronic components are determined, and the placement is then legalized. Furthermore, in various embodiments, the method, system, or computer program product starts with an initial placement of an electronic design and derives a legal placement by using the incremental placement technique while minimizing the perturbation impact or the total quadratic movement of instances. In some embodiments, an augmented or incremental clumping technique based data structure is utilized for rapid and substantially exact perturbation prediction of effects of local incremental placement operations. | 02-11-2010 |
| 20100050144 | SYSTEM AND METHOD FOR EMPLOYING SIGNOFF-QUALITY TIMING ANALYSIS INFORMATION TO REDUCE LEAKAGE POWER IN AN ELECTRONIC CIRCUIT AND ELECTRONIC DESIGN AUTOMATION TOOL INCORPORATING THE SAME - A leakage power recovery system and method, and a electronic design automation (EDA) tool incorporating either or both of the system and the method. In one embodiment, the timing signoff tool includes: (1) a power recovery module configured to make first conditional replacements of cells in at least one path in a circuit design with lower leakage cells and estimate a delay and a slack of the at least one path based on the first conditional replacement and (2) a speed recovery module associated with the power recovery module and configured to determine whether the first conditional replacements cause a timing violation with respect to the at least one path and make second conditional replacements with higher leakage cells until the timing violation is removed. | 02-25-2010 |
| 20100058267 | PLACE-AND-ROUTE LAYOUT METHOD WITH SAME FOOTPRINT CELLS - This invention discloses a method for automatically generating an integrated circuit (IC) layout, the method comprises determining a first cell height, creating a plurality of standard cells all having the first cell height, and generating the IC layout from the plurality of standard cells by placing and routing thereof. | 03-04-2010 |
| 20100095262 | Schematic Generation From Analog Netlists - The invention concerns the generation of schematics from analog netlists. Various implementations of the invention provide that an analog netlist defining a number of hardware components and the connectivity between the hardware components is identified. Subsequently, the netlist is sorted and partitioned into component groups. The component groups are arranged and lines are routed between the component groups. The corresponding hardware components are arranged within the component groups and a schematic corresponding to the arranged hardware components is generated. | 04-15-2010 |
| 20100100861 | Modifying integrated circuit layout - A layout for an integrated circuit includes standard cells | 04-22-2010 |
| 20100131912 | RETIMING OF MULTIRATE SYSTEM - Methods and apparatuses for retiming of multirate system for clock period minimization with a polynomial time without sub-optimality. In an embodiment, a normalized factor vector for the nodes of multirate graph is introduced, allowing the formulation of the multirate graph retiming constraints to a form similar to a single rate graph. In an aspect, the retiming constraints are formulated to allowed the usage of linear programming methodology instead of integer linear programming, thus significantly reducing the complexity of the solving algorithm. The present methodology also uses multirate constraints, avoiding unfolding to single rate equivalent, thus avoiding graph size increase. In a preferred embodiment, the parameters of the multirate system are normalized to the normalized factor vector, providing efficient algorithm in term of computational time and memory usage, without any sub-optimality. | 05-27-2010 |
| 20100131913 | METHOD AND APPARATUS FOR SCALING I/O-CELL PLACEMENT DURING DIE-SIZE OPTIMIZATION - One embodiment of the present invention provides a system that scales an I/O-cell placement during die-size optimization. During operation, the system starts by receiving an initial die-size for a die and an initial I/O-cell placement for a set of I/O cells. The system also receives a target die-size for the die. The system then determines die-size changes between the initial die-size and the target die-size. Next, the system identifies available spaces between the set of I/O cells in the initial I/O-cell placement. The system subsequently scales the initial I/O-cell placement based on the identified available spaces and the die-size changes to obtain a new I/O-cell placement which fits in the target die-size. | 05-27-2010 |
| 20100153897 | SYSTEM AND METHOD FOR EMPLOYING SIGNOFF-QUALITY TIMING ANALYSIS INFORMATION CONCURRENTLY IN MULTIPLE SCENARIOS TO REDUCE LEAKAGE POWER IN AN ELECTRONIC CIRCUIT AND ELECTRONIC DESIGN AUTOMATION TOOL INCORPORATING THE SAME - A leakage power recovery system and method, and a electronic design automation (EDA) tool incorporating either or both of the system and the method. In one embodiment, the timing signoff tool includes: (1) a power recovery module configured to carry out an instance of an initial power recovery process in each of multiple scenarios concurrently, the initial power recovery process including making first conditional replacements of cells in at least one path in a circuit design with lower leakage cells and estimating a delay and a slack of the at least one path based on the first conditional replacements and (2) a speed recovery module associated with the power recovery module and configured to carry out a speed recovery process in each of the multiple scenarios concurrently, the speed recovery process including determining whether the first conditional replacements cause a timing violation with respect to the at least one path and making second conditional replacements with higher leakage cells until the timing violation is removed. | 06-17-2010 |
| 20100218154 | METHOD FOR DESIGNING CELL LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT - With a conventional method for designing cell layout, it is necessary to give relative positional information in advance to all cells to be arranged. Furthermore, the conventional method is troublesome because it is necessary to correct relative positional information of cells after confirming a result of temporary layout. Therefore, it takes time to obtain a layout result. To avoid these problems, cells of a specific type specified from outside, or cells satisfying specific conditions, are extracted and arranged first or limited to a layout position by specifying a layout position, then arranging the remaining cells using a general layout algorithm. | 08-26-2010 |
| 20100223585 | DUMMY FILL TO REDUCE SHALLOW TRENCH ISOLATION (STI) STRESS VARIATION ON TRANSISTOR PERFORMANCE - A method of forming an integrated circuit structure on a chip includes extracting an active layer from a design of the integrated circuit structure, forming a guard band conforming to the shape of the active layer, the guard band surrounds the active layer, and the guard band is spaced from the active layer at a first spacing in the X-axis direction and at a second spacing in the Y-axis direction, removing any part of the guard band that violates design rules, removing convex corners of the guard band, and adding dummy diffusion patterns into the remaining space of the chip outside the guard band. The first and second spacing can be specified as the same spacings in a Spice model characterization of the integrated circuit structure. The dummy diffusion patterns with different granularities can be added so that the diffusion density is substantially uniform over the chip. | 09-02-2010 |
| 20100229140 | METHOD AND SYSTEM FOR ADAPTING A CIRCUIT LAYOUT TO A PREDEFINED GRID - A method for adapting objects of a circuit layout to a predefined grid, wherein the objects are a representation of an integrated circuit, each object being defined by elements including a reference element. A reference element is selected which is unaligned to the predefined grid, and a gridline is selected from the predefined grid. A grid-constraint is generated which is subsequently added to a set of constraints associated with the circuit layout. The set of constraints includes design-rule constraints for applying a design rule to groups of objects of the circuit layout. The objects of the circuit layout are adapted to substantially comply with the set of constraints. Reference elements unaligned to the predefined grid are gridded while compliance of the circuit layout with the design rules is maintained. | 09-09-2010 |
| 20100229141 | TIMING VIOLATION DEBUGGING INSIDE PLACE AND ROUTE TOOL - A storage medium for use in a computer to develop a circuit design. The storage medium recording a software tool that may be readable and executable by the computer. The software tool generally includes the steps of (A) receiving a first user input that identifies a specific cell of a plurality of existing cells in the circuit design, the specific cell having a timing characteristic, (B) generating a replacement display corresponding to the specific cell, the replacement display comprising a plurality of alternate cells suitable to replace the specific cell, each of the alternate cells having a different value associated with the timing characteristic of the specific cell, (C) receiving a second user input that identifies a replacement cell of the alternate cells and (D) automatically generating a first engineering change order to replace the specific cell with the replacement cell. | 09-09-2010 |
| 20100262944 | OBJECT PLACEMENT IN INTEGRATED CIRCUIT DESIGN - A method, system, and computer usable program product for an improved object placement in integrated circuit design are provided in the illustrative embodiments. The IC design includes cells, the cells including electronic components, wires, and pins defined for interconnections of the IC. An initial placement corresponding to the design is received. A characteristic of the initial placement is estimated, which may include congestion, pin density, or both in an area of the initial placement. A transformation is performed on a part of the initial placement including the area to improve the characteristic. If the characteristic has improved in the transformed placement, a final placement corresponding to the transformed placement is produced. The transformation may be any combination of resizing an object, weighting a connection, clustering a plurality of objects, shortening of a route taken by a wire, and straightening a bend in a wire in the initial placement. | 10-14-2010 |
| 20100269081 | Standard Cells Having Flexible Layout Architecture/Boundaries - An integrated circuit layout includes a standard cell, which includes a first gate strip and a second gate strip parallel to each other and having a gate pitch; a first boundary and a second boundary on opposite ends of the first standard cell; and a third boundary and a fourth boundary on opposite ends of the first standard cell and parallel to the first gate strip and the second gate strip. A cell pitch between the third boundary and the fourth boundary is not equal to integer times the gate pitch. A PMOS transistor is formed of the first gate strip and a first active region. An NMOS transistor is formed of the first gate strip and a second active region. | 10-21-2010 |
| 20100287518 | Cell Circuit and Layout with Linear Finfet Structures - A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively. | 11-11-2010 |
