| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 716007000 | Partitioning (e.g., function block, ordering constraint) | 24 |
| 20080216037 | SYSTEM FOR USING PARTITIONED MASKS TO BUILD A CHIP - A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A system is provided comprising a mask set having a plurality of reusable masks corresponding to a plurality of hard intellectual property (IP) components; a generic array type cell mask; and a custom blocking mask that includes blocking regions that positionally correspond with a set of IP components printed on a die. | 09-04-2008 |
| 20080222587 | Integrated Circuit Cell Library for Multiple Patterning - A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium. | 09-11-2008 |
| 20080250373 | OPTIMIZING ASIC PINOUTS FOR HDI - Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB. | 10-09-2008 |
| 20080256501 | System and Method for Updating a Time-Related State of a Migrating Logical Partition - An apparatus, program product and method for automatically and transparently determining the time required to migrate a logical partition. This determined latency may be used to update clocks and other time-related values of the migrated logical partition. | 10-16-2008 |
| 20080301607 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR HIERARCHICAL INTEGRATED CIRCUIT REPARTITIONING - A method, system, and computer program product for hierarchical integrated circuit repartitioning are provided. The method includes receiving parent level placement data for one or more interconnecting elements and designating at least one child to receive a pushdown of the one or more interconnecting elements from the parent level. For each child designated to receive the pushdown of the one or more interconnecting elements, the method further includes determining a physical coverage area of the child, identifying which of the one or more interconnecting elements within the physical coverage area of the child to pushdown into the child, generating an interconnecting element pushdown list for the child, including wiring layer information, and outputting the interconnecting element pushdown list. | 12-04-2008 |
| 20080301608 | Methods and apparatuses for designing multiplexers - Methods and apparatuses for designing multiplexers in one or more integrated circuits are described. One exemplary method includes receiving a representation of a first multiplexer and converting the representation to a partition neutral representation of the first multiplexer and partitioning the partition neutral representation to create a plurality of second multiplexers. Another exemplary method includes decomposing a representation of a first multiplexer into a representation of a plurality of second multiplexers, which are coupled together at a common output without any intervening multiplexers between the second multiplexers and the common output, and partitioning the second multiplexers between portions of at least one integrated circuit. | 12-04-2008 |
| 20090037861 | SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA FOR ADJUSTING LAYOUT DATABASE HIERARCHIES FOR MORE EFFICIENT DATABASE PROCESSING AND STORAGE - Systems and methods are disclosed for organizing layout data. A layout database is analyzed to determine a statistical distribution of cells within the database based on the shape complexity of each cell. Cells with a shape complexity that exceeds a complex threshold may be defined as complex cells, which are examined to find candidate shapes that may be moved to one or more child cells within the complex cell. The layout database is then stored as an output layout database with at least some of these candidate shapes moved to child cells within the complex cells. Simple cells with a shape complexity that is less than a simple threshold may have their layout shapes moved to a parent cell of that simple cell. The database may also be partitioned into multiple dispatchable segments, which may be distributed to multiple processing threads for performing additional processes on the database. | 02-05-2009 |
| 20090044161 | THIN-FILM TRANSISTOR CIRCUIT, DESIGN METHOD FOR THIN-FILM TRANSISTOR, DESIGN PROGRAM FOR THIN-FILM TRANSISTOR CIRCUIT, DESIGN PROGRAM RECORDING MEDIUM, DESIGN LIBRARY DATABASE, AND DISPLAY DEVICE - A thin-film transistor circuit includes a crystallized semiconductor thin film two-dimensionally partitioned into crystal-grain-defining areas each of which accommodates a crystal grain larger than a predetermined size, thin-film transistors each of which has a channel region placed at the center position of a corresponding one of the crystal-grain-defining areas, and wirings which interconnect the thin-film transistors. | 02-12-2009 |
| 20090089730 | Scalable Dependent State Element Identification - Methods, systems and software products are provided to enhance the scalability of dependent state analysis element identification. In a method of partitioning a model representing a state machine, a variable is selected from the variables of the model, and a first set of variables are identified that support the selected variable. Then a second set of variables is identified that have overlapping support of the first set of variables. The second set of variables is a partition suitable for use in determining an overapproximation of the reachable states of the selected variable. | 04-02-2009 |
| 20090106723 | SEMICONDUCTOR DEVICE METAL PROGRAMMABLE POOLING AND DIES - A pool of die designs includes die designs having metal programmable base layers. Die designs from the pool are selected for use in fabricating dies. Die designs are added to the pool by customization of die designs already in the pool or by preparing custom die designs that incorporate a metal programmable base layer. In some embodiments multi-tile dies are provided with I/O slots configurable for either inter tile communication or inter die communication. | 04-23-2009 |
| 20090106724 | Transition Balancing For Noise Reduction/Di/Dt Reduction During Design, Synthesis, and Physical Design - An embodiment of a design structure is shown for noise reduction comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks. | 04-23-2009 |
| 20090125859 | Methods for Optimal Timing-Driven Cloning Under Linear Delay Model - A timing-driven cloning method iteratively partitions sinks of the net into different sets of clusters and for each set computes a figure of merit for a cloned gate location which optimizes timing based on linear delay, that is, a delay proportional to the distance between the cloned gate location and the sinks. The set having the highest figure of merit is selected as the best solution. The original gate may also be moved to a timing-optimized location. The sinks are advantageously partitioned using boundaries of Voronoi polygons defined by a diamond region surrounding the original gate, or vice versa. The figure of merit may be for example worst slack, a sum of slacks at the sinks in the second cluster, or a linear combination of worst slack and sum of the slacks. | 05-14-2009 |
| 20090158229 | METHOD OF AREA COMPACTION FOR INTEGRATED CIRCUIT LAYOUT DESIGN - A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block. | 06-18-2009 |
| 20090217227 | METHOD AND APPARATUS FOR PARALLEL PROCESSING OF SEMICONDUCTOR CHIP DESIGNS - In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel. | 08-27-2009 |
| 20090222782 | NETWORK ANALYSIS WITH STEINER TREES - Networks may be analyzed using Steiner trees. In an example embodiment, a method includes acts of receiving, accepting, creating, and analyzing. Data specifying a network is received. Steiner tree parameters are accepted. A Steiner tree model is created on the data specifying the network responsive to the Steiner tree parameters. The Steiner tree model includes a local representation having a depth constraint for neighborhood vertices. The data specifying the network is analyzed to ascertain a Steiner tree solution based on the Steiner tree model, which includes the local representation, and using a locally-oriented combinatorial algorithm. | 09-03-2009 |
| 20090276747 | Segmenting Integrated Circuit Layout Design Files Using Speculative Parsing - A method of parsing integrated circuit layout design data. According to some implementations, the segment boundaries are designated by first identifying data in the integrated circuit layout design data that matches a cell record start value. Next, the subsequent data is parsed, until a threshold amount of subsequent data has been parsed without identifying another cell record start value. When the threshold amount of subsequent data has been parsed without identifying another cell record start value, the next data in the integrated circuit layout design data matching a cell record start value is designated as a segment boundary. Integrated circuit layout design data can be segmented sequentially, or by using dyadic division. Once the integrated circuit layout design data has been broken up into segments, the segments can be provided to a parallel processing computing system for parsing in parallel. | 11-05-2009 |
| 20090293034 | METHOD AND SYSTEM FOR PROCESSING GEOMETRICAL LAYOUT DESIGN DATA - A method and system for processing geometrical layout design data in a computation network. The method includes assigning one or more partitions of the geometrical layout design data to one or more computing devices. One or more partitions are assigned based on first predefined parameters. The method further includes receiving a minimum-hierarchy representation of the geometrical layout design data and a partition information corresponding to one or more partition assigned. The partition information corresponding to a partition assigned includes a spatial information corresponding to the partition. Further, the minimum-hierarchy representation includes a plurality of cells. Each cell in the minimum-hierarchy representation may include zero or more bounding box information and zero or more cell-references. Further, the method includes retrieving one or more fragments based on each of the partition information and the minimum-hierarchy representation. A fragment can include one or more parts of a cell of the geometrical layout design data. | 11-26-2009 |
| 20090300566 | Hierarchical Partitioning - Some embodiments provide a method of simulating an electrical circuit that receives a circuit description that has a set of sub-circuits. The method defines several partitions for several sub-circuits. The method then simulates the circuit using the partitioned sub-circuits. In some embodiments, the method ranks the sub-circuits prior to partitioning based on a parent-child relationship that shows how a sub-circuit is instantiated by other sub-circuits. These embodiments partition child sub-circuits first. Some embodiments provide a method of partitioning an electrical circuit that has a set of sub-circuits. For a particular sub-circuit that is instantiated from other sub-circuits, the method duplicates the particular sub-circuit into a first copy and a second copy when one port of the particular sub-circuit is connected to a voltage source in at least one instance and the same port is not connected to a voltage source in at least another instance. | 12-03-2009 |
| 20100011326 | PRINTED CIRCUIT BOARD DESIGN SUPPORT PROGRAM, RECORDING MEDIUM, AND PRINTED CIRCUIT BOARD DESIGN SUPPORT METHOD - To automatically arrange vias on a printed circuit board so as to satisfy a predetermined condition. A printed circuit board design support method for causing a computer to execute a ground conductive area identifying conductive areas which can be used as grounds of a printed circuit board having a plurality of condicutive layers, an extracting an overlapping conductive area in which the conductive areas identified in the ground conductive area identifying are two-dimensionally overlapped with one another, and an automatic arranging interlayer connection members configured to electrically connect at least two layers with one another among the plurality of conductive areas in the overlapping conductive area extracted in the extracting at an interval within a predetermined distance. | 01-14-2010 |
| 20100023905 | Critical Area Deterministic Sampling - A layout design for a portion of a microdevice design is partitioned into sections or “bins.” Next, a critical area value is estimated for one or more of the bins. One or more of these estimated bins is then selected for a more detailed analysis. After the estimated bins have been selected, a detailed critical area analysis of the selected bins is performed. Once the actual critical area for each of the estimated bins has been determined, the actual critical areas for selected estimated bins are correlated with those bin's corresponding estimated values. By correlating the actual critical areas of selected estimated bin to those bin's corresponding estimated values, a mapping function can be determined. After the mapping function has been determined, it is applied to the estimated values for each of the remaining bins of the layout design (i.e., the bins for which an actual critical area have not yet been determined) to obtain critical area information for the layout design. The layout design can then be modified based upon the obtained critical area information. | 01-28-2010 |
| 20100031210 | APPARATUS, METHOD AND PROGRAM FOR PROCESSING DATA - A data processor which includes: a circuit data providing section which provides circuit data including a character string; a replacement section which bijectively maps the character string of the provided circuit data to integer values; and a data developer which executes data processing including hierarchical development with respect to the circuit data of the integer values obtained by the replacement section. | 02-04-2010 |
| 20100031211 | Methods for Controlling Microloading Variation in Semiconductor Wafer Layout and Fabrication - Problematic open areas are identified in a semiconductor wafer layout. The problematic open areas have a size variation relative to one or more neighboring open areas of the layout sufficient to cause adverse microloading variation. In one embodiment, the adverse microloading variation is controlled by shifting a number of layout features to interdict the problematic open areas. In another embodiment, the adverse microloading variation is controlled by defining and placing a number of dummy layout features to shield actual layout features that neighbor the problematic open areas. In another embodiment, the adverse microloading variation is controlled by utilizing sacrificial layout features which are actually fabricated on the wafer temporarily to eliminate microloading variation, and which are subsequently removed from the wafer to leave behind the desired permanent structures. | 02-04-2010 |
| 20100077369 | LAYOUT DESIGN METHOD, APPARATUS AND STORAGE MEDIUM - A layout design support apparatus divides a first module obtained by dividing a semiconductor integrated circuit into a plurality of second modules in order to support a layout design for determining the disposition of each cell constituting the semiconductor integrated circuit and wiring, and makes the detailed design of a layout for determining the disposition of each cell in the second module and wiring for each second module. | 03-25-2010 |
| 20100083207 | System for Designing Functional Circuit and Method for Designing Functional Circuit - A hierarchizing means | 04-01-2010 |
