Entries |
Document | Title | Date |
20080201669 | METHOD AND APPARATUS FOR IDENTIFYING REDUNDANT SCAN ELEMENTS - An approach for producing optimized integrated circuit designs that support sequential flow partial scan testing may be embedded within an integrated circuit electronic design device. Using the approach, an integrated circuit design may be analyzed to identify and remove scan-enabled memory elements, or scan elements, that are redundant. The redundant scan elements may be replaced with memory elements that do not support scan testing. Once the redundant scan elements are removed, the integrated circuit design my be optimized using automated techniques to reduce the area of the integrated circuit physical layout and to simplify/minimize routing connections between remaining features within the integrated circuit design. The described approach may achieve a reduced total area layout and complexity, an improved time/frequency response, and/or reduced power consumption and/or heat generation within the circuit design, without reducing the fault coverage achieve during testing. | 08-21-2008 |
20080216025 | Tunneling as a Boundary Congestion Relief Mechanism - Simultaneous Dynamical Integration modeling techniques are applied to global placement of elements of integrated circuits as described by netlists specifying interconnection of morphable-devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through a continuous location space in continuous time, and is used to derive placements of the morphable-devices having one-to-one correspondences with the nodes. Nodes under the influence of net attractive forces, computed based on the interconnections between the morphable devices, tend to coalesce into well-organized topologies. Nodes are also affected by spreading forces determined by density fields that are developed based on local spatial node population. | 09-04-2008 |
20080216026 | INTEGRATED CIRCUIT LAYOUT DESIGN SUPPORTING DEVICE - Provided is an integrated circuit layout design supporting device which can reduce the wiring length by avoiding bypass wirings when a plurality of same-type macro blocks are used. The integrated circuit layout design supporting device includes a terminal coordinate calculation control unit and a layout processing control unit. The terminal coordinate calculation control unit considers the plurality of same-type macro blocks included in a plurality of types of macro blocks as each of different types of macro blocks, and calculates the optimum coordinate positions of each macro terminal of each macro block. The layout processing control unit performs various types of wiring layout processing related to each of the macro terminals based on each of the macro terminal positions calculated by the terminal coordinate calculation control unit. | 09-04-2008 |
20080222577 | Method for designing array antennas - A method for designing low signature array antennas using a calculation method. The method proposes a way of improving antenna and signature performance of array antennas. According to the method electromagnetic antenna and signature characteristics are specified, an iterative optimizing method is performed to design the antenna to fulfil the specified characteristics, the iterative method is interrupted when a design fulfils the specified characteristics, and the specified characteristics are readjusted in an iterative optimizing method to follow if the specified characteristics not are fulfilled. | 09-11-2008 |
20080244472 | METHOD FOR ACCELERATING THE GENERATION OF AN OPTIMIZED GATE-LEVEL REPRESENTATION FROM A RTL REPRESENTATION - A method for accelerating the generation of an optimized netlist from a RTL representation is provided. The method optimizes a given RTL description of an integrated circuit (IC) design by: generating a static single assignment (SSA) graph; creating value range propagation for each variable in the SSA graph; and, applying one or more of a set of optimization algorithms on the SSA graph. The optimization algorithms include, but are not limited to, dead-code elimination, bitwidth analysis, redundancy elimination, iteration loop optimization, algebraic simplification and so on. These algorithms operate on a word-level description to enable fast optimization. Furthermore, the optimized RTL accelerates the overall flow of an IC design. | 10-02-2008 |
20080244473 | Modifying Integrated Circuit Designs to Achieve Multiple Operating Frequency Targets - A first integrated circuit design with a first maximum operating frequency is modified to achieve a second integrated circuit design with a second maximum operating frequency. The integrated circuit design comprises an arrangement of cells. Each of these cells drives a signal that propagates through a net of other circuit elements to one or more nodes that are limited by respective signal timing constraints. An analytical cost function is assigned to each of the cells. Each analytical cost function comprises a value for its respective cell that is based on one or more speed-related factors indicative of the impact of the respective cell on the first maximum operating frequency of the first integrated circuit design. One or more of the cells are replaced with different cells based on the determined analytical cost functions. | 10-02-2008 |
20080244474 | Cell library management for power optimization - A method of managing a cell library regarding power optimization is disclosed. The method generally includes the steps of (A) reading a plurality of first modules within a first region of a circuit design stored in a design file, (B) calculating a first merit value indicating a relative sensitivity of the first region to a power consumption, the first merit value having a range from a static power dominated value to a dynamic power dominated value and (C) creating a constraint file configured to limit a design tool to a first subset of a plurality of replacement modules based on the first merit value such that the design tool automatically optimizes the power consumption of the first region by replacing at least one of the first modules with at least one of the replacement modules within the first subset, the replacement modules residing in a library file. | 10-02-2008 |
20080250360 | METHOD FOR GENERATING COMPILER, SIMULATION, SYNTHESIS AND TEST SUITE FROM A COMMON PROCESSOR SPECIFICATION - A hardware/software design tool converts an electronic design specification and zero or more technology specifications into realization of the electronic design in computer hardware, software and firmware. It compiles design and logic technology specifications into a model which can be utilized for behavioral analysis of logical characteristics. It translates partitions of the design and one or more logic technologies into one or more processor intermediates or binaries suitable for execution on multi-purpose processing units. It translates partitions of the design and logic technology into a collection of cells and interconnects suitable for input to physical design processes such as is required to target a FPGA, ASIC, system-on-a-chip or custom logic. It analyzes behavior of the embedded binaries running on processing units and implementations augmented by additional physical technology and parameters, yielding a more detailed prediction of the resulting hardware/software system behavior when realized through manufacturing. | 10-09-2008 |
20080250361 | Method of correcting a design pattern for an integrated circuit and an apparatus for performing the same - In an apparatus and method for automatically correcting a design pattern in view of different process defects, defect characteristic functions that indicate frequencies of each process defect independent from one another are generated, and a normalization factor that indicates relationships between the defect characteristic functions is determined. A general defect characteristic function indicating a frequency of general defects is generated using the defect characteristic functions and the normalization factor. The general defect causes the same process failure as caused by each of the process defects. The design pattern is modified using the general defect characteristic function in such a manner that the frequency of the general defects is minimized when at least one portion of the design pattern corresponding to the model pattern is transcribed on the substrate. Accordingly, the whole design pattern may be automatically corrected based on the general defect characteristic function. | 10-09-2008 |
20080250362 | Method and System Product for Implementing Uncertainty in Integrated Circuit Designs with Programmable Logic - Disclosed is a method, system and computer program product to specify an integrated circuit. The integrated circuit includes a hardwired specific logic technology portion and a programmable specific logic technology portion. The method includes generating a hybrid logic network by mapping each uncertain logic function to an abstract programmable logic element implementation thereof and by mapping each known logic function to a technology-independent logic element implementation thereof; simplifying the hybrid logic network using logic synthesis optimizations; mapping the simplified hybrid logic network to a specific technology by mapping the abstract programmable logic element implementation to the specific programmable logic technology and the technology-independent logic element implementation to the specific logic technology; and further includes optimizing the mapped network to meet performance constraints. Generating involves using integrated circuit specification language extensions that include an Uncertain Function that is used in place of a logic function or operator, an Uncertain Function Assertion for imposing at least one constraint on the Uncertain Function, an Uncertain Register for a register having a programmable size within a specified range and an Uncertain Constant. | 10-09-2008 |
20080256496 | METHOD OF DESIGNING AND MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device designing method includes calculating capacitance. The semiconductor device has a semiconductor substrate, an insulator formed on the semiconductor substrate, and an electrode formed on the insulator. The capacitance is calculated under an approximation assuming a portion of the semiconductor substrate, the insulator and a portion of the electrode to be one of a conductor and a dielectric depending on electric characteristics thereof, respectively. | 10-16-2008 |
20080263481 | APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS - A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD. | 10-23-2008 |
20080288898 | PREDICTION OF DYNAMIC CURRENT WAVEFORM AND SPECTRUM IN A SEMICONDUCTOR DEVICE - A method for determining a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption characteristics for the circuit design. From the timing characteristics and the power consumption characteristics a time domain current waveform is constructed. The time domain current waveform is then converted to a frequency domain current waveform. With the frequency domain waveform, one skilled in the art can then identify a location and an amount of decoupling capacitors for a printed circuit board housing the circuit design based on the frequency domain current waveform. A computing system configured to perform the method is also provided. | 11-20-2008 |
20080288899 | TECHNIQUES FOR USE WITH AUTOMATED CIRCUIT DESIGN AND SIMULATIONS - An apparatus having two or more parallel carry chain structures, each of the carry chain structures comprising a series of logical structures, where at least one of the logical structures within each of the carry chain structures has an associated input node, output node and carry node. The input node corresponds to a function input term, the output node corresponds to an output term of the function and the carry node corresponds to a carry value to a following logical structure in the series of logical structures. | 11-20-2008 |
20080295041 | System and Method for Power Domain Optimization - A method for electronic circuit power plane design includes analyzing direct current (DC) properties of a power plane of an electronic circuit. The method includes analyzing power net inductance (PNI) properties of the power plane and identifying victim areas of the power plane having predetermined current density properties based on the DC properties and the PNI properties of the power plane. The method further includes replacing the identified victim areas with ground (GND) shapes to form a modified power plane. | 11-27-2008 |
20080295042 | SYSTEM FOR DELAY REDUCTION DURING TECHNOLOGY MAPPING IN FPGA - The present invention relates to a system for reducing the delay during technology mapping in FPGA that comprises locating and replicating the critical fan-in nodes in the mapping logic. Parallel computation is performed on the replicated nodes followed by selection of the output. The delay reduction approach in the present invention gives a highly efficient logic implementation when delay is the prime concern and area can be afforded to be expanded. The technique relies on replicating logic and performing parallel computation on delay critical LUT's. | 11-27-2008 |
20080301592 | METHODOLOGY FOR AUTOMATED DESIGN OF VERTICAL PARALLEL PLATE CAPACITORS - Apparatus and program product for designing vertical parallel plate (VPP) capacitor structures in which the capacitor plates in different conductive layers of the capacitor stack have a different physical spacing. The methodology optimizes the physical spacing of the plates in each conductive layer to achieve a targeted electrostatic discharge protection level and, thereby, supply electrostatic discharge robustness. | 12-04-2008 |
20080301593 | Method For Automatic Clock Gating To Save Power - A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure. | 12-04-2008 |
20080301594 | Method For Optimized Automatic Clock Gating - A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic. | 12-04-2008 |
20080301595 | OPTIMIZATION OF LASER PARAMETERS TO ACHIEVE DESIRED PERFORMANCE - One example disclosed herein relates to a method of at least partially optimizing one or more output performance parameters of a laser die. The method includes an act of identifying one or more output performance parameters to be at least partially optimized, an act of identifying one or more design parameters associated with the one or more output performance parameters, an act of determining a subset of the one or more design parameters that should be varied so as to at least partially effect the one or more output performance parameters, an act of varying the subset of design parameters to produce one or more intermediate results, and an act of using the intermediate results to determine values for the one or more design parameters such that the one or more performance parameters are at least partially optimized | 12-04-2008 |
20080307372 | METHOD AND SYSTEM FOR PERFORMING MINIMIZATION OF INPUT COUNT DURING STRUCTURAL NETLIST OVERAPPROXIMATION - A method for performing verification is disclosed. The method includes selecting a set of gates to add to a first localization netlist and forming a refinement netlist. A min-cut is computed with sinks having one or more gates in the refinement netlist and sources comprising one or more inputs of an original netlist and one or more registers registers of the original netlist which are not part of the refinement netlist. A final localized netlist is obtained by adding one or more gates to the refinement netlist to grow the refinement netlist until reaching one or more cut-gates of the min-cut. | 12-11-2008 |
20080313576 | SYSTEM AND METHOD FOR INCLUDING PROTECTIVE VOLTAGE SWITCHABLE DIELECTRIC MATERIAL IN THE DESIGN OR SIMULATION OF SUBSTRATE DEVICES - A substrate device is designed by identifying one or more criteria for handling of a transient electrical event on the substrate device. The one or more criteria may be based at least in part on an input provided from a designer. From the one or more criteria, one or more characteristics may be determined for integrating VSD material as a layer within or on at least a portion of the substrate device. The layer of VSD material may be positioned to protect one or more components of the substrate from the transient electrical condition | 12-18-2008 |
20080313577 | VLSI ARTWORK LEGALIZATION FOR HIERARCHICAL DESIGNS WITH MULTIPLE GRID CONSTRAINTS - A system and method are disclosed for legalizing a flat or hierarchical VLSI layout to meet multiple grid constraints and conventional ground rules. Given a set of ground rules with multiple grid constraints and a VLSI layout (either hierarchical or flat) which is layout-versus-schematic (LVS) correct but may not be ground rule correct, the system and method provide a legalized layout which meets the multiple grid constraints while maintaining LVS correctness and fixing the ground rule errors as much as possible with minimum layout perturbation from the input design. The system and method support multiple grid pitch constraints for hierarchical design, and provide for LVS correctness to be maintained while an on-grid solution possibly with some spacing violations. | 12-18-2008 |
20080320420 | EFFICIENT CELL SWAPPING SYSTEM FOR LEAKAGE POWER REDUCTION IN A MULTI-THRESHOLD VOLTAGE PROCESS - A method for designing an integrated circuit, comprising the steps of (A) calculating an efficiency value for each of a plurality of equivalent cells in the design; and (B) selecting a number of the plurality of equivalent cells based on the efficiency values. The equivalent cells (i) decrease an overall delay of a path to meet a timing specification, and (ii) minimize an increase in overall leakage current. | 12-25-2008 |
20090007027 | TRANSLATING A USER DESIGN IN A CONFIGURABLE IC FOR DEBUGGING THE USER DESIGN - Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit elements(s). The method defines the second IC design for the configurable IC and generates output data for the eliminated circuit element(s) to allow for monitoring the user design. | 01-01-2009 |
20090007028 | WAFER LAYOUT OPTIMIZATION METHOD AND SYSTEM - For determining an optimized wafer layout, at least two wafer layouts are specified for a given wafer, each wafer layout defining the location of a plurality of die with regard to the wafer. An optimization parameter value of at least one optimization parameter is determined for each of the at least two wafer layouts. The at least one optimization parameter includes at least one of a number of exposure fields necessary for exposing the respective wafer layout and a number of die of the wafer layout. The optimized wafer layout is selected out of the at least two wafer layouts depending on the optimization parameter values. | 01-01-2009 |
20090007029 | METHOD FOR DESIGNING DRIVER - A method for designing a driver including matching stages having transistors matched to each other is disclosed, including interpreting an offset caused by a mismatched characteristic difference of a plurality of transistors using a current change in a matching stage. A size of the transistors may be determined using the results of interpreting of the offset, and the size may be adjusted until a simulated yield of the driver obtained by a simulation using measured matching information and the determined size of the transistors approximates a targeted yield. The resulting determined size may be used to fabricate the driver, to obtain a test yield of the manufactured driver. If the test yield is not the targeted yield, the measured matching information may be adjusted until the adjusted yield of the driver obtained by the simulation approximates the test yield. Therefore, the offset of the driver may be minimized, making it possible to improve output characteristics of the driver, optimize the area, improve the yield, reduce the frequency of revisions in the development of the chip, and/or shorten the period of the chip design. | 01-01-2009 |
20090013289 | CIRCUIT DESIGN OPTIMIZATION OF INTEGRATED CIRCUIT BASED CLOCK GATED MEMORY ELEMENTS - A novel method for optimizing the design of digital circuits containing clock gated memory elements. The method unclock gates memory elements by adding necessary feedback loops. Logic functions of memory element outputs in the circuit are viewed as a whole, rather than as separate functions for each input. Detection of duplicate unclock gated memory elements is then effected by identifying identical danonical representations of said unclock gated memory elements. Identified duplicate clock gated memory elements can then be eliminated from the original digital circuit. Further optimization can be accomplished by applying standard logic optimization algorithms to all unclock gated memory elements in said digital circuit. The resulting optimized circuit is clock gated and replaces the original clock gated circuit in said digital circuit. | 01-08-2009 |
20090031259 | OBTAINING A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIRCUIT LAYOUT OPTIMIZATION - An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represented as an original integer linear programming problem. A relaxed linear programming problem is derived from the original integer linear programming problem by relaxing integer constraints and using relaxation variables on infeasible constraints. The relaxed linear programming problem is solved to obtain a linear programming solution. A subset of variables from the relaxed linear programming problem is rounded to integer values according to the linear programming solution. Next, it is determined whether all the variables are rounded to integer values. Unrounded variables are iterated back through the deriving of the integer linear programming problem, solving of the relaxed linear programming problem, and rounding of a subset of variables. A modified hierarchical circuit layout is generated in response to a determination that all the variables are rounded to integer values. | 01-29-2009 |
20090031260 | Method, Computer Program and System Providing for Semiconductor Processes Optimization - A method, computer program and system for the optimization of semiconductor process parameters given a pre-specified set of targets and constraints on electrical performance metrics are disclosed. Semiconductor process engineers who are not expert in the art of electrical analysis or mathematical optimization can readily use the method of this invention in optimizing semiconductor process parameters. Accommodates the differences in design styles, metal layer routing, and electrical metrics using priority schedules that are easy to input and understand. Enables the exploration of the process parameter space using primitive process tolerances and accurate electrical information provided by field solvers and circuit analysis programs. | 01-29-2009 |
20090031261 | CHARACTERIZATION AND REDUCTION OF VARIATION FOR INTEGRATED CIRCUITS - A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits. | 01-29-2009 |
20090031262 | MASK PATTERN FORMATION METHOD, MASK PATTERN FORMATION APPARATUS, AND LITHOGRAPHY MASK - A mask pattern formation method and apparatus capable of performing OPC and lithography verification and obtaining OPC result, and a lithography mask are provided. The method of forming a mask pattern from a design layout of a semiconductor integrated circuit comprises inputting a design layout, performing first OPC on the design layout, calculating a first evaluation value for a finished planar shape of a resist pattern corresponding to the design layout based on the first OPC, determining whether the first evaluation value satisfies a predetermined value, if the first evaluation value does not satisfy the predetermined value, locally altering the design layout, performing second OPC on the altered design layout, calculating a second evaluation value for the altered design layout, performing second determination, and if the second evaluation value satisfies the predetermined value, outputting the result of OPC and the first and second evaluation values. | 01-29-2009 |
20090037850 | POLYGONAL AREA DESIGN RULE CORRECTION METHOD FOR VLSI LAYOUTS - A method of polygonal area design rule correction for use in an electronic design automation tool for governing integrated circuit (IC) design layouts using one-dimensional (1-D) optimization, with steps of analyzing IC design layout data to identify violating polygons, partitioning violating polygons into rectangles in a direction of optimization, formulating an area constraint for each violating polygon to formulate a global linear programming (LP) problem that includes each constraint for each violating polygon and solving the global LP problem to obtain a real-valued solution. A next LP problem is created for each area constraint, and solved. The creating a next and solving the next LP problem and solving are repeated until the last “next LP problem” is solved using constraints and objectives representing sums or differences of no more than two optimization variables. | 02-05-2009 |
20090037851 | CONTEXT AWARE SUB-CIRCUIT LAYOUT MODIFICATION - A method, system and program product for context aware sub-circuit layout modification are disclosed. The method may include defining at least one context for the sub-circuit for each circuit that uses the sub-circuit; in the case that a plurality of contexts are defined, minimizing a number of contexts for the sub-circuit by combining contexts into at least one stage; placing each stage into a staged layout; and modifying the sub-circuit by modifying the staged layout. | 02-05-2009 |
20090037852 | PATTERN DATA GENERATION METHOD AND PATTERN DATA GENERATION PROGRAM - A pattern data generation method of an aspect of the present invention, the method includes creating at least one modification guide to modify a modification target point contained in pattern data, evaluating the modification guides on the basis of an evaluation item, the evaluation item being a change in the shape of the pattern data for the modification target point caused by the modification based on the modification guides or a change in electric characteristics of a pattern formed in accordance with the pattern data, selecting a predetermined modification guide from among the modification guides on the basis of the evaluation result of the modification guides, and modifying the modification target point in accordance with the selected modification guide. | 02-05-2009 |
20090044155 | METHOD AND SYSTEM FOR DESIGNING AN ELECTRONIC CIRCUIT - A method and system of designing an electronic circuit includes dividing a chip area of a design into a plurality of bins, identifying a candidate bin in the plurality of bins, and performing an area reduction on the candidate bin. | 02-12-2009 |
20090044156 | METHOD AND APPARATUS FOR NORMALIZING THERMAL GRADIENTS OVER SEMICONDUCTOR CHIP DESIGNS - A method and apparatus for normalizing thermal gradients over semiconductor chip designs is provided. One embodiment of a novel method for normalizing an expected thermal gradient includes determining a location of the thermal gradient in the semiconductor chip design and inserting at least one supplemental heat source into the semiconductor chip design such that the thermal gradient is normalized by heat dissipated by the supplemental heat source. | 02-12-2009 |
20090049414 | METHOD AND SYSTEM FOR REDUCING VIA STUB RESONANCE - Reducing via stub resonance in printed circuit boards. In one aspect, a method for reducing via stub resonance in a circuit board includes determining that resonance exists for a signal to be transmitted through a signal via extending across a plurality of layers in the circuit board. The resonance is caused by a via stub of the signal via, the via stub extending past a layer connected to the signal via. A location is determined for a ground via to be placed relative to the signal via, the location of the ground via being determined based on reducing the resonance for the signal to be transmitted in the signal via. | 02-19-2009 |
20090055780 | Simultaneous Power and Timing Optimization in Integrated Circuits by Performing Discrete Actions on Circuit Components - A graph-based iterative method is provided for selecting component modifications in an integrated circuit design that reduce the power consumption to a minimum while still meeting timing constraints. Channel-connected components are represented as nodes in a timing graph and edges in the timing graph represent directed paths. From the timing graph, a move graph is constructed containing a plurality of move nodes. Each move node represents a change to one of the components in one of the timing graph nodes. A given timing graph node can result in a plurality of move nodes. Move nodes can be merged into group nodes, and both the move nodes and group nodes are assigned a weight based on the change in power and timing effects of the associated components changes. These weights are used to select move nodes or group nodes. In general, a set of move or group nodes is selected representing the maximum cumulative weight and the components changes associated with the nodes in the set are performed on the integrated circuit design. Moves that cause timing violations are reversed. The node weights are updated following components changes and the selection of node sets is repeated iteratively until the power consumption converges to a minimum. | 02-26-2009 |
20090064061 | Layout Optimization Using Parameterized Cells - A method of layout optimization containing parameterized cells includes reading a physical design containing parameterized cells, creating a new version for each of usage of a given parameterized cell. The method optimizes physical design shapes of each new version of the parameterized cell by assigning variables to parameters of the parameterized cell according to a desired objective. Then, the method updates the parameters of each new version of the parameterized cell and replaces each new version of the parameterized cell with an instance of the parameterized cell having updated parameters. The method can optionally adjust physical design shapes based on constraints related to the parameters. | 03-05-2009 |
20090070714 | Identifying And Improving Robust Designs Using Statistical Timing Anaysis - Statistical timing analysis techniques can be used to lead to the construction of robust circuits in a consistent manner through the entire design flow of synthesis, placement and routing. An exemplary technique can include receiving library data for a design including timing models. By comparing implementations of this data, a robust circuit can be defined based on a set of criteria, which can include worst negative slack, endpoint slack distribution, timing constraint violations, and total negative slack. At this point, statistical timing analysis can be used to drive logic changes that generate improved robustness in the design. The statistical timing analysis can use a static timing delay associated with the arc in statistical timing analysis as a mean and a specified percentage of the mean as the standard deviation. | 03-12-2009 |
20090070715 | METHOD FOR ELIMINATING NEGATIVE SLACK IN A NETLIST VIA TRANSFORMATION AND SLACK CATEGORIZATION - A method for eliminating negative slack in a netlist representing a chip design uses a contrived timing environment to overlay information onto the design environment during logic and physical synthesis phase. The overlaid timing information determines which netlist transformation provides a maximum leverage for the negative slack elimination and a way for creating a dynamic transformation recipe tuned for each design. The method further provides upper bounds on the negative slack elimination to prevent the netlist transforms from being applied to situations exceeding the capabilities for improving the design. | 03-12-2009 |
20090070716 | SYSTEM AND METHOD FOR OPTIMIZATION AND PREDICATION OF VARIABILITY AND YIELD IN INTEGRATED CIRUITS - A system and method for designing a circuit includes generating physics based equations to describe phenomena of a circuit component, representing physical device geometry by correlating the physical device geometry with features of a circuit component design, and integrating the physical based equations and correlated physical device geometry into a computer based model to represent aspects of behavior and geometry for the circuit component. The circuit component is modeled in the presence of variability by statistically analyzing a design space defined by a plurality of parameters in the physics based equations and the physical device geometry to optimize at least one of cost and yield to determine an optimal design point. The circuit component is provided using the optimal design point. | 03-12-2009 |
20090077506 | Simultaneous Multi-Layer Fill Generation - Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design until a specified target density is met. | 03-19-2009 |
20090083679 | Efficient Second Harmonic Generation (SHG) Laser Design - A method, a data processing method, and a computer program product for the design of efficient second harmonic generation semiconductor lasers is disclosed. A method for determining an optimum laser configuration includes the determination of a conversion efficiency curve for each SHG configuration using a target conversion efficiency. Each curve, on a log | 03-26-2009 |
20090089721 | METHOD FOR INCREMENTAL, TIMING-DRIVEN, PHYSICAL-SYNTHESIS OPTIMIZATION - A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Rip Up and Move Boxes with Linear Evaluation (RUMBLE) utility identifies movable gate(s) for timing-driven optimization. The RUMBLE utility isolates an original subcircuit corresponding to the movable gate(s) and builds an unbuffered model of the original subcircuit. Notably, a new optimized placement of the movable gate is yielded to optimize the timing (i.e., maximize the minimum slack) of the original subcircuit, while accounting for future interconnect optimizations. The new subcircuit containing the new optimized gate placement and interconnect optimization is evaluated as to whether a timing degradation exists in the new subcircuit. If a timing degradation exists in the new subcircuit, the RUMBLE utility can restore an original subcircuit and a timing state associated with the original subcircuit. | 04-02-2009 |
20090089722 | Method and System for Mapping Source Elements to Destination Elements as Interconnect Routing Assignments - Aspects for optimized mapping of source elements to destination elements as interconnect routing assignments are described. The aspects include utilizing chosen rules to establish a priority for mapping, and generating mapping assignments based on the priority. The mapping assignments are recursively refined to converge on an optimized solution. | 04-02-2009 |
20090094564 | METHOD FOR RAPID RETURN PATH TRACING - A method for quickly tracing minimum-length conductive return paths through an electronic structure utilizes a raster based (cellular) memory model comprising individual grids for each layer of the structure. Each grid comprises a reduced resolution N×M cell representation of the conductive structures on that layer. Cellular methodologies are then used to determine, for each signal net, the shortest return path. This information can then be used for various purposes, including determining if the return path is sufficient to ensure adequate signal integrity. | 04-09-2009 |
20090094565 | METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT - A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications. | 04-09-2009 |
20090100385 | Optimal Simplification of Constraint-Based Testbenches - Methods and systems are provided for determining redundancies in a system model such as a complex circuit design including gates that are state components. A candidate redundant gate is selected, and a merged model is built that eliminates the candidate redundant gate. If the candidate redundant gate is within the merged constraint cone the pre-merge model is used to validate redundancy of the candidate redundant gate. However, if the candidate redundant gate is not within the merged constraint cone the merged model is instead used to validate redundancy of the candidate redundant gate. | 04-16-2009 |
20090100386 | IC Layout Optimization to Improve Yield - Optimizing an integrated circuit design to improve manufacturing yield using manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The process further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced. | 04-16-2009 |
20090106709 | System for Improving a Logic Circuit and Associated Methods - A system for improving a logic circuit may include a processor, and a logic circuit analyzer in communication with the processor to model a plurality of nets. The system may also include an interface in communication with the logic circuit analyzer to select a target slack-value for each one of the plurality of nets. The logic circuit analyzer may determine a slack-value for each net. In addition, the logic circuit analyzer may selectively reduce resistive-capacitive delay for each net respectively if the determined slack-value is less than the target slack-value for each respective net. | 04-23-2009 |
20090106710 | METHOD AND APPARATUS FOR SYNTHESIS - Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements. Also, in some embodiments, the generated sub-network performs a set of two or more functions. Some embodiments store each generated sub-network in an encoded manner. Some embodiments provide a method for producing a circuit description of a design. This method (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the identified replacement sub-network in certain conditions. In some embodiments, this method is performed to map a design to a particular technology library. Some embodiments provide a data storage structure that stores a plurality of sub-networks based on parameters derived from the output functions of the sub-networks. | 04-23-2009 |
20090106711 | Method for Optimizing of Pipeline Structure Placement - Using a computer and storage, a circuit design process is executed to preserve overall design quality while obtaining quality placements for a full class of pipeline structure signatures. These signatures include classic latch to latch pipelines, as well as a variety of latch to latch and mixed logic pipelines. The process employs a method for optimizing pipeline structure placement in a circuit design, by initiating an analysis of pipeline logic structures for correcting poor quality of result (QOR) placements by identifying poor placements caused by placement algorithmic response to degenerate cases and in the process of analysis preserving high quality placements of global placement and timing to preserve preponderant non-degenerate cases in said circuit design. Then employing a plurality of global placement steps, wherein each subsequent placement's quality of result (QOR) is dependent upon the prior placement's quality of result (QOR), circuits are identified as being involved in a class of degenerate cases, and circuits having poor placements are removed by unplacing them from the global placement solution and also other non-degenerate poor quality placements are corrected. | 04-23-2009 |
20090113356 | Optimization of Post-Layout Arrays of Cells for Accelerated Transistor Level Simulation - A method for optimizing post-layout array for accelerated transistor level simulation is provided. In some embodiments of the present invention, a post-layout array of cells having a plurality array lines is optimized by forming array line models for the array lines of the post-layout array of cells. Ideal sub-arrays are formed with the cells of the post-layout array. The ideal sub-array can be simulated using conventional techniques such as HAR or SOFA. Furthermore, some embodiments of the present invention also detect and optimize parasitic capacitors to facilitate formation of the ideal sub-arrays. | 04-30-2009 |
20090119621 | Variability-Aware Asynchronous Scheme for Optimal-Performance Delay Matching - A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow. Exemplary circuits used in the application of the aforementioned techniques are provided. Application of mathematical models and techniques used for proving equivalence between the input description and the resulting desynchronized circuit are presented and explained. | 05-07-2009 |
20090132970 | METHOD FOR INCREMENTAL, TIMING-DRIVEN, PHYSICAL-SYNTHESIS OPTIMIZATION UNDER A LINEAR DELAY MODEL - A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Pyramids utility identifies and selects movable gate(s) for timing-driven optimization. A delay pyramid and a required arrival time (RAT) surface are generated for each net in the selected subcircuit. A slack pyramid for each net is generated from the difference between the RAT surface and delay pyramid of each net. The slack pyramids are grown and tested using test points to generate a worst-case slack region based on a plurality of slack pyramids in the selected subcircuit. The worst-case slack region is mapped on a placement region and a set of coordinates representing the optimal locations of the movable element(s) in the placement region are determined and outputted. | 05-21-2009 |
20090132971 | Structure for a Circuit Obtaining Desired Phase Locked Loop Duty Cycle without Pre-Scaler - A design structure for a circuit for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler is provided. The PLL circuit of the illustrative embodiments utilizes two separate loops that simultaneously operate on the VCO. One loop ensures the frequency and phase lock while the other loop ensures the duty cycle lock. The VCO is modified to have an additional control port to adjust the duty cycle. Thus, the VCO has one control port for performing frequency adjustment and one control port for duty cycle adjustment. As a result, both the duty cycle and the frequency may be controlled using the VCO of the PLL circuit of the illustrative embodiments so as to achieve any desired duty cycle output without requiring a VCO pre-scaler circuit or duty cycle correction circuit. | 05-21-2009 |
20090138832 | IMPLEMENTING ENHANCED WIRING CAPABILITY FOR ELECTRONIC LAMINATE PACKAGES - Structures and a computer program product are provided for implementing enhanced wiring capability for electronic laminate packages. Electronic package physical design data are received. Instances of line width and space limit violations in the electronic package physical design data are identified. The identified instances of line width and space limit violations are evaluated using predefined qualified options and tolerance limitations and the electronic package physical design data are modified to optimize shapes to replace the instances of line width and space limit violations. | 05-28-2009 |
20090138833 | METHOD, APPARATUS AND COMPUTER PROGRAM FOR FACILITATING THE IMPROVEMENT OF A USER INTERFACE - There is disclosed a method, apparatus and computer program for facilitating improvement of a user interface. A plurality of critical paths though the user interface are determined. A complexity of each of the critical paths is calculated. The complexity of the critical paths relative to a level of criticality of those paths is then indicated. | 05-28-2009 |
20090144670 | AUTOMATED OPTIMIZATION OF DEVICE STRUCTURE DURING CIRCUIT DESIGN STAGE - A method of improving a circuit design for a very large scale integrated circuit is provided which represents a plurality of semiconductor devices interconnected in a circuit. It is determined whether an edge of a feature of one of the plurality of semiconductor devices in the design can be moved in a first direction by a distance within a permitted range, such that a performance goal and a matching goal for the circuit are served. If so, the edge is moved in the first direction by the distance calculated to best serve the performance goal and the matching goal. The foregoing steps may be repeated for each of the plurality of semiconductor devices. If necessary, the foregoing steps may be repeated until the performance goal and matching goal for the circuit are deemed to be adequately served. | 06-04-2009 |
20090144671 | DESIGNING INTEGRATED CIRCUITS FOR YIELD - Method and system for designing integrated circuits for yield are described. Integrated circuits are designed for yield by finding worst yield corners based on design, statistical, and environmental variables and optimizing the design in light of the worst yield corners found. | 06-04-2009 |
20090144672 | DETERMINATION OF VALUES OF PHYSICAL PARAMETERS OF ONE OR SEVERAL COMPONENTS OF AN ELECTRONIC CIRCUIT OR OF A MICROELECTRO-MECHANICAL SYSTEM - A method for determining, for each of at least p physical parameters of one or several components of an electronic circuit or of a microelectromechanical system, a number n of experiment values of the physical parameter includes determining n vectors of dimension p, each component of each of the vectors corresponding to one of n initial values of one of physical parameters; and iteratively modifying at least some of the n vectors to bring to a maximum, at least locally, for each pair of vectors from among pairs of n vectors, the smallest average of the sum of distances between the vectors of said pair projected onto sub-spaces of dimension k, where k belongs to a set of integers ranging between 1 and p and at least comprising 1, 2, and p, the components of each of the n vectors corresponding, at the end of the iterations, to experiment values. | 06-04-2009 |
20090144673 | PARTIAL GOOD SCHEMA FOR INTEGRATED CIRCUITS HAVING PARALLEL EXECUTION UNITS - Processing engines (PE's) disposed on the substrate. Each processing engine includes a measurement and storage unit, and a PE controller coupled to each of the processing engines. The processing engines perform self-tests and store the results of the self-tests in the measurement and storage unit. The PE controller reads the results and selects a sub-set of processing engines based on the results and an optimization algorithm. | 06-04-2009 |
20090158223 | ADAPTIVE WEIGHTING METHOD FOR LAYOUT OPTIMIZATION WITH MULTIPLE PRIORITIES - An adaptive weighting method for layout optimization differentiates different priorities by assigning the weight of a higher priority (p | 06-18-2009 |
20090164953 | Simultaneous optimization of analog design parameters using a cost function of responses - An analog system consists of a multitude of interconnected components. Design of such a system involves optimization of the component parameters to achieve a target behavior, collectively called specification. The present invention provides a generic cost function for analog design optimization. It also provides cost surface modeling to speed up the optimization. The cost function compares the behavior of a design to a quantitative specification, which can be a ‘golden’ reference behavior (specification), and measures the error cost, an index of the behavioral discrepancy. That is, the target behavior is explicitly embedded in the cost function. By using the cost function, one can readily qualify a design and thereby identify good/optimum designs. The cost surface modeling with a Latin Hypercube Sampling design-of-experiment provides a statistical mathematical approximation of the actual design's error cost surface, speeding up the optimization by replacing the costly simulation of the actual design with mere evaluation of the mathematical cost surface model expression. | 06-25-2009 |
20090164954 | AUTOMATIC ANTENNA DESIGNING APPARATUS AND AUTOMATIC ANTENNA DESIGNING METHOD - An automatic antenna designing apparatus for designing a tag antenna of an IC tag, has a model storage unit configured to store models serving as templates of the tag antenna to be designed; and a design input unit configured to read out a model from the model storage unit on the basis of a designer's instruction, to display the read out model on a screen, and to display an input screen allowing the designer to input a change in a shape of the model as length information. | 06-25-2009 |
20090178012 | METHODOLOGY FOR IMPROVING DEVICE PERFORMANCE PREDICTION FROM EFFECTS OF ACTIVE AREA CORNER ROUNDING - A system and method for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device in a circuit to be modeled, the transistor including an active device (RX) area over which the gate is formed and over which the conductive line feature extends. The method includes providing an analytical model representation including a function for modeling a lithographic flare effect impacting the active device area width; and, from the modeling function, relating an effective change in active device area width (deltaW adder) as a function of a distance from a defined edge of the RX area. Then, transistor model parameter values in a transistor compact model for the device are updated to include deltaW adder values to be added to a built-in deltaW value. A netlist used in a simulation includes the deltaW adder values to more accurately describe the characteristics of the transistor device being modeled including modeling of lithographic corner rounding effect on transistor device parametrics. | 07-09-2009 |
20090178013 | SYSTEM FOR IMPLEMENTING POST-SILICON IC DESIGN CHANGES - An engineering change order (ECO) modifying an IC having spare cell instances is implemented by converting active cell instances implementing portions of the IC to be deleted into additional spare cell instances, by creating a technology independent behavioral model of portions of the IC to be added, by selecting spare cell instances to implement the behavior model, and by routing nets to the selected spare cell instances in a way that minimizes a number of metal layers of the IC that are modified. | 07-09-2009 |
20090178014 | HEURISTIC CLUSTERING OF CIRCUIT ELEMENTS IN A CIRCUIT DESIGN - An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the scan chains in a scan architecture for a circuit design. | 07-09-2009 |
20090193368 | INTEGRATED CIRCUIT DEVICES AND METHODS AND APPARATUSES FOR DESIGNING INTEGRATED CIRCUIT DEVICES - Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed. | 07-30-2009 |
20090199136 | Optimization of Integrated Circuit Design and Library - A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum nearly optimum set of cells to optimize a design. This involves the simultaneous optimization of a cell-based design and a cell library used to implement it. The invention can produce only an optimized library for a specific application, when the circuit is disregarded. The method takes into account a set of new cells described as finalized cells or as virtual cells, possibly having different transistor topologies, different sizes, different logic functions, and/or different cell template than the original library. | 08-06-2009 |
20090217216 | CARBON NANOTUBE CIRCUITS DESIGN METHODOLOGY - A methodology is provided for optimizing circuit parameters of circuits including carbon nanotube transistors. The method comprises mapping ( | 08-27-2009 |
20090217217 | METHOD OF CORRELATING SILICON STRESS TO DEVICE INSTANCE PARAMETERS FOR CIRCUIT SIMULATION - Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard, stress-sensitive, transistor model is used to develop a mathematical relationship between the first transistor performance measure and one or more instance parameters that are available as inputs to a second, stress-insensitive, transistor model. The second transistor model may for example be the same as the first model, with its stress sensitivity disabled. Thereafter, a substitute stress analyzer can be used to determine a stress-adjusted value for the first performance measure, and the mathematical relationship can be used to convert that value into specific values for the one or more instance parameters. These values are then provided to the second transistor model for use in simulating the characteristics of the particular transistor during circuit simulation. | 08-27-2009 |
20090217218 | OPC SIMULATION MODEL USING SOCS DECOMPOSITION OF EDGE FRAGMENTS - A system for estimating image intensity within a window area of a wafer using a SOCS decomposition to determine the horizontal and vertical edge fragments that correspond to objects within the window area. Results of the decomposition are used to access lookup tables that store data related to the contribution of the edge fragment to the image intensity. Each lookup table stores data that are computed under a different illumination and feature fabrication or placement conditions. | 08-27-2009 |
20090222772 | Power Gating Logic Cones - Power gating logic cones is described. In one embodiment a method includes synthesizing logic for an integrated circuit (IC) design; identifying low switching nodes within the logic that switch less than a threshold; determining a potential power gating cone (PGC) based on the identified low switching nodes; determining a power gating logic expression for the potential PGC that includes a minimum set of inputs to the potential PGC that are least switching; determining whether energy savings using the power gating logic expression meets a criteria; and accepting the potential PGC in response to meeting the criteria. | 09-03-2009 |
20090235210 | ORIENTATION OPTIMIZATION METHOD OF 2-PIN LOGIC CELL - In an orientation optimization, at least one signal chain path starting from a signal source and passing through a series of M 2-pin logic cells is located according to a netlist. An output of the Nth 2-pin logic cell in the series of M 2-pin logic cells, where N09-17-2009 | |
20090235211 | METHOD OF PREDICTING SUBSTRATE CURRENT IN HIGH VOLTAGE DEVICE - A method of predicting a substrate current in a high voltage device that may accurately predict substrate current components in each of a first region, a second region, and a third region. This may be accomplished by modeling a substrate current component in a third region, in which an inconsistency may occur when a substrate current in a high voltage device is calculated, for example using BSIM3-based modeling. According to embodiments, a substrate current for a third region may be modeled by an expression with a ternary operator, and the modeled substrate current may be added to a substrate current obtained through BSIM3-based modeling. | 09-17-2009 |
20090241073 | Radiation Tolerance by Clock Signal Interleaving - A method for designing integrated circuits uses clock signal interleaving to reduce the likelihood of a soft error arising from an upset in a clock distribution network. At least two circuits in a circuit description are identified as being sensitive to radiation, and different clock distribution nodes are assigned to the two circuits. Several exemplary implementations are disclosed. The second circuit may be a redundant replica of the first circuit, such as a reset circuit. The first and second circuits may be components of a modular redundant circuit such as a triple modular redundancy flip-flop. The first circuit may include a set of data bits for an entry of a storage array such as a register or memory array, and the second circuit may include a set of check bits associated with the entry. | 09-24-2009 |
20090249261 | METHOD AND APPARATUS FOR OPTIMIZING AN OPTICAL PROXIMITY CORRECTION MODEL - A method includes receiving optical profiles for a plurality of design target features associated with an integrated circuit device and optical profiles for a plurality of test features. An optical proximity correction (OPC) model including a plurality of terms is defined. Each term relates to at least one parameter in the optical profiles. A subset of the model terms is identified as being priority terms. Parameters of the optical profiles of the test features are matched to parameters of the optical profiles of the design target features using the priority terms to generate a set of matched test features. A metrology request is generated to collect metrology data from a test wafer having formed thereon at least a first subset of the matched test features and a second subset of the design target features. | 10-01-2009 |
20090249262 | BEHAVIORAL SYNTHESIS DEVICE, BEHAVIORAL SYNTHESIS METHOD, AND COMPUTER PROGRAM PRODUCT - A behavioral synthesis device include a profile unit that implements an electronic circuit at a reconfigurable hardware based on a first register transfer level description generated by a behavioral synthesis unit, actuates the implemented electronic circuit, and causes the electric circuit to output profile information from the actuated electronic circuit; and an optimizer that generates optimization information for optimizing a behavioral synthesis carried out by the behavioral synthesis unit based on the profile information that the profile unit causes the electric circuit to output, and outputs the generated optimization information to the behavioral synthesis unit, wherein the behavioral synthesis unit acquires a first behavioral level description, and subjects the acquired first behavioral level description to behavioral synthesis and generates the second register transfer level description based on the optimization information outputted by the optimizer. | 10-01-2009 |
20090249263 | SEMICONDUCTOR CIRCUIT DESIGN METHOD AND SEMICONDUCTOR CIRCUIT MANUFACTURING METHOD - A computer converts dimensions of design patterns of components of the transistors configuring the semiconductor circuit or component parameters extracted from in-design physical characteristics of the transistors into simulation parameters inputted to the simulator, organize the plurality of transistors included in the semiconductor circuit into a plurality of groups, selects any selection groups from the plurality of groups, sets fixed parameter values as component parameters of the non-selected groups other than the selection groups in the plurality of groups, sets the combinations of the component parameters in the selection groups, acquires circuit characteristics with respect to each combination of the component parameters, selects a group as a next selection group different from the selected groups, and repeatedly executing the setting the fixed parameter values through the selects a group as a next selection group different. | 10-01-2009 |
20090254870 | Automatic transistor arrangement device to arrange serially connected transistors, and method thereof - When first and second hard macro transistors are arranged adjacently to each other, based on a circuit connection information and potentials of the first and second hard macro transistors are equal, a first programmable transistor is obtained by removing an unwanted diffusion region or an unwanted contact in the first hard macro transistor, and a second programmable transistor is obtained by removing an unwanted diffusion region or an unwanted contact in the second hard macro transistor. The first and second programmable transistors are arranged based on the circuit connection information. | 10-08-2009 |
20090271746 | METHOD OF CIRCUIT POWER TUNING THROUGH POST-PROCESS FLATTENING - A method is provided for optimizing a hierarchical circuit design containing at least one reused cell. A first optimization is performed on the circuit design to meet a first objective. The first optimization is subject to a first constraint that all instances of the at least one reused cell are kept identical. The at least one reused cell is uniquified. A second optimization is performed to meet a second objective allowing uniquified instances of the at least one reused cell to be independently modified. The second optimization is subject to a second constraint that the first objective remains met. | 10-29-2009 |
20090271747 | LOGIC CIRCUIT DESIGNING DEVICE, LOGIC CIRCUIT DESIGNING METHOD AND LOGIC CIRCUIT DESIGNING PROGRAM FOR ASYNCHRONOUS LOGIC CIRCUIT - A logic circuit designing device for designing an asynchronous logic circuit which satisfies characteristic constraints of a state holding element represented by a latch or a flip-flop is provided. A signal transition series which generates a control signal pulse of the state holding element is extracted by the state storage control signal transition series extraction unit | 10-29-2009 |
20090282374 | Dummy Pattern Design for Reducing Device Performance Drift - A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip. | 11-12-2009 |
20090293022 | Virtual Machine Placement Based on Power Calculations - An optimized placement of virtual machines may be determined by optimizing an energy cost for a group of virtual machines in various configurations. For various hardware platforms, an energy cost per performance value may be determined. Based on the performance usage of a group of virtual machines, a total power cost may be determined and used for optimization. In some implementations, an optimized placement may include operating a group of virtual machines in a manner that does not exceed a total energy cost for a period of time. | 11-26-2009 |
20090307636 | SOLUTION EFFICIENCY OF GENETIC ALGORITHM APPLICATIONS - A method of optimizing a very large scale integrated circuit design takes a circuit description which includes interconnected circuit components and characteristic variables assigned to the circuit components such as environmental, operational or process parameters, computes a first solution for the characteristic variables using a statistical analysis, and then computes a second solution for the characteristic variables using an evolutionary analysis seeded by the first solution. In the exemplary implementation the statistical analysis is a central composite design (CCD) and the evolutionary analysis is a genetic algorithm. Best case and worst case CCD solutions may be used to seed separate genetic algorithm runs and derive global best case and global worst case solutions. These solutions may be compared for sensitivity analysis. The method thereby provides significant reduction in time-to-solution with accurate simulation results. | 12-10-2009 |
20090313588 | Method to Extract and Apply Circuit Features in Organic Substrate for Automation of Warp Modeling - A method of characterizing an organic substrate including a plurality of circuit layers is provided includes the steps of: receiving an image of the organic substrate, the image including a geometric description of the circuit layers of the substrate; segmenting the substrate into multiple processing regions based, at least in part, on geometric coordinates of circuit structures defined in the image of the substrate; generating a circuit layer image corresponding to a selected one of the processing regions of the substrate; identifying one or more geometric features in the circuit layer image; estimating at least one thermomechanical property of the circuit layer image as a function of the identified geometric features; repeating the steps of receiving an image, generating a circuit layer image, identifying one or more geometric features in the circuit layer image, and estimating at least one thermomechanical property of the circuit layer image until all circuit layers in the substrate have been processed; and generating a 3-D representation of the selected one of the processing regions of the substrate including the plurality of circuit layer images as a function of the at least one thermomechanical property of each of the plurality of circuit layer images. | 12-17-2009 |
20090319960 | Minimizing Effects of Interconnect Variations in Integrated Circuit Designs - Roughly described, method and apparatus for laying out an integrated circuit, in which a subject interconnect has predetermined values for a plurality of variables affecting propagation delay of the subject interconnect. The value of an adjustment one of the variables is adjusted to minimize exposure of the propagation delay of the interconnect to process variations causing variations in the value of a subject fabrication variable, and a revised layout is developed in dependence upon the adjusted value for the adjustment variable. In an embodiment, the adjustment is made in dependence upon a pre-calculated “interconnect optimization database” indicating combinations of values for the plurality of variables which have been pre-determined to minimize exposure of interconnect propagation delay to process variations affecting the subject variable. Different databases, or different entries in the same database, can be provided for minimizing exposure of interconnect propagation delay to process variations affecting each subject variable of interest. | 12-24-2009 |
20090327980 | SYSTEM AND METHOD FOR EVALUATING A DYNAMIC POWER CONSUMPTION OF A BLOCK - A method for evaluating a dynamic power consumption of a block, the method includes: receiving or generating information representative of the block during a preliminary block design stage that precedes a gate level simulation of the block; estimating change probabilities of signals of internal components of the block; and evaluating a dynamic power consumption of the block in response to the change probabilities of the signals of internal components of the block. | 12-31-2009 |
20100011324 | Structured Placement For Bit Slices - Techniques are disclosed for improving bit slice placement and wiring. Some embodiments include swapping cells to improve routing. An alternative embodiment includes copying wiring from a first bit slice to a second bit slice. Another embodiment includes copying blocks or cells from a first bit slice to a second bit slice. Further, the wiring from the first bit slice may be copied to the second bit slice. | 01-14-2010 |
20100017760 | TEST DESIGN OPTIMIZER FOR CONFIGURABLE SCAN ARCHITECTURES - Roughly described, a scan-based test architecture is optimized in dependence upon the circuit design under consideration. In one embodiment, a plurality of candidate test designs are developed. For each, a plurality of test vectors are generated in dependence upon the circuit design and the candidate test design, preferably using the same ATPG algorithm that will be used downstream to generate the final test vectors for the production integrated circuit device. A test protocol quality measure such as fault coverage is determined for each of the candidate test designs, and one of the candidate test designs is selected for implementation in an integrated circuit device in dependence upon a comparison of such test protocol quality measures. Preferably, only a sampling of the full set of test vectors that ATPG could generate, is used to determine the number of potential faults that would be found by each particular candidate test design. | 01-21-2010 |
20100031206 | METHOD AND TECHNIQUE FOR ANALOGUE CIRCUIT SYNTHESIS - Method and technique for analogue circuit synthesis. An analogue circuit usually includes many circuit components, and characteristics and functions of each circuit component are controlled by many corresponding parameters. In the presented invention, selected key design parameters of selected critical circuit components, as well as optimization targets, design specification or/and design constraint, are transformed into an optimization plan, and an optimization engine iterates circuit level or system level numerical simulations by changing values of the selected key design parameters recorded in the optimization plan, so as to find optimized parameters and circuit components which allow the analogue circuit to match the design specification/constraint and to approach the optimization target. Thus a systematic automation for analogue circuit synthesis/design/optimization is achieved. | 02-04-2010 |
20100037188 | SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZATION TECHNIQUES FOR INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY - Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional IC design that meets the performance objectives by employing a unitless performance/power quantifier as a metric to gauge a degree of optimization thereof and (6) performing a timing signoff of the layout at the optimization target voltage. | 02-11-2010 |
20100042955 | Method of Minimizing Early-mode Violations Causing Minimum Impact to a Chip Design - A system and a method for correcting early-mode timing violations that operate across the process space of a circuit design. Optimizations are performed to replace padding that increase path delays on fast paths. At the stage in the design process where early-mode violations are addressed, placement, late-mode timing closure, routing, and detailed electrical and timing analysis are assumed to have been completed. The optimizations are designed to be effective in delaying fast paths while minimizing the impact on already-completed work on the chip, in contrast to relying only on adding pads that can have a negative impact on all of these quantities. The optimizations are classified according to their invasiveness and are followed by their deployment. The deployment is designed to minimize using delay pads, reduce design disruptions, and minimize effects on other aspects of the design. | 02-18-2010 |
20100042956 | System, and Method, And Computer Readable Medium For Designing A Scalable Clustered Storage Integrated Circuit For Multi-Media Processing - An integrated circuit includes a clustered memory storage subsystem. The integrated circuit utilizes a baseline design that supports a scalable number of memory clusters. The number of storage devices within an individual memory cluster may also be selected to adjust the memory capacity. A single baseline design of a clustered memory storage subsystem design is customized for a particular integrated circuit with the number of memory clusters and storage devices within memory clusters selected for the memory requirements of a particular application. The design and verification costs to fabricate different versions of the integrated circuit are thus reduced. | 02-18-2010 |
20100042957 | REPLACING SINGLE-CUT VIA INTO MULTI-CUT VIA IN SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN - According an aspect of the invention, there is provided a design support system of a semiconductor integrated circuit includes: a first unit configured to determine a wiring path by calculating wiring resource consuming information for carrying out a connection through a multi-cut via in case that the connection is carried out through the multi-cut via in a wiring region having a plurality of layers; and a second unit configured to replacing a single-cut via into the multi-cut via. | 02-18-2010 |
20100050135 | VARIOUS METHODS AND APPARATUSES FOR EFFECTIVE YIELD ENHANCEMENT OF GOOD CHIP DIES HAVING MEMORIES PER WAFER - A method and apparatus are described in which an optimal configuration of memory instances is determined. The optimal configuration of memory instances to be fabricated with built-in repair capacity and memory instances that are non-repairable may provide a maximum number of good chip dies per wafer. An amount of memory instances to be fabricated with built-in repair capacity as well as a remaining amount of memory instances to be fabricated without any built-in repair components in the integrated circuit design is determined relative to achieving the maximum number of good chip dies per wafer for a given defect density and wafer area. The amount of good dies produced per fabricated wafer for a populated amount of memories with built-in repair components is determined to be between an amount established by a minimum limit for the die area up to the amount established by a maximum limit for the die area. | 02-25-2010 |
20100050136 | SYSTEM AND METHOD FOR OPTIMIZING ANALOG CIRCUIT DESIGNS - A system for optimizing analog circuit designs includes an input device, a data processing device, and a data storage device. The data processing device includes a selecting module, a calculation module, and a determining module. The selecting module is for receiving input from the input device and selecting electronic components composing the circuit from the data storage device. The calculation module is for calculating average values and standard deviations of each electronic component, generating normal distribution samples of each electronic component, and calculating output voltages of the circuit. The determining module is for determining whether the circuit meets a process capability standard. | 02-25-2010 |
20100058256 | CO-OPTIMIZATION OF EMBEDDED SYSTEMS UTILIZING SYMBOLIC EXECUTION - Co-Optimization utilizing Symbolic Execution (COSE) works across components of an embedded design to optimize structures therein. COSE utilizes symbolic execution (SE) to analyze software components and defines a limited set of values that software feeds hardware as constraints. SE explores substantially all possible paths of execution of the code specifying a component. It accomplishes this by accumulating path conditions (PCs) and annotating them to the corresponding segments of the component. A PC is associated with a branch of code and consists of the conjunction of conditions over input and state variables necessary and sufficient for the branch to execute. These PCs define constraints that limit the set of values that software feeds hardware. These constraints are then propagated across the networks of the design and employ static analysis techniques such as constant propagation, redundancy removal, and don't care optimizations to reduce the hardware components. | 03-04-2010 |
20100058257 | TOPOLOGY OPTIMIZATION METHOD USING EQUIVALENT STATIC LOADS - A topology optimization method. Characteristics of a structure to be designed are differentiated to calculate equivalent static loads. A relative fraction of material is adopted as a design variable. It is determined whether or not an element exists based on an objective function and constraints. Design topology is derived through a linear static analysis that processes the equivalent static loads as multiple loading conditions. Topology of the structure to be designed is compared with the design topology, and thereby the progress of optimization is determined. The topology optimization processes are terminated when a difference of the compared result is less than a setup value, and are returned to an initial step when the difference is greater than the setup value, and the equivalent static loads are calculated using the design topology as a new structure to be designed. | 03-04-2010 |
20100064263 | METHOD FOR COMPACTION OF TIMING EXCEPTION PATHS - A technique and apparatus for reducing the complexity of optimizing the performance of a designed semiconductor circuit is disclosed. This technique of path compaction is used to reduce the time taken for optimization. The path compaction tool is used in design optimization to reduce the optimizer execution time. Compaction helps readability, usability and reduces synthesis and static timing analyzer (STA) runtime. The aim of path compaction is to reduce the number of constraints the optimizer has to go through during the optimization process. Path compaction has three dimensions. The first is to reduce number of “-through” elements in the constraint, thereby reducing the complexity of constraints developed The second is to combine the paths to reduce the number of constraints. The third is to combine the constraints to reduce the number of constraints to be checked and optimized. Path compaction is used when generating timing exception using timing exception tools. | 03-11-2010 |
20100064264 | METHOD TO GRAPHICALLY IDENTIFY REGISTERS WITH UNBALANCED SLACK AS PART OF PLACEMENT DRIVEN SYNTHESIS OPTIMIZATION - A method for identifying latches in physical designs with unbalanced slack, comprising: creating a netlist describing a logical design, the logical design having a plurality of latches therein; performing a placement of the logical design to obtain a physical design; measuring a slack difference of each of the plurality of latches; selecting a color for each of the plurality of latches based on the slack difference correspondingly measured for each of the plurality of latches; and generating a graphical image identifying each one of the plurality of latches with slack difference in color, the color selected for each one of the plurality of latches with slack difference being indicative of the severity of the slack difference. | 03-11-2010 |
20100070933 | METHOD FOR SELECTIVELY IMPLEMENTING LOW THRESHOLD VOLTAGE TRANSISTORS IN DIGITAL LOGIC DESIGNS - A system and method for selectively replacing standard threshold voltage devices with low threshold voltage devices in a digital logic design. The system identifies at least one path having a first timing value, the path having a plurality of standard threshold devices. The path is reverse traversed, or otherwise analyzed or traversed, to identify at least one of the standard threshold devices to possibly replace with a corresponding low threshold device. The system also determines a timing value for the path associated with replacing the at least one standard threshold device with the corresponding low threshold device. Depending the analysis, the standard threshold device may be replaced with a low threshold device, such as when the path timing improves by replacement. Such replacement may be used in various paths, such as paths considered critical paths in a digital logic design. | 03-18-2010 |
20100077363 | ISOLATION METHOD AND PACKAGE USING A HIGH ISOLATION DIFFERENTIAL BALL GRID ARRAY (BGA) PATTERN - According to an embodiment an improved Application Specific Integrated Circuit (ASIC) isolation method and system for assigning signal pins in an ASIC package having a plurality of signal pins is disclosed. The method and system comprise identifying an isolation requirement of the ASIC and determining an optimized pattern for substantially diagonal pairing of signal pins in relation to the isolation requirement. The method includes pairing signal pairs substantially diagonally in accordance with the pattern. | 03-25-2010 |
20100083194 | SYSTEM AND METHOD FOR FINDING CONNECTED COMPONENTS IN A LARGE-SCALE GRAPH - An improved system and method for finding connected components in a large-scale graph is provided. In a map-reduce framework, subsets of a collection of edges for unique vertices may be distributed to several mappers. Connected components of subgraphs represented by each subset of edges may be computed by each mapper. Then the sets of edges for connected components of subgraphs may be sorted by vertex. The sets of edges representing connected components of subgraphs may be distributed to one or more reducers to find maximal sets of weakly connected components of the large-scale graph. The sorted sets of edges for each vertex representing the maximal sets of connected components for subgraphs may be merged by a reducer to identify maximal sets of connected components of a graph, and the maximal sets of connected components of a graph may be output. | 04-01-2010 |
20100083195 | CONTROL SIGNAL SOURCE REPLICATION - Disclosed is a method of replicating control signal sources, comprising: receiving a description of a functional block that comprises at least one of, a plurality of multiplexer structures, a plurality of memory blocks, and a combination of at least one multiplexer structure and at least one memory block; identifying a control signal that controls said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block; and, determining a first replica control signal and a second replica control signal, said first replica control signal and said second replica control signal collectively functioning as said control signal to control said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block. | 04-01-2010 |
20100083196 | AUTOMATIC CIRCUIT DESIGN APPARATUS AND METHOD - By carrying out circuit simulations, paretos that are non-dominated solutions in a solution specification space for respective items in the requirement specification are obtained for all of circuit configurations having possibility that requirement specification is satisfied, and a provisional optimal solution, which is on a pareto curved surface identified by the obtained paretos and whose distance with the requirement specification is shortest, is identified. Furthermore, a circuit configuration corresponding to the provisional optimal solution is identified and the provisional optimal solution is mapped to values of circuit parameters. Then, the pertinent circuit configuration and values of the circuit parameters, which are obtained by the mapping, are outputted. | 04-01-2010 |
20100083197 | TURNING OFF CLOCK TO FLIP FLOPS - Exemplary techniques for turning off the clock signal to flip flops are described, which may reduce power consumption by electronic devices. In an implementation, a clock-gating logic turns off the clock signal to a flip flop when a data input of the flip flop remains untoggled. The reduction in power consumption is envisioned to also reduce heat generation. | 04-01-2010 |
20100095253 | TABLE-BASED DFM FOR ACCURATE POST-LAYOUT ANALYSIS - Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data. | 04-15-2010 |
20100100856 | Automated optimization of an integrated circuit layout using cost functions associated with circuit performance characteristics - An integrated circuit (IC) design system and method provide an optimization of a layout of an integrated circuit wherein an assessment is taken into account of the circuit performance characteristics and the layout of the IC design. The system and method assess associated circuit performance characteristics, each as a cost function of a local pattern of shapes in an initial circuit layout, aggregate cost functions of the associated circuit performance characteristics to derive an integral performance number associated to the initial global circuit layout, perturb the integral performance number by varying the global circuit layout, and select perturbations that optimize the performance number, so as to optimize the global circuit layout. Assessment is taken into account of the circuit performance characteristics based on the layout and the interdependence of the circuit performance characteristics for the IC design. The physical process related effects such as well proximity effect and stress/strain engineering and/or performance parameters such as the P-N transistor size ratio are taken into account to achieve optimization. | 04-22-2010 |
20100115475 | Integrated Circuit Performance Enhancement Using On-Chip Adaptive Voltage Scaling - Techniques for enhancing the performance of an IC are provided. A method of enhancing IC performance includes the steps of: associating at least one performance result of at least one performance monitor, formed on the IC, with deterministic combinations of IC performance and a processing parameter, a supply voltage, and/or a temperature of the IC; determining an IC processing characterization of the IC as a function of the performance result for at least one prescribed supply voltage and temperature of the IC, the IC processing characterization being indicative of a type of processing received by the IC during fabrication of the IC; and controlling a voltage supplied to at least a portion of the IC, the voltage being controlled as a function of the IC processing characterization and/or the temperature of the IC so as to satisfy at least one prescribed performance parameter of the IC. | 05-06-2010 |
20100115476 | CONGESTION OPTIMIZATION DURING SYNTHESIS - One embodiment of the present invention provides a system that optimizes a circuit design during a logic design stage to reduce routing congestion during a placement and routing stage. During operation, this system identifies a first circuit structure in the circuit design which is expected to cause routing congestion during the placement and routing stage. Next, the system generates a second circuit structure which is functionally equivalent to the first circuit structure, and is not expected to cause routing congestion during the placement and routing stage. The system then replaces the first circuit structure in the circuit design with the second circuit structure, thereby mitigating routing congestion during the placement and routing stage. | 05-06-2010 |
20100115477 | OPTIMIZING INTEGRATED CIRCUIT DESIGN THROUGH USE OF SEQUENTIAL TIMING INFORMATION - A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow. | 05-06-2010 |
20100122221 | METHOD AND APPARATUS FOR DESIGNING A DEVICE FOR ELECTRO-OPTICAL MODULATION OF LIGHT INCIDENT UPON THE DEVICE - A method and apparatus for designing a device to operate in a coupling mode, a detection mode, or a reflection mode for incident light. The incident light has a wavelength λ and is incident upon a semiconductor structure of the device at an angle of incidence (θ | 05-13-2010 |
20100125820 | UNFOLDING ALGORITHM IN MULTIRATE SYSTEM FOLDING - Methods and apparatuses to optimize a circuit representation using unfolding as a preprocessing of the multirate folding. In at least one embodiment of the present invention, a portion of a data flow graph representation of a circuit is optimized using circuit operation level before using optimizing with data flow algorithm and mapping the design onto hardware. In an aspect, the present invention discloses circuit operation level optimization for data flow graph representations with optimizing zero inputs caused by the upsamplers, or with optimizing unused outputs caused by the downsamplers. In at least one embodiment of the present invention, multirate data graph is converted to a single rate data graph before data flow optimizing. In an aspect, converting a multirate data graph to a single rate data graph comprises unfolding the multirate data graph with minimum unfolding factors that are inversely proportional to the clock values. | 05-20-2010 |
20100146465 | Method for Optimizing and Integerated Circuit Physical Layout - The invention relates to a method of optimizing an integrated circuit layout, wherein an initial integrated circuit layout is provided. A predetermined set of physical characteristics of a predetermined set of polygons of said initial circuit layout, is assessed and said physical characteristics are aggregated to derive an integral quality number associated to said initial circuit layout. According to the invention, cost functions are generated to evaluate a perturbed quality number of said perturbed layout and layout perturbations are selected that optimize the quality number, so that the circuit layout is optimized. | 06-10-2010 |
20100153892 | METHODS TO OBTAIN A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIRCUIT LAYOUT OPTIMIZATION - An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represented as an original integer linear programming problem. A relaxed linear programming problem is derived from the original integer linear programming problem by relaxing integer constraints and using relaxation variables on infeasible constraints. The relaxed linear programming problem is solved to obtain a linear programming solution. Variables are then clustered, and at least one variable from each cluster is rounded to an integer value according to the linear programming solution. Next, it is determined whether all the variables are rounded to integer values. Unrounded variables are iterated back through the deriving of the integer linear programming problem, solving of the relaxed linear programming problem, and rounding of a subset of variables. A modified hierarchical circuit layout is generated in response to a determination that all the variables are rounded to integer values. | 06-17-2010 |
20100162185 | ELECTRONIC CIRCUIT DESIGN - A system for optimising electronic circuits to be designed has two parts or phases, a training phase | 06-24-2010 |
20100162186 | Optimal Distance Based Buffer Tree for Data Path and Clock - A device development tool selects a source component and identifies a plurality of sink components in a device design layout. The device development tool determines whether the sink components are configured in a single-sided layout, a multi-sided layout, or a multi-distance layout. Next, the device development tool computes a first level center of gravity for the plurality of sink components and also computes an X distance and a Y distance from the source component to the first level center of gravity. The device development tool then groups the plurality of sink components into sets and places buffers in the layout using an algorithm that is specific for the identified layout type. | 06-24-2010 |
20100162187 | Mixed-Height High Speed Reduced Area Cell Library - A mixed-height cell library for designing integrated circuits is provided. The mixed-height cell library includes a first plurality of cells having a first track height and a second plurality of cells having a second track height that are configured to be coupled to the first plurality of cells at respective power and ground rail lines. A method for mixed-height cell placement and optimization is also provided. The method comprises abutting cells of different track heights to form a plurality of rows of cells by coupling power and ground rails of the cells at a secondary layer that is different from a primary layer that is used to connect active material and determining whether re-ordering cells within rows allows for further compaction of adjacent rows. The method further comprises re-ordering cells within rows so to allow for further compaction of adjacent rows. The method also includes the steps of splitting rows vertically to minimize the distance between the split rows. | 06-24-2010 |
20100169845 | METHOD OF OPTIMIZING ESD PROTECTION FOR AN IC, AN ESD PROTECTION OPTIMIZER AND AN ESD PROTECTION OPTIMIZATION SYSTEM - An ESD protection optimizer, a method of optimizing ESD protection for an IC and an ESD protection optimization system is disclosed. In one embodiment, the ESD protection optimizer includes: (1) a circuit analyzer configured to identify ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) an ESD resistance determiner configured to calculate a resistance value to couple in series with the circuitry, the resistance value based on protection cell physical attributes associated with the identified ESD cells and circuitry physical attributes associated with the identified circuitry. | 07-01-2010 |
20100169846 | METHODS FOR GATE-LENGTH BIASING USING ANNOTATION DATA - Methods for generating a biased layout for making an integrated circuit are disclosed. One such method includes obtaining a nominal layout defined by one or more cells, where each cell has one or more transistor gate features with a nominal gate length. Then, obtaining an annotated layout. The annotated layout contains information describing gate-length biasing of one or more of the transistor gate features in one or more cells of the nominal layout. A biased layout is produced by modifying the nominal layout using the information from the annotated layout. The biasing modifies a gate length of those transistor gate features identified by the information of the annotated layout. | 07-01-2010 |
20100169847 | STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING - A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device. | 07-01-2010 |
20100185991 | COMPUTER-IMPLEMENTED METHOD OF OPTIMIZING REFRACTION AND TIR STRUCTURES TO ENHANCE PATH LENGTHS IN PV DEVICES - A computer-implemented method is provided for optimizing configuration of absorption enhancement structures for use in a photovoltaic enhancement film that is applied onto a PV device to improve absorption. The method includes receiving optimization run input defining a PV enhancement film including defining absorption enhancement structures with differing configurations. The method includes modeling a PV device including PV material such as a silicon thin film. A first ray tracing is performed over a range of incidence angles for the PV device. The method includes determining a set of base path angles for the PV material layer based on this first ray tracing. A second ray tracing is performed for the PV device with the enhancement film, which has absorption enhancement structures. Enhanced path lengths are determined based on the second ray tracking, and path length ratios are determined by comparing the enhanced path lengths to the base path lengths. | 07-22-2010 |
20100192111 | PERFORMING LOGIC OPTIMIZATION AND STATE-SPACE REDUCTION FOR HYBRID VERIFICATION - One embodiment of the present invention provides a system that facilitates optimization and verification of a circuit design. The system can receive a set of assumptions associated with a circuit. The set of assumptions can specify a set of logical constraints on at least a set of primary inputs of the circuit. Note that the set of assumptions are expected to be satisfied during normal circuit operation. The system can generate a stimulus generator based in part on an assumption in the set of assumptions. The output values from the stimulus generator, which when assigned to the set of primary inputs of the circuit, cause the set of primary inputs to satisfy the assumption. Next, the system can generate a modified circuit by coupling the outputs of the stimulus generator with a set of primary inputs of the circuit. The system can then perform logic optimization on the modified circuit to obtain an optimized circuit. | 07-29-2010 |
20100199234 | METHODS AND APPARATUSES FOR CIRCUIT DESIGN AND OPTIMIZATION - In one aspect of an embodiment, a method implemented on a data processing system for circuit design, includes: identifying one or more first portions (e.g., islands) of a design of a circuit, where each of the one or more first portions contains a set of elements interconnected via timing critical nets; and reporting inter-dependency between portions of the circuit in view of the one or more first portions. In one aspect of an embodiment, a method implemented on a data processing system for circuit design, includes: identifying a first portion (e.g., island) of a design of a circuit, the first portion containing a set of elements interconnected via timing critical nets; and performing a synthesis transformation of the first portion to isolate timing dependency of the first portion on a non-critical net connected to an element of the first portion. | 08-05-2010 |
20100199235 | SEMICONDUCTOR LAYOUT MODIFICATION METHOD BASED ON DESIGN RULE AND USER CONSTRAINTS - A method of modification of a semiconductor layout is provided. The layout comprises objects of semiconductor material with corners and edges. The method comprises a step of receiving ( | 08-05-2010 |
20100229131 | SWARM INTELLIGENCE FOR ELECTRICAL DESIGN SPACE MODELING AND OPTIMIZATION - A method, system, and computer program product for exploring and optimizing an electrical design space. A computer receiving a design space assigns a plurality of initial values (random or predetermined) for optimizing the design space. A particle swarm containing a plurality of particles is created and an optimization of the design space is then performed using the assigned initial values. Following completion of optimization, the global best and personal best for each particle are updated. Velocity vectors and position vectors of the design space are then updated before the computer performs the optimization process again. The process loops, continually updating global and personal bests and velocity and position vectors until a termination criteria is reached. Upon reaching the termination criteria, the best fitness of each particle of the swarm is assigned as an optimized design space. In an alternate embodiment, the particle with the worst target fitness may be assigned. | 09-09-2010 |
20100229132 | STATISTICAL FORMAL ACTIVITY ANALYSIS WITH CONSIDERATION OF TEMPORAL AND SPATIAL CORRELATIONS - Techniques for statistical formal activity analysis with consideration of temporal and/or spatial correlations are described herein. According to one embodiment, a sequential circuit having a feedback loop is unrolled into multiple unrolled circuits, where the sequential circuit is represented by a finite state machine (FSM). A temporal correlation is introduced to each of the unrolled circuits via a correlation network for an activity analysis of the sequential circuit. The temporal correlation represents a dependency relationship between a current logic state of a signal and a previous logic state of the signal. Other methods and apparatuses are also described. | 09-09-2010 |
20100251190 | SEMICONDUCTOR SUBSTRATE WIRING DESIGN SUPPORT DEVICE AND CONTROL METHOD THEREOF - A semiconductor substrate wiring design support device includes a memory unit that stores logical connection information and a wiring unit that performs wiring based on the logical connection information and provides a single via between a first and a second wire layer when the wiring is a wire between the first and the second wire layer. An isolated-via-error detection unit detects the single via as an isolated-via-error when only the single via is provided in a case where a plurality of vias may be needed according to a via alteration rule. An isolated-via-error-treatment via alteration unit alters a single via detected as the isolated-via-error to an isolated-via-error-treatment via, and a redundancy via alteration unit alters a single via to a redundancy via after the alteration to the isolated-via-error-treatment via. | 09-30-2010 |
20100262939 | SYSTEM AND METHOD FOR CLOCK OPTIMIZATION TO ACHIEVE TIMING SIGNOFF IN AN ELECTRONIC CIRCUIT AND ELECTRONIC DESIGN AUTOMATION TOOL INCORPORATING THE SAME - A system and method for clock optimization to achieve timing signoff in an electronic circuit and an EDA tool that embodies the system or the method. In one embodiment, the system includes: (1) a clock cell identifier/sorter configured to identify at least some clock cells in a clock network associated with an electronic circuit design and sort the cells according to breadth, (2) a slack analyzer associated with the clock cell identifier/sorter and configured to identify flops that are downstream of the cells and determine a worst setup and hold timing slack thereof and (3) a clock cell delay adjuster associated with the slack analyzer and configured to adjust delays of the cells subject to the worst setup and hold timing slack. | 10-14-2010 |
20100275167 | Cell-Context Aware Integrated Circuit Design - A method of designing an integrated circuit includes providing a standard cell database including a plurality of standard cells; providing an index file having cell-context information indexed to the plurality of standard cells; retrieving the cell-context information of one of the plurality of standard cells from the cell-context file; and applying the index information to a design of the integrated circuit. | 10-28-2010 |
20100275168 | DESIGN METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROGRAM - An object of the present invention is to largely reduce a period required for a layout design of a semiconductor integrated circuit device by simplifying a hierarchical layout process. It is necessary to couple a signal line between a circuit belonging to a top and a signal terminal of a block, and there is such an inadequate situation that the signal line cannot be coupled to a predetermined location of the signal terminal of the block or the signal line needs to be largely detoured depending on congestion conditions of the other signal lines in the block and the signal lines of the top coupled to the other blocks. Accordingly, location information of the signal terminal is deleted before the signal line is coupled, so that the signal line can be coupled irrespective of the location information of the signal terminal of the block. Further, the signal line can be optimally coupled in some cases by arranging the circuit of the top on the inner side relative to a boundary of the block, so that location information of the boundary of the block as well as the location information of the signal terminal is deleted. | 10-28-2010 |
20100293512 | CHIP DESIGN AND FABRICATION METHOD OPTIMIZED FOR PROFIT - Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated. Based on this profit model, changes to the chip design can be made in order to optimize yield as a function of all of the diverse metrics (e.g., performance, power consumption, etc.) and further to maximize the profit potential of the resulting chips. | 11-18-2010 |