Entries |
Document | Title | Date |
20080229158 | RESTORATION DEVICE FOR BIOS STALL FAILURES AND METHOD AND COMPUTER PROGRAM PRODUCT FOR THE SAME - A restoration device for restoring a system when the BIOS falls in a stall failure includes a first watchdog timer and a second watchdog timer, a setter for setting timer values respectively in the first watchdog timer and in the second watchdog timer, a suspender for suspending the decrement of the timer value of the first watchdog timer when the BIOS is started and also execution of a BIOS process is started, a switch for switching the BIOS data region for starting when the timer value of the first watchdog timer becomes equal to 0 or a prescribed number, a resetter for resetting the system when the timer value of the first watchdog timer becomes equal to 0 or a prescribed number, a suspender for suspending the decrement of the timer value of the second watchdog timer when the BIOS of the system starts and a resetter for resetting the system when the timer value of the second watchdog timer becomes equal to 0 or a prescribed number. | 09-18-2008 |
20080276132 | MICROPROCESSOR SUPERVISION IN A SPECIAL PURPOSE COMPUTER SYSTEM - Devices and methods for microprocessor supervision in a special purpose computer system are provided. One illustrative embodiment includes a first watchdog timer internal to the microprocessor and a second watchdog timer external to the microprocessor. In some cases, the internal watchdog timer may be initiated prior to or during the operating system startup and the external watchdog timer may be initiated after the operating system is up and running. The internal watchdog timer may have a relatively longer timer duration than the external watchdog timer, but is not required in all embodiments. In some embodiments, the internal watchdog timer may monitor the microprocessor's startup sequence and the internal watchdog timer and/or external watchdog timer may monitor the microprocessor when the operating system is up and running. If the microprocessor faults at any time during startup or while the operating system is up and running, the internal and/or external watchdog timer may trigger a microprocessor reset. | 11-06-2008 |
20090013221 | Multi-component system - To reset only the CPU in a component in an abnormal condition without affecting CPUs of components in a normal condition, a multi-component system, in which a plurality of components each including at least a CPU are connected via a common bus to each other, includes a first reset signal generating unit which generates a reset signal by a switch operation to send the reset signal to respective components and a judge unit which is disposed in each component to determine whether or not resetting of a CPU is allowed. The judge unit inhibits, if the CPU is in a normal condition, the resetting of the CPU in response to the reset signal and resets, if the CPU is in an abnormal condition, the CPU in response to the reset signal. | 01-08-2009 |
20090019322 | Production Line Control System - A production line control system ( | 01-15-2009 |
20090113255 | Software Fault Detection Using Progress Tracker - The invention provides for software fault detection. A software process tracks its own progress. In the event the timer times out, a handler checks the progress. If the progress meets a fault criterion, a fault response is executed. | 04-30-2009 |
20090119552 | Dynamic Frequency Scaling Sequence for Multi-Gigahertz Microprocessors - The present invention provides for reducing current spikes in a circuit when changing clocking frequencies. A first frequency is applied to a clock distribution network. A final frequency is selected. The first frequency is applied to a logic element over the clock distribution network. A hold signal is applied to the logic element. The clock rate of the clock distribution network is changed from the first frequency to the final frequency. The hold signal is unapplied to the logic element. | 05-07-2009 |
20090132869 | TIMEOUT REQUEST SCHEDULING USING GROUPING AND NONSYNCHRONIZED PROCESSING TO ENHANCE PERFORMANCE - An invention is disclosed for a computer software timeout algorithm that reduces the amount of list manipulation needed to satisfy system or network requirements for scheduling and cancelling timeout requests to determine whether the expiration time has been reached for execution of an input/output (I/O) request, thereby requiring action to cancel the I/O operation if it has not yet been completed. | 05-21-2009 |
20090199049 | PROGRAM PROCESSING DEVICE AND PROGRAM PROCESSING METHOD - A program processing device has a non-volatile storage, a volatile storage and a controller. The controller has a detector that detects a bit flip in the program, the variable data, and the constant data in the volatile storage, a constant recovery unit that, when the detector detects an error in the constant data, writes the constant data in the non-volatile storage into the volatile storage, and then continues the execution of the program from a point at which the program was being executed before the detector detected the error, and a restart that, when the detector detects an error in one of the variable data and the program, writes the program, the initial value of the variable data, and the constant data in the non-volatile storage into the volatile storage, and then executes the program written into the volatile storage from a beginning of the program. | 08-06-2009 |
20090292957 | SYSTEM FOR REPEATED UNMOUNT ATTEMPTS OF DISTRIBUTED FILE SYSTEMS - The present invention provides a computer implemented method and apparatus for unmounting file systems from a plurality of file servers. The method comprises of issuing an unmount command targeting a file system of a first server among the plurality of file servers. The timeout period is then expired without receiving an unmount acknowledgement associated with the unmount command. Thus, the timeout period is associated with an allowable time for the file system to acknowledge unmounting. In response to expiring the timeout period, a ping is transmitted to the first server among the plurality of file servers. The ping timeout then expires based on a failure to receive a ping acknowledgment corresponding to the ping. This action marks the first server for a later retry of unmounting to form a marked set based on the first server. | 11-26-2009 |
20090300435 | Method and Device for Monitoring a Process Execution - A method for monitoring a process execution of a plurality of sequentially executed processes starts one of a plurality of timers in cyclic permutation when one of the processes is started, and outputs a first error signal when a period of time recorded by one of the timers exceeds a predefined maximum period of time. | 12-03-2009 |
20100023814 | HANDLING OF CLUSTERED MEDIA ERRORS IN RAID ENVIRONMENT - A method, apparatus, and system of improved handling of clustered media errors in raid environment are disclosed. In one embodiment, a method includes starting a command timer when a firmware accepts a command from a host, tracking an amount of time the command spends on handling of a clustered media error through the command timer, and stopping the command timer when at least one of the command is completed and a time limit expires. The method may complete a read as a success when a host IO is a read command. The method may complete a write as a success, after writing parity, and data when the host IO may be a write command. | 01-28-2010 |
20100211830 | Multi-input multi-output read-channel architecture for recording systems - In a particular embodiment, a storage device includes a data storage medium and a read/write circuit coupled the data storage medium via a communication channel. The read/write circuit includes a formatter circuit to receive a read back signal related to data stored on the data storage medium and to produce an output vector related to the read back signal. The read/write circuit further includes a multiple-input multiple-output (MIMO) equalizer coupled to the formatter circuit and adapted to generate an equalized output vector related to the output vector. The read/write circuit also includes a MIMO detector coupled to the MIMO equalizer and adapted to generate hard bit decisions based on the equalized output vector. | 08-19-2010 |
20100287421 | Virtual Lock Stepping in a Vital Processing Environment for Safety Assurance - An apparatus and method for train control utilizing virtual lock stepping are disclosed. In accordance with the illustrative embodiment, an improved method of train control utilizes identical software applications executing on redundant processors. The redundant processors are maintained in virtual lock step to ensure the safety integrity of the overall system being controlled. In accordance with the illustrative embodiment, one software process is a master and one software process is a slave. The master and the slave both independently execute application logic based upon detected events (e.g., input data, etc.). In order to ensure that any anomalies that might result in a hazard are detected in the timeliest manner, and that false anomalies are minimized, the redundant software processes must process the same event within a specified time frame. | 11-11-2010 |
20100287422 | TRANSMISSION DEVICE AND METHOD FOR PUTTING TRANSMISSION DEVICE TO SLEEP - A transmission device including at least one transmitter/receiver unit that is coupled to another transmission device via a communication line, a power supply unit that supplies power to the at least one transmitter/receiver unit, and a control unit that notifies the another transmission device about first sleep start information specifying time at which an operating mode of the at least one transmitter/receiver unit is to be changed to a sleep mode and that stops the supply of power from the power supply unit to the at least one transmitter/receiver unit at the time specified by the first sleep start information. | 11-11-2010 |
20100306601 | INTEGRATED MICROPROCESSOR SYSTEM FOR SAFETY-CRITICAL CONTROL SYSTEMS - An integrated microprocessor system for safety-critical control systems, comprising at least two microprocessor system modules each comprising at least one processor core, a read/write memory and a memory protection unit, and a read-only memory which is jointly assigned to the processor cores of the microprocessor system modules. Each of the microprocessor system modules executes a main program and a monitoring program which may comprise a plurality of subprograms. If the memory protection unit detects unauthorized operations by one of the programs for accessing a separate address area (A, B) of another program, then the respective memory protection unit assigns a separate address area (A, B) of the read/write memory to the main program and to the monitoring program. | 12-02-2010 |
20110035632 | COMMUNICATION SYSTEM WITH AUTOMATIC RESTORING FUNCTION AGAINST FAULTY OPERATION AND RESTORING METHOD THEREOF - Provided are a communication system and a method of restoring the communication system. The communication system includes a master device for transmitting a reference clock through a clock line, transmitting and receiving data through a data line, and requesting and receiving input data and error detection data, and a slave device for detecting human touch input data, transmitting and receiving the data in synchronization with the reference clock or generating and transmitting the input data, and transmitting the error detection data in response to the request for error detection data. Here, the master device compares stored error detection data with the received error detection data and initializes the slave device when the stored error detection data is not the same as the received error detection data. Therefore, in the master-slave communication system capable of automatic restoration from a malfunction and the method of restoring the communication system, a master device recognizes malfunction of a slave device having a volatile storage due to its surroundings, initializes the slave device, and thus can restore the slave device to its normal operating state. | 02-10-2011 |
20110072321 | OPTIMISTIC DATA WRITING IN A DISPERSED STORAGE NETWORK - A method begins by a processing module dispersed storage error encoding data to produce a set of encoded data slices and sending a set of write request messages to a set of dispersed storage (DS) units, wherein each of the set of write request messages includes an encoded data slice of the set of encoded data slices. The method continues with the processing module determining whether a pillar width number of favorable write response messages has been received within a write acknowledgement (ACK) time period. The method continues with the processing module executing a retry write process to at least one DS unit of the set of DS units from which a favorable write response message was not received during the write ACK time period when the pillar width number of favorable write response messages has not been received within the write ACK time period. | 03-24-2011 |
20110225467 | STARTING VIRTUAL INSTANCES WITHIN A CLOUD COMPUTING ENVIRONMENT - Embodiments of the present invention provide a system that leverages the Operational Support System(s) (OSS) and Business Support system(s) (BSS) of a (e.g., public) computing Cloud with a service to automate virtual instance restarts. For example, under embodiments of the present invention, a failed virtual instance is detected within the Cloud computing environment, and a request for a new virtual instance is received in response thereto. Upon receiving the request, an entitlement of a user associated with the failed virtual instance will be tested. Specifically, a set of authentication calls and checks are deployed in accordance herewith to ensure the integrity of the requests, as well as the authorization of the requester for the resource use. Assuming testing is passed, a countdown timer associated with the failed virtual instance will be decreased. When the countdown timer reaches a predetermined threshold (e.g., zero), the new virtual instance will be started, the failed virtual instance will be terminated, and the countdown timer will be reset/restarted by instance. Integration with BSS further allows for monitoring and charging of service usage as well as opening the option for pay-as-you-go charges for the restart service itself. | 09-15-2011 |
20110246839 | CONTROL DEVICE - An RTC, having a crystal oscillator of different characteristics from those of a crystal oscillator, is provided, and the pulse period of the pulse signal from the RTC and the pulse signal based on the crystal oscillator are compared to detect a fault in the crystal oscillator. As a result, even if, for example, located in a high temperature environment, the degrees to the decrease in frequency will be different, thus making it possible to detect reliably a fault in the crystal oscillator. | 10-06-2011 |
20110276843 | INTELLIGENT ERROR-REPORTING APPARATUS AND METHOD - A method for intelligently reporting errors is disclosed herein. In one embodiment, such a method includes detecting an error and determining whether the error belongs to an error group. Such an error group may include errors that together are an indicator of a potentially more serious error or condition. The method may further determine whether all errors in the error group have occurred within a specified time period. If all errors in the error group have occurred within the specified time period, the method automatically sends a notification to an administrator or other hardware or software-based system so that the problem or error can be addressed. A corresponding apparatus and computer program product are also disclosed herein. | 11-10-2011 |
20110302460 | Apparatus and method for detecting an approaching error condition - An apparatus and method are provided for detecting an approaching error condition within a data processing apparatus. The data processing apparatus includes a second sequential storage structure which is arranged to latch the output signal generated by combinatorial circuitry dependent on a second clock signal. The second sequential storage structure has a main storage element to latch a value of the output signal for provision to subsequent combinatorial circuitry, and transition detection circuitry for detecting a change of the value of the output signal latched by the main storage element during a predetermined timing window, said change indicating an approaching error condition whilst the value stored in the main storage element is still correct. The second sequential storage structure can be operated in either a first mode of operation or a second mode of operation. In the first mode of operation, the predetermined timing window is a timing window ahead of a time at which the main storage element latches said value of the output signal, to thereby enable an approaching setup timing error due to a propagation delay within the combinatorial circuitry to be detected. In the second mode of operation, the predetermined timing window is a timing window after the time at which the main storage element latches said value of the output signal such that an approaching hold timing error due to an increase in skew between the first and second clock signals is detected. Such a technique provides a simple and efficient mechanism for detecting a variety of approaching error conditions whilst the second sequence storage structure continues to operate correctly. | 12-08-2011 |
20110320889 | Server Reachability Detection - An application attempts to use a first protocol stack to send a first message to a server. After attempting to send the first message to the server, the application attempts to use a second protocol stack to send a second message to the server. After attempting to send the second message to the server, the application performs a timeout activity before a timeout period for the second message expires when the first message timed out. Alternatively, when the timeout period for the second message expires and the first message did not time out, the application performs the timeout activity. When the client device received a response to the second message from the server before the timeout period for the second message expires, the application performs a different activity. | 12-29-2011 |
20120030525 | NOTIFICATION SYSTEMS AND METHODS WHERE A NOTIFIED PCD CAUSES IMPLEMENTATION OF A TASK(S) BASED UPON FAILURE TO RECEIVE A NOTIFICATION - Systems and methods are disclosed for automated notification systems. A representative system, among others, can be summarized as follows. A host computer system, or base station, is designed to monitor travel data corresponding to a mobile thing and to initiate a notification communication to a personal communications device (PCD) indicating travel status of the mobile thing (MT) to a remote computer system. The remote computer system, within or associated with the PCD, is designed to detect a failure to receive the notification communication and to cause one or more tasks to be performed based upon the notification communication failure. | 02-02-2012 |
20120047407 | USING A VARIABLE TIMER FOR SENDING AN ERROR INDICATION - Upon receiving a particular data unit by a receiving layer of a wireless device, it is detected that a previous data unit earlier in sequence to the particular data unit has not yet been received by the receiving layer. A timer is started in response to the detecting, where the timer has a time-out period that is variable dependent upon a parameter associated with receipt of the particular data unit. Upon expiration of the timer based on the timeout period, the receiving layer generates an error indication. | 02-23-2012 |
20120066557 | APPARATUS FOR DETECTING PRESENCE OR ABSENCE OF OSCILLATION OF CLOCK SIGNAL - A semiconductor apparatus includes an arithmetic circuit that executes a program based on an operating clock signal input through a clock transfer node, an internal oscillator that generates an internal clock signal to be used internally, a watch dog timer that counts the internal clock signal, detect that a count value reaches a predetermined value of an execution time of the program in the arithmetic circuit and output a notification signal, and a clock monitor circuit that detects presence or absence of the operating clock signal in response to the notification signal. | 03-15-2012 |
20120124431 | METHOD AND SYSTEM FOR CLIENT RECOVERY STRATEGY IN A REDUNDANT SERVER CONFIGURATION - A method and system for client recovery strategy to maximize service availability for redundant configurations is provided. The technique includes adaptively adjusting timing parameter(s), detecting failures based on adaptively-adjusted timing parameter(s), and switching over to a redundant server. The timing parameter(s) include a maximum number of retries, response timers, and keepalive messages. Switching over to alternate servers engaged in warm sessions with the client may also be implemented to improve performance. The method and system allow for improved recovery time and suitable shaping of traffic to redundant servers. | 05-17-2012 |
20120144250 | Visual Outage Management Tool - Described herein are systems related to a visual tool for providing a dynamic and accessible collaborative environment during a production outage or network downtime. An outage management tool comprising a server application tool receiving and storing monitoring data related to an operation of a network and application-level components of the network, wherein the monitoring data includes outage information corresponding to one of the network and the application-level components, and a visualization tool generating an interactive representation of the network including the outage information, the visualization tool and generating, in response to a request, an adjusted interactive representation of the network including application-level components affected by an outage and event traffic related to the outage | 06-07-2012 |
20120159267 | DISTRIBUTED COMPUTING SYSTEM THAT MONITORS CLIENT DEVICE REQUEST TIME AND SERVER SERVICING TIME IN ORDER TO DETECT PERFORMANCE PROBLEMS AND AUTOMATICALLY ISSUE ALTERTS - A client device in a distributed system may include a timer for timing a request time duration substantially including a period of time that the client device is waiting for results to be received via a network from a server in response to a request sent by the client device. A network interface may receive a value of a service time duration from the server. The service time duration may correspond to time that the server spent servicing the request. A processor may subtract the service time duration from the request time duration to thereby calculate a difference time duration, and automatically control the network interface to issue one or more alert messages to a network operation center (NOC) via the network when the difference time duration is greater than a difference time threshold. The difference time threshold may be determined according to a type of the request. | 06-21-2012 |
20120239989 | Monitoring and Verifying a Clock State of a Chip - A mechanism is provided for monitoring and verifying a clock state of a chip that does not write out clock state information. Responsive to identifying an access to the chip, the access is scanned to identify a chip register and a clock domain that will be accessed. A determination is made as to whether a bit of a clock trust unit associated with the chip register and the clock domain indicates whether to trust a clock state associated with the bit in a logical clock state unit. Responsive to the bit of the clock trust unit indicating that the clock state associated with the bit in the logical clock state unit is trusted, the clock state from the logical clock state unit is identified. Responsive to the clock state matching the clock state required by the access, the access is forwarded to the chip for execution. | 09-20-2012 |
20120254674 | COMMUNICATION DEVICE AND TIME SYNCHRONIZATION SYSTEM - In an embodiment, provided is a communication device connected to time servers via a network with transfer devices. In the communication device: a network controller receives a message containing time information counted by the time server and containing a network identifier, and obtains a receiving timing of the message; a network processing unit, when the network identifier in the message does not match with any network identifier, destroys the message; a protocol processing unit, when the network identifier has a match, calculates a time error by the time information in the message and the receiving timing, detects whether a first time server is malfunctioning, and when detected the first time server malfunctioning, outputs the time error calculated by a network identifier assigned to a second time server; a servo calculates an operation amount by the time error; and a clock varies a clock rate according to the operation amount. | 10-04-2012 |
20130024734 | STORAGE CONTROL APPARATUS AND CONTROL METHOD OF STORAGE CONTROL APPARATUS - [This invention] inhibits the response time of the storage control apparatus from being longer even if the response time of the storage apparatus is long. | 01-24-2013 |
20130246866 | SYSTEM AND METHOD FOR VERIFYING THE INTEGRITY OF A SAFETY-CRITICAL VEHICLE CONTROL SYSTEM - A control system according to the principles of the present disclosure includes an operation control module, a fault detection module, a remedial action module, and a reset module. The operation control module controls operation of a vehicle system. The fault detection module detects a fault in the operation control module when the operation control module fails an integrity test. The remedial action module takes a remedial action when the fault is detected. The reset module resets the operation control module when the fault is detected and the remedial action is not taken. | 09-19-2013 |
20130254598 | ACCESS METHOD AND MULTI-CORE PROCESSOR SYSTEM - An access method is executed by a multi-core processor system. The access method includes activating a driver that corresponds to a first CPU, based on a start of execution of a first application; starting measurement of an access time period, based on access of a peripheral device; outputting, when the access time period exceeds a predetermined time period, a detection signal to reset the driver; and prohibiting, when the access time period exceeds a predetermined time period, writing into a register retaining data to be written into the peripheral device from the first CPU. | 09-26-2013 |
20140019815 | PROCESSING ERROR DETECTION WITHIN PIPELINE CIRCUITRY - An integrated circuit | 01-16-2014 |
20140032983 | Computer Program Product for Handling Communication Link Problems Between a First Communication Means and a Second Communication Means - A computer program product for handling communication link problems between a first communication means and a second communication means. Data signals, control signals and/or error information are transferred between the first communication means and the second communication means using the communication link. The method includes activating a static identification pattern in the first communication means representing an error information, and stopping a clock signal (Clk) inside the first communication means to freeze a present error condition, in response to a communication link problem being detected, and transferring the activated static identification pattern permanently and/or repeatedly to the second communication means using the communication link. | 01-30-2014 |
20140068354 | APPARATUS AND METHOD FOR DETERMINING A STATE OF A MOBILE TERMINAL - A method for determining an operational status of a terminal includes transmitting, from a first processor to a second processor, a request for determining a status of the second processor; executing a timer operation for a time period; determining that the second processor is in a hang state if a response message is not received from the second processor within the time period; and transmitting a reboot command for rebooting the second processor. A terminal includes a first processor to transmit a status request message to a second processor, to initialize a timer to run until expiration of a time period, and to transmit a reboot command to a power management unit if the response message is not received within the time period; and the second processor to transmit a response message prior to expiration of the time period if the second processor is operating normally. | 03-06-2014 |
20140082434 | SAFETY SYSTEM CHALLENGE-AND-RESPONSE USING MODIFIED WATCHDOG TIMER - Some embodiments of the present disclosure relate to a watchdog timer having an enhanced functionality that enables the watchdog timer to monitor a process flow of the microprocessor on a task-by-task basis that enables a simple output signal to be used to determine if the watchdog timer is malfunctioning. The watchdog timer has a state machine that increments a state variable from an initial value over a watchdog period. A deterministic service request, received from a microprocessor, controls operation of the watchdog timer. The deterministic service request has an indicator of a monitoring operation to be performed, a password, and an estimated state variable. A comparison element determines if the microprocessor is operating properly based upon a comparison of the received password to an expected password and the received estimated state variable to an actual state variable. | 03-20-2014 |
20140115408 | MAXIMUM FREQUENCY AND MINIMUM VOLTAGE DISCOVERY - Selection of a minimum voltage and/or maximum clock frequency in an integrated circuit is described. Selection of the minimum voltage and/or maximum clock frequency is accomplished by generating a timing error prediction signal and a timing error detection signal in a timing error module that is placed in a critical path in the integrated circuit. | 04-24-2014 |
20140149809 | Method for Monitoring at least Two Microcontrollers - A method for monitoring at least two microcontrollers using a watchdog is described. The watchdog is associated with a first microcontroller and monitors the communication of a message from the first microcontroller within a time interval of a predefined duration. The message communicated to the watchdog by the first microcontroller contains a contribution which is formed on account of communication between the first microcontroller and a second microcontroller connected to the latter and on the basis of which the watchdog checks the proper method of operation of the second microcontroller. The disclosure also describes a circuit arrangement and a battery with a battery management unit which are configured to carry out the method according to the disclosure. | 05-29-2014 |
20140181599 | TASK SERVER AND METHOD FOR ALLOCATING TASKS - At least two task servers connect to a database server. The database server includes a task list. A task server accesses the task list to search a task which is an earliest presenting task. When the searched task has not been executed, the task server marks the searched task with a serial number of the task. The task server records an execution start time of the searched task. When a time of executing the searched task is more than a predefined time, the task server prompts a user to deal with an error of the task server. | 06-26-2014 |
20140201578 | MULTI-TIER WATCHDOG TIMER - Due to software bugs, hardware bugs, power fluctuations, cosmic rays, and various other causes, computing systems may from time to time enter various types of error states. This disclosure relates generally to the field of watchdog timers configured to take corrective action when a computing system enters such an error state. In various embodiments, this disclosure provides systems, methods, apparatuses, and computer-readable media for multi-tier watchdog timers. Such multi-tier watchdog timers may be configured to take different levels of corrective action at different times and/or under different conditions. | 07-17-2014 |
20140298117 | DETECTION OF USER BEHAVIOR USING TIME SERIES MODELING - The embodiments provide a way to predict when a storage device will be accessed. In order to enhance performance, the storage device may proactively prepare for the access operation, and thus, minimize the access-time response of the storage device. The user behavior is recorded over time and collected into a dataset. In one embodiment, the intervals between the data points in the dataset are calculated and arranged into a matrix. Patterns in the matrix are recognized and used to recognize the next likely access by the user. The storage device may then take various actions, such as drive spin up, in anticipation of the next predicted access to minimize access-time response. | 10-02-2014 |
20150033085 | SYSTEMS AND METHODS FOR STORING INFORMATION - Embodiments relate to multi-contact sensor devices and operating methods thereof that can reduce or eliminate offset error. In embodiments, sensor devices can comprise three or more contacts, and multiple such sensor devices can be combined. The sensor devices can comprise Hall sensor devices, such as vertical Hall devices, or other sensor types in embodiments. Operating modes can be implemented for the multi-contact sensor devices which offer significant modifications of and improvements over conventional spinning current principles, including reduced residual offset. | 01-29-2015 |
20150052407 | SEMICONDUCTOR DEVICE THAT DETECTS ABNORMALITIES OF WATCHDOG TIMER CIRCUITS - A diagnosis circuit | 02-19-2015 |
20150067413 | METHODS FOR TRANSITIONING CONTROL BETWEEN TWO CONTROLLERS OF A STORAGE SYSTEM - Described herein are methods for transitioning control between a first and second controller of a storage system. In such transition, the first controller transmits a message to a memory element shared by the first and second controllers, the message capable of notifying the second controller of an imminent failure of the first controller. The second controller receives the message from the shared memory element, the message notifying the second controller of an imminent failure of the first controller. Subsequent to transmitting the message to the shared memory element, the first controller becomes unavailable to facilitate access to the storage devices of the storage system. Subsequent to receiving the message from the shared memory element, the second controller becomes available to facilitate access to the storage devices of the storage system. | 03-05-2015 |
20150067414 | METHODS FOR TRANSITIONING CONTROL BETWEEN TWO CONTROLLERS OF A STORAGE SYSTEM - Described herein are techniques for transitioning control between a first and second controller of a storage system. In such transition, the first controller transmits a message to a memory element shared by the first and second controllers, the message capable of notifying the second controller of an imminent failure of the first controller. The second controller receives the message from the shared memory element, the message notifying the second controller of an imminent failure of the first controller. Subsequent to transmitting the message to the shared memory element, the first controller becomes unavailable to facilitate access to the storage devices of the storage system. Subsequent to receiving the message from the shared memory element, the second controller becomes available to facilitate access to the storage devices of the storage system. | 03-05-2015 |
20150089307 | WATCHDOG TIMER AND CONTROL METHOD THEREFOR - A watchdog timer including a first register that stores a first overflow time, a second register that stores a second overflow time, a detector and a counter that continues to count a clock signal to the first overflow time. When the detector detects an execution of a program for a flash memory, the counter clears a count value and continues to count the clock signal to the second overflow time. | 03-26-2015 |
20150095724 | WATCHDOG APPARATUS AND CONTROL METHOD THEREOF - The present invention provides a watchdog apparatus in which a main MCU and a sub MCU are connected by SPI communication, including: a token generating unit which generates a seed value and generates at least two tokens using the seed value; a watchdog signal generating unit which generates a watchdog signal corresponding to the generated token; a signal determining unit which determines whether the generated watchdog signal is in a normal state and thus provides an advantageous effect which may detect an abnormality of the MCU only using a software logic without providing an additional configuration. | 04-02-2015 |
20150113340 | METHOD AND APPARATUS FOR IMPLEMENTING HEARTBEAT SERVICE OF HIGH AVAILABILITY CLUSTER - Embodiments of the present invention provide a method for implementing a heartbeat service of a high availability cluster, including: writing, by a server, heartbeat counting information to a disk array, where the heartbeat counting information includes a write heartbeat message sequence number, a read peer heartbeat message sequence number, active-standby state information, a heartbeat message, and a heartbeat message length of the server, so that one or more corresponding servers read the heartbeat counting information, in the disk array, of the server; and reading heartbeat counting information, which is written by the one or more corresponding servers to the disk array, of the one or more corresponding servers, and repeating the write operation and the read operation. Correspondingly, the embodiments of the present invention further provide a server, which solves a spit-brain problem, and improves data security. | 04-23-2015 |
20150127997 | MINIMIZING THE AMOUNT OF TIME STAMP INFORMATION REPORTED WITH INSTRUMENTATION DATA - This invention is time stamping subsystem of an electronic apparatus. A time stamp generator generates a multibit time stamp value including a predetermined number of least significant bits overlapping a predetermined number of most significant bits. Each client receives the least significant bits. Each client associates captured data with a corresponding set of the least significant bits in a message. A central scheduling unit associates most significant bits of the time stamp value with the least significant bits of the message. This associating compares overlap bits of the most significant bits and least significant bits. The most significant bits are decremented until the overlap bits are equal. | 05-07-2015 |
20150135021 | Context Analysis at an Information Handling System to Manage Authentication Cycles - Context captured with sensors of an information handling system is applied to selectively lock access to currently unlocked information, with conditions for locking access based upon the context. Nervous states enforce locking of selected information based upon the confidence of the security of the information under sensed external conditions. Increased sensitivity for locking access includes reduced timeouts to a lock command, increased response to sensed conditions, and more rapid response where unlocked access is to sensitive information. | 05-14-2015 |
20150301879 | SEMICONDUCTOR DEVICE HAVING A SERIAL COMMUNICATION CIRCUIT FOR A HOST UNIT - In a serial communication circuit, a data extracting section extracts reception data based on a reception clock signal with maximum speed. A pattern determining section compares a reception bit pattern of the reception data corresponding to a characteristic pattern and each of a plurality of detection bit patterns for the characteristic pattern, and indicates when the reception bit pattern matches one of the detection bit patterns. A periodicity determining section determines a period when the reception bit pattern matches the detection bit pattern, based on the pattern match indication, detects that the detection bit pattern emerges continuously in a stream of the reception data every the period, and determines a generation difference between transmission and reception speeds based on the detection bit pattern. A transmission rate setting section determines the transmission speed of a connected device transmitting the reception data based on the generation difference and maximum speed. | 10-22-2015 |
20150302024 | Storage System and Method for Processing Data Operation Request - A storage system and a method for processing a data operation request are disclosed. The method is applied to a storage system that has a write once read many (WORM) function. In the method, after the storage system receives a data operation request, which is used to change data stored in the storage system, sent by an application server, the storage system acquires a time difference between a real-time clock (RTC) and a reference clock, wherein the RTC is configured to provide system time for the storage system, and the reference clock cannot be modified when the system is running. Then, the storage system determines whether the time difference is greater than an accumulated time precision error of the reference clock, and refuses to execute the data operation request when the time difference is greater than the accumulated time precision error. | 10-22-2015 |
20150331739 | Method and Apparatus for Controlling Sending of Heartbeat Signal - A method and an apparatus for controlling sending of a heartbeat signal are provided. The method includes acquiring a target push delay corresponding to all target applications; sending the target push delay to a push server; receiving a first heartbeat signal control time sent by the push server and corresponding to the target push delay; and sending a heartbeat signal to the push server at an interval of the first heartbeat signal control time. According to the embodiments of the present invention, a first heartbeat signal control time may be determined according to an acquired target push delay corresponding to all target applications, and the first heartbeat signal control time may be adjusted according to a target application, so that a push client can send a heartbeat signal to a push server at an interval of the first heartbeat signal control time, to maintain a Push connection. | 11-19-2015 |
20150339178 | PROCESSING SYSTEM AND METHOD OF OPERATING A PROCESSING SYSTEM - A processing device, comprising one or more functional units and a hardware-serviced watchdog timer connected to the functional units is described. The functional units are capable of generating service events which are hardware events of said one or more functional units. The functional units are arranged to generate the signals in response to an application executed on the processing device and making use of the functionality thereof. The watchdog timer is arranged to start a new timeout period in response to any one of said signals. The service events may include, for example, a start or an end of a data transfer operation to or from one of the functional units. | 11-26-2015 |
20150363251 | METHOD FOR GENERATING A MACHINE HEARTBEAT - A method and system for generating a heartbeat of a process including at least one machine configured to perform a process cycle consisting of timed events performed in a process sequence includes determining the duration of each timed event during performance of the process cycle, ordering the durations of the timed events in the process sequence, and generating a heartbeat defined by the ordered durations of a process cycle. One or more process parameters can be sensed and displayed with the heartbeat in real time. The variance of a current heartbeat to a baseline heartbeat and/or a comparison of a process parameter to a parameter limit can be analyzed to monitor and/or control the process or machine. The heartbeat, the process parameter corresponding to the heartbeat can be displayed on a user interface which can include a message corresponding to the heartbeat and/or the process parameter. | 12-17-2015 |
20160055049 | ULTRA LOW POWER PROGRAMMABLE SUPERVISORY CIRCUIT - An ultra-low-power supervisory circuits can employ floating gate transistors. In an example, a supervisory circuit can include a reset output circuit, a voltage comparator circuit configured to reset the reset output circuit when a first input voltage falls below a reference voltage, and a watchdog circuit configured to receive a watchdog signal and to reset the reset output circuit if the watchdog signal does not transition within a predetermined watchdog interval. The voltage comparator circuit can include a first floating gate transistor circuit configured to establish a reference current for generating the reference voltage, and the watchdog circuit can include a second floating gate transistor circuit for selecting the predetermined watchdog interval. | 02-25-2016 |
20160055050 | HARDWARE DEVICE CONTROLLER, IMAGE FORMING APPARATUS, AND CONTROL METHOD - A hardware device controller includes a controlling unit, a relay unit, and a watchdog timer. The controlling unit outputs a control signal to control a hardware device. The relay unit outputs, on the basis of the control signal, a control signal to the hardware device. When not receiving a first signal output from the controlling unit via the relay unit for a predetermined length of time or longer, the watchdog timer outputs a second signal. When the second signal is output, the controlling unit and the relay unit perform initialization process, and the hardware device stops driving. | 02-25-2016 |
20160077909 | WATCHDOG CIRCUIT, POWER IC AND WATCHDOG MONITOR SYSTEM - A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit interrupts the clock signal counting operation of the timer circuit. During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit allows the timer circuit to restart the clock signal counting operation. | 03-17-2016 |
20160098313 | WATCHDOG METHOD AND DEVICE - Each task assigned to a core can be considered an “active” task. Sequential strobe signals of a watchdog signal can be spaced apart in time by a certain duration. The duration between strobe signals is longer than the expected duration of an active task. By knowing that all tasks being monitored are expected to execute within an expected amount of time, the duration between the strobe signals can be set to be longer than that expected amount of time. If a task has not transitioned to inactive by a next strobe, a watchdog error has occurred. | 04-07-2016 |
20160098326 | METHOD AND APPARATUS FOR ENABLING TEMPORAL ALIGNMENT OF DEBUG INFORMATION - A signal processing device includes at least one timestamp generation component arranged to generate at least one local timestamp value, and to provide the at least one local timestamp value to at least one data link layer module for timestamping of data packets. The signal processing device further includes at least one debug module arranged to receive the at least one local timestamp value and to timestamp debug information based at least partly on the at least one local timestamp value. | 04-07-2016 |
20160110245 | METHOD FOR SAVING FAULT WAVE DATA - There is provided a method for saving fault wave data, in which when a fault wave generated in a system is saved, a size of wave data is calculated, and the saving of the wave data is performed according to the size of the wave data, so that it is possible to implement the use of spaces of a buffer and a memory and the simultaneous saving of wave data simultaneously or subsequently generated. Accordingly, it is possible to minimize a delay in the saving of the wave data. Also, it is possible to record all accurate wave data even when consecutive faults occur. Also, it is possible to efficiently use the space of the memory. | 04-21-2016 |
20160117213 | DYNAMIC ADAPTIVE APPROACH FOR FAILURE DETECTION OF NODE IN A CLUSTER - The present disclosure discloses a method and a network device for failure detection of nodes in a cluster. Specifically, a network device transmits data to another device at a first time. The network device then receives an acknowledgment of the data from the second device at a second time. Next, the network device determines a Round Trip Time (RTT) for the first device and the second device based on the first time and the second time. Based on the RTT, the network device determines a first frequency for transmitting a heartbeat protocol message between the first device and the second device, and transmits a heartbeat protocol message between the first device and the second device at the first frequency. | 04-28-2016 |
20160117214 | CONTROLLER - A controller includes a microcomputer that operates in a normal mode or in a low power mode and communicates with an external device, a monitor circuit that monitors an operation state of the microcomputer based on a monitor signal output from the microcomputer, and a start circuit that controls a drive of the monitor circuit. Communication signals exchanged between the microcomputer and the external device include a dominant state and a recessive state, and the start circuit monitors the communication signals. When the communication signals in the low power mode of the microcomputer include the dominant state, the start circuit puts the monitor circuit in a monitoring state. When no monitor signal is input from the microcomputer to the monitor circuit that is operating in the monitoring state, the monitor circuit determines that an abnormality has occurred in the microcomputer. | 04-28-2016 |
20160132378 | METHOD AND APPARATUS FOR CONTROLLING WATCHDOG - A method of controlling a watchdog and an apparatus for the same are provided. The method of controlling a watchdog within a controller includes determining, by a processor, whether to respond to a fault in the controller by comparing a watchdog count with a predetermined watchdog warning level when the fault is detected. Further, the method includes storing, by the processor, information regarding a program group related to the detected fault and a watchdog reset count that corresponds to the program group within a memory after increasing the watchdog reset count when the fault is to be responded to. In addition the processor is configured to reset the controller when the watchdog count exceeds a predetermined watchdog timeout level. Therefore, the present invention prevents occurrence of repeated resets that result from the same cause within the controller. | 05-12-2016 |
20160188398 | REESTABLISHING SYNCHRONIZATION IN A MEMORY SYSTEM - Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving an out-of-synchronization indication associated with at least one of the channels. The memory control unit performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period. | 06-30-2016 |
20160188423 | SYNCHRONIZATION AND ORDER DETECTION IN A MEMORY SYSTEM - Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted. | 06-30-2016 |
20160253233 | Watchdog Timer | 09-01-2016 |
20160378587 | DETECTING UNRESPONSIVENESS OF A PROCESS - Embodiments of the present disclosure disclose a method for detecting unresponsiveness of a process, wherein for each target process in a plurality of target processes, creating and activating a timer on a system kernel side, so as to time the target process; and when timing of the corresponding timer exceeds a predetermined time threshold, determining the target process to be unresponsive, and performing a predetermined associated action. | 12-29-2016 |
20160378619 | Systems and Methods for Serial Data Transfer Margin Increase - Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for enhancing margin in a serial data transfer. | 12-29-2016 |