| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 714036000 | Test sequence at power-up or initialization | 55 |
| 20080201610 | Integrated test method on multi-operating system platform - An integrated test method on a multi-operation system (OS) platform for performing an integrated test of a file system and disk performance in a computer with an extended firmware interface (EFI) system environment on multiple OS platforms is provided. The method includes the following steps. Scan sectors of an entire physical hard disk and perform a hardware underlying test of a disk device in the EFI environment; select and load an OS, then enter the OS environment to test the file system and the disk performance in the system environment; exit from the OS and return to the EFI environment to summarize a test result; determine whether it is necessary to load other OSes, if necessary, return and load other OSes, and if not, send the summarized test result to a server terminal for analysis and processing. | 08-21-2008 |
| 20080209271 | DEVICE AND METHOD FOR TEST COMPUTER - A test device for testing startup performance of a computer comprises a setting circuit for recording triggering times for triggering startup of the computer and a time interval between two successive startups of the computer, a monolithic chip ( | 08-28-2008 |
| 20080288824 | POWER-ON SELF TEST PROGRAM MANAGEMENT APPARATUS AND ITS MANAGEMENT METHOD AND PROGRAM - A POST management apparatus for managing a POST of an SB in a partition which operates in units of an OS using the CPU of the SB as a resource accesses the storage area storing the POST of the SB so as to perform read/write operation and to acquire/recognize the individual information on the SB and the version number information of the POST, transmits the POST of a predetermined version number according to at least one of the individual information and the version number information, and manages the version number of the POST so that the version numbers of the POSTs used in the SBs in units of a partition coincide with each other. | 11-20-2008 |
| 20090077423 | MEMORY DEVICE AND SYSTEM WITH BOOTLOADING OPERATION - Provided are a semiconductor memory device, memory system and method of executing a bootloading operation. The method includes cyclically executing a bootloading operation cycle that includes loading the boot information from the memory to the controller, and performing an ECC operation on the boot information. The ECC operation provides a fail condition indication or a pass condition indication and if the fail condition indication is provided, the next bootloading operation cycle is executed. | 03-19-2009 |
| 20090106592 | TECHNIQUE FOR RESOLVING "NO-TROUBLE-FOUND" (NTF) EVENTS IN ELECTRONIC SYSTEMS - A system that diagnoses a failure in a computer system is described. During operation, the system tests the computer system using a sequence of tests, where a given test includes a given load associated with a pre-determined failure mechanism for a given failure condition. During the given test, the system obtains results, which include telemetry signals that are monitored within the computer system. If the results indicate the given failure condition, the system ceases the testing and indicates that the computer system has the given failure condition. Otherwise, the system continues the sequence of tests until the sequence is completed, at which point, if no fault has been detected, the system indicates that a no-trouble-found (NTF) condition exists. | 04-23-2009 |
| 20090144585 | Debugging method of the basic input/output system - A debugging method of the BIOS is disclosed. Firstly a debugging routine is written into a boot program. Then the BIOS executes the boot program. The BIOS judges whether a status value is equal to a default value of the debugging routine or not. When the status value is equal to the default value, the BIOS outputs a test value according to the debugging routine. When the status value is not equal to the default value, the debugging routine is quit, and the BIOS continues to execute the boot program. | 06-04-2009 |
| 20090172472 | COMPUTER, AND METHOD FOR ERROR-DETECTING AND BOOTING OF BIOS THEREOF - A computer has a first BIOS unit, a second BIOS unit, a bus, a detecting unit, and a first delay unit. The detecting unit is connected to the bus, the first BIOS unit, and the second BIOS unit operationally. In addition, the first delay unit is electrically connected to the detecting unit for controlling the detecting unit to check a status of a bus signal on the bus after a predetermined delay time. Accordingly, the detecting unit may enable the first BIOS unit or the second BIOS unit to boot the computer system according to the state of the bus signal. | 07-02-2009 |
| 20090177925 | Method for memory testing - A method for memory testing implemented on an embedded system, the method comprising steps of loading a booting program when the embedded system is booted; activating a RAM of the embedded system by the booting program; duplicating the booting program itself and writing the duplicated booting program into a first section of the RAM by the booting program; downloading a testing program from an on-line source and writing the downloaded testing program into a second section of the RAM by the duplicated booting program; and enabling the downloaded testing program to check a third section the rest part of the RAM excepting the first and second sections, after the downloaded testing program is executed by the duplicated booting program. | 07-09-2009 |
| 20090292949 | SYSTEM AND METHOD OF MANAGING BIOS TEST ROUTNES - A system and method of a basic input output system (BIOS) test system are disclosed. According to an aspect, a basic input output system (BIOS) test system can include a BIOS test manager configured to enable BIOS testing of multiple information handling systems within a test environment. The BIOS test system can also include a local test harness driver operable to be coupled to the remote BIOS test manager to receive test routines, and a test buffer configured to receive a test routine from the BIOS test manager. The test routine can further be executed using a test engine integrated as a part of a BIOS of a particular information handling system. | 11-26-2009 |
| 20090292950 | METHOD FOR MAKING TEST FIXTURE - A method for making a test fixture includes the following steps. A Linux operating system is installed to a computer storage device and a test program is installed to the storage device. Which kernels have been installed in the Linux operating system is checked to obtain a check result. A part of or entire content of the storage device is copied to a system image file except a boot file. A boot file directory structure is made in the system image file. The boot file in the storage device is customized to make a disc boot file in the boot file directory structure. The check result is recorded in the disc boot file. An initrd file corresponding to the check result is created in the boot file directory structure according to the boot file in the storage device. A bootable test disc is made using the system image file. | 11-26-2009 |
| 20090300421 | METHOD AND APPARATUS FOR CHANGING BIOS PARAMETER VIA AN EXCHANGE FILE - An apparatus for changing BIOS parameters via an exchange file, including a control unit, a microprocessor, a first memory, a second memory, a third memory and a keyboard. The method includes the steps of saving N parameter banks of BIOS in the third memory, forming the exchange file and performing a operation process via parameter banks, which including the steps of forming, writing, reading, revising and opening the exchange file, selecting one of parameter banks and performing corresponding operations according to the selected parameter bank. | 12-03-2009 |
| 20090313504 | BIOS TEST SYSTEM AND TEST METHOD THEREOF - A basic input output system (BIOS) test system includes a protocol conversion module and a computer. The protocol conversion module is connected to a tested device. The computer is connected to the protocol conversion module. The computer controls the protocol conversion module to simulate a keyboard to send keyboard commands to the device. The computer storing correct setting lists and comments of the setting lists of the BIOS. The tested device selects setting lists and comments thereof according to the keyboard selection commands sent by the protocol conversion module. The tested device is connected to the computer to deliver selected setting lists and comments thereof to the computer. The computer compares the selected setting lists and comments thereof with the correct setting lists. | 12-17-2009 |
| 20090327813 | METHOD TO RECOVER FROM A BOOT DEVICE FAILURE DURING REBOOT OR SYSTEM IPL - A method of automatic recovery from a boot device failure and an initial program load (IPL) failure of an operating system (OS) comprises: receiving and complying with a user selected option of an action upon an event of a boot device failure and an IPL failure. The user selected option may consist of taking the action of attempting an auto reboot of the server with the selected boot device and continuing the reboot attempts using the reduced priority boot devices from the bootlist until detection of a boot success, or taking no action allowing for manual user intervention. | 12-31-2009 |
| 20100017659 | Secure Boot Circuit and Method - A circuit includes a circuit identification storage module and a control module. The circuit identification storage module stores circuit identification information. The control module receives the circuit identification information and in response thereto selectively performs a secure boot procedure or a test boot procedure. The control circuit performs the secure boot procedure when the circuit identification information indicates that the circuit is a production circuit. The control circuit performs the test boot procedure when the circuit identification information indicates that the circuit is a test circuit. A related method is also disclosed. | 01-21-2010 |
| 20100088547 | COMPUTER MOTHERBOARD AND POWER-ON SELF-TEST METHOD THEREOF - An exemplary computer motherboard of a computer includes a basic input output system (BIOS) chip having a detecting module, a plurality of function elements, and a control chip connected to the BIOS chip. The control chip includes a plurality of detecting pins each corresponding to a corresponding one of the plurality of function elements. Each of the plurality of detecting pins is grounded via a switch. Each of the plurality of detecting pins is connected to a power source via a resistor. The detecting module of the BIOS chip is configured for detecting voltage levels of the plurality of detecting pins of the control chip, and controlling power states of the plurality of function elements according to the voltage levels of the plurality of detecting pins of the control chip. | 04-08-2010 |
| 20100100769 | POWER ON SELF TEST DEVICE AND COMPUTER SYSTEM APPLYING THE SAME - A power on self test (POST) device and a computer system applying the same are disclosed, wherein the POST device comprises a micro controller and a displaying unit. The micro controller is embedded on a motherboard of the computer system for receiving a plurality of POST codes generated by the computer system during a booting procedure and transforming the POST codes into a displaying signal. The displaying unit which is capable for receiving and showing the displaying signal is connected to the micro controller through a flexible line. | 04-22-2010 |
| 20100107010 | ON-LINE MEMORY TESTING - A method of testing on-line and spare memory is disclosed. Such memory may currently store in-use data at some addresses. The testing is initiated upon an occurrence of a pre-selected condition. An address range is determined that excludes at least the addresses currently storing functional data. The address range is subjected to a test pattern, and errors in the address range are reported. | 04-29-2010 |
| 20100107011 | Device and Method for Outputting BIOS Post Code - A device and method for outputting BIOS POST code, applied to a computer system. The device includes a basic input output system (BIOS), a transfer module and a video graphics array (VGA) connector. The BIOS generates a power-on self-test (POST) code using a low pin count (LPC) interface format. The transfer module receives the POST code and transfers the format of the POST code to a system management bus (SMBus) format. The VGA connector receives and outputs the POST code transmitted from the transfer module. | 04-29-2010 |
| 20100125754 | METHOD FOR ACCESSING A BIG STRUCTURE IN A 64K OPERATING ENVIRONMENT - A method for accessing a big structure in a 64 k operating environment is disclosed. The method includes changing the big structure into plural sub structures; arranging a big memory space by a power on self test (POST) memory manager; and allocating the sub structures to the big memory space. Wherein a length of each sub structure is shorter than 64k | 05-20-2010 |
| 20100223503 | COMPUTER DEBUG METHOD - A computer debug method includes following steps: a Power-On Self Test (POST) is started; several function tests of the POST are executed respectively, wherein at least one set of codes corresponding to each following executing function test is stored in a memory before executing each of the function tests; when the POST is interrupted, wait for a user to input a guess signal through an input device; compare the set of stored codes in the memory with the guess signal; a signal representing that the set of stored codes in the memory equals to the guess signal is output if the set of stored codes in the memory equals to the guess signal. | 09-02-2010 |
| 20100306592 | COMPUTER SYSTEM ON AND OFF TEST APPARATUS AND METHOD - A computer system on/off test apparatus includes a time control unit receiving a time interval value and a repetition value, a detecting unit detecting signal parameters of the computer system, and a test control unit receiving an external power supply and switching the power connection between the external power supply and the computer system. The test control unit saves a number of acceptable ranges. The test control unit receives a power-on status signal returned from the computer system in response to the computer system is powered. The test control unit determines whether the power-on status signal is correct and the detected signal parameters of the computer system are within the acceptable ranges correspondingly. The test control unit turns off the computer system after the interval time, and then turns on the computer system to repeat the above process until the test number of tests reaches the repetition value. | 12-02-2010 |
| 20110029815 | Electronic Device and Method for Operating the Electronic Device - The invention describes an electronic device and a method for operating the electronic device. The electronic device includes one or more circuit components. The electronic device further includes one or more fuses and one or more non-volatile memories to disable the access of at least one of the one or more circuit components. Each of the one or more non-volatile memories includes one or more firmware, which are used to program at least one bit to manage the access of the at least one circuit component. The method includes performing a power-up sequence in a power cycle for the electronic device. The method further includes determining a state of circuit and a state of a bit for selectively enabling a test function. | 02-03-2011 |
| 20110029816 | PERSONAL COMPUTER DIAGNOSTIC TEST BEFORE EXECUTING OPERATING SYSTEM - A personal computer component diagnostic method is executed to recognize the status or potential problems of a computer before executing an operating system. The personal computer component diagnostic method comprising: calling a BIOS program; executing a component basic diagnostic program; and executing a component functional test after executing a predetermined step. The component functional test includes a CPU MSR/MTRR test, a hard disk S.M.A.R.T. test, a boot path test and a PCI device scanning test. | 02-03-2011 |
| 20110161737 | POST CODE MONITORING SYSTEM AND METHOD - A system is configured for monitoring power-on self-test (POST) codes generated by a motherboard under a power cycling test. The system includes a recording device configured to save the POST codes and a monitoring circuit board. The monitoring circuit board is configured to receive the POST codes from the motherboard and output the POST codes to the recording device. The monitoring circuit board is capable of displaying the POST codes one by one to indicate a current running state of the motherboard and outputting the POST codes in a format that the recording device is receivable. A method for monitoring power-on self-test (POST) codes generated by a motherboard under a power cycling test is also disclosed. | 06-30-2011 |
| 20110239049 | Computer Data Protection Lock - An information handling system includes a lock, a switch, and a south bridge. The lock is configured to receive a key and to alternate between a locked position and an unlocked position. The switch is in communication with the lock. The switch is configured to receive a signal from the lock, to close if the lock is in the locked position, and to open if the lock is in the unlocked position. The south bridge is in communication with the switch. The south bridge is configured to disable a plurality of communication ports of the information handling system when the switch is closed, and configured to enable the communication ports when the switch is opened. | 09-29-2011 |
| 20120036396 | Built-in-Self-Test Using Embedded Memory and Processor in an Application Specific Integrated Circuit - A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implement using a few terminals of the ASIC. | 02-09-2012 |
| 20120137179 | PROCESSING SYSTEM FOR MONITORING POWER-ON SELF-TEST INFORMATION - A processing system for monitoring the power-on self-test information is used for monitoring an operating state of a complex programmable logic device (CPLD) of a main board. The processing system includes a basic input/output system (BIOS) device, a CPLD and a monitoring device. The BIOS device sends power-on self-test information at a first frequency. The CPLD is electrically connected to the BIOS device. The CPLD further includes a first in first out (FIFO) register, and the FIFO register is used for storing the received power-on self-test information. The CPLD sends the power-on self-test information stored in the FIFO register at a second frequency. The monitoring device is electrically connected to the CPLD. The monitoring device is used for receiving the power-on self-test information sent from the CPLD. | 05-31-2012 |
| 20120159254 | Debugging Apparatus for Computer System and Method Thereof - The present invention relates to a debugging apparatus for a computer system and a method thereof. A detecting unit detects if a debugging unit connects to the computer system. When a debugging unit connects to the computer system, the detecting unit produces a detecting signal, which contains information of a bus in the computer system electrically connected with the debugging unit. Then a selection unit selects the bus electrically connected with the debugging unit according to the detecting signal. Besides, a testing unit tests the computer system and produces a power-on self-test (POST) code, so that the selected bus can be used for outputting the POST code to the debugging unit. Thereby, the present invention can choose to use the bus reserved in the computer system for outputting the POST code to the debugging unit, and hence facilitating inspection personnel to debug the computer system. | 06-21-2012 |
| 20120304011 | SERVER AND POWER SUPPLY TEST METHOD - A control server is electronically connected with a number of test servers via a number network interfaces. The control server records a network interface number and an IP address of a baseboard management controller (BMC) of each test server, sets an IP address of a network card of the control server, and generates a test command. The test command comprises information in relation to a number of times for powering on a test server, a number of times for powering off the test server, and a time interval between a power-on operation and a power-off operation. The test command is sent to each test server by the control server according to the network interface number and the IP address of the test server. After receiving the test command, the BMC of the test server performs power-on/power-off operations of the test server according to the test command. | 11-29-2012 |
| 20130080835 | BUILT-IN-SELF-TEST USING EMBEDDED MEMORY AND PROCESSOR IN AN APPLICATION SPECIFIC INTERGRATED CIRCUIT - A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implement using a few terminals of the ASIC. | 03-28-2013 |
| 20130117612 | Starting a Field Device - During starting of a field device for pressure measurement, flow measurement and/or fill level measurement, which field device including a memory that includes a boot memory region in which a boot function is stored, and an operating memory region in which an operating function is stored, the following steps are carried out: carrying out the boot function; determining whether a memory check of the operating memory region is to be carried out; carrying out a memory check of the operating memory region when it has been determined that a memory check is to be carried out; and carrying out the operating function. | 05-09-2013 |
| 20130132776 | METHOD FOR OUTPUTTING POWER-ON SELF TEST INFORMATION, VIRTUAL MACHINE MANAGER, AND PROCESSOR - The present disclosure provides a method for outputting power-on self test information, a virtual machine manager, and a processor. The method includes: receiving trigger information generated by a BIOS program when the BIOS program runs a predefined virtual mode trigger instruction, starting, by a virtual machine manager, the virtual machine manager and monitoring a processor, where the processor is a processor that enters a virtual mode after receiving the trigger information of the BIOS program; when detecting that the processor generates an exit instruction, obtaining power-on self test information after the BIOS program performs a power-on self test operation, and outputting the power-on self test information to a serial port. Power-on self test information may be output without using a motherboard diagnostic card, so that device resources are saved. In addition, the operation is simple, and no human control operation is required. | 05-23-2013 |
| 20130166956 | DIAGNOSTIC CARD FOR RECORDING REBOOT TIMES OF SERVERS - A diagnostic card includes a circuit board, a connector, a controller, and a first display. The connector is coupled to a low pin count (LPC) to receive a reset signal outputted by a basic input output system as a server reboots. The controller is configured to record the total number of reboot times of the server and displays the total number of reboot times on the first display area. | 06-27-2013 |
| 20130238937 | DISPLAY DEVICE AND COMPUTER USING THE SAME - A display device is coupled to a computer, and the computer accommodates a motherboard. The display device includes an interface unit connected to the motherboard, a display panel, and a processor electrically coupled to the interface unit. The processor is used to: receive a power-on self test (POST) code from the motherboard via the interface unit, convert the POST code into a debug code, and control the display panel to display the debug code. | 09-12-2013 |
| 20130339794 | METHOD AND SYSTEM FOR INTER-PROCESSOR COMMUNICATION - A system including a DCU with a DMS located on the first node, where the DMS is associated with an interrupt receive register. The system further includes a second DCU located on second node that includes a GMS located on the second node, where the GMS is associated with an interrupt dispatch register. The GMS is configured to identify the DMS, determine a payload to transmit to DMS, issue cross-calls using the interrupt dispatch register, where a cross-call is issued for each non-zero bit in the payload, and issue a cross-call including a completion vector. The DCU is configured to receive the cross-calls from the GMS, in response to each of the cross-calls, set a corresponding bit-location in the second interrupt receive register to one, and after receiving the completion vector, use a current state of the interrupt receive register to determine a physical address. | 12-19-2013 |
| 20140143601 | DEBUG DEVICE AND DEBUG METHOD - A debug device is presented, which is applicable to a server having a control chip. The debug device includes a receiving unit, a retrieving unit, an analyzing unit, and a processing unit. The receiving unit is coupled to the control chip and is used for receiving a boot detection signal (BDS). The retrieving unit is coupled to the receiving unit and is used for receiving the BDS through the receiving unit and retrieving an information code of the BDS. The analyzing unit has a lookup table, is coupled to the retrieving unit, and is used for receiving the information code, using the lookup table to analyze the information code and generating an analysis result. The processing unit is coupled to the analyzing unit and is used for receiving the analysis result and generating a processing signal according to the analysis result. | 05-22-2014 |
| 20140181586 | METHOD AND APPARATUS FOR PERFORMING HOST BASED DIAGNOSTICS USING A SERVICE PROCESSOR - A method for performing a set of diagnostics on a host system using a service processor. The method includes recognizing a power-on event, and in response checking a diagnostic flag, where the diagnostic flag indicates the set of diagnostics to be performed. Retrieving, from internal storage of the service processor, a disk image including the set of diagnostics to be performed. Mounting, using a disk image reader, the disk image to obtain a mounted disk image. Making the mounted disk image accessible as a device using a virtual device driver. Mounting, using a connection between the service processor and the host system, the device within the host system, and performing the set of diagnostics on the host system. | 06-26-2014 |
| 20140195854 | System and Method to Remotely Recover from a System Halt During System Initialization - An information handling system includes a memory, a processor, and a management controller. The memory includes code to implement a power on self test (POST). The management controller operates to receive an indication that the POST has halted execution in response to a POST error, to log the indication and the POST error, and to send an input to the POST. The POST operates to receive the input and to continue execution based upon the input. | 07-10-2014 |
| 20140195855 | METHOD AND SYSTEM FOR DIAGNOSING APPARATUS - A method for diagnosing an apparatus in a computer system, which includes: determining to enter a diagnostic mode after the computer system is started; initializing a cache in the computer system; after initializing the cache, performing a diagnosis of the apparatus by executing a diagnostic program; and after the diagnosis of the apparatus is completed, executing a Basic Input Output System (BIOS) or Extensible Firmware Interface (EFI) program and loading an operating system. | 07-10-2014 |
| 20150039939 | System and Method for Secure Remote Diagnostics - An information handling system includes a processor and a management controller separate from the processor. The management controller is operable to boot the information handling system to a system service management module, direct the system service management module to execute diagnostics code on the processor and to store a result from the execution of the diagnostics code in a predetermined memory location. The management controller is also operable to retrieve the result from the predetermined memory location. | 02-05-2015 |
| 20150074460 | APPARATUS AND METHOD FOR COMPUTER DEBUG - A computer debug module for use in a computer at least includes a power sequence monitor module. The power sequence monitor module includes a monitor unit, a register, and an output control unit. The monitor unit is configured to monitor a plurality of power sequence signals relative to the computer and generate a monitor result. The register is configured to store the monitor result. When the power sequence monitor module operates in a debug mode, the output control unit generates a detection signal according to the stored monitor result and transmits the detection signal to an output device. | 03-12-2015 |
| 20150074461 | METHOD AND RELEVANT APPARATUS FOR STARTING BOOT PROGRAM - A method and a relevant apparatus for starting a boot program are provided. The method includes: when a boot request is detected, determining whether a first physical block in a NAND flash is a bad block; reading first boot data stored in the first physical block if the first physical block is not a bad block; determining whether the read first boot data has a data error; re-reading the first boot data from a first backup block when the read first boot data has a data error; determining whether the first boot data that is re-read from the first backup block has a data error; when the first boot data that is re-read from the first backup block has no data error, continuing to process other boot data that needs to be read to start the boot program, until start of the boot program is complete. | 03-12-2015 |
| 20150089293 | Non-Volatile Logic Based Processing Device - A processing device boots or wakes using non-volatile logic element (NVL) array(s) that store a machine state. A standard boot sequence is used to restore a first portion of data. A second portion of data is restored, in parallel with the standard boot sequence, from the NVL array(s). A data corruption check is performed on the second portion of data. If the second data is valid, a standard boot sequence is used to restore a third portion of data. If the second data is invalid or the boot is an initial boot, a standard boot sequence is executed to determine the second portion of data, which is then stored in the NVL array(s). The processing device restores the second portion of the data during a portion of the boot/wake process that is not reading data from other non-volatile devices to avoid overloading the respective power domain. | 03-26-2015 |
| 20150095706 | OFFLINE AT START UP OF A POWERED ON DEVICE - A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence. | 04-02-2015 |
| 20150106655 | FAULT DIAGNOSING METHOD BASED ON SIMULATED VACCINE - A fault diagnosing method based on a simulated vaccine is provided. The fault diagnosing method comprises steps of: establishing a dynamic simulation model for simulating a start-up operation and a steady-state operation of a technological process according to process information, an operating procedure and historical data of the technological process; running the dynamic simulation model; extracting data within a first predetermined time from the simulated normal sample set to generate a normal simulated vaccine, and extracting data within a second predetermined time from the simulated fault sample set to generate a fault simulated vaccine; acquiring the historical data of the technological process; obtaining an immune antibody coefficient of the normal simulated vaccine, and generating a normal antibody library; and obtaining an immune antibody coefficient of the fault simulated vaccine, and generating a fault antibody library according to the fault simulated vaccine. | 04-16-2015 |
| 20150121141 | HOST DEVICE AND METHOD FOR TESTING BOOTING OF SERVERS - In a method for testing booting of servers, the servers are controlled to boot and perform a booting test, and are controlled to quit the booting test and a current state of the booting test is stored in a test log, if the booting of one of the servers is unsuccessful. System logs of all of the servers are saved if the booting times of all of the servers do not exceed the first predefined time. An alarm device is controlled to alarm if the booting time of one of the servers exceeds the first predefined time but does not exceed the second predefined time. And the servers are controlled to quit the booting test if the booting time of one of the servers exceeds the first predefined time and further exceeds the second predefined time. | 04-30-2015 |
| 20150121142 | HOST DEVICE AND METHOD FOR TESTING BOOTING OF SERVERS - In a method for testing a booting of servers, the servers are controlled to boot to perform a booting test, and are controlled to quit the booting test. A current state of the booting test is stored in a test log, if the booting of one of the servers is unsuccessful. A system log of each server is saved in the storage device if a first component list of each server is identical to the second component list of the server. The servers are controlled to quit the booting test, and a current state of the booting test is recorded in the test log if the component list of one of the servers is not identical to the second component list the server. | 04-30-2015 |
| 20150370672 | TRIGGER DETECTION FOR POST CONFIGURATION TESTING OF PROGRAMMABLE LOGIC DEVICES - Various techniques are provided to determine signal values of a programmable logic device (PLD) prior to the running of an external test application. In one example, a machine-implemented method includes monitoring, by a PLD, a signal of the PLD. The method also includes detecting a trigger condition associated with the signal. The method also includes storing data in memory of the PLD corresponding to values of the signal. The method also includes passing the stored data from the PLD to an external device running a test application. The stored data comprises values of the signal occurring before the running of the test application. | 12-24-2015 |
| 20160103747 | POST (POWER-ON-SELF-TEST) DEBUGGING METHOD AND APPARATUSES USING THE SAME - The invention introduces a POST (power-On-Self-Test) debugging method, executed by a processing unit, which contains at least the following steps. A phase number indicative of a current POST phase is set. A driver is selected from a scheduled queue. A GUID (Globally Unique Identifier) of the driver is obtained. The phase number and the GUID are stored or output, so as to recognize the phase of the driver being interrupted upon a break point of the driver. After that, the driver is executed. | 04-14-2016 |
| 20160147604 | SERVER SYSTEM - A server system is disclosed herein, which comprises a first BIOS (Basic Input/Output System chip, a second BIOS chip, a baseboard management controller (BMC) and a platform controller. In a preset mode, the platform controller is conductively connected with the first BIOS chip through the BMC and the multiplexer so that the server system is activated by the first BIOS chip. Upon detecting a failure of a POST (Power-on self-test) initialization of the first BIOS chip, the BMC transmits a control command to the multiplexer so as to make the platform controller conductively connecting with the second BIOS chip through the BMC and the multiplexer so that the server system is activated by the second BIOS chip. | 05-26-2016 |
| 20160147626 | System and Method for Reducing Boot Time of a Workload Configuration on a Target Server - An information handling system includes a communication device and a service processor. The communication device includes first terminal, and a second terminal to communicate with a network storage array. The service processor includes a first terminal to receive configuration settings for the communication device, and a second terminal to provide the configuration settings to the communication device. The service processor configures the communication device based on the configuration settings during a first boot sequence of the information handling system. A power-on self test of a basic input/output system of the information handling system is stalled while the service processor configures the communication device based on the configuration settings, and the information handling system is booted from a workload on a storage array identified in the configuration settings without using a second boot sequence of the information handling system. | 05-26-2016 |
| 20160147627 | System and Method for Policy Based Management of a Communication Device Configuration Persistence - An information handling system includes a communication device and a service processor. The communication device includes a first terminal, and a second terminal to communicate with a network storage array. The service processor includes a first terminal to receive persistence policy for the communication device. The service processor is configured to detect a reset of the information handling system, to determine a type of reset performed in an information handling system, to evaluate the persistence policy with respect to the type of reset during a power-on self test executed in the information handling system after the information handling system, and to configure, via the first terminal of the communication device, the attributes of the communication device based on the persistence policy and the type of reset. | 05-26-2016 |
| 20160180094 | METHOD FOR OPTIMIZING BOOT TIME OF AN INFORMATION HANDLING SYSTEM | 06-23-2016 |
| 20160378604 | AGENTLESS AND/OR PRE-BOOT SUPPORT, AND FIELD REPLACEABLE UNIT (FRU) ISOLATION - Systems and methods for providing agentless and/or pre-boot technical support, and Field Replaceable Unit (FRU) isolation. In some embodiments, an Information Handling System (IHS) includes an embedded controller (EC) distinct from any processor or Basic I/O System (BIOS), the EC having program instructions stored thereon that, upon execution, cause the IHS to: implement a network stack independently of an operational status of the processor or BIOS, perform one or more diagnostic operations upon the IHS, and communicate a result of the one or more diagnostic operations to a remote server using the network stack. | 12-29-2016 |
| 20160378605 | PROACTIVE FAULT AVOIDANCE - Systems and methods for proactive fault avoidance. In some embodiments, an Information Handling System (IHS) includes: a processor and a Basic I/O System (BIOS) coupled to the processor, the BIOS having program instructions that, upon execution by the processor, cause the IHS to: accumulate telemetry data received from one or more sensors over a period of time; determine, based upon the accumulated telemetry data, that the IHS has been subject to a given type of environmental or stress condition; and identify, based upon the given type of environmental or stress condition, a potential IHS fault before the fault occurs. | 12-29-2016 |
