Entries |
Document | Title | Date |
20080229150 | Address translation system for use in a simulation environment - Methods and systems for simulation of a testable system are provided in which a virtual testable system is used. One method includes inputting a system definition file into a translation utility, where the system definition file includes a plurality of physical addresses required for execution of the system definition file in the testable system. The method also includes inputting a memory map file into the translation utility, the memory map representing a virtual memory space for a virtual testable system. The method further includes generating virtual translation information by translating the physical addresses into virtual addresses using the memory map file. | 09-18-2008 |
20080256392 | Techniques for prioritizing test dependencies - Techniques for prioritizing test dependencies are described. A computer system employing such techniques may present a test structure for a set of test cases. The test structure may comprise prioritized test cases and dependencies between test cases. The dependencies may be based on predicted test case failure given failure of another test case. Other embodiments are described and claimed. | 10-16-2008 |
20080270834 | CONTROL METHOD FOR READ OPERATION OF MEMORY - Received read commands and address signals are respectively decoded into internal column strobe signals and internal address signals for reading data out of a data storage portion of a memory. A waiting interval during which a readout data becomes ready is simulated or a transmission path on which the readout data is transmitted is simulated. When the simulation result indicates the readout data is ready, an error check operation is performed on the readout data. The operation interval of the error check is simulated. When the simulation for the error check operation indicates that the error check is completed, an error check result is sent out of the memory. | 10-30-2008 |
20090055686 | SERVER SIDE LOGIC UNIT TESTING - A method for server side logic unit testing in an application server environment is provided. The method includes reading a plurality of input parameters from an XML input repository, where the input parameters define an initial state of a test environment, and configuring the test environment to the initial state using the input parameters. The method further includes executing a unit test case using a command test manager to interface between the unit test case and the test environment, where the command test manager translates a command from the unit test case into a test command. The method also includes passing the test command to controller command logic, and accessing test data stored in a database through an access bean using a bean simulator. The method additionally includes receiving test results, including catching an exception on an error condition, and outputting the test results to an XML output repository. | 02-26-2009 |
20090077422 | METHOD AND SYSTEM FOR ACCELERATING TEST AUTOMATION OF SOFTWARE APPLICATIONS - Disclosed is a method and system for capturing a user action on a user interface and fetching user interface elements in the user interface into a first list and operations of the user interface elements into a second list. A test case for the user action is created in an automation accelerator by selecting a user interface element from the first list and an operation of the user interface element from the second list. An automation accelerator script of the test case is created by the automation accelerator. | 03-19-2009 |
20090089618 | System and Method for Providing Automatic Test Generation for Web Applications - In accordance with a particular embodiment of the present invention, a method is offered that includes generating an automatic test case generation using model checking for web applications, the automatic test case generation including: developing a specification; verifying a property using model checking on the specification; obtaining a counterexample, whereby the counterexample is mapped to a web test case; and executing the web test case on an implementation. In more specific embodiments, the method includes generating counterexamples by negating a desirable property and then model checking the specification, whereby the counterexamples represent a set of witnesses that are mapped to the web test case; and executing the web test case on the implementation. In still other specific embodiments, the generating step and the executing step are repeated on available properties and on their available counterexamples. The witnesses can be mapped to the web test case through selected framework technology. | 04-02-2009 |
20090094485 | METHOD FOR ENHANCING FUNCTIONALITY OF AN AUTOMATED TESTING TOOL - A method for enhancing functionality of an automated testing tool. Embodiments of the present invention provide for dynamically adjusting a date in an automated testing tool. System time in a system time format is adjusted according to a date offset. Embodiments of the present invention provide a method of formatting a date in an automated testing tool. System time in a system time format is accessed, wherein the system time comprises a current date and a current time. The date is formatted according to a predetermined date format. Embodiments of the present invention provide a method of regulating access to variables of an automated testing tool. An electronic document of the automated testing tool is populated with at least one variable and at least one value corresponding to the variable. In response to a request to access the variable, access to the variable and the value is provided. | 04-09-2009 |
20090113245 | PROTOCOL AWARE DIGITAL CHANNEL APPARATUS - In one embodiment, provided is a protocol specific circuit for simulating a functional operational environment into which a device-under-test is placed for functional testing. The protocol specific circuit includes a protocol aware circuit constructed to receive a non-deterministic signal communicated by a device-under-test and to control a transfer of the test stimulus signal to the device-under-test in response to the a non-deterministic signal. | 04-30-2009 |
20090119542 | SYSTEM, METHOD, AND PROGRAM PRODUCT FOR SIMULATING TEST EQUIPMENT - The simulation method includes a step of measuring a predetermined characteristic from a real device by using test equipment that supplies a test signal to a device-under-test (DUT); a step of saving Response Data generated from measurements obtained by measuring in a file; and a step of verifying activities of a test plan program in a simulation system that simulates the test equipment by using the Response Data saved in the file. | 05-07-2009 |
20090177924 | CONTEXT SENSITIVE DETECTION OF FAILING I/O DEVICES - Methods for context sensitive detection of failing I/O devices sample and record a response time of an I/O device for each of a first plurality of time intervals to generate a first plurality of sampled and recorded response times, and to determine whether or not at least one I/O error has occurred in each of the first plurality of time intervals. A mathematical model is applied which characterizes the first plurality of sampled and recorded response times. The mathematical model is applied in accordance with an I/O device category corresponding to the I/O device. The mathematical model provides a frame of reference for defining an I/O failure. | 07-09-2009 |
20090193296 | Method and Apparatus for Testing a Full System Integrated Circuit Design by Statistical Fault Injection Using Hardware-Based Simulation - A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator simulator thus emulates the full system IC model. Of all possible fault injection points in the model, the test manager IHS selects a subset of those injection points for fault injection via a statistical sampling method in one embodiment. In response to commands from the test manager IHS, the simulator serially injects faults into the selected fault injection points. The test manager IHS stores results for respective fault injections at the selected injection points. If a machine checkstop or silent data corruption error occurs as a result of an injected fault, the DUT IC model may return to a stored checkpoint and resume operation from the stored checkpoint. The result information is useful in determining a soft error rate (SER) for the DUT IC. | 07-30-2009 |
20090287960 | METHODS, SYSTEMS AND COMPUTER PROGRAM PRODUCTS FOR CPU SIGNATURING TO AIDE IN PERFORMANCE ANALYSIS - Methods, systems and computer program products for CPU signaturing to aide in performance analysis. Exemplary embodiments include a performance analysis method including identifying a workload having one or more testcases, assigning a CPU signature to each of the one or more testcases, calling a CPU signature application programming interface that toggles the CPU to generate the CPU signature, passing four parameters to the CPU signature application programming interface, prior to running each of the one or more testcases of the workload, generating the CPU signature, dynamically determining a run order of the one or more testcases at a run time of the workload and reviewing performance data during the running of each of the one or more testcases, each of the one or more testcases being identifiable by its respective CPU signature. | 11-19-2009 |
20100138695 | Signal Integrity Measurement Systems and Methods Using a Predominantly Digital Time-Base Generator - Signal-integrity measurement systems and methods utilizing unique time-base generation techniques for controlling the sampling of one or more signals under test. A time-base generator made in accordance with the present disclosure includes a phase filter and modulation circuitry that generates a rapidly varying phase signal as a function of the output of a sigma-delta modulator. The phase filter filters unwanted high-frequency phase components from the rapidly varying phase signal. The filtered signal is used to clock one or more samplers so as to create sampling instances of the signal(s) under test. The sampling instances are then analyze using any one or more of a variety of techniques suited to the type of signal(s) under test. | 06-03-2010 |
20100146338 | AUTOMATED SEMICONDUCTOR DESIGN FLAW DETECTION SYSTEM - The process by which a logical simulation model is implemented in a physical device may introduce errors in the resulting implementation. A simulation system enables comparison of a realized physical implementation against the simulation models that produce them, thereby detecting differences between an initial, logical design and the resulting physical embodiment. Errors introduced by an initial design, faulty Intellectual Property blocks, faulty programmable logic device silicon, faulty synthesis algorithms and software, and faulty place and route algorithms and software may be detected. As a result, the simulation system reflects both the accuracy of the actual implemented device with the capacity and performance of a purpose built hardware-assisted solution. | 06-10-2010 |
20100241902 | System and method for performing automated testing of protective relay equipment - A system and method are provided that avoid the need to tether a computer to a test set in order to run a test sequence on a protective relay and obtain result data. A decoupling can be performed by generating command files that can be placed in storage media or provided to the test set separately rather than sending timed commands directly from the computer to the test set. Similarly, a result file generator on the test set can obtain test results and generate a result file that can be placed in such storage media or transported separately to be used by a reporting tool on the computer in the normal fashion. It has been found that various ways of decoupling are possible, using any suitable transport scheme including physical and electronic, both wired and wireless. | 09-23-2010 |
20100281303 | Systems And Methods For Automated Determination Of Error Handling - Systems and methods for automated determination of error handling. Data is received including one or more procedural operations to be tested. A first test is run on the data to capture one or more first tracebacks, where each traceback is associated with a procedural operation. A determination is made as to whether each captured first traceback is unique, where unique tracebacks are added to a unique traceback list. An error condition is simulated on each unique traceback on the unique traceback list by running a second test. The second test is run once for each unique traceback. One or more second tracebacks are captured during each run of the second test. When a unique traceback being tested matches a captured second traceback, an error code is returned and the second test may be run to completion. Errors encountered during each iteration of the second test running to completion are identified. | 11-04-2010 |
20100287411 | METHOD FOR COMPUTER-AIDED SIMULATION OF OPERATING PARAMETERS OF A TECHNICAL SYSTEM - A method for computer-aided simulation of operating parameters of a technical system including a plurality of modules which each contain one or more components is provided. Failure events with associated downtimes for each component are simulated in a predetermined operating period using a first probability distribution for the moment of failure of the components and a second probability distribution for the length of the failure of the components, and a third probability distribution for a degree of reliability of the modules is determined. Based upon the probability distributions for the degrees of reliability of the modules, operating parameters of the technical system are simulated for the predetermined operating period. The method is used for any technical facilities, in particular for energy generation facilities. | 11-11-2010 |
20100318850 | GENERATION OF A STIMULI BASED ON A TEST TEMPLATE - A test template comprising a repetitive block instruction is translated to a stimuli to be used by a target computerized system or a simulator of such a system. The translation comprises reusing translated portion of the repetitive block instruction in order to reduce translation time and to hasten testing phase of the target computerized system. Reuse may be affected by subcomponents of the target computerized system, a predetermined minimal or maximal number of instructions to reuse, and a heuristic determination to increase possibility of discovering a bug using the stimuli. | 12-16-2010 |
20110022893 | DETECTING DATA RACE AND ATOMICITY VIOLATION VIA TYPESTATE-GUIDED STATIC ANALYSIS - Mechanisms for analyzing computer instructions implementing a program in which typestate analysis is informed by concurrency analysis. The concurrency-guided typestate analysis may simulate the “worst case” scenario due to thread interleaving by transitioning a simulated state of the variable to a special state whenever the variable is not guarded by its intended guarding lock. While in the special state, the analysis may assume that the state of the simulated variable is the worst possible state with respect to processing operations that may lead to an error depending on the state of the variable. Thus, the analysis performed may assume that referencing the variable in a state-dependent operation while the simulated state of the variable is in the special state may lead to an error, and the analysis may generate a warning, accordingly. The analysis may process the computer instructions to infer which lock is intended to guard a shared variable. | 01-27-2011 |
20110107147 | APPLICATION PORTAL TESTING - A first test script that includes at least one first step for executing a test of a test portal is provided in a computing device. An indication that an event has occurred in response to the test is received in the computing device. A second test script that includes at least one second step for executing the test is generated in the computing device, the at least one second step being at least in part a response to the event. | 05-05-2011 |
20110126052 | Generation of Test Information for Testing a Circuit - System and method for generating test information for a physical circuit. A virtual circuit may be generated. First user input specifying one or more test conditions and/or instrument settings for the virtual circuit may be received. In response to the first user input, first test information may be generated. The first test information may be configured for use in performing one or more virtual tests on the virtual circuit. Second user input requesting that second test information be generated based on the first test information may be received. The second test information may be automatically generated based on the first test information in response to the second user input, without user input specifying the one or more test conditions and/or instrument settings. The second test information may be configured for use in performing one or more physical tests on a physical circuit corresponding to the virtual circuit. | 05-26-2011 |
20110131451 | METHODS AND SYSTEM FOR TESTING AN ENTERPRISE SYSTEM - A computer storage medium having a computer-readable code segment for performing a method may be provided. The method may include receiving inputs from a user using an interface, the inputs define a test that is run against the application software; associating a resource with the test, the resource selected by the user using the interface; executing the test against the application software; comparing an outputted value of the application software with an expected value; and outputting a result. | 06-02-2011 |
20110145643 | REPRODUCIBLE TEST FRAMEWORK FOR RANDOMIZED STRESS TEST - A test framework architecture that separates the generation of random test actions from test execution and provides a way to record the state of the system under test at user controlled intervals. This saved state is used to bring the test system to the last known state before failure and then execute the much smaller set of actions to the point of failure, thus requiring shorter run time. Given the same time constraints, this enables the execution of this smaller set more frequently, providing better bug fix verification and shorter reproduction time. | 06-16-2011 |
20110154110 | Verifying a Register-Transfer Level Design of an Execution Unit - A mechanism is provided for verifying a register-transfer level design of an execution unit a set of instruction records associated with a test case are generated and stored in a buffer. For each instruction record in the set of instruction records associated with the test case: the instruction record is retrieved from the buffer and sent to both a reference model and an execution unit in the data processing system. Separately, the reference model and the execution unit execute the instruction record and send results of the execution of the instruction record to a result checker in the data processing system. The result checker compares the two results and, responsive to a mismatch in the results, a failure of the test case is indicted, the verification of the test case is stopped, and all data associated with the test case is output from the buffer for analysis, | 06-23-2011 |
20110209004 | INTEGRATING TEMPLATES INTO TESTS - Test template may comprise a source code template instruction associated with source code commands. The source code template instruction is utilized in generation of a test. The generation of instructions associated with the source code template instruction takes into account utilization of shared resources by both the source code commands and by generated instructions that are generated by other template instructions. | 08-25-2011 |
20110314335 | Failure reproducing apparatus and failure reproducing method - A failure reproducing apparatus according to the present invention includes a log analyzing unit that determines processes that have caused a failure when the failure has occurred in a server system, a target-value calculating unit that calculates a target value on the basis of execution time of each process, and a time-lag calculating unit that calculates a time lag. An execution control unit adjusts timing of outputting an execution command of each process to the server system on the basis of the target value and the time lag and executes a reproduction test. | 12-22-2011 |
20120084605 | REPLAYING CAPTURED NETWORK TRAFFIC - Systems, methods, and machine readable and executable instructions are provided for replaying captured network traffic. A method for replaying captured network traffic can include replaying multiple captured network traffic files simultaneously on the same network device, the captured network traffic files including original network traffic captured from N original connections between C original clients and S original servers. During replaying, rewriting IF addresses and/or port number information of data packets comprising the original network traffic to reflect test network traffic from M test connections between X test clients and Y test servers, where at least X is different than C or Y is different than S. The method further includes modifying checksums, during replaying, to correct values corresponding to the rewritten IF addresses and port number information. N, C, S, M, X, and Y are positive integers. | 04-05-2012 |
20120089872 | METHOD AND SYSTEM FOR SUBNET DEFECT DIAGNOSTICS THROUGH FAULT COMPOSITING - A method and system for subnet defect diagnostics through fault compositing is disclosed. Each fault contained in callout data comprises explain failure data and conflict counts. A first fault on a fan-out sink of a fan-out net that explains a first failure is selected from the callout data. A second fault on a different sink of the same fan-out net that explains a second failure that the first fault does not explain is selected. The first fault and the second fault are composited to yield a composite fault. The composite fault unions the failures explained by the first fault with the failures explained by the second fault. A composite conflict count is generated by combining the conflict count of the first fault and the conflict count of the second fault, and a score is assigned to the composite fault. A best candidate composite fault is determined based on the score. | 04-12-2012 |
20120089873 | SYSTEMS AND METHODS FOR AUTOMATED SYSTEMATIC CONCURRENCY TESTING - Systems and method provide a coverage-guided systematic testing framework by dynamically learning HaPSet ordering constraints over shared object accesses; and applying the learned HaPSet ordering constraints to select high-risk interleavings for future test execution. | 04-12-2012 |
20120117427 | VERIFICATION OF OPERATING SELF MODIFYING CODE - Verification of a system-under-test (SUT) supporting the functionality of operating a self modifying code is disclosed. A generator may generate a self modifying code. In response to identification that a simulator is about to simulate code generated by the self modifying code, the simulator may simulate the execution in a “rollover mode”. The code may include instruction codes having variable byte size, branching instructions, loops or the like. The simulator may further simulate execution of an invalid instruction. The simulator may perform rollback the simulation of the rollover mode in certain cases and avoid entering the rollover mode. The simulator may perform rollback in response to identifying a termination condition, as to insure avoiding endless loops. The simulator may perform rollback in response to reading an initialized value that is indefinite. | 05-10-2012 |
20120254665 | GENERATION OF FUNCTIONAL TESTS FOR RE-HOSTED APPLICATIONS - A system and method for generating functional tests to verify code migrated from a first host to a second host. In one embodiment, source code is analyzed in order to generate functional tests that can be used for testing the re-hosted application. In particular, user-input scenarios are extracted from the source code and system output responses are determined based on the user-input scenarios. Functional tests can then be generated using the extracted user-input scenarios and output responses to ensure that the re-hosted application responds in a like manner. | 10-04-2012 |
20120284567 | MODEL-BASED TESTING OF AN APPLICATION PROGRAM UNDER TEST - A method includes receiving a first processing request for an application program under test. The method includes generating a second processing request for a model of the application program, wherein the second processing request is equivalent to said first processing request. The method includes communicating said first and second requests to said application program under test and said model of the application program respectively. The method includes receiving a first response data set from the application program under test and a second response data set from the model of the application program. The method includes comparing said first and second response data sets and generating a success indication if said comparing said first and second response data sets does not identify a difference. The method includes generating an error indication if said comparing said first and second response data sets identifies a difference between the first and second data sets. | 11-08-2012 |
20120304009 | TEST APPARATUS AND TEST METHOD - A test apparatus that tests a device under test outputting a data signal and a clock signal indicating a timing at which the data signal is to be sampled, comprising an acquiring section that acquires the data signal output by the device under test, at a timing corresponding to the clock signal; a buffer section that includes a plurality of entries, buffers the data signal acquired by the acquiring section at the timing corresponding to the clock signal sequentially in the entries, and outputs the data signal buffered in the entries at a timing of a timing signal generated according to a test period of the test apparatus; and a judging section that judges pass/fail of the device under test based on a result of a comparison between the data signal output from the buffer section and an expected value. | 11-29-2012 |
20120311387 | METHOD AND APPARATUS FOR LOAD TESTING ONLINE SERVER SYSTEMS - A method includes capturing data that is representative of actions performed by each of a plurality of human user operated clients as they interact with an online software application, loading at least one or more portions of the captured data into one or more automated simulation clients, and using the one or more automated simulation clients to perform load testing of an online server system. A system includes a data capturing stage, one or more automated simulation clients, and a configuration stage. A computer readable storage medium stores one or more computer programs that will cause a processor based system to execute steps including receiving data that was captured during a running of an online software application and that is representative of actions performed by each of a plurality of human user operated clients as they interacted with the online software application, and loading at least one or more portions of the data into one or more automated simulation clients that are configured to perform load testing of an online server system. | 12-06-2012 |
20130055027 | LOW COST ERROR-BASED PROGRAM TESTING APPARATUS AND METHOD - A low cost error-based program testing apparatus and method are provided. The testing apparatus according to an embodiment of the present invention generates error programs by adding errors to a test target program, selects a test target error program associated with test data among the error programs using error information obtained through the error addition, receives the test data to execute the test target error program, and tests for presence/absence of the errors. Accordingly, it is possible to reduce a text execution time and testing costs. | 02-28-2013 |
20130086426 | EXCEPTION HANDLING TEST DEVICE AND METHOD THEREOF - The present invention relates to an exception handling test apparatus and method. The exception handling test apparatus includes a generation module configured to generate a modified device driver based on a defect model and information obtained from the device manager, a hooking module configured to hook the device driver using the modified device driver, a scanning module configured to collect test information returned from the hooked modified device driver to the application while the application operates, and an analysis module configured to analyze the collected test information. | 04-04-2013 |
20130117611 | AUTOMATED TEST EXECUTION PLAN DERIVATION SYSTEM AND METHOD - A system and method is disclosed that has the ability to automatically derive a test execution plan for parallel execution of test cases, while considering the complex dependencies across the test cases and preserving the semantics of test execution. The execution plan, so generated, provides for balanced workload distribution and scheduling of the test cases for improving the test execution cycles of the test suites in a cost effective manner. | 05-09-2013 |
20130124921 | METHOD AND DEVICE FOR PREDICTING FAULTS IN AN IT SYSTEM - A method and device for predicting faults in a distributed heterogeneous IT system ( | 05-16-2013 |
20130132775 | DIAGNOSTIC MODULE DELIVERY DEVICE, DIAGNOSTIC MODULE DELIVERY METHOD, AND RECORDING MEDIUM - A diagnostic module delivery server includes a diagnostic selecting unit that reads a failure rate of a component from a component database that stores therein the failure rates of the components obtained based on the maintenance history of the components constituting a maintenance target server. Furthermore, the diagnostic selecting unit determines whether to diagnose the component in accordance with the result of comparing the read failure rate of the component and a failure rate reference value that is stored in a diagnostic reference value database. Furthermore, the diagnostic module delivery server transmits, to the maintenance target server, a diagnostic module that is used to diagnose the component in which it is determined, by the diagnostic selecting unit, that the diagnostics is to be performed. | 05-23-2013 |
20130145213 | Dynamic Design Partitioning For Diagnosis - Aspects of the invention relate to techniques for fault diagnosis based on dynamic circuit design partitioning. According to various implementations of the invention, a sub-circuit is extracted from a circuit design based on failure information of one or more integrated circuit devices. The extraction process may comprise combining fan-in cones of failing observation points included in the failure information. The extraction process may further comprise adding fan-in cones of one or more passing observation points to the combined fan-in cones of the failing observation points. Clock information of test patterns and/or layout information of the circuit design may be extracted and used in the sub-circuit extraction process. The extracted sub-circuit may then be used for diagnosing the one or more integrated circuit devices. | 06-06-2013 |
20130159774 | DYNAMIC REPRIORITIZATION OF TEST CASES DURING TEST EXECUTION - Systems and methods are described that dynamically reprioritize test cases for Model-Based Testing (MBT) during test execution. Test case execution is prioritized according to their potential to detect uncovered failures within a design model. | 06-20-2013 |
20130173963 | DYNAMIC TESTING OF NETWORKS - Service providers strive to maintain networks with high levels of availability and performance. To maintain the networks, the service providers measure performance and perform network diagnostics. Measuring performance and performing network diagnostics typically involves manual verification of functionality or performing individual tests between user agents. Service providers who maintain networks and service providers who use networks can dynamically run tests with operations of a signaling protocol (e.g., session initiation protocol) to diagnose network problems and determine appropriate responses. An agent manager can coordinate the dynamic tests across multiple user agents to gather more information to increase problem diagnosis accuracy. | 07-04-2013 |
20130173964 | METHOD OF MANAGING FAILURE, SYSTEM FOR MANAGING FAILURE, FAILURE MANAGEMENT DEVICE, AND COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN FAILURE REPRODUCING PROGRAM - A failure management device includes a stored position obtainer that obtains stored position data that represents a position at which failure data is generated by an information processing apparatus when a failure is occurring; a failure data obtainer that obtains the failure data generated by the information processing apparatus from a memory device, communicably connected to the information processing apparatus and the failure management device, on the basis of the stored position data; and a configuration controller that changes, on the basis of the failure data obtained by the failure data obtainer, a configuration of the failure management device so as to conform to that of the information processing apparatus. This configuration makes it possible to easily reproduce the failure occurred in the information processing apparatus and consequently, a reproducing test can be accomplished efficiently. | 07-04-2013 |
20130198570 | COMMUNICATION SYSTEM AND GENERATING APPARATUS - A communication system includes a switch that switches output ports according to an address of transmission data; a storing unit that stores a first set of addresses associated with the switch; a determining unit that determines, when a second set of addresses including in the transmission data a response to which is not received matches the first set of addresses in the storing unit, that there is a failure in the switch associated with the first set of addresses. | 08-01-2013 |
20130246852 | TEST METHOD, TEST APPARATUS, AND RECORDING MEDIUM - A test method which tests a processing device includes: obtaining a maximum number of processing units with which the processing device as a test target can simultaneously parallel process a plurality of threads; specifying a number of threads, causing the processing device as the test target to parallel process the threads, and obtaining a processing time corresponding to the number of threads; and outputting information indicating that the processing device as the test target is normal when the number of threads for which the processing time is more than or equal to a threshold matches the maximum number of processing units which can simultaneously parallel process, or outputting information indicating that the processing device as the test target is abnormal when the number of threads does not match. | 09-19-2013 |
20130326275 | HARDWARE PLATFORM VALIDATION - A system for validating a hardware platform is provided. The system includes a database that stores one or more test specifications, a compiler that generates a target image based on (i) a device driver obtained from a device driver generator, (ii) a platform independent target application code, (iii) a kernel source, and (iv) a run time environment, and a software driven validation generator that analyses the run time specification and the device programming specification and generates (i) one or more test cases based on (a) the one or more test specifications, and (b) the device programming specification, and (ii) a control software based on the test cases. The test cases include configurations that are specific to the hardware platform. The hardware platform is validated based on (i) an execution of the target image and the control software on the hardware platform, and (ii) the one or more test cases. | 12-05-2013 |
20140006867 | Test Executive System With Process Model Plug-ins | 01-02-2014 |
20140006868 | Test Executive System With Offline Results Processing | 01-02-2014 |
20140013162 | INFORMATION PROCESSING APPARATUS, TRANSMITTING DEVICE AND CONTROL METHOD OF INFORMATION PROCESSING APPARATUS - A transmission device has a first input unit that inputs data, a second input unit that inputs data, a first information processing unit that outputs data resulting from information processing of data input by the first input unit or data input by the second input unit, a first holding unit that holds data output by the first information processing unit, a second holding unit that holds data output by the first information processing unit, a control information holding unit that holds control information, a first selection unit that selects, on the basis of the control information, either the data held by the first holding unit or the data held by the second holding unit, and a first output unit that returns data selected by the first selection unit to the first input unit, on the basis of the control information. | 01-09-2014 |
20140019806 | CLASSIFYING PROCESSOR TESTCASES - Embodiments of a testcase checker system are disclosed herein. Embodiments of a testcase checker system may include an instruction set simulator configured to simulate execution of instructions of a testcase on a microprocessor using a reference model associated with an architecture of the microprocessor. The instruction set simulator may generate logging data associated with the each instruction based on the simulated execution of that instruction. The testcase checker system may also include checker module comprising a set of rules. Each of these rules may be associated with a boundedly undefined condition. The checker module is configured to receive the logging data associated with an instruction from the instruction set simulator and process the logging data based on the rules to determine if any of the rules are violated. | 01-16-2014 |
20140025994 | SYSTEM AND METHOD FOR GRAMMAR BASED TEST PLANNING - The present disclosure generally relates to the testing of a system that includes software or hardware components. In some embodiments, a testing framework generates a set of test cases for a system under test using a grammar. Each test case may perform an action, such as provide an input to the system under test, and result in an output from the system under test. The inputs and outputs are then compared to the expected results to determine whether the system under test is performing correctly. Prior to generating the set of test cases from the grammar, the testing framework processes the grammar to identify attributes of the test cases to be derived from the grammar and facilitates the modification of the grammar. | 01-23-2014 |
20140032969 | Post-silicon validation using a partial reference model - Method, system and product for post silicon validation using a partial reference model. The method performed by a device having registers, the method comprising: first executing, by the device when operating in trace mode, a test-case, wherein during the execution utilizing a partial reference model to determine an expected value of at least one register; second executing, by the device when operating in non-trace mode, the test-case; and in response to said second executing, checking values of registers based on, at least in part, values determined during said first execution. | 01-30-2014 |
20140059385 | COMPLIANCE TESTING ENGINE FOR INTEGRATED COMPUTING SYSTEM - A technique tests whether an integrated computing system having server, network and storage components complies with a configuration benchmark expressed as rules in first markup-language statements such as XML. The rules are parsed to obtain test definition identifiers identifying test definitions in a second set of markup-language statements, each test definition including a test value and an attribute identifier of system component attribute. A management database is organized as an integrated object model of all system components. An interpreter invoked with the test definition identifier from each rule process each test definition to (a) access the management database using the attribute identifier obtain the actual value for the corresponding attribute, and (b) compare the actual value to the test value of the test definition to generate a comparison result value that can be stored or communicated as a compliance indicator to a human or machine user. | 02-27-2014 |
20140059386 | REAL-TIME RULE ENGINE FOR ADAPTIVE TESTING OF INTEGRATED CIRCUITS - A method of testing a device is disclosed. Test data is obtained for a device testing program that tests the device. An adaptation command for testing the device is determined at an adaptive testing engine using obtained test data. The adaptation command is sent from the adaptive testing engine to a tool control application. The tool control application uses the adaptation command to control an operation related to the testing of the device. | 02-27-2014 |
20140059387 | MANAGEMENT OF TEST ARTIFACTS USING CASCADING SNAPSHOT MECHANISM - Described are an apparatus and method for managing test artifacts. A test plan is selected for a product having a plurality of test artifacts comprising one selected from a group consisting of an execution record and a product requirement. One of the test artifacts is selected for a snapshot at a current time. The snapshot includes a storage record that includes information associated with the selected test artifact and its relationship with other test artifacts at the current time. The snapshot of the selected test artifact is acquired. A current state of the selected test artifact is stored as an element of the snapshot. A current state of relationships of the selected test artifact to the other test artifacts is stored. A current state of the other test artifacts having a relationship with the selected test artifact is stored. A type of snapshot is determined, comprising cascading through artifacts of the test plan to capture all information and relationships associated with the test artifact, its child artifacts, and the group consisting of the execution record and the product requirement. | 02-27-2014 |
20140082420 | AUTOMATED PROGRAM TESTING TO FACILITATE RECREATION OF TEST FAILURE - Automated program testing is facilitated. Test results generated based on performance of one or more tests by a program are obtained, where a test passes or fails based on output obtained based on performance of the test by the program. A failure output of the test results is identified, the failure output being of a failing test that includes at least one command, and the failure output being obtained based on performing the at least one command. A modified test is automatically generated based on the failing test, where the modified test is provided for performance thereof by the program to facilitate testing of the program. The modified test includes the at least one command of the failing test, and the modified test passes based on obtaining the identified failure output of the failing test. | 03-20-2014 |
20140095935 | SIMULATION BASED FAULT DIAGNOSIS USING EXTENDED HEAT FLOW MODELS - In order to reduce computation time and cost involved with detecting and diagnosing a fault in a system, simplified representations of components of the system are used to estimate valid intervals for state variables at the components. Generic failure rules are configured to compare the estimated valid intervals to related intervals for the same state variables, from either observations or propagations, for overlap. Failure output vectors are generated based on the comparison, and the failure output vectors are compared to diagnostic matrices to determine a source of the fault. | 04-03-2014 |
20140101486 | SICHERHEITSSYSTEM - Multiple safety related participants are arranged along a bus line in such a way that both a forward test signal path and a return test signal path run through the same safety related participants and the safety related participants are adapted in such a way that the occurrence of a non-secure state of their protective device brings about an interruption of the test signal path. A termination element connects the forward test signal path to the return test signal path. The safety unit is configured to transmit an output signal at its output and the termination element is configured to receive the output signal from the forward test signal path and to output a test signal to the return test signal path. The test signal is changed with respect to the received output signal in dependence on the received output signal. | 04-10-2014 |
20140115396 | Mutations on input for test generation - A method, apparatus and product to be used in verification. The method comprising: based on a test generation input that defines a plurality of requirements automatically determining a mutated test generation input, wherein the mutated test generation input defining a mutated requirement which is absent from the test generation input, wherein the mutated requirement is based on a requirement of the plurality of requirements and contradicts, at least in part, the plurality of requirements; and generating one or more test-cases based on the mutated test generation input, whereby the one or more test-cases violate at least one requirement of the test generation input. | 04-24-2014 |
20140136897 | DATA VERIFICATION - A data verification application receives a test configuration data, the test configuration data comprising a seed value and a parameter. The data verification application generates a pseudo-random test data stream comprising a plurality of words, wherein a value of each of the plurality of words is based on the seed value, the parameter and an offset of each word within the pseudo-random test data stream. | 05-15-2014 |
20140143599 | TEST PROGRAM GENERATOR USING KEY ENUMERATION AND STRING REPLACEMENT - A system and method are provided for test program generation using key enumeration and string replacement. A system includes a test program generator and a tester. The tester receives a test program from the test program generator and tests one or more products according to the test program. The test program generator receives a seed file from a seed file database and a configuration file from a configuration file database. The test program generator iterates over enumeration keys in the configuration file and, for each key, apply to the seed file one or more rules in the configuration file keyed to the enumeration key. Applying a rule includes replacing in the seed file one or more occurrences of a predicate value of the rule with a transformation value of the rule. The test program generator also outputs to the tester the modified first seed file as the test program. | 05-22-2014 |
20140157054 | MEMORY ERROR IDENTIFICATION BASED ON CORRUPTED SYMBOL PATTERNS - A system includes a memory controller, a buffer, a first channel to couple the memory controller to the buffer, and a second channel to couple the buffer to a memory. The first channel and second channel are to transmit a codeword including a plurality of symbols. A symbol is formed from a plurality of bursts based on data access of the memory. The memory controller is to identify a memory error based on a corrupted symbol pattern of the codeword. The memory controller is to discriminate between a chip failure, a first pin failure of the first channel, and a second pin failure of the second channel, as being a type of the memory error, according to the corrupted symbol pattern. | 06-05-2014 |
20140157055 | MEMORY SUBSYSTEM COMMAND BUS STRESS TESTING - A memory subsystem includes logic buffer coupled to a command bus between a memory controller and a memory device. The logic buffer detects that the memory controller places the command bus in a state where the memory controller does not drive the command bus with a valid executable memory device command. In response to detecting the state of the command bus, the logic buffer generates a signal pattern and injects the signal pattern on the command bus after a scheduler of the memory controller to drive the command bus with the signal pattern. | 06-05-2014 |
20140164835 | SYSTEMS AND METHODS FOR ERROR SIMULATION AND CODE TESTING - A method for error simulation in a data storage subsystem providing abstractions of one or more storage devices. The method includes dividing the data storage subsystem into two or more hierarchically organized subsystems, wherein the subsystems interact using IO Request Packets (IORPs), such that relatively higher level subsystems create and populate IORPs and pass them to relatively lower level subsystems for corresponding processing. The method further includes defining an IORP modifier configured to attach to matching IORPs based on one or more attributes of the IORP modifier and to modify at least one of the processing and one or more attributes of the IORP in order to simulate errors in the data storage subsystem. | 06-12-2014 |
20140195852 | MEMORY TESTING OF THREE DIMENSIONAL (3D) STACKED MEMORY - A method includes reading, at a memory controller, data from a first dynamic random-access memory (DRAM) die layer of a DRAM stack. The method also includes writing the data to a second DRAM die layer of the DRAM stack. The method further includes sending a request to a test engine to test the first DRAM die layer after writing the data to the second DRAM die layer. | 07-10-2014 |
20140195853 | CLOUD MANAGEMENT USING A COMPONENT HEALTH MODEL - Embodiments are directed to establishing a model for testing cloud components and to preventing cascading failures in cloud components. In one scenario, a computer system models identified cloud components (including cloud hardware components and/or cloud software components) as health entities. Each health entity is configured to provide state information about the cloud component. The computer system establishes declarative safety conditions which declaratively describe cloud computing conditions that are to be maintained at the identified cloud components. The computer system then tests against the declarative safety conditions to determine which cloud components are or are becoming problematic. Upon determining that an error has occurred, the computer system notifies users of the error and the component at which the error occurred. Guarded interfaces are established to ensure that actions taken to fix the error do not cause further failures. | 07-10-2014 |
20140223237 | SYSTEMS AND METHODS FOR DYNAMIC SCAN SCHEDULING - A system and method for dynamically modifying scheduling of scan operations for a system under test includes a processing module configured to apply input test data to the system under test based on the scan operations via a test access port and a scheduler adapted to provide the processing module with scheduling for the plurality of scan operations. The scheduler includes a circuit model of the system under test. The circuit model includes at least one attribute providing enhancing information for at least a portion of the system under test. The scheduler is adapted to schedule the scan operations based on the circuit model and to modify the schedule based on the at least one attribute. The processing module is configured to receive the modified scheduled scan operations and to apply the input test data to the system under test based on the modified scheduled scan operations. | 08-07-2014 |
20140258782 | RECOVERY MATURITY MODEL (RMM) FOR READINESS-BASED CONTROL OF DISASTER RECOVERY TESTING - A Recovery Maturity Model (RMM) is used to determine whether a particular Information Technology (IT) production environment can be expected, with some level of confidence, to successfully execute a test for disaster recovery (DR). The RMM provides a quantitative analysis in terms of the extent to which best practices are seen to have been implemented as a set of categories for elements of the environment and multiple elements for each category. A summation of the scoring elements, which may be a weighted summation, results in an overall quantitative metric which is then used to control whether or not testing will proceed. | 09-11-2014 |
20140281720 | SYSTEM AND METHOD OF PERFORMING A HEALTH CHECK ON A PROCESS INTEGRATION COMPONENT - In an example embodiment, a method of performing a health check on a process integration (PI) component is provided. A PI health check scenario is loaded into the PI component, the PI health check scenario including a reference to a list of checks. The PI health check scenario is then executed using the PI component, causing one or more checks in the list of checks to be performed at a predetermined frequency. The system can then automatically determine if one or more of the one or more checks fail. | 09-18-2014 |
20140281721 | AUTOMATIC GENERATION OF TEST SCRIPTS - Systems and methods for automatically generating test scripts are described. The systems and methods may access information from a template that includes at least one entry associated with a test case to be applied to a system under testing, apply a translation scheme to the accessed information, and generate a test script in a language that is associated with the translation scheme and that is based on the information accessed from the template. The systems and methods may then utilize the test script to test the functionality of a system under testing, among other things. | 09-18-2014 |
20140298095 | MEDICAL TEST SIGNAL GENERATOR AND INTERFACE - A cardiac signal generator includes a first circuit, a user input device, an output display, and a processing circuit. The first circuit provides, according to any of predetermined plurality of settings, cardiac signals comprising a repeating cardiac waveform, and respiratory signals comprising a repeated respiratory waveform. The output display includes a plurality of indicators, each indicator corresponding to one of the plurality of settings. Each setting includes a combination of a frequency of repetition of the cardiac waveform and a frequency of repetition of the respiratory waveform. The processing circuit causes the first circuit to provide cardiac and respiratory signals according to a selected one of the plurality of settings. The processing circuit is further configured to receive a signal from the user input device, and change the selected setting from a first setting of the plurality of settings to a second setting of the plurality of settings responsive thereto. | 10-02-2014 |
20140298096 | LOW POWER TEST SIGNAL GENERATOR FOR MEDICAL EQUIPMENT - A cardiac signal generator includes a portable housing, a memory, a processing device, a digital to analog converter, and at least one analog output. The memory stores programming instructions including instructions defining a plurality of mathematical relationships. The processing device is configured to execute said programming instructions to generate a sequence of output values using the plurality of mathematic relationships as a function of time, wherein said sequence of output values defines a sampled waveform output simulating an ECG signal and having linear portions and at least one curved portion. The processing device furthermore provides the sequence of output values at an output. The digital to analog converter is operably coupled to receive the sequence of output values from the output, and generates an electrical signal having a waveform corresponding to the sampled waveform output. The analog output is operably coupled to the digital to analog converter. | 10-02-2014 |
20140325278 | METHOD AND SYSTEM FOR INTERACTIVE AND AUTOMATED TESTING BETWEEN DEPLOYED AND TEST ENVIRONMENTS - An approach for interactive automated testing and deployment/field troubleshooting includes extracting one or more field parameters associated with a deployed network resource management environment; determining and/or updating one or more test parameters associated with a test network resource management environment based on the one or more field parameters; inputting the determined and/or updated test parameters within the test network resource management environment to evaluate the one or more test parameters; and modifying a configuration of at least one of the deployed network resource management environment and the test network resource management environment based on the one or more evaluated test parameters. | 10-30-2014 |
20140359361 | TEST SYSTEM - A server stores multiple configuration data which respectively provide different functions to a test system. A tester hardware is configured to be capable of changing at least a part of its functions according to the configuration data stored in nonvolatile memory included in the tester hardware. A control program is installed on an information processing apparatus. The control program provides the information processing apparatus with (i) a function of displaying multiple configuration data candidates on a display when the test system is set up, and (ii) a function of writing the configuration data selected by the user to the nonvolatile memory of the tester hardware. | 12-04-2014 |
20140359362 | INFORMATION INTERACTION TEST DEVICE AND METHOD BASED ON AUTOMATIC GENERATION OF ASSOCIATED TEST CASES - The present invention proposes an information interaction testing device and method based on the associated testing case automatic generation. The associated testing case generation module in said device may automatically generate the associated testing case files corresponding to all associated information interactions which can be triggered by said reference information interaction based on the reference information interaction and the predefined rules determined by the application type provided by the system under test. The information interaction testing device and method based on the associated testing case automatic generation disclosed in the present invention have the higher testing speed and the higher testing usability as well as are low-cost. | 12-04-2014 |
20150052398 | Out-of-Band Signaling Support Over Standard Optical SFP - An out-of-band to optical conversion component is provided that uses a transmit disable signal and a receive loss of signal (LOS) signal built into optical small form-factor pluggable transceiver and cable to pass the out-of-band protocol between serial attached. SCSI enclosures. The transmit disable signal, when asserted, turns off the optical output, while the receive LOS signal detects the loss of signal. The out-of-band to optical conversion component sits in line on the serial attached SCSI data traffic and strips off the out-of-band signals from the serial attached SCSI expander so that only data flows over the optical cable. The out-of-band to optical conversion component sends the out-of-band signals to the other enclosure using the transmit disable pin on the small form-factor pluggable transceiver and cable. The other enclosure receives the message on the receive LOS signal and transmit it back onto the serial attached SCSI receive data pair. | 02-19-2015 |
20150058672 | SYSTEM AND METHOD FOR GRAMMAR BASED TEST PLANNING - The present disclosure generally relates to the testing of a system that includes software or hardware components. In some embodiments, a testing framework generates a set of test cases for a system under test using a grammar. Each test case may perform an action, such as provide an input to the system under test, and result in an output from the system under test. The inputs and outputs are then compared to the expected results to determine whether the system under test is performing correctly. Prior to generating the set of test cases from the grammar, the testing framework processes the grammar to identify attributes of the test cases to be derived from the grammar and facilitates the modification of the grammar. | 02-26-2015 |
20150058673 | TESTING DEVELOPMENT USING REAL-TIME TRAFFIC - Testing a test component is disclosed. A real-time input communication that has been forked from an input communication intended for a deployed component is received at the test component. At least a portion of the received real-time input communication is processed. A result of the processing is used to at least in part determine a test result of the test component. | 02-26-2015 |
20150082095 | AUTOMATED OPERATING SYSTEM TEST FRAMEWORK - Techniques for automating testing of a first computing system comprises identifying a plurality of system interface elements of a second computing system; determining an untested state at the first computing system of one of the identified plurality of system interface elements; determining the existence of any dependency of the one of the identified plurality of system interface elements upon another of the identified plurality of system interface elements; responsive to a finding of no the dependency, seeking in a repository a system interface element test corresponding to the one of the identified plurality of system interface elements and having an expected output according to a structure of the second computing system; and executing the system interface element test at the first computing system. | 03-19-2015 |
20150089291 | METHOD FOR DETECTING FAILURE AND SLAVE STATION FOR USE IN SAME - A transmission signal transmitted via a common data signal line, includes a management data region different from a control/monitoring data region including data of control data and monitoring data signals. The slave station acquires input information from an input part corresponding to its own station, acquires control data for reference by an output part of another station in a correspondence relation with the input part from the transmission signal, and obtains a pseudo output change timing equal to a true output change timing of the output part based on the control data. A signal configuring data indicating a first failure state when a time difference between the pseudo output change timing and an input change timing of the input part is smaller than a first threshold value or a second failure state when the time difference is larger than a second threshold value is superimposed on the management data region. | 03-26-2015 |
20150089292 | VIRTUAL MACHINE TEST SYSTEM, VIRTUAL MACHINE TEST METHOD - An objective of the present invention is to efficiently perform a platform level test on a computer system comprising virtual machines that are automatically built according to predefined templates. A virtual machine test system according to the present invention creates a virtual machine according to a system template defining a combination of a network topology type of virtual machines and a role of each of the virtual machines, and performs a platform level test according to a test item defined for each of the combination (refer to FIG. | 03-26-2015 |
20150106654 | METHOD AND SYSTEM FOR NON-INTRUSIVE MONITORING OF LIBRARY COMPONENTS - Embodiments of the present invention provide a method for monitoring components in a library by tracking the movement of library components. By tracking the movement of library components, the degradation of library components can be monitored and the reliability of library components determined, allowing unreliable components to be bypassed or replaced, enhancing the reliability of the library and preventing data loss. | 04-16-2015 |
20150121140 | TESTING A CONTROL UNIT BY MEANS OF A TEST ENVIRONMENT - An arrangement for testing a control unit via a test environment, having a computer-based test management tool, wherein the test management tool is configured for model-based development and/or management of at least one test plan implemented as a data structure in order to test the control unit, and the test plan has at least one test and a start condition for initiating execution of the test plan; a computer-based test execution control tool, wherein the test execution control tool is configured to initiate execution of the test plan on the test environment when the start condition is met; and a computer-based database, wherein the database is configured to store the test plan implemented as a data structure and is also configured for shared, common access to the test plan by the test management tool and the test execution control tool. | 04-30-2015 |
20150127984 | Tightly-Coupled Context-Aware Irritator Thread Creation for Verification of Microprocessors - A mechanism is provided for context-aware irritation of a micro-processor. At each executed phase in a set of phases of a test case being executed on a set of micro-processors, a determination is made of a set of characteristics associated with the given executed phase of the test case. Based on the set of determined set of characteristics associated with the given executed phase, a determination is made of an irritation to be executed alongside the given executed phase of the test case. The determined irritation is then executed alongside the given executed phase of the test case. | 05-07-2015 |
20150127985 | INFORMATION PROCESSING APPARATUS AND ACCESS CONTROL METHOD - A detection unit detects access status of an information recording device and forms the detected access status into access records at predetermined time intervals. A generation unit generates history information from the access records that have been formed over a predetermined period. A control unit selects an access record that has a predetermined relationship with the current time, out of the history information. A control unit determines when to start a diagnosis of the information recording device, assuming that the selected access record represents the current access status of the device. Specifically, the control unit instructs a diagnosis unit to start a diagnosis when the selected access record suggests that the diagnosis would not impose an excessive load on the information recording device. | 05-07-2015 |
20150127986 | TEST PROGRAM AND TEST SYSTEM - A test program allows an information technology equipment connected to a tester hardware to control the tester hardware. The tester hardware is configured to be capable of changing at least a part of its functions according to configuration data stored in rewritable nonvolatile memory. The test program is configured as a combination of a control program and a test algorithm module. The test program comprises: a module that acquires the configuration data from the nonvolatile memory of the tester hardware and a module that judges whether or not a storage device holds a test algorithm module that can be used together with the configuration data. | 05-07-2015 |
20150135015 | CLOUD AUTO-TEST SYSTEM, METHOD AND NON-TRANSITORY COMPUTER READABLE STORAGE MEDIUM OF THE SAME - A cloud auto-test method used in a cloud auto-test system including a processing module is provided. The cloud auto-test method includes the steps outlined below. A test management virtual machine is constructed by the processing module. An under-test object is read to monitor and update the version of the under-test object. At least one test flow including at least one test item is established and managed. A test operation virtual machine is constructed such that the under-test object having the latest version is loaded to the test operation virtual machine. An auto-test process is performed on the under-test object in the test operation virtual machine according to the test flow. A result of the test process analyzed. | 05-14-2015 |
20150293828 | TESTING APPARATUS, TESTING SYSTEM AND TESTING METHOD THEREOF - A testing apparatus, a testing system and a testing method thereof are provided. The testing apparatus is used to test at least one electronic apparatus. The testing apparatus includes a testing data transceiver and a processor. The testing data transceiver is coupled to functional circuits of the at least one electronic apparatus through connection interfaces and transports several testing data correspondingly to the functional circuits for testing the functional circuits to obtain several corresponding data. The processor receives the corresponding data and determines a product group of the at least one electronic apparatus according to the corresponding data. | 10-15-2015 |
20150309906 | SYSTEM AND METHODS FOR AUTOMATED TESTING OF FUNCTIONALLY COMPLEX SYSTEMS - A system for automated testing of functionally complex systems prior to placing them into production, comprising a test manager module operating on a server computer, a test data storage subsystem coupled to the test manager module and adapted to store at least test results, a test execution module operating on a server computer, and a test analysis module operating on a server computer and adapted to receive test data from the test data storage subsystem. The test manager module causes tests to be executed by the test execution engine, and on detection of an anomalous test result, the test manager module at least causes additional testing to be performed and causes the test analysis module to analyze the results of at least some of the additional testing in order to isolate at least one component exhibiting anomalous behavior. | 10-29-2015 |
20150331733 | TAG BASED SELECTION OF TEST SCRIPTS FOR FAILURE ANALYSIS - A service system can include numerous test scripts that are candidates for execution against a failure message to determine a solution for a failure in a distributed storage system. To efficiently ascertain a solution for a failure with the test scripts, a service system can analyze the failure message to determine tags and use the tags to guide selection of test scripts. The selected test scripts are then executed to analyze the failure message, and to generate, based on the analysis, a solution corresponding to the failure. Instead of executing the numerous test scripts against the failure message, only selected test scripts are executed against the failure message to generate a solution. The solution is then communicated to the distributed storage system. | 11-19-2015 |
20150331734 | DIAGNOSTIC TESTING BASED ON INFORMATION HANDLING SYSTEM VARIABLES - Methods and systems for performing diagnostic testing based on information handling system variables include receiving a first indication specifying diagnostic tests to be performed on an information handling system, receiving a second indication specifying diagnostic test conditions respectively associated with the diagnostic tests, receiving a third indication specifying health condition severity of the information handling system, and receiving a fourth indication specifying a user profile including user usage patterns. Based on the first indication, the second indication, the third indication, and the fourth indication, a schedule for executing diagnostic tests is generated. | 11-19-2015 |
20150331770 | EXTRACTING TEST MODEL FROM TEXTUAL TEST SUITE - Computer-implemented method, computerized apparatus and computer program product for extracting test model from a textual test suite. The method comprises obtaining a test suite comprising test descriptions. The test descriptions are analyzed to extract attributes and values of a test model modeling a test space. Using the extracted attributes and values, the test model may be created. In some cases, the test model may be partial test model that a user can use as a starting point for manually modeling the textual test suite. | 11-19-2015 |
20150347215 | DETECTION OF DATA CONNECTION LOSS - A method of detecting loss of data connection in a plurality of links between an exchange and one or more of a plurality of network terminals arising during presence of a user at an intervention point node on the links between the exchange and the network terminals, comprising: receiving connection information about a loss of data connection on any one of the links; receiving duration information about a duration of the user presence at the intervention point node; determining if the loss of data connection occurred within the user presence duration; causing line tests to be conducted on each of the links for which loss of data connection is determined to have occurred within the user presence duration; receiving results of the line tests including a number of links being determined, by the line test, to exhibit a fault; and determining if the number of links determined to exhibit a fault exceeds a predetermined threshold number. | 12-03-2015 |
20150347257 | NON-INTRUSIVE MONITORING AND CONTROL OF INTEGRATED CIRCUITS - A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an incremental second set of configuration data based on the definition of the event and the set of corresponding actions. While the first IC is performing the operations of the user design, the method loads the incremental second set of configuration data into the first IC and monitors the signals received from the second IC at the first IC. | 12-03-2015 |
20150370675 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR UTILIZING ABSTRACTED USER-DEFINED DATA TO CONDUCT NETWORK PROTOCOL TESTING - Methods, systems and computer readable media for utilizing abstracted user-defined data to conduct network protocol testing are disclosed. According to one aspect, the subject matter described herein comprises a method that includes receiving, by a test system abstraction (TSA) module from a device under test (DUT), a packet containing a command that is associated with a native protocol and converting the command included in the received packet into a TSA protocol command. The method further includes processing the TSA protocol command at a TSA engine module that is provisioned with at least one instruction sequence enabling the TSA engine module to emulate a network test device and generating, by the TSA engine module, a TSA protocol command response in accordance with protocol behavior specified by the at least one instruction sequence. | 12-24-2015 |
20150370676 | System for Generating a Test Pattern to Detect and Isolate Stuck Faults for an Interface Using Transition Coding - Conventional methods using signal test patterns to identify wiring errors are difficult to apply to interfaces encoding information as signal state transitions rather than directly as signal states. A system utilizing excitation of wires with selected transition coded patterns and evaluation of received results is described to identify failed wire connections. This approach may be advantageously used to provide fault detection and redundant path selection in systems incorporating stacked chip interconnections using Through Silicon Vias. | 12-24-2015 |
20160004583 | SYSTEM FOR PROJECT MANAGEMENT FROM NON-FUNCTION EVALUATION, METHOD FOR PROJECT MANAGEMENT FROM NON-FUNCTION EVALUATION, AND PROGRAM FOR PROJECT MANAGEMENT FROM NON-FUNCTION EVALUATION - Provided is a progress management technique for a project, the technique also covering a non-functional requirement of the project. A parameter required for evaluating the non-functional requirement is adjusted according to the progress of the project, and calculation is made, using the adjusted parameter, on to which extent the non-functional requirement may finally differ from a target value. | 01-07-2016 |
20160011953 | Integrated Circuit Including a Programmable Logic Analyzer with Enhanced Analyzing and Debugging Capabilities and a Method Therefor | 01-14-2016 |
20160014238 | System and Method for Testing Applications with a Load Tester and Testing Translator | 01-14-2016 |
20160034372 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR SCALING A WORKLOAD - Methods, systems, and computer readable media for scaling a workload are disclosed. According to one exemplary method, the method occurs at a network equipment test device. The method includes generating a first workload comprising a plurality of messages associated with one or more transactions. The method also includes determining one or more workload segments in the first workload, wherein each of the one or more workload segments represents one or more messages associated with a particular transaction and generating a second workload using the one or more workload segments, wherein the second workload includes a number of the workload segments based on a workload scale attribute. | 02-04-2016 |
20160041859 | SYNCHRONIZATION TESTING OF ACTIVE CLUSTERED SERVERS - In a computing device that performs synchronization testing of a plurality of active clustered servers, a request to check synchronization between slave data stored and master data is received. The request includes master synchronization test values computed by a master node that include a number of records included in a dataset and a sum of modification time values for the records. Slave synchronization test values are computed that include a number of records included in the dataset of the slave data and a sum of modification time values for the records in the dataset of the slave data. The computed slave synchronization test values are compared to the master synchronization test values. A message is sent to the requesting device indicating the slave node is synchronized when the computed synchronization test values match or indicating the slave node is not synchronized when the computed synchronization test values do not match. | 02-11-2016 |
20160048437 | MULTIPLE TEST TYPE ANALYSIS FOR A TEST CASE USING TEST CASE METADATA - In one embodiment, a method determines a test case containing test code for testing a functionality of a computer system. The test case is associated with metadata. The metadata is parsed to determine a plurality of system test types and one or more parameters for the plurality of system test types wherein the one or more parameters indicate system conditions for the computer system. The method executes a set of tests using the test code with the computer system using the system conditions. Results of the executed set of tests are output for the plurality of system test types. | 02-18-2016 |
20160048438 | AUTOMATED TESTING OF PHYSICAL SERVERS USING A VIRTUAL MACHINE - An illustrative method for validating integrity of a source server backup includes receiving, at a recovery server, data indicating a state of a data storage unit associated with a source server, creating a virtual hard drive image from the received data, and storing, in memory of the recovery server, the created virtual hard drive image. The method also includes booting a virtual machine using the stored hard drive image and mounting a second drive image to the virtual machine including tools facilitating access to an operating system running on the virtual machine by an application running on the recovery server. The tools are prevented from being installed in an operating system running on the source server. The method further includes automatically detecting, by a recovery application running on the virtual machine, that the drive includes the tools, automatically installing, by the recovery application and without user intervention, the tools in the operating system running on the virtual machine, and controlling, by the application running on the recovery server, applications running on the virtual machine. | 02-18-2016 |
20160062862 | DATA PROCESSING SYSTEM WITH DEBUG CONTROL - A data processing system includes a processor configured to execute processor instructions and a memory. The memory has a data array and a checkbit array wherein each entry of the checkbit array includes a plurality of checkbits and corresponds to a storage location of the data array. The system includes error detection/correction logic configured to, during normal operation, detect an error in data access from a storage location of the data array using the plurality of checkbits in the entry corresponding to the storage location. The system further includes debug logic configured to, during debug mode, use a portion of the plurality of the checkbits in the entry corresponding to the storage location to generate a breakpoint/watchpoint request for the processor. | 03-03-2016 |
20160070630 | DEBUGGING IN A DATA PROCESSING APPARATUS - A data processing apparatus has a debug state in which processing circuitry | 03-10-2016 |
20160077906 | HIGH VOLTAGE FAILURE RECOVERY FOR EMULATED ELECTRICALLY ERASABLE (EEE) MEMORY SYSTEM - The present disclosure provides methods and circuits for managing failing sectors in a non-volatile memory. A record address and a read control signal are received, where the record address identifies a location in the non-volatile memory. The record address is compared with a plurality of dead sector addresses, where the dead sector addresses correspond to a subset of sectors located in the non-volatile memory. Data located at the record address is determined to be invalid in response to a combination of a first detection that the record address matches one of the dead sector addresses and a second detection that the read control signal indicates a read operation is requested to be performed on the non-volatile memory. | 03-17-2016 |
20160077944 | SYSTEMS AND METHODS OF BUILDING SEQUENCEABLE TEST METHODOLOGIES - Networks and applications can have many different profiles. Template configurations can consist of a wide variety of technologies such as IPv4, DHCP, and BGP. A list of application profiles would include web services, VoIP, Email, and Point-to-point. Network and application profiles can be combined into topology templates. Test methodologies can include complex sets of instructions that allow for testing any number of topology templates in a number of ways. The technology disclosed allows for the assembly, edit, and execution of those profiles and methodologies by someone who does not possess detailed domain knowledge. | 03-17-2016 |
20160085610 | AUTOMATED NETWORK INFRASTRUCTURE TEST AND DIAGNOSTIC SYSTEM AND METHOD THEREFOR - A testing system provides automated testing of one or more network infrastructures. The testing system may automatically reconfigure one or more devices within a network infrastructure and then conduct testing on the newly configured network infrastructure. Test results may be used to diagnose network anomalies and to compare performance or other characteristics of various network configurations. In one embodiment, the testing system tests a communication channel between a front-end and back-end mechanism where data traffic is encoded between the front-end and back-end mechanism. | 03-24-2016 |
20160092327 | DEBUGGING SYSTEM AND DEBUGGING METHOD OF MULTI-CORE PROCESSOR - The invention relates to a debugging system and a debugging method of a multi-core processor. The debugging system includes a debugging host, a target processor, and a mapping and protocol conversion device. The debugging host includes a debugger, and the target processor includes a plurality of cores. The mapping and protocol conversion device is connected between the debugging host and the target processor, identifies a core architecture to which each of the cores belongs, and maps each of the cores respectively to at least one thread of at least one process according to the core architecture to which each of the cores belongs. Afterwards, the debugger executes a debugging procedure on the target processor according to the process and the thread corresponded to each of the cores. | 03-31-2016 |
20160092328 | MEMORY DEVICE TEST APPARATUS AND METHOD - Disclosed herein are a method and an apparatus for shortening a data comparison test time by using peer-to-peer transfers between peripheral component interconnect express (PCIe) endpoints when testing solid state drive (SSD) devices. A memory device test apparatus performing a data comparison test of a memory device mounted in a downstream port of a peripheral component interconnect express (PCIe) switch by performing a writing process and a reading-back process by a control of a host central processing unit (CPU) includes: a comparison test unit (FPGA) connected to the downstream port of the PCIe switch, performing peer-to-peer communication with the memory device to supply write data to the memory device and receive read-back data from the memory device, and performing the data comparison test. | 03-31-2016 |
20160092329 | Final Result Checking For System With Pre-Verified Cores - Provided are a system and method for generating final result checking for a test case. A test case is executed for a coherent memory system having a processor core. An event log is generated for the processor core. The event log is analyzed. The test case for the core is annotated with a checker for performing expected data checking for physical addresses modified by the processor core. | 03-31-2016 |
20160092330 | DEVICE, METHOD AND PROGRAM FOR PERFORMING SYSTEM TESTING - In an approach for testing the operations of a host system during a host system migration, a terminal agent exchanges messages already exchanged between the current host system and a terminal with the new host system. A manual operation replay unit replays messages generated by manual operations among the messages sent to the current host system by the terminal. An automatic response unit automatically generates a response message for messages received from the new host system. The automatic response unit also generates screen data for a screen displayed on the terminal on the basis of messages received from the new host system. A comparison unit compares and evaluates screen data generated by the automatic response unit and screen data from a screen generated by the terminal on the basis of messages received from the current host system. | 03-31-2016 |
20160103723 | SYSTEM-ON-CHIP VERIFICATION - Disclosed herein are method, system and computer program product embodiments for improving the verification process of a system on chip (SoC). An embodiment operates by employing an active interconnect (AIC) between a processing subsystem (e.g., a central processing unit or CPU) and a plurality of peripherals, wherein the processing subsystem is linked to a plurality of applications via a plurality of drivers, and implementing a common set of software codes by at least one of the applications for a software development process and a hardware verification process. The AIC includes a plurality of communication protocols. During the software development process, the AIC configures at least one of the communication protocols to not enforce a timing limitation on one or more transactions between the processing subsystem and at least one of the peripherals, and a high-level programming language model is used for the peripherals. During the hardware verification process, the AIC configures at least one of the communication protocols to enforce a timing limitation on one or more transactions between the processing subsystem and at least one of the peripherals, and a register-transfer level model is used for a least one of the plurality of peripherals. The AIC may further configure at least one of the communication protocols to enforce one or more constraints on the transactions to achieve increased hardware verification coverage. | 04-14-2016 |
20160103748 | Test Case Execution - Systems, methods, computer readable media and apparatuses for executing one or more test cases associated with verifying a functionality of a computer system, software application, or the like are presented. The test cases may be received by a system and may be prioritized and integrated into an existing queue of test cases based on the determined priority. In some examples, a configuration for a computing device to execute the test cases may be identified and transmitted to one or more computing devices available to or scheduled to execute the test cases. Accordingly, the test cases may be dynamically allocated to available computing devices for execution. In some arrangements, one or more reports may be generated and/or transmitted reporting the results of the execution of the test cases. The reports may be accessible via the system and/or may be transmitted to a user via, for example, an email message. | 04-14-2016 |
20160110273 | METHOD AND SYSTEM FOR REMOTE DIAGNOSTICS OF A DISPLAY DEVICE - In one embodiment a method of remotely communicating with an information handling system may include a first processing device executing one or more diagnostic routines in response to an error signal corresponding to a failure of an integrated display of a first information handling system. The first processing device may establish a peer to peer connection. The first information handling system may connect remotely to a second information handling system via the peer to peer connection. A web browser of the second information handling system may receive and display a HyperText Markup Language (HTML) page that may include an error description and a diagnostic log corresponding to the failure of the integrated display. | 04-21-2016 |
20160124825 | PSEUDO-RANDOM ERROR INSERTION FOR NETWORK TESTING - A method is provided for generating errored test message words in network traffic used for testing. The method includes for each error cycle, select an error generator threshold, using a pseudo random sequence generator that advances with a new error cycle. The method includes for each test word generation cycle, determine whether to apply a bit error mask to a generated test word. An accumulator value is accumulated by an increment that takes into account at least a bit error rate and a bus width. The accumulator value is tested against the threshold. Upon reaching the threshold, a bit error mask is selected from a set of bit error masks, and applied to the generated test word. The threshold is then subtracted from the accumulator value, and a new error generator threshold is selected. The generated test word is output with or without a bit error as determined. | 05-05-2016 |
20160132415 | TESTING INSECURE COMPUTING ENVIRONMENTS USING RANDOM DATA SETS GENERATED FROM CHARACTERIZATIONS OF REAL DATA SETS - The disclosed embodiments provide a system that facilitates testing of an insecure computing environment. During operation, the system obtains a real data set comprising a set of data strings. Next, the system determines a set of frequency distributions associated with the set of data strings. The system then generates a test data set from the real data set, wherein the test data set comprises a set of random data strings that conforms to the set of frequency distributions. Finally, the system tests the insecure computing environment using the test data set. | 05-12-2016 |
20160140006 | TESTBENCH BUILDER, SYSTEM, DEVICE AND METHOD HAVING AGENT LOOPBACK FUNCTIONALITY - A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT. | 05-19-2016 |
20160140008 | FLASH COPY FOR DISASTER RECOVERY (DR) TESTING - In one embodiment, a computer program product for disaster recovery (DR) testing includes a computer readable storage device having program code embodied therewith. The program code is readable and/or executable by a hardware processor to define a DR family including one or more DR clusters accessible to a DR host and one or more production clusters accessible to a production host, create a backup copy of data stored to the one or more production clusters, store the backup copy to the one or more DR clusters, establish a time-zero in the DR family, create a snapshot of each backup copy stored to the one or more DR clusters, share a point-in-time data consistency at the time-zero among all clusters within the DR family and perform DR testing. The DR host is configured to replicate data from the one or more production clusters to the one or more DR clusters. | 05-19-2016 |
20160162380 | IMPLEMENTING PROCESSOR FUNCTIONAL VERIFICATION BY GENERATING AND RUNNING CONSTRAINED RANDOM IRRITATOR TESTS FOR MULTIPLE PROCESSOR SYSTEM AND PROCESSOR CORE WITH MULTIPLE THREADS - A method and system are provided for implementing functional verification including generating and running constrained random irritator tests for a multiple processor system and for a processor core with multiple threads. Separate tests are generated, a main test for one thread, and an irritator test for each other thread in the configuration. The main test and each irritator test are saved and randomly mixed then combined together again, where the main thread is not forced to be generated with any particular irritator. | 06-09-2016 |
20160162381 | IMPLEMENTING PROCESSOR FUNCTIONAL VERIFICATION BY GENERATING AND RUNNING CONSTRAINED RANDOM IRRITATOR TESTS FOR MULTIPLE PROCESSOR SYSTEM AND PROCESSOR CORE WITH MULTIPLE THREADS - A method and system are provided for implementing functional verification including generating and running constrained random irritator tests for a multiple processor system and for a processor core with multiple threads. Separate tests are generated, a main test for one thread, and an irritator test for each other thread in the configuration. The main test and each irritator test are saved and randomly mixed then combined together again, where the main thread is not forced to be generated with any particular irritator. | 06-09-2016 |
20160162393 | Testing Coordinator - A system for testing two or more applications associated with a computerized process may include a central repository, a user interface and a testing coordinator. The central repository may be used to store at least one test case each including a test data set and two or more sets of test scripts. The user interface may facilitate a selection of one or more test cases for use by the testing coordinator. The testing coordinator may be configured to test the operation of the computerized process by initiating testing of a first application by a first test tool using the test data set and a first set of scripts and initiating testing of the second application by the second test tool using the test data set and the second set of scripts from the selected test case. In some cases, the first test tool is incompatible with the second test tool. | 06-09-2016 |
20160170865 | DETECTING ERROR STATES WHEN INTERACTING WITH WEB APPLICATIONS | 06-16-2016 |
20160196197 | TESTING SOC WITH PORTABLE SCENARIO MODELS AND AT DIFFERENT LEVELS | 07-07-2016 |
20160203068 | Instruction and logic to test transactional execution status | 07-14-2016 |
20160378627 | FLEXIBLE CONFIGURATION AND CONTROL OF A TESTING SYSTEM - A method is provided to get a high test coverage through a large number of test cases with a minimum number of test programs. Tests are performed flexibly in various environments, using parameters in multiple dimensions. The parameters can be dynamically extracted from the machine or simulator either by controlling scripts or by the test program itself. Multiple ways are offered to execute subsets of the test combinations. | 12-29-2016 |