Entries |
Document | Title | Date |
20080209270 | Automation Of Testing In Remote Sessions - Systems and methods are described for implementing automation of testing in remote sessions. In an implementation, a test agent is deployed at a remote server to automate testing of various components in a remote session between the remote server and a remote client. The test agent enables automation, synchronization and monitoring of test commands between the remote client and the remote server. The test agent communicates with test applications deployed at the remote client to test the components in the remote session. | 08-28-2008 |
20080229149 | REMOTE TESTING OF COMPUTER DEVICES - In embodiments of the present invention improved capabilities are described for a method and system of software testing that may used on a computer network, the network may include a plurality of computer devices; may use a network management system to transmit test data over the computer network to at least one of the plurality of computer devices; test configuration settings on the at least one computer device using the transmitted test data; and report an actual test result of the at least one computer device back to the network management system. | 09-18-2008 |
20080263400 | Fault insertion system - A method of scheduling a simulated hardware fault on a computer system by specifying at least a termination point where the simulated hardware fault will be automatically removed from the computer system. The computer system may comprise at least one control computer that can be remote from a computer into which a simulated hardware fault is inserted and that schedules and controls simulation of the simulated hardware fault. | 10-23-2008 |
20080282110 | SCAN CLOCK ARCHITECTURE SUPPORTING SLOW SPEED SCAN, AT SPEED SCAN, AND LOGIC BIST - Herein described are at least a method and a system to perform scan testing of an integrated circuit chip using one or more internal and external clock sources. In a representative embodiment, the method comprises receiving at least one external clock signal and three control signals generated by an off-chip clock source, generating at least one internal clock signal from an on-chip clock source, and using the at least one external clock signal and the at least one internal clock signal by a logic circuitry to generate one or more scan test clocks to perform scan testing of one or more corresponding clock domains. In a representative embodiment, the system comprises at least one on-chip clock source and first and second circuitries for generating a scan test clock for a clock domain. | 11-13-2008 |
20080301500 | System and Method for Identifying and Manipulating Logic Analyzer Data from Multiple Clock Domains - A system and method for identifying and manipulating logic analyzer data from multiple clock domains is presented. A logic analyzer receives debug data and determines whether the debug data is a full frequency data type, a half frequency data type, or a crossed data type. Once determined, the logic analyzer reconstructs the debug data such that debug condition-matching logic may process the reconstructed data in a full frequency domain. For half frequency data types, the logic analyzer adds masked data values to the data in order to reconstruct the data into to the full frequency domain before processing the data. For crossed data types, the logic analyzer reconstructs the data into its original format before processing the data in a full frequency domain. | 12-04-2008 |
20080307261 | ACTIVATING A DESIGN TEST MODE IN A GRAPHICS CARD HAVING MULTIPLE EXECUTION UNITS - Provided are a method and system for activating a design test mode in a graphics card having multiple execution units. A design test mode is activated in a graphics module comprising multiple execution units coupled to a cache on a bus. The bus is configured to return test instructions from the cache to the execution units in response to a request from one execution unit for the test instructions from the cache in the design test mode. The execution units execute the test instructions during the design test mode. Interrupts are prevented during the design test mode. | 12-11-2008 |
20080313499 | DEBUG CIRCUIT - The present invention provide a debug circuit which has a structure in which a conversion block latches plural internal signals which are supposed to be effective in finding a cause of a malfunction and are outputted from a selection block, using a signal that is outputted from a timing generation block, converts these signals into serial data, and outputs the serial data to an output block, thereby observing plural signals in the LSI using fewer external pins, and performing analysis of the malfunction of the LSI speedy and reliably. | 12-18-2008 |
20090013214 | ON-CHIP SAMPLERS FOR ASYNCHRONOUSLY TRIGGERED EVENTS - Embodiments of an integrated circuit that includes a debug circuit are described. This debug circuit is configured to test an asynchronous circuit by performing analog measurements on asynchronous signals associated with the asynchronous circuit, and includes a triggering module configured to gate the debug circuit based on one or more of the asynchronous signals. This triggering module has a continuous mode of operation and a single-shot mode of operation. A timing module within the debug circuit has a timing range exceeding a pre-determined value, and is configured to provide signals corresponding to a first time base or signals corresponding to a second time base. Furthermore, control logic within the debug circuit is configured to select a mode of operation and a given time base for the debug circuit, which is either the first time base or the second time base. | 01-08-2009 |
20090055685 | Electronic apparatus in which functioning of of a microcomputer is monitored by another microcomputer to detect abnormal operation - In an electronic apparatus, a first microcomputer is monitored by a second microcomputer, which periodically transmits data relating to a main function to the first microcomputer to be processed. The first microcomputer periodically updates a variable value, performs a predetermined calculation operation whose final result should be a specific fixed value, adds that final result to the updated variable value to obtain a sum value, and transmits the sum value and updated variable value concurrently to the second microcomputer. The second microcomputer determines that the first microcomputer is operating abnormally if the difference between the received sum value and variable value is not equal to the specific fixed value. | 02-26-2009 |
20090083579 | METHOD FOR CACHE CORRECTION USING FUNCTIONAL TESTS TRANSLATED TO FUSE REPAIR - A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error syndrome and a failing address. The functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory using a test pattern based on a random seed. The functional test procedure may be carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets some of the fuses. | 03-26-2009 |
20090150723 | COMPUTER CHIP SET HAVING ON BOARD WIRELESS INTERFACES TO SUPPORT TEST OPERATIONS - A method and apparatus are provided for an embedded wireless interface that is embedded in, for example, one of an input and output controller device for controlling input and output communications with off-board devices, within a memory controller device and a processor motherboard. The embedded wireless interface may be utilized as a wireless test access point to provide signal stimulations for test purposes or to monitor communications over a specified wired communication link. | 06-11-2009 |
20090158092 | SYSTEM AND METHOD FOR INDICATING STATUS OF AN ON-CHIP POWER SUPPLY SYSTEM - The status of multiple on-chip power supply systems is indicated for use in modifying chip test flow and diagnosing chip failure. Digital compliance signals are received, each compliance signal associated with one of multiple on-chip power supplies. Each power supply has an associated compliance level, and each compliance signal indicates whether its associated power supply is operating at the associated compliance level. The compliance signals are converted into a power supply status signal indicating status of the compliance signals associated with the power supply. The power supply status signal is output. If a power supply is operating at its associated compliance level, the output power supply status signal indicates that the power supply is passing. If the power supply is not operating at its associated compliance level, the output power supply status signal indicates that the power supply is failing. If a power supply is failing, a memory test may be aborted, simplifying chip failure diagnosis. | 06-18-2009 |
20090164846 | Fault Injection In Dynamic Random Access Memory Modules For Performing Built-In Self-Tests - Fault injection in dynamic random access memory (‘DRAM’) modules for performing built-in self-tests (‘BISTs’) including establishing, in the mode registers of the DRAM modules by the memory controller through the shared address bus, an injection of a fault into one or more signal lines of a DRAM module, the fault characterized by a fault type; writing data by the memory controller through a data bus to the DRAM modules, the data identifying a particular DRAM module; and responsive to receiving the data, injecting, by the particular DRAM module, the fault characterized by the fault type into the one or more signal lines of the particular DRAM module. | 06-25-2009 |
20090177923 | Apparatus and method for test and debug of a processor/core having advanced power management - An interface unit is provided in a JTAG test and debug procedure involving a plurality of processor cores. The interface unit includes a TAP unit. A switch unit is coupled to the interface unit and switch units are coupled to each of the plurality of processor/cores. When the processor/cores have advanced power management systems, a sleep inhibit signal can be applied to the processor/core state machine preventing the state machine from entering a lower power state. The parameters of the processor/core can be tested to determine when the test and debug procedures can be implemented. When the (power) parameters are to low to permit test and debug, the test and debug unit can provide a command forcing the state machine into a state for which test and debug procedures can be implemented. | 07-09-2009 |
20090217093 | Fault Diagnosis of Serially-Addressed Memory Modules on a PC Motherboard - A test adaptor board connects to a personal computer (PC) motherboard that tests a memory module in a test socket. A standard memory module socket is removed from a target DRAM module slot on the component side and the test adaptor board connects to the target DRAM module slot on the reverse (solder) side of the motherboard. The target DRAM module slot is a middle slot, such as the second or third of four DRAM module slots. The first and fourth DRAM module slots are populated with known good memory modules storing the BIOS at a high address and an operating system image and a test program at a low address. The test program accesses a memory module in the test socket to locate defects. The motherboard does not crash since the BIOS, OS image, and test program are not stored in the memory module under test. | 08-27-2009 |
20090222695 | SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS - A system and method for sharing a communications link between multiple protocols is described that comprises a system comprising a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols. | 09-03-2009 |
20090259888 | APPARATUS FOR DISPLAYING BIOS POST CODE AND METHOD THEREOF - An apparatus for displaying a basic input output system (BIOS) power-on self-test (POST) code and a method thereof are provided. The apparatus includes a BIOS, a conversion module, and an output module. The BIOS is used for generating a POST code. The POST code is transmitted via a low pin count (LPC) interface. The conversion module receives the POST code and converts the POST code into a system management bus (SMBus) format. The output module is used for receiving and outputting the POST code transmitted by the conversion module. The output module is an SMBus interface. | 10-15-2009 |
20090287959 | SYSTEM AND METHOD FOR TESTING COMPUTER - A test system includes at least one computer and a control circuit for testing the computer. The computer includes an input interface and an output interface. The control circuit is configured for sending test signals to the input interface and receiving feedback signals from the output interface for facilitating locating and recording errors during testing of the computer. A testing method for testing the computer is also disclosed. | 11-19-2009 |
20090300419 | REALTIME TEST RESULT PROMULGATION FROM NETWORK COMPONENT TEST DEVICE - The technology disclosed relates to real-time collection and flexible reporting of test data. In particular, it is useful when collecting packet counts during tests of network devices that simulate thousands or even millions of data sessions conducted through a device under test (“DUT”). | 12-03-2009 |
20090319828 | System, Method, and Device Including Built-In Self Tests for Communication Bus Device - A method, device, and system including built-in self tests for a communication bus device is disclosed. In one form, a method of testing a device operable to be coupled to a communication port an information handling system includes accessing a configuration descriptor of a first device operable to be coupled to a communication bus of an information handling system. The method can also include detecting a self-test descriptor associated with the configuration descriptor and testing a portion of the first device using test information associated with the self-test descriptor. The device and system can include logic to perform the methods described herein. | 12-24-2009 |
20100011249 | DEVICE FOR TESTING A FUNCTION OF A DISPLAY PORT, AND SYSTEM AND METHOD FOR TESTING THE SAME - A device is disclosed for testing the function of a display port. The device includes a display port transmitting part, a field programmable gate array, and a memory. The display port transmitting part transmits connecting signals to a display port timing controller mounted on a display panel. The field programmable gate array applies a test signal to the display port timing controller, and controls the connecting signals applied from the display port transmitting part to the display port timing controller. The memory has software that determines acceptance or rejection of the display port function based on data output from the display port timing controller in response to the connecting signals or the test signal. | 01-14-2010 |
20100011250 | MICROCONTROLLER INFORMATION EXTRACTION SYSTEM AND METHOD - A system for debugging a device under test may include a processor register with a program count and a debug program register that receives the program count upon execution of an instruction by a processor. In one implementation, a microcontroller under test by a debugger is accessed using a serial interface, such as a JTAG interface. The interface can communicate directly with a debug register to retrieve program count values, both when the microcontroller is halted and when it is executing instructions. The polling interval to retrieve the program count values may be adjusted by a user of the debugger based on considerations such as bandwidth and accuracy. The microcontroller may transmit the program count value to the debug register from a processing register that is not accessible to the debugger. | 01-14-2010 |
20100023807 | TEST DEVICE AND METHOD FOR THE SOC TEST ARCHITECTURE - A test device for the SoC test architecture is disclosed. The device comprises plural test groups connected in parallel and a test control flag register within a controller. Each test group comprises single or plural core circuits. The test control flag register enables a set of test signals to input in one of the test groups, testing the core circuits in the test group. | 01-28-2010 |
20100023808 | TRANSACTIONAL FLOW MANAGEMENT INTERRUPT DEBUG ARCHITECTURE - According to some embodiments, a first bus may be monitored, the first bus being to exchange data between a first processing system and a second processing system. A second bus may also be monitored, the second bus being to exchange data between the second processing system and a third processing system. Responsive to the monitoring of at least one of the first or second buses, execution of applications, executing on at least two of the processing units, may be interrupted. | 01-28-2010 |
20100023809 | Memory test circuit, semiconductor integrated circuit, and memory test method - A memory test circuit includes a counter circuit that outputs a set signal that is set to the first set value or the second set value alternately in a cycle of the clock signal, an OR circuit that calculates a logical sum of the set signal and the input signal each time when the set signal is output from the counter circuit and outputs a control signal indicating the logical sum of the set signal and the input signal, and a test pattern generation circuit that generates the test pattern for causing the memory to operate in each first cycle if a set value of the control signal is the first set value, or generates the test pattern for causing the memory to operate in each second cycle if the set value of the control signal is the second set value. | 01-28-2010 |
20100031089 | Dynamic Broadcast of Configuration Loads Supporting Multiple Transfer Formats - A method for dynamically broadcasting configuration information to controllers connected in a scan topology in a target system is provided in which a selection event followed by the configuration information is received from a signal line at each of the controllers, wherein the plurality of controllers are connected in parallel to the signal line and the configuration information is stored within each controller that matches a selection criteria following the selection event when the selection event initiates a selection sequence. | 02-04-2010 |
20100050019 | TEST ACCESS PORT - Briefly, descriptions of embodiments in accordance with the invention, a test access port for a multi-core processor. | 02-25-2010 |
20100064173 | MECHANISM FOR STORING AND EXTRACTING TRACE INFORMATION USING INTERNAL MEMORY IN MICRO CONTROLLERS - This document relates to apparatus and methods to store and retrieve trace information in on-chip system memory of microcontrollers. A microcontroller comprises a microprocessor and a memory device accessible through a data bus and an address bus coupled to the microprocessor. The microcontroller includes on-chip debug logic coupled to the microprocessor. Trace data can be retrieved from system memory using a debug port of the debug logic. A system in accordance with the present invention will lower the cost of implementation of trace features in microcontrollers, and strongly reduce the cost of supporting such features in debug tools. | 03-11-2010 |
20100070802 | SEMICONDUCTOR INTEGRATED CIRCUIT AND TESTING METHOD THEREFOR - A semiconductor integrated circuit comprises a plurality of cores ( | 03-18-2010 |
20100070803 | Sequencer and test system including the sequencer - A test system | 03-18-2010 |
20100095154 | IN-CIRCUIT DEBUGGING SYSTEM AND RELATED METHOD - An in-circuit debugging (ICD) system includes at least a first target processor, an embedded debug mode with a debug information memory (DIM), a debug host, and an ICD bridge. The first target processor has an embedded debug module (EDM) and performs a program code in normal mode, where the first EDM controls the first target processor in debug mode. The DIM stores debug information for debugging in debug mode, and is invisible to the first target processor when the first target processor operates in normal mode. The debug host has debug software, and is utilized for debugging the program code by using the debug information in debug mode. The ICD bridge has a host debug module (HDM) coupled to the first EDM, and is coupled between the first target processor and the debug host and utilized for bridging information communicated between the first target processor and the debug host. | 04-15-2010 |
20100115337 | VERIFICATION OF ARRAY BUILT-IN SELF-TEST (ABIST) DESIGN-FOR-TEST/DESIGN-FOR-DIAGNOSTICS (DFT/DFD) - A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays. | 05-06-2010 |
20100122116 | Internally Controlling and Enhancing Advanced Test and Characterization in a Multiple Core Microprocessor - A mechanism is provided for internally controlling and enhancing advanced test and characterization in a multiple core microprocessor. To decrease the time needed to test a multiple core chip, the mechanism uses micro-architectural support that allows one core, a control core, to run a functional program to test the other cores. Any core on the chip can be designated to be the control core as long as it has already been tested for functionality at one safe frequency and voltage operating point. An external testing device loads a small program into the control core's dedicated memory. The program functionally running on the control core uses micro-architectural support for functional scan and external scan communication to independently test the other cores while adjusting the frequencies and/or voltages of the other cores until failure. The control core may independently test the other cores by starting, stopping, and determining pass/fail results. | 05-13-2010 |
20100180154 | Built In Self-Test of Memory Stressor - A method and system for generating addresses in a memory card built in self-test (MCBIST) for testing memory devices. The method includes receiving a MCBIST command and determining an addressing mode of the MCBIST command. Sequential addresses are generated and modified in response to the addressing mode being a stress test mode. The modifying includes swapping bits in a sequential address with other bits in the sequential address to target selected portions of a memory. The modified sequential addresses are output to the memory to be utilized in a MCBIST stress test of the memory. | 07-15-2010 |
20100229041 | DEVICE AND METHOD FOR EXPEDITING FEEDBACK ON CHANGES OF CONNECTION STATUS OF MONITIORING EQUIPMENTS - The present invention relates to a device and method for expediting feedback on changes of connection status of monitoring equipments, comprising a CPU, a switch module and at least an optical fiber connector, wherein the CPU contains multiple reserved pins and is connected with the switch module, while the switch module is connected with at least one optical fiber connector, which includes signal detect pins that are used to connect with the switch module. The CPU is connected through one of the reserved pins with the SD pin of the optical fiber connector, and controlled by a system software to read the bit value of the signal address of the SD pin. This allows the system software to analyze and determine if the address value of the signals received by the reserved pin is changed or not, and to take action to respond when the connection status is changed. Because signals are transported without using the switch module, it will save the time required for bus communication and synchronous processing of signals, thus expediting feedback on change of connection status. | 09-09-2010 |
20100251022 | INTEGRATED CIRCUIT, DEBUGGING CIRCUIT, AND DEBUGGING COMMAND CONTROL METHOD - An integrated circuit includes a bus; a processing unit configured to execute a user program; and a debugging circuit connected to the bus, the debugging circuit transferring a command in a command register to the processing unit via the bus in response to a command transfer request from the processing unit, wherein, when the processing unit halts the execution of the user program and makes a request for the command transfer request to the debugging circuit, the debugging circuit makes a response for freeing the use right of the bus from the processing unit in a period between the command transfer request and the command transfer operation. | 09-30-2010 |
20100251023 | SYSTEM AND METHOD FOR IMPROVED PERFORMANCE AND OPTIMIZATION OF DATA EXCHANGES OVER A COMMUNICATIONS LINK - A system and method for improved performance and optimization of data exchanges over a communications link is described, including a method for communicating data that includes transmitting a first control segment of a message from a first system to a second system (the first control segment including control information that selects an active communications protocol from a plurality of communications protocols); sequencing at least part of the first and second systems through a series of states that control the active communications protocol based upon the control information in the first control segment; and exchanging a data segment of the message (after the first control segment) between the first system and the second system The series of states represents inert sequences to the remaining communications protocols of the plurality of communications protocols that were not selected as active. | 09-30-2010 |
20100281301 | CIRCUIT FOR A TRANSPONDER AND METHOD FOR TESTING THE CIRCUIT - A method for testing a circuit for a transponder, and transponder circuit, is provided, in which the circuit is operated in a passive mode in that the circuit is supplied with energy from a field, in which, during the passive mode, the circuit receives a command via the field to activate a test routine, in which memory content is stored by the test routine as test data in a memory area of a memory of the circuit predetermined by the test routine, in which, during the passive mode, the test data are transmitted via the field. | 11-04-2010 |
20100306589 | COMPUTER CHIP SET HAVING ON BOARD WIRELESS INTERFACES TO SUPPORT TEST OPERATIONS - A method and apparatus are provided for an embedded wireless interface that is embedded in, for example, one of an input and output controller device for controlling input and output communications with off-board devices, within a memory controller device and a processor motherboard. The embedded wireless interface may be utilized as a wireless test access point to provide signal stimulations for test purposes or to monitor communications over a specified wired communication link. | 12-02-2010 |
20100318848 | Establishing a connection between a testing and/or debugging interface and a connector - This invention relates to automatically establishing a connection between a testing and/or debugging interface to an integrated circuit and a connector of an apparatus, the connector being connectable to a testing and/or debugging apparatus configured to communicate with the testing and/or debugging interface via the connector in a testing and/or debugging mode of the apparatus and connectable to an accessory apparatus to be used in a normal operation mode of the apparatus, if the testing and/or debugging apparatus is connected to the connector, thereby establishing the testing and/or debugging mode of the apparatus. | 12-16-2010 |
20100332903 | LOCATING AND LABELING DEVICE IN A MULTI DROP CONFIGURATION - An identification (ID) process comprises in each of a plurality of bit times, a debug test system asserting a control signal at a predefined state to a plurality of target systems, and each target system, having a bit pattern and the bit patterns being different among the target systems, outputting a bit from its bit pattern on the control signal. The process further comprises each target system comparing the resulting state of the control signal to that target system's output bit. If the target system's output bit differs from the resulting control signal state, the target system ceases participating in the ID process or, if the target system's output bit matches the resulting control signal state, the target system continues to participate in the ID process. | 12-30-2010 |
20110029813 | CIRCUITS AND METHODS FOR PROCESSING MEMORY REDUNDANCY DATA - An interface processes memory redundancy data on an application specific integrated circuit (ASIC) with self-repairing random access memory (RAM) devices. The interface includes a state machine, a counter, and an array of registers. The state machine is coupled to a redundancy chain. The redundancy chain includes coupled redundant elements of respective memory elements on the ASIC. In a shift-in mode, the interface shifts data from each of the elements in the redundancy chain and compresses the data in the array of registers. The interface communicates with a test access port coupled to one or more eFuse devices to store and retrieve the compressed data. In a shift-out mode, the interface decompresses the data stored in the array of registers and shifts the decompressed data to each unit in the redundancy chain. The interface functions absent knowledge of the number, bit size and type of self-repairing RAM devices in the redundancy chain. | 02-03-2011 |
20110041010 | SYSTEM-ON-CHIP WITH MASTER/SLAVE DEBUG INTERFACE - A System-on-Chip (SOC) integrated circuit (IC) debugging system includes a plurality of SOC ICs connected to a shared debug bus. One of the plurality of SOC ICs is a master SOC IC having a master/slave debug interface. The master/slave debug interface on the master SOC IC is a bidirectional debug interface operable to send and receive debug data between the SOC ICs and an external host system. | 02-17-2011 |
20110113286 | SCAN TEST CIRCUIT AND SCAN TEST METHOD - A scan test circuit for a memory with a first memory cell column, a second memory cell column that replaces a failed column of the first memory cell column, a first switching circuit that connects one of the memory cell columns to a first peripheral circuit disposed at an input side, and a second switching circuit that connects one of the memory cell columns to a second peripheral circuit disposed at an output side, comprises: a test priority control circuit that controls the switching circuits to establish at least two patterns of connections of the memory cell columns to the peripheral circuits; and a test point circuit that includes scan flip-flop circuits employed in a scan test for detecting a delay fault of the peripheral circuits, and is disposed between the memory cell columns and the first switching circuit. | 05-12-2011 |
20110126051 | Error recover within processing stages of an integrated circuit - An integrated circuit includes a plurality of processing stages each including processing logic | 05-26-2011 |
20110161735 | SEMICONDUCTOR DEVICE CONTROLLING DEBUG OPERATION OF PROCESSING UNIT IN RESPONSE TO PERMISSION OR PROHIBITION FROM OTHER PROCESSING UNIT - A semiconductor device is capable of being coupled to first and second debuggers, the first and second debuggers being capable of debugging a program in the semiconductor device. The semiconductor device includes a first chip, and a second chip that is coupled to the first chip. The first chip includes a first processing unit that executes a first instruction group, and a first debug control unit capable of being coupled to the first debugger to control a communication with the first debugger. The second chip includes a nonvolatile memory that stores an ID code and the program including the first and second instruction groups and, the ID code stored in the nonvolatile memory being compared with an ID code inputted from the second debugger to control permission or prohibition of a connection configuration to the second debugger, a second processing unit that executes the second instruction group, and a second debug control unit capable of being coupled to the second debugger to control a communication with the second debugger. The first debug control unit controls permission or prohibition of a connection configuration to the first debugger based on whether the connection configuration to the second debugger is permitted or not. | 06-30-2011 |
20110209002 | Programmable Test Engine (PCDTE) For Emerging Memory Technologies - A programmable characterization-debug-test engine (PCDTE) on an integrated circuit chip. The PCDTE includes an instruction memory that receives and stores instructions provided on a chip interface, and a configuration memory that receives and stores configuration values provided on the chip interface. The PCDTE also includes a controller that configures a plurality of address counters and data registers in response to the configuration values. The controller also executes the instructions, wherein read/write addresses and write data are retrieved from the counters in response to the instructions. The retrieved read/write addresses and write data are used to access a memory under test. Multiple ports of the memory under test may be simultaneously accessed. Multiple instructions may be linked. The instructions may specify special counting functions within the counters and/or specify integrated (linked) counters. The PCDTE may transmit information off of the chip to exercise transmit/receive circuitry of the chip. | 08-25-2011 |
20110209003 | INFORMATION PROCESSING APPARATUS WITH DEBUGGING UNIT AND DEBUGGING METHOD THEREFOR - An information processing apparatus includes an external tool unit configured to provide a man-machine interface to a debugging user; and a microcontroller. The microcontroller includes: a CPU section configured to execute a program as a debugging target in a response to a first clock signal, wherein a clock rate of the first clock signal is changed in response to an instruction from the CPU section; a first transmitting section configured to transmit debugging data to the external tool unit in response to the first clock signal; a second transmitting section configured to transmit the debugging data to the external tool unit in response to a second clock signal which is different from the first clock signal; and a receiving section configured to receive data transmitted from the external tool unit. | 08-25-2011 |
20110276829 | CLIENT SERVER AND METHOD FOR MONITORING FUNCTION TESTS THEREOF - A client server and a test monitoring method for the client server include receiving a customization Intelligent Platform Management Interface (IPMI) from the monitor server and parsing the customization IPMI command to be a command suitable for the client server. The monitor method further includes obtaining a test result of the customization IPMI command and transmitting a determined IPMI return value corresponding to the test result to the monitor server, with the monitor server recording a test of the customization IPMI command. | 11-10-2011 |
20110283141 | SYSTEM-ON-CHIP AND DEBUGGING METHOD THEREOF - A system-on-chip (SoC) includes a core, a plurality of power domain blocks, and a power control circuit including a debug circuit. The power control circuit is configured to control power supplied to the core and each of the power domain blocks, and the debug circuit is configured to debug the power control circuit. | 11-17-2011 |
20110320871 | RS-485 PORT TEST APPARATUS - An RS-485 port test apparatus includes an RS-485 connector, a micro control unit (MCU), a multiprotocol transceiver, and a display. The RS-485 connector receives a first test code signal from a test RS-485 port of an electronic device. The multiprotocol transceiver receives the first test code signal from the RS-485 connector, converts the first test code signal to a second test code signal which can be identified by the MCU, and transmits the second signal to the MCU. The MCU receives the second test code signal and displays the second test code signal by the display. The MCU sends back the second test code signal to the multiprotocol transceiver. The multiprotocol transceiver converts the second test code signal to the first test code and transmits the first test code to the test RS-485 port of the electronic device through the RS-485 connector. | 12-29-2011 |
20120011403 | METHODS SYSTEMS AND APPARATUS FOR DETERMINING WHETHER BUILT-IN-TEST FAULT CODES ARE INDICATIVE OF AN ACTUAL FAULT CONDITION OR A FALSE ALARM - Methods and apparatus are provided for determining whether a built-in-test fault code (BITFC) data sequence generated by a built-in-test (BIT) of a particular module of a complex system is indicative of an actual fault condition. A regression function is generated for the particular module based on stored BITFC data sequences generated by the BIT and stored repair data for that module from a fault history database. Later, during operation of the particular module, the BIT generates a new BITFC data sequence. A processor can then load the new BITFC data sequence and execute the regression function with respect to the new BITFC data sequence to determine whether the new BITFC data sequence is indicative of an actual fault condition at the particular module or is indicative of a false fault condition at the particular module. | 01-12-2012 |
20120011404 | METHOD AND SYSTEM OF A PROCESSOR-AGNOSTIC ENCODED DEBUG-ARCHITECTURE IN A PIPELINED ENVIRONMENT - A method and/or a system of a processor-agnostic encoded debug architecture in a pipelined environment is disclosed. In one embodiment, a method of a processor includes processing an event specified by a data processing system coupled to the processor to determine a boundary of the event, generating a matrix having combinations of the event and other events occurring simultaneously in the processor, capturing an output data of observed ones of the event and other events, and applying the matrix to generate an encoded debug data of the output data. The method may also include determining which of the combinations are valid based on an architecture of the processor. The event may be a trace-worthy event whose output value cannot be reliably predicted in an executable file in the data processing system and/or a sync event that is specified by a user of the data processing system. | 01-12-2012 |
20120060058 | TESTING OF NON STUCK-AT FAULTS IN MEMORY - A method for identifying non stuck-at faults in a read-only memory (ROM) includes generating a golden value of a victim cell, providing a fault-specific pattern through an aggressor cell, generating a test reading of the victim cell in response to the provided fault-specific pattern, and determining whether the ROM has at least one non stuck-at fault. The determination is based on a comparison of the golden value and the test reading of the victim cell. | 03-08-2012 |
20120084603 | EVALUATION OF MULTIPLE INPUT SIGNATURE REGISTER RESULTS - Provided is an apparatus that includes a processor comprising a plurality of processing cores and a corresponding plurality of LBIST modules, each LBIST module corresponding to one of the plurality of processing cores; a MISR read out connection, comprising a compare value register, a plurality of MISR registers equal in number to the plurality of cores, each MISR register corresponding to one of the plurality of processing cores and a corresponding plurality of XOR logic gates, each XOR logic gate coupled to the compare value register and a corresponding one of the MISR registers and configured to signal whether or not the event the compare value register and the corresponding MISR register match and logic, stored and executed on the processor, for transmitting the signals generated by the plurality of XOR logic gates. | 04-05-2012 |
20120089870 | BIOS REFRESH DEVICE AND METHOD USING THE SAME - A BIOS refresh device includes a first socket, a second socket, and a jumper. The first socket includes a first elastic contact, a first voltage contact, and a first ground contact. The second socket includes a second elastic contact, a second voltage contact, and a second ground contact. The jumper includes a first pin, a second pin, a third pin, and a fourth pin. The first pin is electronically connected with the second elastic contact. The second pin is electronically connected with the first voltage contact or the second voltage contact. The third pin is electronically connected with the first elastic contact. The fourth pin is electronically connected with the second ground contact or the second ground contact. | 04-12-2012 |
20120096314 | DYNAMIC DETECTION AND IDENTIFICATION OF THE FUNCTIONAL STATE OF MULTI-PROCESSOR CORES - Exemplary embodiments include a sequential and concurrent status detection and evaluation method for multiple processor cores, including receiving data from a plurality of processor cores, for each of the plurality of processor cores, simultaneously running a built-in self test to determine if each of the plurality of cores has failed, checking the data for a dominant logic state and recording a subset of the plurality of processor cores that have failed. | 04-19-2012 |
20120137176 | MICROCOMPUTER - A debug circuit of a microcomputer, providing an on-chip debug function, is provided as a measurement permission circuit for outputting a measurement permission signal to a timer that measures, as a measurement object, a time period between two events in a program execution period of the CPU, according to a user-specified condition. The measurement permission circuit includes an interrupt level register for setting an interrupt level that either permits or prohibits a time measurement operation of the timer, and a comparator for determining by comparison a high-low relationship between an interrupt level of an interrupt process executed by the CPU and an interrupt level set in the interrupt level register, and a determination result of the comparator is specified as the measurement permission signal. | 05-31-2012 |
20120151263 | DEBUG STATE MACHINES AND METHODS OF THEIR OPERATION - Embodiments include methods for performing various operations in a computing system that includes an electronic module and a debug circuit. The method includes programming the debug circuit to monitor for pre-selected triggers produced by the computing system, and to perform actions in response to detecting the pre-select triggers. For example, in response to various pre-selected triggers, the debug circuit may, among other things: perform state transitions and log information indicating whether or not the state transitions were performed; monitor various signals when the debug circuit has determined that a test escape has occurred; and/or perform one or more actions that initiate stopping one or more clocks in response to certain pre-selected triggers. | 06-14-2012 |
20120159251 | Test Device and Method for the SoC Test Architecture - A test device for an SoC test architecture has a test input port, a test output port, a plurality of cores, a register, and a plurality of user defined logics. The register has a plurality of bits corresponding to the cores. Each of the user defined logics is connected to a corresponding bit of the register and a corresponding one of the cores. Each of the user defined logic receives a plurality of test control signals, and receives the corresponding bit of the register to change values of the test control signals. Outputs of each of the user defined logics are connected to the corresponding core to determine whether a test instruction of the corresponding core is or is not needed to be updated. | 06-21-2012 |
20120198278 | CONTROLLING GENERATION OF DEBUG EXCEPTIONS - A data processing apparatus for performing data processing operations in response to execution of program instructions and debug circuitry for performing operations. The data processing apparatus includes a data store for storing a current debug exception mask value. The data processing circuitry is configured to set the mask value to a first value in the data store in response to executing critical code and on termination of execution of the critical code to reset the mask value to not store the first value. The data processing circuitry is configured, in response to receipt of a control signal indicating a debug exception is to be taken, to allow the exception to be taken if the mask value is not set to the first value and not to allow said exception to be taken if the mask value is set to the first value. | 08-02-2012 |
20120226942 | INTERRUPTIBLE NON-DESTRUCTIVE RUN-TIME BUILT-IN SELF-TEST FOR FIELD TESTING - A built-in self-test (BIST) diagnostic system tests the execution of a processor. The processor is arranged to execute a normal application for controlling a process that is external to the processor. The normal execution is executed in normal execution timeslots that have idle timeslots that are interspersed in time between the normal execution timeslots. A BIST controller is arranged to detect the presence of an idle timeslot in the execution of the processor and to use a scan chain to scan-in a first test pattern for a test application for testing the processor. The first test pattern is executed by the processor during the detected idle timeslot and a first result pattern generated by the execution of the first test pattern is scanned-out. The scanned-out first test pattern is evaluated to determine the presence of an error. The first test pattern application is conditionally interruptible. | 09-06-2012 |
20120233504 | FUNCTIONAL FABRIC BASED TEST ACCESS MECHANISM FOR SOCS - A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric. | 09-13-2012 |
20120284563 | Hardware/Software Debugging - Debug circuitry is operated in a manner that facilitates debugging one or more hardware and/or software components that are included in a system that includes a system memory. The debug circuitry receives information from one of the hardware and/or software components and/or from the system memory, and ascertains whether the received information includes memory address parameters. If the received information includes memory address parameters, then the memory address parameters are used to retrieve data from the system memory. The retrieved data is supplied at an output port of the debug circuitry. | 11-08-2012 |
20130031411 | COMPUTER SYSTEM AND DIAGNOSTIC METHOD THEREOF - A computer system and a diagnostic method thereof are provided. The computer system comprises a system management bus (SMBus) switch, a plurality of servers and a remote management controller (RMC). Each server comprises a diagnostic message port, a basic input output system (BIOS) and a logic circuit. The BIOS outputs a diagnostic message to the diagnostic message port. The logic circuit catches the diagnostic message. The RMC comprises a SMBus host controller. The SMBus host controller controls the SMBus switch to connect the SMBus host controller to a corresponding logic circuit according to a request. The logic circuit responds the diagnostic message to the SMBus host controller according to the request. | 01-31-2013 |
20130042144 | EDRAM MACRO DISABLEMENT IN CACHE MEMORY - A computer implemented method of embedded dynamic random access memory (EDRAM) macro disablement. The method includes isolating an EDRAM macro of a cache memory bank, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros, the EDRAM macro being associated with one of the at least three rows. Each line of the EDRAM macro is iteratively tested, the testing including attempting at least one write operation at each line of the EDRAM macro. It is determined that an error occurred during the testing. Write perations for an entire row of EDRAM macros associated with the EDRAM macro are disabled based on the determining. | 02-14-2013 |
20130055023 | VERIFICATION OF SOC SCAN DUMP AND MEMORY DUMP OPERATIONS - Techniques are disclosed for verifying memory dump operations and scan dump operations. A memory specification is analyzed and parsed to generate a script for performing a memory dump operation. To verify the memory dump operation, first, a set of values are written to one or more memories of a SoC. Next, the script is executed to perform the memory dump operation, and then an output bitstream from the operation is compared to the set of values. The scan dump operation involves taking a snapshot of a model of a SoC in an emulator. A scan dump operation is performed, and an output bitstream from the operation is compared to the snapshot. The memory and scan dump operations are invoked using commands in a first language, and the commands are translated into a second language to perform the operations. | 02-28-2013 |
20130055024 | CENTRAL PROCESSING UNIT TEST SYSTEM - A central processing unit (CPU) test system includes a CPU socket, a CPU core controller, and a CPU test device. The CPU core controller stores a start voltage message. The CPU test device includes a voltage detection pin, an analog to digital (A/D) converter, and a microcontroller. The voltage detection pin detects a voltage of an electronic device connected to the CPU socket. The A/D converter converts the detected voltage into a digital signal. The microcontroller controls the CPU core controller to output the start voltage to the CPU socket according to the digital signal. The microcontroller stores a predetermined start voltage message. The microcontroller reads the start voltage message after controlling the CPU core controller to output the start voltage, and determines whether the CPU core controller supplies the start voltage to the CPU socket by comparing the read start voltage message with the predetermined start voltage message. | 02-28-2013 |
20130073906 | MOTHERBOARD TESTING DEVICE AND TESTING METHOD THEREOF - A motherboard testing device applied to a motherboard which includes two memory channels, and a CPU. Each of the two memory channels includes two memory slots. The motherboard testing device includes four memory modules received in the four memory slots, a switching chip, a microcontroller, and a testing module. The switching chip includes four input pins electrically connected to the four memory modules, four output pins electrically connected to the CPU, and a controlling pin electrically connected to the microcontroller. The microcontroller forms a plurality of combination modes of the memory slots by electrically combining the four memory slots, and controls the switching chip to electrically connect memory slots of each combination mode to the CPU. The testing module tests whether the CPU controls the memory modules received in the memory slots of each combination mode to work in proper working modes. | 03-21-2013 |
20130124920 | METHOD, APPARATUS and product FOR testing transactions - A computer-implemented method and apparatus, comprising: having a plurality of processing entities operating substantially concurrently in a computerized platform enabling transaction operations, wherein the plurality of processing entities comprise two or more entities adapted to store values, and one or more entity adapted to load values, wherein each writing entity is associated with a private memory location within a memory unit; storing symbols into an associated target memory location by each of the entities adapted to store values, wherein symbols are stored according to a predetermined order, wherein a symbol is stored using a transaction; loading a multiplicity of private memory locations by the at least one entity adapted to load values, to obtain loaded values; and analyzing the loaded values for at least one invariant. | 05-16-2013 |
20130139002 | DEBUGGING METHOD AND COMPUTER SYSTEM USING THE SAME - A debugging method for a plurality of processor cores is disclosed, which includes defining a debug data transmitting zone in a storage device, utilizing a first processor core for generating a debug data and transmitting the debug data to a second processor core via the debug data transmitting zone for debugging. | 05-30-2013 |
20130151901 | High Volume Recording of Instrumentation Data Varying Instrumentation Volumes to Prevent Data Loss - This invention is an apparatus and method for monitoring an electronic apparatus. At least one capture unit captures data to be monitored. A repeater corresponding to each capture unit repeats the captured data. A first-in-first-out buffer corresponding to each capture unit temporarily stores the captured data. The buffered data supplies a utilization unit. Captured data may be merged after repeating. The capture unit may be in a different voltage domain than the repeater, buffer and utilization unit. | 06-13-2013 |
20130151902 | DEBUG SYSTEM AND METHOD - A debug system includes a debug device and a computer. The debug device includes an IIC reading and writing module, a first control module; and a signal receiving and transmitting module. The computer includes a second control module. The IIC reading and writing module is connected to an IIC device. The second control module sends an inputted command to the first control module via the signal receiving and transmitting module. The first control module reads data from the IIC device or writes data to the IIC device via the IIC reading and writing module according to the inputted command | 06-13-2013 |
20130151903 | IMAGE FORMING APPARATUS - An image forming apparatus has a plurality of device modules for executing predetermined functions; and a control module for controlling operation of the device modules. The control module comprises an initialization section for establishing a link; a master data transfer section for transferring data to a device module; and a link checking section for checking the state of the link. When a request for data transfer to a first device module out of the plurality of device modules is made, the link checking section checks the state of the link between the control module and the first device module. When the state of the link checked is determined to be abnormal, the initialization section establishes the link between the control module and the first device module, and then the master data transfer section transfers the data requested to be transferred to the first device module. | 06-13-2013 |
20130151904 | Memory-Module Extender Card for Visually Decoding Addresses from Diagnostic Programs and Ignoring Operating System Accesses - A diagnostic extender card is plugged into a memory module socket on a personal computer (PC) motherboard. The extender card has a test socket that receives a memory module and an intercepting decoder chip that receives the chip-select (CS) from the motherboard that selects the memory module for access. When CS is activated, the intercepting decoder chip illuminates a visual indicator on the extender card, allowing a user to locate a memory module being accessed. The exact translation or mapping from logical addresses of test programs to physical addresses of the memory modules is not needed, since the visual indicator shows which memory module is really being accessed, regardless of proprietary address mapping by north bridge chips. Operating system memory accesses are filtered out by a counter that counts accesses during a period set by a timer. When the number of accesses exceeds a threshold, the visual indicator is lit. | 06-13-2013 |
20130159771 | Accelerated Processing Unit Debugging Using a Graphics Processing Unit Centric Debug Core - An Accelerated Processing Unit (APU) comprising a central processing unit (CPU) core portion and a graphics processing unit (GPU) core portion coupled to the CPU core portion. The GPU core portion includes a GPU core and a dedicated GPU debugging core, the dedicated GPU debugging core enabling performance of GPU centric debug functions. | 06-20-2013 |
20130198566 | Method and Apparatus for Debugging System-on-Chip Devices - A device that provides debug mode information associated with a System-on-Chip (SoC) device includes a multiplexer, debug controller, and a memory device internal to the SoC device and coupled to the multiplexer. The multiplexer directs debug mode information to the memory device in response to the SoC device being in a debug mode. The debug controller stores the debug mode information in the memory device in response to a triggering signal, and the triggering signal is associated with a triggering event. The debug controller reads data from memory device and provides the debug mode information external to the SoC device. The memory may include a first memory block and a second memory block, which store debug mode information. The first memory block may store debug mode information, and the second memory block may store normal mode information. A corresponding method and computer-readable medium are also disclosed. | 08-01-2013 |
20130238933 | MULTI-CORE SOC HAVING DEBUGGING FUNCTION - There present invention relates to a multi-core System On Chip (SoC) having a debugging function. The multi-core SoC having a debugging function includes one or more processors each configured to include an On Core Debug (OCD); a bus matrix configured to connect buses between the one or more processors and one or more peripheral devices; and a debug interface configured to include Processor Debug Interfaces (PDIs) for communicating with the respective OCDs and a Bus Debug Interface (BDI) for communicating with the bus matrix. In accordance with the present invention, the function of a multi-core SoC which has become complicated as compared with the existing singe core SoC may be efficiently verified. | 09-12-2013 |
20130290785 | SYSTEMS AND METHODS FOR A SHARED DEBUG PIN - In some examples, a computer system includes a first component associated with a first power domain and a second component associated with a second power domain. The computer system also includes a debug port with a debug port pin shared by a debug operation pin of the first component and a corresponding debug operation pin of the second component. The computer system also includes a switch associated with the debug port pin to selectively isolate the debug operation pin of the first component from leakage current of the corresponding debug operation pin of the second component. | 10-31-2013 |
20130297974 | Processor Device with Reset Condition Trace Capabilities - A processor device with debug capabilities has a central processing unit, debug circuitry including a trace module, a system clock module for providing internal clock signals, and a reset detection unit which during a debug mode prevents the system clock module from receiving a reset signal. | 11-07-2013 |
20130339790 | APPARATUS, SYSTEM AND METHOD FOR A COMMON UNIFIED DEBUG ARCHITECTURE FOR INTEGRATED CIRCUITS AND SoCs - A system and method for a common unified debug architecture for integrated circuits and System on Chips (SoCs) are provided. A system consistent with the present disclosure may comprise of an integrated circuit or SoC which includes a display port, plurality of logic blocks, and debug logic. The debug logic may receive debug data from one or more of the plurality of logic blocks in response to the integrated circuit or SoC operating in a debug mode. In addition, control logic coupled to the debug logic. The control logic provides display data to the display port in response to the integrated circuit operating in an operational mode. The control logic further directs high-speed debug data to the display port in response to the integrated circuit or SoC operating in the debug mode. The high-speed debug data is to be based on the debug data. | 12-19-2013 |
20130346800 | System on a Chip (SOC) Debug Controllability - In one embodiment, an SOC includes multiple components including a CPU complex and one or more non-CPU components such as peripheral interface controllers, memory controllers, media components, etc. The SOC also includes an SOC debug control unit, which is coupled to receive detected debug events from the components. Each component may include a local debug control unit that is configured to monitor for various debug events within that component. The debug events may be specific to the component. The local debug control units may transmit detected events to the SOC debug control unit. The SOC debug control unit may detect one or more events from one or more components, and may halt the components of the SOC responsive to detecting the selected events. | 12-26-2013 |
20140006863 | TEST CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE SAME | 01-02-2014 |
20140013156 | METHOD AND SYSTEM FOR MANAGING IMAGE FORMING APPARATUS THROUGH NETWORK - A method of managing an image forming apparatus through a network, the method including: logging in to a server through a diagnostic control unit application from a user terminal; receiving, by the user terminal, device information of an image forming apparatus from the image forming apparatus; requesting for and receiving, by the user terminal, diagnostic control unit information corresponding to the received device information from the server; performing a diagnostic control on the image forming apparatus through the diagnostic control unit application by using the received diagnostic control unit information; and uploading results of performing the diagnostic control on the server. | 01-09-2014 |
20140013157 | DEBUG ARCHITECTURE - Roughly described, an integrated circuit chip comprises a plurality of peripheral circuits, each peripheral circuit connected to a respective debug unit, the respective debug unit configured to generate debug information of that peripheral circuit; and a plurality of separate stores for receiving debug information, storing debug information, and outputting debug information; wherein in response to a single trigger signal, the debug units are configured to stream their generated debug information to the plurality of separate stores; and wherein each of the plurality of separate stores is configured to receive debug information at a higher stream rate than it outputs debug information. | 01-09-2014 |
20140013158 | REALTIME TEST RESULT PROMULGATION FROM NETWORK COMPONENT TEST DEVICE - The technology disclosed relates to real-time collection and flexible reporting of test data. In particular, it is useful when collecting packet counts during tests of network devices that simulate thousands or even millions of data sessions conducted through a device under test (“DUT”). | 01-09-2014 |
20140032965 | MONITORING DEVICE, INFORMATION PROCESSING APPARATUS, AND MONITORING METHOD - A monitoring device includes a detection unit which is inserted between the device to be monitored and a processing apparatus performing processing for the device to be monitored and detects a failure which occurs in the device to be monitored, a notification unit generating failure information indicating a content of the failure detected by the detection unit and notifying the generated failure information and the occurrence of the failure to the processing apparatus, and an acquisition unit acquiring status information after the occurrence of the failure of the device to be monitored from the device to be monitored and storing the acquired status information in a storage unit as the failure occurs. | 01-30-2014 |
20140053023 | PSEUDO DEDICATED DEBUG PORT WITH AN APPLICATION INTERFACE - A method is shown to provide remote access to one or more debug access points whose functions include capabilities other than accessing memories across an application interface such as USB, IEEE 802.3 (Ethernet) and other protocols. The capabilities available include all or many of the capabilities provided by a dedicated debug interface. | 02-20-2014 |
20140068332 | ELECTRONIC DEVICE HAVING SELF DIAGNOSIS FUNCTION AND SELF DIAGNOSIS METHOD USING THE SAME - An electronic device which has a self diagnosis function and a self diagnosis method using the same are provided. The electronic device includes: an interface which receives a user's selection signal for a hardware of an object to be diagnosed; and a controller which provides a plurality of lines connected to the hardware of the object to be diagnosed with a signal for diagnosis according to the selection signal which is received through the interface and calculates a diagnosis result for the hardware of diagnosis object according to a comparison result of the signal for diagnosis with a return signal which is returned from the hardware of the object to be diagnosed by a loop-back. | 03-06-2014 |
20140068333 | BUILT-IN-SELF-TEST USING EMBEDDED MEMORY AND PROCESSOR IN AN APPLICATION SPECIFIC INTERGRATED CIRCUIT - A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implemented using a few terminals of the ASIC. | 03-06-2014 |
20140095932 | DEBUG SYSTEM, AND RELATED INTEGRATED CIRCUIT AND METHOD - A system includes a processor and a plurality of circuits connected through an interconnection network, wherein associated to each circuit is a respective communication interface configured for exchanging data between the respective circuit and the interconnection network. In particular, a debug unit is associated with each communication interface. Each debug unit is configurable as a data-insertion point, wherein the debug unit transmits data by means of the respective communication interface to the interconnection network, or each debug unit is configurable as a data-reception point, wherein the debug unit receives data by means of the respective communication interface from the interconnection network. | 04-03-2014 |
20140122929 | DISTRIBUTED ON-CHIP DEBUG TRIGGERING - A method and apparatus for distributed on-chip debug triggering is presented. A first bus includes a plurality of lines and a debugging state machine configurable to monitor the plurality of lines of the first bus. One or more nodes are configurable to detect triggering events and provide, in response to detecting one or more triggering events, signals to the debugging state machine using a first subset of the plurality of lines that is allocated to the node(s). | 05-01-2014 |
20140149795 | INFORMATION PROCESSING APPARATUS AND METHOD RELATING TO HARDWARE DIAGNOSIS - A disclosed apparatus includes a memory and circuitry that is configured to execute an operating system, and realize one or plural logical domains that provide a predetermined function as a computer and a hypervisor that manages the logical domain. The operating system is configured to: detect hardware to be diagnosed; upon detecting the hardware to be diagnosed, secure a memory area in the memory, which is used for diagnosis by the operating system; instruct a kernel of the operating system to ignore an error that will occur in the secured memory area; and output a diagnosis request that instructs to ignore the error and includes designation of the hardware to be diagnosed to the hypervisor. The hypervisor is configured to execute: upon receipt of the diagnosis request, perform a setting to ignore the error that will occur; and perform the diagnosis for the hardware. | 05-29-2014 |
20140157051 | METHOD AND DEVICE FOR DEBUGGING A MIPS-STRUCTURE CPU WITH SOUTHBRIDGE AND NORTHBRIDGE CHIPSETS - The present invention discloses a method and a device to debug the Loongson CPU (a MIPS-structure CPU) and bridge chips. The device, including HT bus interfaces and the corresponding switches, connects the Loongson CPU and bridge chips through HT bus interfaces. Southbridge chips and northbridge chips with HT buses are selected in the following order: introducing the pins on the Loongson CPU and bridge chips into the debug device; debugging the pins on the Loongson CPU to identify whether there are any bugs with the pins; connecting the pins from the CPU and bridge chips to debug them. If the HT bus of the Loongson CPU fails to accord with the standard protocol, the problematic signal can be identified and further adjusted to improve the CPU. With the help of FPGA, multiple HT bus interfaces can be simulated. As a result, multiple chipsets can be linked to the Loongson CPU, which may be debugged simultaneously. | 06-05-2014 |
20140164832 | TEST CIRCUIT AND METHOD FOR PROCESSING A TEST ROUTINE - According to one embodiment, a test circuit is provided comprising a tester configured to perform a test routine comprising a plurality of test commands for testing an electronic circuit, wherein the tester comprises a checker configured to, if a test command of the plurality of test commands is to be performed, check, whether there is currently a state in which performing the test command could lead to a damage of the electronic circuit and configured to, in case it determines that there is currently a state in which performing the test routine could lead to a damage of the electronic circuit, output a signal indicating that performing the test routine could lead to a damage of the electronic circuit. | 06-12-2014 |
20140164833 | BUILT-IN SELF-TEST FOR STACKED MEMORY ARCHITECTURE - A built-in self-test for stacked memory architecture. An embodiment of a memory device includes a memory stack including one or more DRAM (dynamic random access memory) elements; and a system element for control of the memory stack. The system element includes a built-in self-test (BIST) engine to generate a write test event or a read test event for the memory stack, a test interface to receive test data for write test event or the read test events from the BIST engine, and a memory controller, the memory control to receive at least a portion of the test data from the test interface and to implement the write test event or read test event at the DRAM elements of the memory stack. | 06-12-2014 |
20140164834 | APPARATUS AND A METHOD FOR MEMORY TESTING BY A PROGRAMMABLE CIRCUIT IN A SAFETY CRITICAL SYSTEM - The invention relates to a method and apparatus. In the method, a programmable random access memory testing circuit detects a signal to initiate testing of at least one random access memory circuit, the testing circuit being connected to a bus to which a processor and the at least one memory circuit is connected, the at least one memory circuit comprising at least a first memory block. The testing circuit determines that the bus is not reserved and reserves the bus. The testing circuit reads application data in a first memory block to a temporary memory of the testing circuit. The testing circuit executes marching test for the first memory block in a memory circuit. The testing circuit returns the application data back to the first memory block in the memory circuit. The testing circuit releases the bus. | 06-12-2014 |
20140173342 | DEBUG ACCESS MECHANISM FOR DUPLICATE TAG STORAGE - A coherence system includes a storage array that may store duplicate tag information associated with a cache memory of a processor. The system may also include a pipeline unit that includes a number of stages to control accesses to the storage array. The pipeline unit may pass through the pipeline stages, without generating an access to the storage array, an input/output (I/O) request that is received on a fabric. The system may also include a debug engine that may reformat the I/O request from the pipeline unit into a debug request. The debug engine may send the debug request to the pipeline unit via a debug bus. In response to receiving the debug request, the pipeline unit may access the storage array. The debug engine may return to the source of the I/O request via the fabric bus, a result of the access to the storage array. | 06-19-2014 |
20140173343 | Method and Apparatus For Supporting A Unified Debug Environment - A field programmable gate array (FPGA) includes a soft processor and a soft processor debug unit implemented by programmable logic on the FPGA. The FPGA includes a system on a chip (SOC) that includes a hard processor and a hard processor debug unit. The FPGA includes a bus bridge, coupled to an input output (IO) of the FPGA, operable to transmit data between the IO and the soft processor debug unit and the hard processor debug unit. | 06-19-2014 |
20140173344 | PROGRAMMABLE BUILT-IN-SELF TESTER (BIST) IN MEMORY CONTROLLER - Some novel features pertain to a memory controller that includes a memory controller logic, a built-in-self-tester (BIST) logic, and a switch. The memory controller logic is for controlling memory on a memory die. The built-in-self tester (BIST) logic is for testing the memory. The switch is coupled to the BIST logic and the memory. In some implementations, the BIST logic bypasses the memory controller logic when testing the memory by accessing the memory through the switch. The switch may be controlled by the BIST logic. In some implementations, the switch is coupled to the memory controller logic. The switch may control data to the memory that is transmitted from the memory controller logic and the BIST logic based on priority of the data. | 06-19-2014 |
20140173345 | MEMORY BIT MBIST ARCHITECTURE FOR PARALLEL MASTER AND SLAVE EXECUTION - A scalable, reconfigurable Memory Built-In Self-Test (MBIST) architecture for a semiconductor device, such as a multiprocessor, having a Master and one or more Slave MBIST controllers is described. The MBIST architecture includes a plurality of MBISTDP interfaces connected in a ring with the Master MBIST controller. Each MBISTDP interface connects to at least one Slave controller for forwarding test information streamed to it from the Master MBIST controller over the ring. Test information includes test data, address, and MBIST test commands. Each MBISTDP interface forwards the information to the Slave controller attached thereto and to the next MBISTDP interface on the ring. Test result data is sent back to the Master MBIST controller from the MBISTDP interfaces over the ring. | 06-19-2014 |
20140173346 | VALIDATING OPERATION OF SYSTEM-ON-CHIP CONTROLLER FOR STORAGE DEVICE USING PROGRAMMABLE STATE MACHINE - A system-on-chip includes a storage controller, a read channel integrated circuit, a programmable state machine controller, a switching circuit, a buffer memory, and an interface to access the buffer memory. The switching circuit connects the storage controller or the programmable state machine controller to the read channel integrated circuit. The interface is used to store test control data in the buffer memory. In a given test mode, the switching circuit switchably connects the programmable state machine controller to the read channel integrated circuit. The programmable state machine controller is enabled to access the test control data from the buffer memory, and to process the test control data to generate test signals that are applied to operate the read channel integrated circuit and validate operation of the system-on-chip based on the operation of the read channel integrated circuit. | 06-19-2014 |
20140208160 | AUTOMATED TEST PLATFORM - A segmented subsystem, for use within an automated test platform, includes a first subsystem segment including a first data sequencer configured to coordinate the execution of one or more instructions within the first subsystem segment. A second subsystem segment includes a second data sequencer configured to coordinate the execution of one or more instructions within the second subsystem segment. | 07-24-2014 |
20140208161 | SCALABLE TEST PLATFORM - A scalable test platform includes a PCIe-based event fabric. One or more CPU subsystems are coupled to the PCIe-based event fabric and configured to execute an automated test process. One or more instrument subsystems are coupled to the PCIe-based event fabric and configured to interface one or more devices under test. | 07-24-2014 |
20140258780 | MEMORY CONTROLLERS INCLUDING TEST MODE ENGINES AND METHODS FOR REPAIR OF MEMORY OVER BUSSES USED DURING NORMAL OPERATION OF THE MEMORY - Examples of memory controllers are described that may repair a memory using a bus between the memory controller and the memory. The memory controllers may include a test mode engine able to place the memory into a test mode of operation using a combination of signals over the bus, which combination of signals may be illegal in normal operation. The memory system controllers may include a BIST engine for testing the memory and obtaining information regarding memory fail information. The test mode engines may be configured to adjust a clock frequency during the test mode of operation, including stopping a clock signal in some examples between test mode commands. | 09-11-2014 |
20140281716 | ANALOG BLOCK AND TEST BLOCKS FOR TESTING THEREOF - An apparatus relating generally to a system-on-chip is disclosed. In this apparatus, the system-on-chip has at least one analog block, an input/output interface, a data test block, and a processing unit. The processing unit is coupled to the input/output interface to control access to the at least one analog block. The data test block is coupled to the at least one analog block through the input/output interface. The processing unit is coupled to the data test block and configured to execute test code having at least one test pattern. The data test block under control of the test code executed by the processing unit is configured to test the at least one analog block with the test pattern. | 09-18-2014 |
20140281717 | BUILT-IN SELF TEST (BIST) WITH CLOCK CONTROL - A processing system includes a clock generator circuit configured to receive a master clock signal and to output a plurality of clock signals, wherein the plurality of clock signals have a first frequency during a built-in self-test (BIST) mode and a plurality of shift-capture clock generator circuits. Each shift-capture clock generator circuit includes a clock gate circuit and a clock divider circuit and is configured to receive a corresponding one of the plurality of clock signals. At least one of the clock divider circuits changes the first frequency of the one of the plurality of clock signals to a second frequency during the BIST mode. | 09-18-2014 |
20140281718 | COMPUTER-ON-MODULE DEBUG CARD ASSEMBLY AND A CONTROL SYSTEM THEREOF - A computer-on-Module debug card assembly and a control system thereof comprising: a carrier module with a carrier board and electronic components thereon wherein the carrier board is provided with a plurality of I/O connectors and at least a bus; a debug module electrically connected to the carrier board and comprising a debug card and electronic components thereon wherein the debug card is equipped with a detecting component, at least a bus, and a plurality of switch buttons used to check switching; a COM express system electrically connected to the debug card and comprising a COM express board and electronic components thereon wherein the COM express board is provided with modular components and at least a bus. As such, it is able to identify messages for a CPU-bearing COM express board and a carrier board in the COM express system during debugging, streamlining the procedure and saving time. | 09-18-2014 |
20140298094 | PROCESSOR POWER MEASUREMENT - A system can include a processing core to execute machine readable instructions. The system can also include a memory accessible by the processor core. The memory can include preprogrammed test data that characterizes one of an impedance of a processor and a current output to the processor during execution of a test routine. The processor can include the processing core and the one of the impedance of the processor and the current output to the processor is based on a power measurement taken during execution of a test routine. The power measurement can be taken with a current sensor that is at least one of lossy or at least about 98% accurate. | 10-02-2014 |
20150026519 | SERIAL ATTACHED SMALL COMPUTER SYSTEM INTERFACE EXPANDER AND DEBUGGING METHOD - A serial attached Small Computer System Interface (SAS) expander comprises a SAS expander chip which comprises a first debug port and a second debug port, a controlling chip which is in communication with the first debug port through a first serial port, in communication with the second debug port through a second serial port, and in communication with a host computer through a third serial port, once the controlling chip controls the third serial port to receive a debug command from the host computer, the controlling chip sends the received debug command to the first debug port or the second debug port according to a reference table. | 01-22-2015 |
20150026520 | DEBUGGING CIRCUIT - A debugging circuit comprises a debugging interface, a switch unit coupled to the debugging interface, a controller coupled to the switch unit, a platform controller hub (PCH), and a central processing unit (CPU). The PCH and the CPU are coupled to the switch unit. The debugging interface is coupled between the switch unit and a debugging device. The switch unit receives a control signal from the controller, and selectively outputs a first data signal from the PCH or a second data signal from the CPU to the debugging device through the debugging interface according to the control signal. | 01-22-2015 |
20150033075 | CACHE DEBUG SYSTEM FOR PROGRAMMABLE CIRCUITS - An integrated circuit may be provided with system-on-chip circuitry including system-on-chip interconnects and a microprocessor unit subsystem. The subsystem may include microprocessor cores that execute instructions stored in memory. Cache may be used to cache data for the microprocessor cores. A memory coherency control unit may be used to maintain memory coherency during operation of the microprocessor unit subsystem. The memory coherency control unit may be coupled to the system-on-chip interconnects by a bus. A command translator may be interposed in the bus. The command translator may have a slave interface that communicates with the interconnects and a master interface that communicates with the memory coherency control unit. The integrated circuit may have programmable circuitry that is programmed to implement a debug master coupled to the interconnects. During debug operations, the command translator may translate commands from the debug master. | 01-29-2015 |
20150058668 | OPTIMAL TEST FLOW SCHEDULING WITHIN AUTOMATED TEST EQUIPMENT FOR MINIMIZED MEAN TIME TO DETECT FAILURE - The present invention describes a method and system for optimizing a test flow within each ATE (Automated Test Equipment) station. The test flow includes a plurality of test blocks. A test block includes a plurality of individual tests. A computing system schedule the test flow based one or more of: a test failure model, test block duration and a yield model. The failure model determines an order or sequence of the test blocks. There are at least two failure models: independent failure model and dependant failure model. The yield model describes whether a semiconductor chip is defective or not. Upon completing the scheduling, the ATE station conducts tests according to the scheduled test flow. The present invention can also be applied to software testing. | 02-26-2015 |
20150058669 | Method and Apparatus for Error Management of an Integrated Circuit System - An apparatus and method for error management in an integrated circuit system are presented. An error management unit (EMU) apparatus manages critical and non-critical errors that may be masked or non-masked. An EMU includes an EMU state machine, having a BOOT state, a CONFIG state, a FUNCT state, a WARNING state and an ERROR state. The method discloses transitions in the EMU state machine. While in the ERROR state an error reaction may be applied. The objective of the error reaction is to recover errors by software and hardware means. The EMU may further appropriately alert the system while in ERROR state and therefore be used as a safety mechanism permitting to collect error signals issued by fault detector units and can further cause action on faulty units for recovery purposes. | 02-26-2015 |
20150074459 | SYSTEM ON CHIP INCLUDING BUILT-IN SELF TEST CIRCUIT AND BUILT-IN SELF TEST METHOD THEREOF - A system on chip is provided which performs a built-in self-test operation using an error access pattern. The system on chip includes a master device and a slave device. A bus is configured to transfer an instruction from the master device to the slave device. A built-in instruction capture circuit is configured to receive and store the instruction. The built-in instruction capture circuit stores the instruction as the error access pattern when an error occurs in the slave device due to the instruction. | 03-12-2015 |
20150082092 | DEBUG APPARATUS AND METHODS FOR DYNAMICALLY SWITCHING POWER DOMAINS - Methods and apparatus are provided that facilitate debugging operations for components that may include different power domains. In an embodiment, an integrated circuit (IC) includes a plurality of hardware sectors, each hardware sector associated with a debug observability circuit that is served by a debug data bus of a debug circuit. The plurality of hardware sectors includes a controlled sector residing in a dynamically-controlled power domain that may be turned off while the power domain of another sector remains on. A selectively switchable data bus component is configured to couple the debug observability circuit associated with the controlled sector to the debug data bus when the power to the controlled sector is on and to switch to bypass the debug observability circuit associated with the controlled sector when the power to the controlled sector is not on. | 03-19-2015 |
20150082093 | DEBUG APPARATUS AND METHODS FOR DYNAMICALLY SWITCHING POWER DOMAINS - Methods and apparatus are provided that facilitate debugging operations for components in dynamic power domains. In an embodiment, an integrated circuit includes hardware sectors associated with observability circuits served by a debug data bus of a debug circuit. A controlled sector residing in a dynamically-controlled power domain may be turned off while the power domain of another sector remains on. To continue to have debug observability all the way through and after these power events, a debug data register is configured to provide data, such as configuration and/or programming data, to the observability circuit of the controlled sector via the debug data bus. A shadow register is configured to capture the data provided to the controlled sector's observability circuit. The shadow register data is used upon restoring power to the controlled sector to restore the controlled sector's observability circuit to a state when the controlled sector was previously powered on. | 03-19-2015 |
20150089288 | TECHNIQUE FOR ESTABLISHING AN AUDIO SOCKET DEBUG CONNECTION - A debug controller monitors a tip-ring-ring-shield (TRRS) socket, within a form factor device, to detect whether a debug unit is transmitting a request for a TRRS socket debug connection. The form factor device also includes a system on chip (SoC), a switch, and an audio codec. The SoC includes the debug controller and a software debug interface. The switch couples a right audio lead and left audio lead of the TRRS socket to the audio codec. If the debug controller detects the request from the debug unit, then the debug controller instructs the switch to establish a TRRS socket debug connection. The switch establishes the TRRS socket debug connection by coupling right audio lead and left audio lead to the software debug interface instead of the audio codec. This establishment of the TRRS socket debug connection eliminates the need for manual configuration of the TRRS socket debug connection. | 03-26-2015 |
20150089289 | PROGRAMMABLE INTERFACE-BASED VALIDATION AND DEBUG - A programmable interface-based validation and debug system includes, for example, a test connector that is arranged to communicatively couple a design under test to the test fixture. A programmable logic interface is communicatively coupled to the test connector and is arranged to receive a downloadable test bench, where the downloadable test bench is arranged to apply test vectors from a first set of test vectors to a first test control bus. A multiplexer is arranged to selectively couple one of the first test control bus and a second test control bus to a shared test bus that is coupled to the test connector, where the second test control bus is arranged to apply test vectors from a second set of test vectors provided by, for example, a debugger that is operated by a human. | 03-26-2015 |
20150127983 | TEST, VALIDATION, AND DEBUG ARCHITECTURE - An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms. | 05-07-2015 |
20150135014 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR EFFICIENT SCRAMBLING OF DATA FOR LINE RATE TRANSMISSION IN HIGH SPEED COMMUNICATIONS NETWORKS - The subject matter described herein includes methods, systems, and computer readable media for efficiently scrambling data in high speed communications networks. One exemplary method includes, in a network equipment test device, providing a scrambler for scrambling data to be transmitted to a device under test. Scrambling the data includes separating a scrambling algorithm into a scramble key portion and a data portion. Scrambling the data further includes pre computing and storing the scramble key portion. Scrambling the data further includes precomputing and storing the data portion. Scrambling the data further includes logically combining the precomputed scramble key portion with the precomputed data portion to produce a data bus width scrambled output data. The method further includes transmitting the scrambled output data over a network to the device under test. | 05-14-2015 |
20150301915 | PROCESSOR WITH DEBUG PIPELINE - A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline. | 10-22-2015 |
20150339205 | BUILT-IN TEST FOR SATELLITE DIGITAL PAYLOAD VERIFICATION - According to an embodiment, a testing system for a satellite payload includes a built-in testing component configured at a satellite, the built-in testing component comprising a built-in testing component input and a built-in testing component output, and a payload component configured at the satellite, the payload component comprising a payload component input communicatively connected to the built-in testing component output and a payload component output communicatively connected to the built-in testing component input, wherein the built-in testing component is configured to transmit a digital test signal from the built-in testing component output to the payload component input and receive a digital output signal at the built-in testing component input from the payload component output. | 11-26-2015 |
20160062865 | SYSTEMS AND METHODS FOR PROCESSING TEST RESULTS - Systems and methods for processing test results. A method of analyzing test results includes receiving a set of test result files, the set of test result files including a plurality of test results. The method also includes identifying a set of data filters based on one or more of the set of test result files or user input. The method further includes generating filtered results based on the set of data filters and the set of test result files, the filtered results including one or more of a subset of the plurality of test results or reordered test results. The method further includes providing a visual representation of the filtered results. | 03-03-2016 |
20160077943 | INPUT MODULE FOR PROGRAMMABLE LOGIC CONTROLLER - The invention relates to an input module ( | 03-17-2016 |
20160098332 | DYNAMIC MULTI-PURPOSE EXTERNAL ACCESS POINTS CONNECTED TO CORE INTERFACES WITHIN A SYSTEM ON CHIP (SOC) - An integrated circuit device comprises multiple cores each comprising one or more separate input and output interfaces, the multiple cores integrated within the integrated circuit device to function as a single computer system. Internal inter-chip connection links are disposed on the integrated circuit device for connecting one or more cores with at least one other core via the one or more separate input and output interfaces. One or more bidirectional access ports are communicatively connected in each path of the inter-chip connection links to enable a separate external access point to each of the one or more separate input and output interfaces of the cores, wherein each of the one or more bidirectional access ports is dynamically selectable as each of an external input interface of the integrated circuit device and an external output interface of the integrated circuit device. | 04-07-2016 |
20160124822 | EMBEDDED UNIVERSAL SERIAL BUS (USB) DEBUG (EUD) FOR MULTI-INTERFACED DEBUGGING IN ELECTRONIC SYSTEMS - Embedded Universal Serial Bus (USB) debug (EUD) for multi-interfaced debugging in electronic systems are disclosed. Electronic systems contain complex integrated circuits (ICs) that require extensive testing and debugging to ensure good quality and performance. In exemplary aspects, an EUD is provided in an electronic system. The EUD is configured to send control information to and/or collect debugging information from multiple internal debugging interfaces in the electronic system. The EUD is also configured to convert the debugging information into a USB format so that the debugging information can be externally accessed through a USB interface provided by the electronic system. The EUD can provide non-invasive monitoring of the electronic system. The electronic system is able to use a USB port for communications in a mission mode while EUD is enabled. Additionally, the electronic system can turn on or off all system clocks during power-saving mode while the EUD continues to function. | 05-05-2016 |
20160124826 | SEMICONDUCTOR DEVICE AND METHOD FOR TESTING RELIABILITY OF SEMICONDUCTOR DEVICE - A semiconductor memory includes a memory controller including a plurality of processing circuits. The plurality of processing units includes an encryption/decryption unit that encrypts and decrypts a signal transmitted to and from the memory controller. The encryption/decryption unit includes a self test unit that performs a reliability test of the encryption/decryption unit on receipt of a predetermined test command from a testing device. | 05-05-2016 |
20160154719 | OPTIMAL TEST FLOW SCHEDULING WITHIN AUTOMATED TEST EQUIPMENT FOR MINIMIZED MEAN TIME TO DETECT FAILURE | 06-02-2016 |
20160179646 | DELAYED AUTHENTICATION DEBUG POLICY | 06-23-2016 |
20170235656 | SYSTEMS AND METHODS FOR INVASIVE DEBUG OF A PROCESSOR WITHOUT PROCESSOR EXECUTION OF INSTRUCTIONS | 08-17-2017 |