Class / Patent application number | Description | Number of patent applications / Date published |
714023000 | Resetting processor | 52 |
20080215917 | Synchronizing Cross Checked Processors During Initialization by Miscompare - A few inexpensive hardware facilities are incorporated in a tightly synchronized cross checked design. These facilities allow initialization software to quickly bring the two processors to the same state by rapid, repeated resets and execution of the initialization software. The resets are done in a way as to be transparent to the rest of the system and to the end user. | 09-04-2008 |
20080301498 | Control device and control method - A control device and a control method for increasing stability of micro controller system are described. The control device comprises a system error detection unit a memory unit, a data error detection unit, an error signal processing unit and a system resetting unit. When the system is error or the data transferred from the memory unit has error, the system error detection unit or the data error detection unit outputs an error signal to the error signal processing unit, and then the error signal processing unit corrects the error data or commands the system resetting unit to reset the system by the error signal for increasing the system stability. | 12-04-2008 |
20080307259 | SYSTEM AND METHOD OF RECOVERING FROM FAILURES IN A VIRTUAL MACHINE - A method and systems for recovering from a failure in a virtual machine are provided. In accordance with one embodiment of the present disclosure, a method for recovering from failures in a virtual machine is provided. The method may include, in a first physical host having a host operating system and a virtual machine running on the host operating system, monitoring one or more parameters associated with a program running on the virtual machine, each parameter having a predetermined acceptable range. The method may further include determining if the one or more parameters are within their respective predetermined acceptable ranges. In response to determining that the one or more parameters associated with the program running on the virtual machine are not within their respective predetermined acceptable ranges, a management module may cause the application running on the virtual machine to be restarted. | 12-11-2008 |
20090019309 | METHOD AND COMPUTER PROGRAM PRODUCT FOR DETERMINING A MINIMALLY DEGRADED CONFIGURATION WHEN FAILURES OCCUR ALONG CONNECTIONS - A minimally degraded configuration is determined when failing connections occur. Associative deconfigurations are determined from deconfiguring hardware items in a server system, associative groups are derived, and failed connections are determined. Failed connections are determined between two hardware items that are in the same associative group, and the two hardware items at both endpoints of the failed connection are deconfigured. Each associative group state is set to unknown, and the failed connections are counted where a single endpoint of the failed connection is within the associative group. The associative group state is set to deconfigured, if a member of the associative group was deconfigured. Counts of the associative groups that remain in the unknown state are analyzed, and the associative group with the smallest failed connection count is selected and set to a configured state. The other associative group at the other end is set to a deconfigured stated, and the hardware item in the other associative group is deconfigured. | 01-15-2009 |
20090089615 | FIELD REPAIRABLE LOGIC - A state matcher for a logic circuit may detect at least one of a buggy state of the logic circuit, a precursor to a buggy state of the logic circuit and a verified state of the logic circuit based on a plurality of signal values indicative of a state of the logic circuit. A recovery controller for a microprocessor may reconfigure the microprocessor to a trusted feature mode in response to receiving a signal indicating that the microprocessor is in a predefined state and operate the microprocessor in the trusted feature mode for a predetermined period of time. | 04-02-2009 |
20090199044 | Device self-maintenance - Software running on a processor is operable to control the cycled powering down and powering up of components of a self-service terminal (SST) in order to attempt to rectify a fault within the SST without the need to power down the SST core processor. The software can also control the resetting of universal serial bus (USB) ports associated with the components of the SST in order to try and clear faults associated with a communications link between a component and the SST core processor. | 08-06-2009 |
20100037098 | TERMINATE OPERATIONS FOR COMPLEX I/O LINK - Method, system and computer program product embodiments for, in an input/output (I/O) link handling complex instruction chains, a messaging scheme incorporating a method of error recovery between an initiator processor and a receiver processor, are provided. An operation initiation message is been sent from the initiator processor to the receiver processor for the receiver processor to begin work on an operation. If determined to be necessary, a terminate operation message is sent from the initiator processor to the receiver processor. The initiator processor withholds sending additional messages for the operation until a terminate operation response message is received. Once the terminate operation message is received, outstanding messages in process are flushed from the receiver processor. The receiver processor withholds sending additional messages to the initiator processor as the outstanding messages are completed. The terminate operation response message is sent from the receiver processor to the initiator processor. | 02-11-2010 |
20100083043 | INFORMATION PROCESSING DEVICE, RECORDING MEDIUM THAT RECORDS AN OPERATION STATE MONITORING PROGRAM, AND OPERATION STATE MONITORING METHOD - The device and method includes outputting a subsistence signal repeatedly that indicates that an information processing device is normally operating when the information processing unit is normally operating, executing a memory dump processing, if necessary, when a fault occurs in the information processing unit, monitoring whether another subsistence signal is output within a first time period after the subsistence signal is output, and determining whether or not the memory dump processing is being executed, requesting a restart or a shutdown of the information processing device if the memory dump processing is not being executed, and requesting the restart or the shut down of the information processing device after a second time period passes if the memory dump processing is being executed. | 04-01-2010 |
20100100766 | TEST APPARATUS - A test apparatus for testing a portable communication unit. The test apparatus comprises a test unit adapted to supply test input data to the portable communication unit and retrieve test output data at least from the portable communication unit in accordance with a test schedule. The test apparatus further comprises a wireless interface unit adapted to provide a communication link between the test apparatus and a server located remotely from the test apparatus. The test unit is adapted to retrieve, from the server, at least part of the test input data. Moreover, the test unit is adapted to forward, to the server, at least part of the test output data. A method of testing the portable communication unit is also disclosed. | 04-22-2010 |
20100162045 | METHOD, APPARATUS AND SYSTEM FOR RESTARTING AN EMULATED MAINFRAME IOP - A method, apparatus and system for restarting an emulated mainframe IOP, such as a failed or hung emulated mainframe IOP within an emulated mainframe commodity computer. The method includes a rescue process that polls a home location for Restart Request information. In response to receiving Restart Request information, the rescue process is configured to shut down the existing emulated mainframe IOP, start a new emulated mainframe IOP, and reset the home location. The Restart Request information can be provided to the home location by the mainframe computer being emulated. Alternatively, the rescue mechanism can use an interface management card instructed to restart the commodity computer hosting the failed or hung IOP, e.g., from a maintenance service and/or a maintenance program residing in an active commodity computer coupled to the commodity computers hosting one of several emulated mainframe IOPs. | 06-24-2010 |
20100211824 | SYSTEMS AND METHODS FOR MEMORY RETENTION ACROSS RESETS - Systems and methods (“utility”) for providing a computer system with a mechanism to record live data on a continuous basis which may be analyzed subsequent to a fault condition is provided. The utility uses the existing DRAM memory of a computer system as a retentive DRAM (RDRAM) device that may be used to store the data. To accomplish this, software and firmware is provided for continuously refreshing the DRAM memory across resets that are due to fault conditions. Further, non-maskable interrupts (NMI) are used to flag a variety of fault conditions to the computer system. To make the utility platform independent, a standardized power and configuration interface is used to implement a computer system reset that preserves the contents of the RDRAM. | 08-19-2010 |
20100268988 | SECURE FLASH MEMORY USING ERROR CORRECTING CODE CIRCUITRY - A processor and memory system includes memory, a table of exceptions, and a processor. The memory includes a plurality of memory blocks. The table of exceptions identifies at least one of the plurality of memory blocks that includes an expected error. The processor diagnoses a security fault based on data stored in at least one of the plurality of memory blocks and the table of exceptions. | 10-21-2010 |
20100332902 | Power efficient watchdog service - An electronic device comprises a first processor, a computer readable memory medium and logic instructions stored in the computer readable medium which, when executed by the first processor, configure the first processor to implement a watchdog module which monitors an operating status of one or more critical processes executing on the first processor and implements a recovery process when the one or more of the critical processes executing on the first processor fails. The device further comprises a system controller unit coupled to the first processor by a communication bus, wherein system controller unit activates the watchdog module periodically and only when the first processor is in at least one predetermined power state. Other embodiments may be described. | 12-30-2010 |
20110041009 | MANAGING EXTRINSIC PROCESSES - Methods, program products, and systems for monitoring extrinsic processes are described. A monitoring process can monitor one or more target processes. The target processes can be extrinsic, e.g., not spawned by the monitoring process. The monitoring process reads a process registry to identify which processes among multiple processes to monitor. The monitoring process can send status requests to the identified target processes periodically to check whether the target processes are healthy. If a target process is terminated, the monitoring process determines whether the termination is normal (e.g., by a user), or abnormal (e.g., the target process crashed). The monitoring process can restart the abnormally terminated or hung target process. | 02-17-2011 |
20110087921 | REPRODUCING APPARATUS, INTEGRATED CIRCUIT, AND REPRODUCING METHOD - A reproducing apparatus | 04-14-2011 |
20110179307 | FAILOVER METHOD AND SYSTEM FOR A COMPUTER SYSTEM HAVING CLUSTERING CONFIGURATION - A failover control method for a virtual computer system including a plurality of virtual computers including: monitoring a second virtual computer via a first line by a first virtual computer among the plurality of virtual computers; detecting a malfunction of the second virtual computer by the first virtual computer; receiving from the other virtual computers a notification including a monitoring result for the second virtual computer in the other virtual computers among the plurality of virtual computers by the first virtual computer; relating the monitoring result to the detected malfunction of the second virtual computer to correspond to each other; judging whether or not the correspondence between the monitoring result and the detected malfunction of the second virtual computer satisfies a predetermined condition; and giving the second computer a reset instruction via a second line, when the predetermined condition is satisfied. | 07-21-2011 |
20110202795 | DATA CORRUPTION PREVENTION DURING APPLICATION RESTART AND RECOVERY - Embodiments of the present invention are directed to a method and system for draining or aborting IO requests of a failed system prior to restarting or recovering an application in virtual environments. The method includes detecting, within an electronic system, an application error condition of an application executing on a virtual machine and determining an application restart target. The method further includes sending an input/output (IO) request drain command to a virtual IO server operable to provide storage to the virtual machine and receiving a signal that the IO requests have been drained. The drain command is operable to drain IO requests issued from the application. The application can then be restarted or recovered. | 08-18-2011 |
20110202796 | MICROPROCESSOR WITH SYSTEM-ROBUST SELF-RESET CAPABILITY - A microprocessor includes a bus interface unit that interfaces the microprocessor to a bus that includes a signal that, when asserted, instructs all bus agents to refrain from initiating bus transactions. Microcode causes the bus interface unit to assert the signal in response to detecting an event and resets the microprocessor, but does not reset a portion of the bus interface unit that asserts the signal on the bus. After the reset, the microcode causes the bus interface unit to deassert the signal on the bus. Additionally, the microcode sets a flag and saves the microprocessor state to memory before resetting itself, but does not reset the interrupt controller. After the reset, the microcode reloads the state of the microprocessor from the memory. However, if the microcode determines that the flag is set, it forgoes reloading the state of the interrupt controller. | 08-18-2011 |
20110314328 | DEVICE FOR DETERMINING AN ERROR INDUCED BY A HIGH-PASS FILTER AND ASSOCIATED ERROR CORRECTION METHOD - Device for determining an error induced by a high-pass filter in a signal, including a unit ( | 12-22-2011 |
20120030512 | PROVISIONING OF DATA TO A VEHICLE INFOTAINMENT COMPUTING SYSTEM - Various embodiments include a software provisioning system and method for a vehicle infotainment computer. Software provisioning of the vehicle infotainment computer may occur during vehicle assembly. A software provisioning request may be received for custom installing software to the vehicle infotainment computer. The custom install may be based on a customization schedule which may include a location identifier (such as uniform resource identifiers or file paths) for locating the software. In response to the request, the software may be located on a provisioning server or a portable memory device based on the customization schedule. The software may be transmitted to memory of the vehicle infotainment computer and custom installed on the vehicle infotainment computer. | 02-02-2012 |
20120102358 | SERVER HAVING MEMORY DUMP FUNCTION AND MEMORY DUMP ACQUISITION METHOD - A server having a plurality of system boards, comprising: a panic processing unit configured to stop (panic) the server; a system board information storage unit configured to store information to identify a system board having a memory used by a kernel; a system board detaching processing unit configured to detach the system board having the memory used by the kernel before server stoppage; and a reboot processing unit configured to reboot the server using system boards other than the separated system board among the plurality of system boards, after detaching the system board having the memory used by the kernel. | 04-26-2012 |
20120124420 | RESET METHOD AND MONITORING APPARATUS - A reset method performs a software reset in a state in which data in a volatile memory is retained, when an abnormality is generated in a monitoring apparatus. Hardware of the monitoring apparatus may include a function to perform a hardware reset in a state in which the data in the volatile memory is retained, but the software reset is performed with respect to the hardware that does not include such a hardware reset function. The volatile memory may store control information for controlling a host computer monitored by the monitoring apparatus, in addition to data including fault check materials to be retained when the fault is generated. The monitoring apparatus may read the fault information from the hardware to judge whether an abnormal value is reached. | 05-17-2012 |
20120159245 | ENHANCED ERROR HANDLING FOR SELF-VIRTUALIZING INPUT/OUTPUT DEVICE IN LOGICALLY-PARTITIONED DATA PROCESSING SYSTEM - Error handling is simplified for a self-virtualizing IO resource that utilizes a physical function adjunct partition for a physical function in the self-virtualizing IO resource to coordinate error recovery for the self-virtualizing IO resource, by restarting each virtual function adjunct partition associated with that physical function to avoid the need to coordinate error recovery within the logical partitions to which such virtual function adjunct partitions are assigned. | 06-21-2012 |
20120159246 | SCALING OUT A MESSAGING SYSTEM - A messaging system may operate on multiple processor partitions in several configurations to provide queuing and topic subscription services on a large scale. A queue service may receive messages from a multiple transmitting services and distribute the messages to a single service. A topic subscription service may receive messages from multiple transmitting services, but distribute the messages to multiple recipients, often with a filter applied to each recipient where the filter defines which messages may be transmitted by the recipient. Large queues or topic subscriptions may be divided across multiple processor partitions with separate sets of recipients for each partition in some cases, or with duplicate sets of recipients in other cases. | 06-21-2012 |
20120166873 | SYSTEM AND METHOD FOR HANDLING SYSTEM FAILURE - A system and a method for handling a system failure are disclosed. The method is adapted for an information handling system having a basic input and output system and a micro-controller. The method includes the following steps: sending, via the micro-controller, a signal; checking, via the micro-controller, whether an acknowledgement is received from the basic input and output system responsive to the signal; and scanning, via the micro-controller, a type of a system failure in response to the acknowledgement being not received. | 06-28-2012 |
20120216075 | METHOD, SYSTEM AND ARTICLE OF MANUFACTURE FOR SYSTEM RECOVERY - Provided are a method, system, and article of manufacture for system recovery. An operating system and a backup copy of the operating system are both maintained in a partition of a computational device. A boot loader receives an indication to load the backup copy of the operating system. The boot loader loads the backup copy of the operating system. The computational device is rebooted with the loaded backup copy of the operating system. | 08-23-2012 |
20120233498 | HIERARCHICAL ERROR CORRECTION FOR LARGE MEMORIES - A mechanism is provided for detecting and correcting a first number of bit errors in a segment of data stored in a memory region being read, while concurrently detecting the presence of higher numbers of bit errors in that segment of data. In the event of detection of a higher number of bit errors in any single segment of data of the memory region, error correction of that higher number of bit errors is performed on the memory region, while concurrently detecting the presence of an even higher level of bit errors. By performing error correction of higher levels of bit errors in such a hierarchical order, memory latency associated with such error correction can be avoided in the majority of data accesses, thereby improving performance of the data access. | 09-13-2012 |
20120233499 | Device for Improving the Fault Tolerance of a Processor - A device for improving the fault tolerance of a processor installed on a motherboard, the motherboard comprising memory units and a data input/output interface, the processor being able to execute at least one application, includes: a software layer, called a hypervisor, centralizing exchanges between the said processor and the said application and implementing fault tolerance management mechanisms, and a programmable electronic component forming an interface between the processor on the one hand. | 09-13-2012 |
20120278654 | REMOTE CABLE ACCESS POINT RESET - The system monitors a wireless device, detects when the device has failed or is not operating properly, and is able to remotely reset the device. The device may be reset remotely without a technician required to physically attend to the device. This out of band management allows for quicker, cheaper and more efficient handling of undesired states of a device, such as failure to operate. For a modem, the system may detect that the modem is not broadcasting a signal or is not communicating with the Internet or other network. The reset may be implemented through an access point in communication with the malfunctioning modem. For an access point, the system may detect that the access point is not communicating with a modem or another access point. The reset may be implemented by a neighboring access point or modem. | 11-01-2012 |
20120331342 | ADDING SCALABILITY AND FAULT TOLERANCE TO GENERIC FINITE STATE MACHINE FRAMEWORKS FOR USE IN AUTOMATED INCIDENT MANAGEMENT OF CLOUD COMPUTING INFRASTRUCTURES - A scalable and fault tolerant finite state machine engine, for example, for use in an automated incident management system, logs or records data in persistent storage at different points or levels during various internal processing of an event associated with an information technology element, and action taken associated with the event, by executing a finite state machine instance that encodes policies for handling incidents on such types of information technology elements. In the event that the finite state machine engine is shutdown during processing, the finite state machine engine is able to pick up from where it left off when it was shutdown, for each abnormally terminated finite state machine instance, by using the data logged in the persistent storage and determining a point of processing from where it should continue its execution. | 12-27-2012 |
20130019123 | STORAGE SYSTEM AND COMMUNICATIONS METHOD - Storage system arrangement wherein: when a transmission destination determines that a source-side serial number included in a received packet is the same as a current destination-side serial number in the transmission destination, the transmission destination processes a content of the received packet in accordance with a command included in the received packet; and when the transmission destination determines that the source-side serial number is not the same as the current destination-side serial number, the transmission destination does not process a content of the received packet. | 01-17-2013 |
20130036329 | UPDATING ROUTING AND OUTAGE INFORMATION IN A COMMUNICATIONS NETWORK - After power is restored to a node in a utility network, that node employs one or more of its neighboring nodes as proxies to route a message to a central control facility of the utility. The message contains information about the restored node, and possibly one or more of its neighbor nodes. This information may include reboot counters, the amount of time that the node was down, momentary outages or power fluctuations, and/or the time of power restoration. The node that creates and initially sends the message can be the restored node itself, or another node that recognizes when a restored node has recently come back online. | 02-07-2013 |
20130166952 | DATA PROCESSING APPARATUS WITH AN EXECUTION PIPELINE AND ERROR RECOVERY UNIT AND METHOD OF OPERATING THE DATA PROCESSING APPARATUS - A data processing apparatus executes instructions in a sequence of pipelined execution stages. An error detection unit twice samples a signal associated with execution of an instruction and generates an error signal if the samples differ. An exception storage unit maintains an age-ordered list of entries corresponding to instructions issued to the execution pipeline and can mark an entry to show if the error signal has been generated in association with that instruction. A timer unit is responsive to generation of the error signal to initiate timing of a predetermined time period. An error recovery unit initiates a soft pipeline flush procedure if an oldest pending entry in the list has said error marker stored in association therewith and initiates a hard pipeline flush procedure if said predetermined time period elapses, said hard flush procedure comprising resetting said pipeline to a predetermined state. | 06-27-2013 |
20130179731 | RECOVERING FROM A THREAD HANG - A method, computer-readable storage medium, and computer system are provided. In an embodiment, a detection is made that at least one thread, in a plurality of threads executing in a computer, has hung. A lock order of a plurality of locks used by the plurality of threads is determined. A determination is made that a first thread in the plurality of threads violates the lock order. After the determination that the first thread violates the lock order, the computer is restarted and the first thread that violates the lock order is scheduled on a reduced-speed processor. | 07-11-2013 |
20130262927 | METHOD AND APPARATUS FOR RESTARTING COMMUNICATION AFTER REGISTRATION OF SUBSCRIBER IDENTITY MODULE SIM CARD FAILS - Disclosed in the present invention are a method and an apparatus for restarting communication after registration of a subscriber identity module SIM card fails, which belongs to the field of mobile communications. The method includes: acquiring failure information about registration of the SIM card; displaying the failure information and prompt information on an interface, and receiving confirmation information that is replied by a user according to the prompt information; and restarting, according to the confirmation information, a communication processor under the condition of not turning off an application processor or not restarting the application processor, so as to re-register the SIM card. | 10-03-2013 |
20140201570 | Reset Supervisor - Multiple processor systems are provided. A first processor is configured to monitor the state of at least one other processor by comparing received signals. When the first processor determines that another processor needs to be reset, the first processor provides a reset signal to a reset pin of the processor that needs to be reset. The first processor may reset itself after providing the reset signal. | 07-17-2014 |
20140223233 | MULTI-CORE RE-INITIALIZATION FAILURE CONTROL SYSTEM - A method of a computer system recovering from a core re-initialization failure is described. The method may include automatically detect a core re-initialization failure during a core re-initialization process by a hypervisor. The hypervisor automatically determines whether the core re-initialization failure is a permanent failure. If the core re-initialization failure is a permanent failure, then automatically determine, by the hypervisor, which cores are re-initialized and which cores are indeterminate. Automatically allocate the re-initialized cores between one or more virtual machines by the hypervisor. | 08-07-2014 |
20140325274 | GRAPHICS PROCESSING WATCHDOG ACTIVE RESET - An advantageous watchdog function deduces faulty operation of a graphics processing unit from historical-indicating parameters while also accommodating more active testing performed by an application. When a GPU fault is detected, the example non-limiting technology rapidly resets the GPU during an interframe time so the GPU is ready to process new frame instructions or display lists and avoids missing or skipping further frames. | 10-30-2014 |
20140380098 | INFORMATION PROCESSING APPARATUS, AND METHOD FOR RESTARTING INPUT/OUTPUT CONTROL PORTION - An information processing apparatus according to one aspect of the present disclosure includes an input/output control portion and a restart control portion. The input/output control portion is configured to be able to have a plurality of electronic devices connected thereto, and is configured to control input/output between each electronic device and the information processing apparatus. The restart control portion is configured to switch whether to restart the input/output control portion in a case where an abnormality defined in advance has occurred with respect to an electronic device, in accordance with the number of the electronic devices connected to the input/output control portion. | 12-25-2014 |
20150067398 | METHOD, APPARATUS, AND RECORDING MEDIUM FOR INTERWORKING WITH EXTERNAL TERMINAL - A method for interworking with an external terminal is provided. The method includes, at a mobile terminal, displaying a screen for selecting whether or not to reset the mobile terminal, if a connection request is received from a second terminal while the mobile terminal interworks with a first terminal, at the mobile terminal, generating first backup data including information about one or more execution files corresponding to one or more functions linked to the first terminal, if resetting of the mobile terminal has been selected on the screen, and at the mobile terminal, transmitting the first backup data to the first terminal, and performing resetting. | 03-05-2015 |
20150089287 | EVENT-TRIGGERED STORAGE OF DATA TO NON-VOLATILE MEMORY - An event management resource monitors a processor environment. In response to detecting occurrence of a trigger event in the processor environment, the event management resource initiates a transfer of processor cache data from volatile storage in the processor environment to non-volatile memory. The event management resource can be configured to produce status information associated with the transfer of cache data to a respective non-volatile memory resource. The event management resource stores the status information in a non-volatile storage resource for later retrieval. Accordingly, status information associated with the event causing the transfer is available for analysis on subsequent power up or reboot of a respective computer system. | 03-26-2015 |
20150095701 | MULTIPLE PROCESSOR SYSTEM - A method, data structure and computer program are provided. A file is stored in a first memory. A duplicate of at least a part of the file is stored in the first memory. A processor is reset based on the duplicate of at least a part of the file. | 04-02-2015 |
20150100825 | INFORMATION PROCESSING DEVICE AND METHOD - An information processing device includes a processor that performs a process. The process includes: when the information stored in the first storage unit is stored in the second storage unit, storing the storing completion information corresponding to the stored information in the storing completion information storing unit; detecting a failure in the information processing device; performing a restart process on the information processing device using a region in which the stored information has been stored in the first storage unit on the basis of the storing completion information when the failure is detected; and discriminating information that has not been stored in the second storage unit from among the pieces of information stored in the first storage unit on the basis of the storing completion information when the failure is detected, and storing the discriminated information in the second storage unit. | 04-09-2015 |
20150143175 | INFORMATION PROCESSING APPARATUS, CONTROL DEVICE, AND COMPUTER-READABLE RECORDING MEDIUM HAVING STORED CONTROL PROGRAM - A first control device includes: a switch device including a first port connected to a second control device among the plurality of control devices via a first channel and a second port connected to the second control device via a second channel and to which a processing device is connected; a detection unit that detects an error in the control devices; a first reset processing unit that performs a port reset of the first port included in the switch device; and a transmitting unit that transmits a reset instruction to the second control device; thereby propagation of an error occurred in a control device can be inhibited. | 05-21-2015 |
20150331754 | BOOT RECOVERY SYSTEM - A boot recovery system includes a serial peripheral interface (SPI) storage that stores a primary boot block. A primary SPI controller is connected to the SPI storage through a primary SPI bus. An embedded controller (EC) includes an EC storage that stores a recovery boot block. The EC is coupled to the primary SPI bus through a secondary SPI bus. The EC is configured to determine that the primary boot block should be replaced, retrieve the recovery boot block from the EC storage, replace the primary boot block in the SPI storage with the recovery boot block through the secondary SPI bus, and initiate an information handling system (IHS) reboot process. The determining, retrieving, replacing, and initiating may be performed by the EC while a processing system that is coupled to the primary SPI controller is not in an operating mode. | 11-19-2015 |
20150355976 | Selecting During A System Shutdown Procedure, A Restart Incident Checkpoint Of An Incident Analyzer In A Distributed Processing System - Methods, apparatuses, and computer program products for selecting during a system shutdown procedure, a restart incident checkpoint of an incident analyzer in a distributed processing system. Embodiments include the incident analyzer determining whether at least one incident is in a queue. If at least one incident is in the queue, the incident analyzer selects as the restart incident checkpoint, a last incident completed checkpoint. If at least one incident is not in the queue, the incident analyzer determines whether the last incident completed checkpoint matches a last incident analysis pool selection checkpoint. If the last incident completed checkpoint matches a last incident analysis pool selection checkpoint, the incident analyzer selects as the restart incident checkpoint, a monitor checkpoint. If the last incident completed checkpoint does not match the last incident analysis pool selection checkpoint, the incident analyzer selects as the restart incident checkpoint, the last incident completed checkpoint. | 12-10-2015 |
20160026225 | RESET SUPERVISOR - Multiple processor systems are provided. A first processor is configured to monitor the state of at least one other processor by comparing received signals. When the first processor determines that another processor needs to be reset, the first processor provides a reset signal to a reset pin of the processor that needs to be reset. The first processor may reset itself after providing the reset signal. | 01-28-2016 |
20160062838 | INFORMATION PROCESSING APPARATUS, METHOD OF CONTROLLING THE SAME, AND STORAGE MEDIUM - In an information processing apparatus, any piece of firmware among pieces of firmware is used to activate the information processing apparatus, a piece of firmware that is different from the piece of firmware used in activation of the information processing apparatus is updated, the image processing apparatus is restarted with a piece of firmware that is different from the currently activated firmware, and the piece of firmware that is different from the piece of firmware used in activation is updated. | 03-03-2016 |
20160070320 | Individual Device Reset and Recovery in a Computer - A computer includes multiple devices, each providing different functionality to the computer, such as communication functionality, input functionality, output functionality, and so forth. A reset control system of the computer manages resetting of the devices, resetting individual devices as appropriate rather than resetting the entire computer. In response to a malfunction of a particular device, the reset control system selects a set of one or more devices to reset. The devices to reset include the particular device as well as any other devices that will be affected by resetting the particular device (e.g., devices that cannot be powered down or reset separately from the particular device, or devices the operation of which relies on the particular device). The reset control system resets the set of one or more devices, and then adds each reset device back into the computer. | 03-10-2016 |
20160092310 | SYSTEMS AND METHODS FOR MANAGING GLOBALLY DISTRIBUTED REMOTE STORAGE DEVICES - Methods and systems are described managing module for remotely managing hardware of at least one of a plurality of distributed remote storage devices. A computer implemented method includes locally monitoring a system (including, for example, a core operating system) of the hardware, locally detecting an abnormal or unresponsive state of the system, generating a notice when the abnormal or unresponsive state is detected, delivering the notice to a remotely located central service, and automatically rebooting the hardware when the abnormal or unresponsive state is detected. | 03-31-2016 |
20160139995 | INFORMATION PROCESSING APPARATUS, MEMORY DUMP METHOD, AND STORAGE MEDIUM - An information processing apparatus includes a processor that executes an operating system, a nonvolatile main memory device to which the processor is directly accessible and that has a controller, and an external storage device to which the processor is not directly accessible. When the processor detects an error of the operating system, the processor resets devices other than the nonvolatile main memory device and restarts the operating system, and the controller writes data of the nonvolatile main memory device to the external storage device. | 05-19-2016 |
20160147540 | SERVER SYSTEM - A server system is disclosed herein, which includes a first BIOS chip, a second BIOS chip, a platform controller, and a baseboard management controller. The platform controller and the baseboard management controller are electrically connected to a first multi-way selector and a second multi-way selector, respectively. The first multi-way selector and the second multi-way selector are individually electrically connected to both the first BIOS chip and the second BIOS chip. The disclosure can accomplish an aspect that when either of the first BIOS chip and the second BIOS chip fails in activating the server system, the server system can be automatically activated by the other BIOS chip. Further, by the baseboard management controller, a firmware of the fail-to-activate BIOS chip can be simultaneously updated, thereby improving security and reliability of the server system. | 05-26-2016 |