| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 714009000 | Access processor affected (e.g., I/O processor, MMU, DMA processor) | 7 |
| 20090006889 | I2C Failure Detection, Correction, and Masking - A method of operation of a computer system having a master and slave Inter-IC (I2C) bus network includes detecting and isolating an I2C bus failure, configuring a failed I2C bus as offline, reconfiguring a remaining I2C bus as a multi-mastered bus, and masking the failed I2C bus from operation until the failed I2C bus can be repaired. A first test request is sent to a remote device from a local device. If the remote device receives the first test request, a remote bus mode is switched to a failure position, a local bus mode is switched to a multi-master position, and a second request is sent to the remote device to indicate position changes. | 01-01-2009 |
| 20090006890 | Storage system and control method of storage system - Provided is a storage system superior in fault tolerance. This storage system is composed of a controller having a plurality of processors and other units. When an error occurs in any one of the components in the controller, the storage system cuts off an I/O path of the controller, specifies the failed component in the cutoff status, and invalidates such failed component. Further, after invalidating the failed component, the storage system determines whether it is operable only with the normal components, cancels (releases) the cutoff of the I/O path when it determines that it is operable, and resumes operation by rebooting itself. | 01-01-2009 |
| 20090119539 | SYSTEM AND PROGRAM FOR ERROR HANDLING IN A DUAL ADAPTOR SYSTEM WHERE ONE ADAPTOR IS A MASTER - Provided is a method, system, and program for processing Input/Output (I/O) requests to a storage network including at least one storage device and at least two adaptors, wherein each adaptor is capable of communicating I/O requests to the at least one storage device. An error is detected in a system including a first adaptor, wherein the first adaptor is capable of communicating on the network after the error is detected. In response to detecting the error, a master switch timer is started that is less than a system timeout period if the first adaptor is the master. An error recovery procedure in the system including the first adaptor would be initiated after the system timeout period has expired. An operation is initiated to designate another adaptor in the storage network as the master if the first adaptor is the master in response to detecting an expiration of the master switch timer. | 05-07-2009 |
| 20100077253 | MEMORY CONTROL DEVICE AND METHODS THEREOF - A method includes establishing a first link between a first processor device and a first memory module at a first time. A second link is established between a second processor device and a second memory module at a second time. In response to receiving a first event indicator, a third link is established between the first processor device and the second memory module at a third time, the third time after the first time and the second time. | 03-25-2010 |
| 20100223497 | Monitoring Processes Via Autocorrelation - A method and apparatus including a monitoring and correction module that monitors process metrics to identify a steady-state for a process, detects a deviation from the steady-state for the process, and executes a corrective measure automatically to reduce an impact of the process in response to the deviation by a monitoring and correction module. The monitoring and correction module also analyzes the deviation to determine whether the deviation is negatively impact in performance for other processes. | 09-02-2010 |
| 20100251014 | COMPUTER AND FAILURE HANDLING METHOD THEREOF - A computer system including a plurality of PCIe paths is configured such that a failed PCIe path only is disabled, thereby preventing the computer system from system resetting. The computer comprises a root port for detecting a failure on a PCIe path, and then for issuing a SMI (System Maintenance Interrupt) to a CPU; and the CPU for, on the receipt of the SMI, executing BIOS to issue, through the root port, a PCIe reset to the PCIe path on which the failure has occurred. | 09-30-2010 |
| 20100251015 | DISK ARRAY DEVICE, DISK CONTROL DEVICE AND LOAD DISTRIBUTION METHOD IN DISK ARRAY DEVICE - Degree of freedom of a device structure is increased to equalize processor loads by separating the function of executing data read and write processing from the host interface and the disk interface. A disk array device including a disk enclosure and a disk control unit, wherein the disk control unit includes a host interface connected to a host computer which accesses the disk array device, a disk interface connected to the disk enclosure, a plurality of processors that execute data read and write processing between the host computer and the disk enclosure, and a switch which connects the host interface and the disk interface, and the plurality of processors, wherein the switch having a function of selecting a processor which executes the data read and write processing. | 09-30-2010 |
