| Entries |
| Document | Title | Date |
|---|
| 20080209252 | PIPELINED CLOCK STRETCHING CIRCUITRY AND METHOD FOR I2C LOGIC SYSTEM - A system for increasing the data throughput of an I2C bus including a serial clock conductor ( | 08-28-2008 |
| 20080229137 | SYSTEMS AND METHODS OF COMPRESSION HISTORY EXPIRATION AND SYNCHRONIZATION - Systems and methods of storing previously transmitted data and using it to reduce bandwidth usage and accelerate future communications are described. By using algorithms to identify long compression history matches, a network device may improve compression efficiently and speed. A network device may also use application specific parsing to improve the length and number of compression history matches. Further, by sharing compression histories, compression history indexes and caches across multiple devices, devices can utilize data previously transmitted to other devices to compress network traffic. Any combination of the systems and methods may be used to efficiently find long matches to stored data, synchronize the storage of previously sent data, and share previously sent data among one or more other devices. | 09-18-2008 |
| 20080229138 | DIRECTLY OBTAINING BY APPLICATION PROGRAMS INFORMATION USABLE IN DETERMINING CLOCK ACCURACY - Information usable in determining the quality of time produced by a clock of a processing environment is obtained. The information is obtained directly by an application program absent use of a supervisor service, such as an operating system or operating system service. The application program invokes an instruction that returns a parameter block that includes the information. | 09-18-2008 |
| 20080244304 | Deriving accurate media position information - Various embodiments utilize different counters or clocks, working in concert, to smooth out position information that is derived for a rendering/capturing device. Specifically, in at least some embodiments, each counter or clock has a different speed. A faster counter or clock is used to determine intra-transition position offsets relative to a slower counter or clock. | 10-02-2008 |
| 20080263384 | SYSTEM AND METHOD FOR PRIORITIZATION OF CLOCK RATES IN A MULTI-CORE PROCESSOR - A system and method for prioritization of clock rates in a multi-core processor is provided. Instruction arrival rates are measured during a time interval T | 10-23-2008 |
| 20080294928 | Coarsely controlling memory power states - In one embodiment, the present invention includes a method determining if an access queue associated with a channel of a memory has been empty for a predetermined time period and if so, de-asserting a clock enable signal for all ranks of the channel of the memory, otherwise providing a next memory access request from the access queue to the channel of the memory. Other embodiments are described and claimed. | 11-27-2008 |
| 20080294929 | Data processing apparatus and method for controlling a transfer of payload data over a communication channel - A data processing apparatus and method are provided for controlling a transfer of payload data over a communication channel. The data processing apparatus has initiator circuitry for initiating a transfer of payload data in a first clock cycle, and recipient circuitry for receiving the payload data the subject of the transfer in a later clock cycle. A communication channel is provided over which the payload data is passed from the initiator circuitry to the recipient circuitry along with associated transfer control information, timing of receipt of the payload data by the recipient circuitry being controlled by the transfer control information. Timing easing circuitry located within the communication channel is then used to temporarily buffer at least the transfer control information generated by the initiator circuitry before outputting that transfer control information to the recipient circuitry. The timing easing circuitry is responsive to a specified timing easing value to determine a time for which the transfer control information is temporarily buffered, whereby the number of clock cycles that elapse between the first clock cycle and the later clock cycle is dependent on the specified timing easing value. This hence enables a multi-cycle path to be provided for the transfer of payload data from the initiator circuitry to the recipient circuitry. | 11-27-2008 |
| 20080301485 | REGISTER WITH PROCESS, SUPPLY VOLTAGE AND TEMPERATURE VARIATION INDEPENDENT PROPAGATION DELAY PATH - The digital data register has a plurality of parallel matched data paths, each data path having a data input for receiving a digital data input signal (CA/CNTRL), an output driver with a data output providing a digital data output signal (Q_CA/CNTRL) for application to an associated memory module and a flip-flop (FF1) arranged between the data input and the data output. The data register further comprises a clock input for receiving a clock input signal (CLK), a clock output for providing an output clock signal (Q_CLKn, Q_NCLKn) to the memory modules, a phase locked loop (PLL) with a clock input (REF), a feedback input (FB), a feedback output providing a feedback output signal (Q_NFB) and a clock output providing a clock output signal (Q_CLK, QNCLK). In addition a flip-flop (FF1 DELAY) and output driver replica are matched with the flip-flop and output driver of the data paths. the flip-flops (FF1) of the data paths and the flip-flop (FF1 DELAY) of the replica are clocked by the feedback signal applied to the feedback input (FB) of the phase locked loop (PLL). The phase locked loop (PLL) includes a phase aligner with a phase interpolator. The phase interpolator has an output that provides the output clock signal (Q_CLKn, Q_NCLKn) to the memory modules through a flip-flop (FF1 DELAY) and output driver matched with the flip-flop and output driver of the data paths. A phase frequency detector (PFD) has a first input (REF) coupled to the output of the output driver replica and a second input (SYS) coupled to the clock output. The phase interpolator is controlled by the output of the phase frequency detector (PFD). The proposed data register satisfies the three requirements of: (i) setup and hold timing on the pre-register side, (ii) clock centering on the post-register side, and (iii) constant propagation delay time (tpd) over PVT variations from the clock input to the data output. | 12-04-2008 |
| 20080307248 | Cpu Clock Control Device, Cpu Clock Control Method, Cpu Clock Control Program, Recording Medium, and Transmission Medium - A program execution time determining portion determines an execution start time and a processing volume per unit time of a program in such a manner that a processing volume necessary to execute the program is made equal to the extent that registered request for the execution time and allowable range are met. It is thus possible to determine the execution time of the program in such a manner that a necessary processing volume is made as equal as possible within the allowable range of the request for the execution time of the program, which enables clock control that suppresses a variation of the operating frequency of the CPU. Power consumption of the CPU can be thus reduced. | 12-11-2008 |
| 20080313486 | Devices, Systems, and Methods Regarding Programmable Logic Controller Communications - Certain exemplary embodiments can provide a system, which can comprise a signal interface that is adapted to transmit a signal between a programmable logic controller and an Input/Output (I/O) module. The programmable logic controller can be communicatively coupled to the I/O module via an opto-coupler, which can be adapted to electrically isolate the programmable logic controller from the I/O module. | 12-18-2008 |
| 20090006882 | Method and Apparatus for Wireless Clock Regeneration - Methods and systems for operating a wireless clock system for multimedia datastream transmission and display. Source clock frames are compared with a reference clock frames and the clock difference are transmitted to a wireless clock receiver which also receives the same reference clock frames. Source clock frames are re-constructed using the reference clock frames, clock difference information and the receiver's local clock system. | 01-01-2009 |
| 20090013206 | Efficient Utilization of a Multi-Source Network of Control Logic to Achieve Timing Closure in a Clocked Logic Circuit - A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit. | 01-08-2009 |
| 20090024865 | Infrared Remote Control Signaling Generator - An IR signaling generator and method divides the functionality of generation between software and hardware to provide a flexible way to generate IR signals, such as remote control signals. The hardware includes a clock generator for generating a carrier clock signal and a data clock signal, a buffer memory that is loaded with instructions representing an encoded data sequence; a control circuit, and a transmitter including a modulator. Each instruction contains an on/off value that is to be modulated with the data clock signal and a pulse duration value that indicates how long the on/off value is to modulate the clock signal. Using the data clock signal, the control circuit measures the amount of time the on/off value modulates the clock signal and causes the buffer to advance to the next instruction in the sequence when the measured amount of time is equal to the pulse duration value. | 01-22-2009 |
| 20090024866 | DIGITAL VLSI CIRCUIT AND IMAGE PROCESSING DEVICE INTO WHICH THE SAME IS ASSEMBLED - A digital VLSI circuit is provided with functions in which the number of switching operations to supply electric power to each arithmetic operation unit is reduced in a restricted period of time while electric power supply is controlled for each arithmetic operation unit, so that low power consumption can be achieved in real pipe-line arithmetic operation. The VLSI circuit that performs each stage of the pipe-line arithmetic operation is comprised of a plurality of arithmetic operation units for carrying out arithmetic operations in synchronization with a clock signal, a detecting means for detecting completion of the stage in the arithmetic operation assigned to the arithmetic operation unit, and a clock signal supply control means for controlling supply/stop operation of the clock signal to each arithmetic operation unit, wherein the clock signal supply control means stops supplying the clock signal to a certain arithmetic operation unit when the detecting means detects the completion of the arithmetic operation assigned to the same, and restarts supplying the clock signal to all the arithmetic operation units for a next pipe-line arithmetic operation when the detecting means detects the completion of the arithmetic operations assigned to them. | 01-22-2009 |
| 20090031160 | DIGITAL WATERMARK INFORMATION ADDING DEVICE, DATA REPRODUCTION DEVICE AND DATA RECORDING DEVICE - In order to prevent content data from being illegally recorded or reproduced, information for detecting that the content data is illegally distributed or recorded is added to watermark information or other information. Two sets of WM (watermark) data, a WM1 data set and a WM2 data set are prepared. For the WM1 data, data representing that the content data is package media data or distribution data, SCMS information, data representing that the content data is recorded in a disk or a semiconductor memory, and data representing the type of disk or semiconductor memory are set. For the WM2 data, the distribution time or the year and date is set as time information representing time when the content data is recorded. According to the WM1 or WM2 data, a data reproducing device ( | 01-29-2009 |
| 20090037761 | Clock Source Control for Modular Computer System - A computer system provides for connecting consecutively positioned modules to operate collectively as server. Each module calculates a modulo difference between its position and that of a module serving as a clock source; each module selects a clock input as a function of the result of that calculation. | 02-05-2009 |
| 20090044039 | Memory system, a memory device, a memory controller and method thereof - The memory system, memory device, memory controller and method may have a reduced power consumption. The memory system, memory device, memory controller and method may transition a data strobe signal to a valid logic level during a standby state. The valid logic level may be less than a logic level associated with a higher impedance level, such as when a bus may be turned off or connected to a ground voltage. A delay locked circuit need not be used in the memory device. | 02-12-2009 |
| 20090049327 | COMPUTER SYSTEM WITH ADJUSTABLE DATA TRANSMISSION RATE - A computer system has an adjustable data transmission rate between a CPU and a core logic chip thereof. In the computer system, the CPU has a power state adjustable in response to a power management control signal issued by the core logic chip. For adjusting data transmission rate between the CPU and the core logic chip, a change of an asserted time of the power management control signal from a first time period to a second time period is first determined to obtain an index value. The data transmission rate is increased or decreased according to the index value. | 02-19-2009 |
| 20090055677 | Asynchronous first in first out interface and operation method thereof - The invention provides an asynchronous first in first out (FIFO) interface and operation method wherein a read-out clock and a write-in clock of the asynchronous FIFO interface is asynchronous. The asynchronous FIFO interface comprises a FIFO buffer, a clock controller and a variable integer divider. The FIFO buffer inputs at least one data with the write-in clock, and outputs the at least one data with the read-out clock. The clock controller outputs a clock control signal according to a number of data stored in the FIFO buffer. The variable integer divider divides a first signal to generate the read-out clock or the write-in clock by an integer divisor controlled by the clock control signal in order to adjust the number of data stored in the FIFO buffer. | 02-26-2009 |
| 20090055678 | Clock processors in high-speed signal converter systems - Clock processors are provided to economically control system and data clocks in high-speed signal converters. The processors generally include at least one of a delay-locked loop, phase-locked loop or a duty cycle stabilizer which generates an error signal in its operation. In the example of a stabilizer, it is configured to respond to an input clock to initiate a first portion of each cycle of the system clock and to include a control loop to provide an error signal that controls a second portion of the cycle to thereby maintain a selected duty cycle. The processors also include a data clock aligner configured to share the error signal and provide a data clock that is delayed by a selected delay from a selected one of the input and system clocks. In addition to providing effective control that is independent of disturbing effects (e.g., temperature and clock rate), the shared use reduces processor costs. | 02-26-2009 |
| 20090077410 | METHOD FOR SETTING ACTUAL OPERTATION FREQUENCY OF MEMORY AND SETTING MODULE THEREOF - A method for setting an actual operation frequency of a memory is provided. The method includes the following steps. First, a memory model list is provided for selecting a memory model. Then, an estimation operation frequency of the memory is obtained according to the selected model. Finally, the operation frequency of a front side bus (FSB) is adjusted and cooperated with a frequency transformation ratio to generate the actual operation frequency of the memory according to the estimation operation frequency. | 03-19-2009 |
| 20090083569 | Generating a Local Clock Domain Using Dynamic Controls - A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times its commencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes. | 03-26-2009 |
| 20090083570 | TRANSMISSION APPARATUS THAT TRANSMITS DATA ACCORDING TO A PROTOCOL, AND METHOD FOR MEASURING TIME IN THE TRANSMISSION APPARATUS - A transmission apparatus that transmits data according to a protocol has a timer, a memory, a processor, and a transmission unit. The processor stores, in the memory, type data indicating a single type of time from a plurality of types of time that are to be measured according to the protocol. The transmission unit transmits data according to the protocol and starts the measurement of time of the type indicated by the type data stored in the memory using the timer after the data has been transmitted. | 03-26-2009 |
| 20090106577 | OPTIMIZE PERSONALIZATION CONDITIONS FOR ELECTRONIC DEVICE TRANSMISSION RATES WITH INCREASED TRANSMITTING FREQUENCY - Systems and/or methods that facilitate expediently transmitting and programming data to an electronic device that contains nonvolatile memory are presented. A host component facilitates the determination of different clock frequencies that an electronic device(s) can accommodate for transmitting data to and receiving data from the electronic device. The host component can facilitate transmitting data to the electronic device at a higher clock frequency than the clock frequency utilized to transmit data from the electronic device to the host component in order to facilitate programming large amounts of data to the electronic device efficiently. The host component can select a downlink and/or uplink clock frequency based in part on the type of electronic device(s), the size of a memory buffer associated with the nonvolatile memory device, and/or a type of protocol associated with the electronic device. | 04-23-2009 |
| 20090119535 | Method and apparatus for managing network synchronization information among multiple line cards - A method and apparatus for handling, maintaining, and controlling network synchronization information emanating from a plurality of line card circuits is described. The technique described may be applied to a redundant pair of line card circuits, where one line card circuit is active, while the other is inactive. Line card activity latches are managed by means of hardware logic that may be configured at the time of line card commissioning. The activity latches are coupled to a logic element. An incoming clock signal is applied to the logic element. If an activity latch indicates that a line card circuit is active, the logic element provides the incoming clock signal as an outgoing clock signal to a control card circuit. If the activity latch indicates that the line card circuit is inactive, the logic element blocks the incoming clock signal from being passed and provides a static output level as the outgoing clock signal to the control card circuit. The control card circuit is provided with circuitry to receive the outgoing clock signals from multiple line card circuits. The circuitry is sensitive to whether or not the line card circuits are configured for redundant operation. One or more of these clock signals are then selected and used for network synchronization. | 05-07-2009 |
| 20090125750 | USING MEMORIES TO CHANGE DATA PHASE OR FREQUENCY - A data processing apparatus includes a first memory which comprises a first input/output port and a second input/output port; a second memory which is connected to the first memory and comprises a third input/output port; and a controller for controlling the first and second memories to perform operations of: (a) writing data to the first memory through the first input/output port; (b) reading the data from the first memory through the second input/output port; (c) writing the data read out of the first memory to the second memory through the third input/output port; and (d) reading the data from the second memory through the third input/output port; wherein the operation (a) is performed at a first frequency and the operations (b), (c), (d) are each performed at a second frequency, wherein either: (i) the first frequency is different from the second frequency, or (ii) the first frequency is equal to the second frequency but in each of the operations (b), (c) and (d) the data is different in phase than in the operation (a). | 05-14-2009 |
| 20090132847 | Information processing apparatus having memory clock setting function and memory clock setting method - A memory clock setting function acquires the band of a memory bus, and acquires the total band of a CPU bus and the I/O buses. When the band of the memory bus is greater than the total band of the CPU bus and I/O buses, the clock rate less than or equal to the current operation clock of a memory is selected so that the band of the memory bus may not be less than the total band of the CPU bus and the I/O buses, and the selected clock rate is set as the operation clock of the memory to a memory controller. | 05-21-2009 |
| 20090150709 | Reducing Inefficiencies of Multi-Clock-Domain Interfaces Using a Modified Latch Bank - A system and method for improving the performance and efficiency of multi-clock-domain data transmission interfaces. The data transmission interface may include a modified slave latch which includes one or more clock splitters and one or more transmission gates may be used. By having such a configuration, space requirements are reduced and a reduction of the number of devices necessary for a multi-domain interface may be realized. The configuration may further allow for independent cycle stealing of N:1 and N:2 logical paths, thus allowing for timing resolution solutions that use fewer devices versus implementations that require the tuning of each individual bit in the cross-clock-domain interface. By implementing such a data transmission interface, space and power requirements may be reduced and timing criticalities may be more easily managed. | 06-11-2009 |
| 20090150710 | Memory System With Extended Memory Density Capability - A system including a central processing unit, a first memory channel being configured to couple the central processing unit to a first semiconductor memory unit, wherein the first memory channel is configured to be clocked with a first clock frequency, and a second memory channel being configured to couple the central processing unit to a second semiconductor memory unit, wherein the second memory channel is configured or configurable to be clocked with a second clock frequency smaller than the first clock frequency. | 06-11-2009 |
| 20090164829 | METHOD FOR INCREASING A PROGRAMMING SPEED FOR A TIME SIGNAL RECEIVER, PROGRAMMABLE TIME SIGNAL RECEIVER, AND PROGRAMMING DEVICE FOR PROGRAMMING A TIME SIGNAL RECEIVER - Method for increasing a programming speed for a time signal receiver, programmable time signal receiver, and programming device for programming a time signal receiver. The method for wireless programming of a time signal receiver provides the following steps: provision to the time signal receiver of a programming clock frequency that is selected to be higher than an internal operating clock frequency of the time signal receiver; provision of programming instructions for the time signal receiver by means of a programming device with a data rate that is matched to the programming clock frequency, decoding of the programming instructions by receiver and/or by processor of the time signal receiver, in particular at the rate of the programming clock frequency, storage in memory within the time signal receiver, in particular at the rate of the programming clock frequency, of the programming instructions intended for execution in the receiver and/or in the processor. | 06-25-2009 |
| 20090164830 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH POWER SAVING FEATURE - A non-volatile semiconductor memory device, which comprises (i) an interface having an input for receiving an input clock and a set of data lines for receiving commands issued by a controller including an erase command; (ii) a module having circuit components in a feedback loop configuration and being driven by a reference clock; (iii) a clock control circuit capable of controllably switching between a first state in which the reference clock tracks the input clock and a second state in which the reference clock is decoupled from the input clock; and (iv) a command processing unit configured to recognize the commands and to cause the clock control circuit to switch from the first state to the second state in response to recognizing the erase command. The module consumes less power when the reference clock is decoupled from the input clock than when the reference clock tracks the input clock. | 06-25-2009 |
| 20090172457 | Monitoring Presentation Timestamps - Techniques to monitor presentation timestamps for content are described, which may be used to render content at a client. In an implementation, content is received having timestamps that define expected timing for output of the content at a client. The timestamps may then be monitored and compared to a client clock to determine if the content rendered matches the content expected to be rendered. When a discrepancy is detected, one or more corrective actions may be undertaken to restore output of the content to the timing defined by the timestamps. | 07-02-2009 |
| 20090172458 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND CLOCK CONTROL METHOD - A plurality of operation units connected in a pipeline structure performs an operation processing on data. A process control unit operates in synchronization with a system clock signal and generates a process control signal for controlling the operation units upon receiving a data notification signal that notifies the process control unit of an arrival of data from outside. A clock-control signal generating unit operates in synchronization with the system clock signal and generates a clock control signal for controlling a clock supply to each of the operation units upon receiving the process control signal. | 07-02-2009 |
| 20090193283 | DESIGN STRUCTURE FOR IMPLEMENTING SPECULATIVE CLOCK GATING OF DIGITAL LOGIC CIRCUITS - A design structure embodied in a machine readable medium used in a design process includes an apparatus for implementing speculative clock gating of digital logic circuits, including operation valid logic configured to generate, in a first pipeline stage n, a valid control signal that is input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and speculative valid logic configured to generate, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly to the first register. | 07-30-2009 |
| 20090193284 | METHODS FOR SYNCHRONIZING APPLICATIVE CLOCK SIGNALS IN A SYNCHRONOUS COMMUNICATIONS NETWORK, CORRESPONDING EMITTER AND RECEIVER DEVICES, COMPUTER-READABLE STORAGE MEANS - A method for transmitting information is proposed, enabling a synchronization of applicative clocks signals between a transmission device and at least one reception device connected to a communications network. For each stream of a source application, the transmission device: writes to a buffer memory associated with the stream, at the rate of a source applicative clock, pieces of applicative data of the stream coming from the source application, transmits, via the network, pieces of applicative data of the stream at the rate of the network clock. For at least one stream of the source application, the transmission device performs the following steps upon detection of a clock adjustment event: determining a piece of time offset information between a starting instant of a current network cycle and an instant of writing one of the pieces of applicative data of the stream, called a reference piece of data, to the buffer memory associated with the stream; determining a piece of information on position of the reference piece of data from among the pieces of applicative data of this stream to be transmitted via the network during a determined network cycle; transmission on the communications network of the information on time offset and position during the same network cycle as the one in which the reference piece of data is transmitted. | 07-30-2009 |
| 20090193285 | Method for the data transfer between at least two clock domains - The invention describes a method for transferring data between a first clock domain having a first clock rate (CLK | 07-30-2009 |
| 20090199038 | LOW-POWER MULTI-OUTPUT LOCAL CLOCK BUFFER - An improved circuit for reducing a capacitance load on a processor. The circuit includes a global clock circuit capable of producing a primary timing signal. The circuit further includes a local clock buffer circuit having a plurality of outputs. The local clock buffer circuit is connected to the global clock circuit. The local clock buffer circuit is capable of producing a secondary timing signal based on the primary timing signal. The circuit also includes a latch connected to the local clock buffer circuit. The latch is capable of producing a select signal that controls which outputs of the plurality of outputs are active. Only a third signal, based on the secondary timing signal, controls an operation of the latch. | 08-06-2009 |
| 20090210741 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD - An information processing apparatus includes a predicting unit to predict temperature of the apparatus when allowing one or more processing units mounted in the apparatus to execute a new program, a temperature determining unit to compare the predicted temperature with a predetermined reference value, a priority determining unit to compare priorities of the new program and an active program in execution if the temperature is equal to or greater than the predetermined reference value, and an operation clock setting unit to set an operation clock to the one or more processing units, the operation clock enabling the predicted temperature to less than the predetermined reference value even if one of the processing units is allowed to execute the new program, and to allow the one or more processing units to execute the new program if the priority of the new program is higher than the priority of the active program. | 08-20-2009 |
| 20090217076 | PERSONAL IDENTIFICATION MEDIUM, DISPLAY METHOD FOR A PERSONAL IDENTIFICATION MEDIUM, TIME AND ATTENDANCE MANAGEMENT SYSTEM, AND CUSTOMER INFORMATION MANAGEMENT SYSTEM - A personal identification medium enables easily confirming specific information. A time and attendance management system and a customer information management system both use the personal identification medium. An individual information storage unit | 08-27-2009 |
| 20090259878 | Multirate transmission system and method for parallel input data - A multirate transmission system for transmitting parallel input data from a first location to a second location includes a transmitter portion and a receiver portion. The transmitter portion receives the parallel data, including the information related to a parallel data clock and stores the data in a buffer where it is subsequently read and serialized for transmission on a serial data link to the receiver portion where it is deserialized, including recovery of the parallel data clock in the serialized data stream. The receiver portion stores the parallel data in a buffer where it is read at a data rate corresponding to the parallel data clock of the incoming parallel data. The parallel data at the transmitter portion is associated with generated control characters when parallel data is not read from the buffer associated with the transmitter portion. | 10-15-2009 |
| 20090265575 | OVERCLOCKING MODULE, A COMPUTER SYSTEM AND A METHOD FOR OVERCLOCKING - An overclocking module, a computer system and a method for overclocking are provided. The method is used to overclock the computer system. The overclocking module of the invention includes a timer, a monitoring unit and a control unit. The timer starts to count when the computer system is booted. The monitoring unit monitors whether the computer system performs a boot-up procedure within a period of time. The control unit adjusts an operating frequency of the computer system to overclock the computer system automatically according to the monitoring result of the monitoring unit. | 10-22-2009 |
| 20090271653 | METHOD AND SYSTEM FOR DATA SYNCHRONIZATION - A data synchronization system and method. The method includes that when a change happens in a source application, data is collected from a source application based on a target application subscribing the source application and collection data is transmitted to the target application or is directly inserted to target database. The system includes data collection unit and distribution unit. The present invention may realize synchronization on demand, simultaneously reduce greatly synchronous data quantity, decrease network load, and guarantee smoothness and stabilization of network. The present invention applies to data synchronization of enterprise internal/external data systems, telecommunication networks, etc. | 10-29-2009 |
| 20090307520 | Apparatus and Method for Processing Wirelessly Communicated Information Within an Electronic Device - An electronic device ( | 12-10-2009 |
| 20090313495 | System and Method for Patient Synchronization Between Independent Applications in a Distributed Environment - A method for synchronizing patient data between at least two independent applications in a distributed environment includes capturing screen information from a display window of a first application client that is displaying a medical image of a patient, analyzing the screen information captured from the first application client display to extract patient identifying information, and synchronizing a display of information of the patient on a second application system display screen with the first application display window using the extracted patient identification information. | 12-17-2009 |
| 20090319820 | CLOCK CONTROLLING APPARATUS OF COMPUTER SYSTEM AND APPLICATIONS THEREOF - A clock controlling apparatus of a computer system used to tuning a clock frequency of a specific electronic device disposed on a motherboard and the application thereof are disclosed, wherein the clock controlling apparatus comprises an input control unit used to output a frequency increasing signal or a frequency decreasing signal, a control circuit connected to a clock generator disposed on the motherboard in order to tune the clock frequency of the electronic device according to the frequency increasing signal or the frequency decreasing signal, and a displaying unit connected to the control circuit in order to show the clock frequency. | 12-24-2009 |
| 20090327794 | Single Interface Access to Multiple Bandwidth and Power Memory Zones - In an embodiment, a system comprises a first memory module interface unit (MMIU) configured to couple to a first one or more memory modules, and a second MMIU configured to couple to a second one or more memory modules. The first MMIU is configured to operate the first one or more memory modules at a first frequency and the second MMIU is configured to concurrently operate the second one or more memory modules at a second operating frequency different from the first operating frequency. | 12-31-2009 |
| 20090327795 | METHOD FOR PROTECTING A SECURED REAL TIME CLOCK MODULE AND A DEVICE HAVING PROTECTION CAPABILITIES - A method for protecting a secured real time clock module, the method includes: locking multiple input ports of the secured real time clock module if the multiple input ports of the secured real time clock module are idle during at least a first duration; unlocking the multiple input ports of the secured real time clock module if a predefined high frequency code is received over a control input port of the secured real time clock module; and providing a secured real time clock signal when the multiple input ports of the secured real time clock module are locked and when the multiple input ports of the secured real time clock module are unlocked; wherein changes in a supply voltage results in a supply voltage induced changes of an input signal provided to an input port of the secured real time clock module; wherein a maximal frequency of the supply voltage induced changes of the input signal is lower then the high frequency of the predefined high frequency code. | 12-31-2009 |
| 20100042866 | Method and Apparatus for Adjusting a System Timer of a Mobile Station - A method and an apparatus for adjusting a system timer of a mobile station (MS) are disclosed, wherein a clock cycle time of the system timer is of a predetermined length. The method comprises the following steps: detecting a frame boundary of a frame from a base station (BS), the frame is with a frame length; adjusting an interrupt signal of the system timer from a predetermined time to a time related to the frame; and adjusting the clock cycle time from the predetermined length to the frame length. The modified system timer of the MS is synchronized to a frame timing of the BS. | 02-18-2010 |
| 20100050010 | Data-Width Translation Between Variable-Width and Fixed-Width Data Ports - Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency. | 02-25-2010 |
| 20100088537 | METHOD AND DEVICE FOR BUS ARBITRATION, CONVERTER AND PRODUCTION FACILITY - A method for bus arbitration is for use when working with multi-carrier modulation methods. Each user on a bus is assigned a unique address which identifies the user and which is transmitted upon each initiation of communication. The address is represented as a sequence of binary numerals, the number of bits of the binary numerals being equal to the number of carriers used in the multi-carrier modulation method. This sequence of binary numerals is transmitted successively for the arbitration via the multi-carrier modulation method, a user being eliminated from the arbitration when a further user at the same time has transmitted a binary numeral having higher priority. The transmission of the binary numeral may be repeated if the arbitration of the numeral does not lead to a result in one step. The method for bus arbitration may be used advantageously in a system for contactless energy supply. A redundant sending of phase-shifted signals reduces the failure rate because of random destructive interference. | 04-08-2010 |
| 20100122107 | Physical Interface Macros (PHYS) Supporting Heterogeneous Electrical Properties - An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage. | 05-13-2010 |
| 20100122108 | ARITHMETIC UNIT AND ARITHMETIC PROCESSING METHOD - There is a need for providing a battery-less integrated circuit (IC) card capable of operating in accordance with a contact usage or a non-contact usage, preventing coprocessor throughput from degrading despite a decreased clock frequency for reduced power consumption under non-contact usage, and ensuring high-speed processing under non-contact usage. A dual interface card is a battery-less IC card capable of operating in accordance with a contact usage or a non-contact usage. The dual interface card operates at a high clock under contact usage and at a low clock under non-contact usage. A targeted operation comprises a plurality of different basic operations. The dual interface card comprises a basic arithmetic circuit group. Under the contact usage, the basic arithmetic circuit group performs one basic operation of the targeted operation at one cycle. Under the non-contact usage, the basic arithmetic circuit group sequentially performs at least two basic operations of the targeted operation at one cycle. | 05-13-2010 |
| 20100122109 | MIPS RECOVERY TECHNIQUE - Self-calibration of devices such as computer and graphics processors permits adjustment of processor clock rates, and access to normally unused processor capacity. Processor clock rates specified by device manufacturers are normally selected to insure operation across the entire manufacturer-specified range of operating temperatures and supply voltages. By limiting processor clock rates to nominal values, even when operating well within manufacturer-specified temperature and/or supply voltage limits, designers sacrifice processor capacity. By determining the upper limits of processor clock rates at which reliable operation can be realized, and adjusting processor clock rates to match those speeds, a representative embodiment of the present invention permits device users to gain additional, previously inaccessible processing capacity. | 05-13-2010 |
| 20100146322 | METHOD FOR OVERCLOCKING CENTRAL PROCESSING UNIT OF COMPUTER MOTHERBOARD - A method for overclocking a central processing unit (CPU) of a computer motherboard is disclosed. Step A is to set a second frequency of front side bus (FSB) by an operating interface of BIOS. Step B is to determine FSB frequency F | 06-10-2010 |
| 20100169700 | Adaptive clock enable for memory control - In some embodiments a memory rank idle counter enables de-assertion of a clock enable signal of a rank of a memory for idle systems. Clock enable signal assertion is maintained when there is a lot of traffic to the memory rank. A memory rank idle time prediction counter transfers a value to the memory rank idle counter when the memory rank is idle. Other embodiments are described and claimed. | 07-01-2010 |
| 20100169701 | COMPUTER SYSTEM CAPABLE OF DYNAMICALLY MODULATING OPERATION VOLTAGE AND FREQUENCY OF CPU - A computer system capable of dynamically modulating an operation voltage and an operation frequency of a CPU comprises: a CPU from which a VID | 07-01-2010 |
| 20100169702 | MEMORY CONTROL APPARATUS, MEMORY OPTIMIZATION PROGRAM PRODUCT, AND MEMORY OPTIMIZATION METHOD - According to one embodiment, a memory control apparatus includes a generator configured to delay a clock signal having a rise and a fall that appear in a constant cycle and to generate a plurality of delay clock signals having delay times different from each other; an extractor configured to extract, from a data signal including reference data, data of a portion corresponding to the rise or fall of each delay clock signal generated; a first determiner configured to determine whether each data extracted coincides with the reference data; and a second determiner configured to determine, from the delay times of the delay clock signals corresponding to the data that have been determined to coincide, a range of the delay time with respect to the rise of the clock signal and a range of the delay time with respect to the fall of the clock signal. | 07-01-2010 |
| 20100180143 | TECHNIQUES FOR IMPROVED TIMING CONTROL OF MEMORY DEVICES - Techniques for improved timing control of memory devices are disclosed. In one embodiment, the techniques may be realized as a memory controller to communicate with a memory device via a communications link. The memory controller may comprise a memory interface to exchange data with the memory device via a set of N conductors according to at least one clock, the data being encoded such that each M bits of data are represented by at least one symbol and each symbol is associated with a combination of signal levels on a group of n conductors, wherein M| 07-15-2010 | |
| 20100199120 | STRATEGY TO VERIFY ASYNCHRONOUS LINKS ACROSS CHIPS - Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier. | 08-05-2010 |
| 20100205473 | SYNCHRONIZATION OF TWO COMMUNICATION NETWORKS OF AN ELECTRONIC DATA-PROCESSING SYSTEM - A method for synchronizing two communication networks of an electronic data-processing system. One or a plurality of nodes is connected to the two communication networks in each case. Each of the two communication networks has a schedule, which specifies at least one time slot for a synchronization message. One of the nodes of the first communication network, and one of the nodes of the second communication network are linked to one another by a shared arithmetic unit. A deviation between the time slots for the synchronization messages on the two communication networks is determined as a function of the schedules of the two communication networks. The deviation is used to determine correction values, which are forwarded to at least one other node. The occurrence of the time slots for the synchronization messages is modified by the other node as a function of the correction values. | 08-12-2010 |
| 20100229019 | Method of Controlling Spread-Spectrum Clock Generation - A method of controlling spread-spectrum clock generation is disclosed. A first-in first-out (FIFO) buffer is first monitored. When the FIFO buffer is determined to be abnormal, an associated spread-spectrum clock generator (SSCG) is turned off or its spread range is decreased. | 09-09-2010 |
| 20100229020 | PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS USING SELECTIVE DATA TRANSFER THROUGH COMMUNICATON ELEMENTS - A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements. | 09-09-2010 |
| 20100235674 | Systolic Merge Sorter - A sorter system includes a clock continuously generating a series of clock signals, a systolic array circuit, and control circuitry in communication with serial access memory that stores data items of a sequence to be sorted and with the systolic array circuit to supply thereto data items as input and to receive therefrom data items as output. The systolic array circuit includes at least one processing module and K−1 registers, where K is an integer value greater than two. Each processing module has at least one of the registers, each register for storing one data item. The control circuitry serially presents K data items for input to the systolic array circuit in synchronization with the clock signals. On the next clock cycle after the control circuitry presents to the systolic array circuit the last of the K data items, the data item of least value in the given subsequence is output. | 09-16-2010 |
| 20100235675 | Non-blocking Address Switch with Shallow Per Agent Queues - In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated. | 09-16-2010 |
| 20100250999 | SWITCHING AMONG APPLICATIONS ACCORDING TO DATE-AND-TIME OF SCHEDULE ITEM - An approach for switching from one application to another, according to time information of a schedule item and including converting data of the first application to data suitable for use in the other application, is provided. | 09-30-2010 |
| 20100281292 | METHOD AND APPARATUS FOR RESOLVING CLOCK MANAGEMENT ISSUES IN EMULATION INVOLVING BOTH INTERPRETED AND TRANSLATED CODE - Methods and systems for resolving clock management issues in emulation of a target system on a host system are disclosed. A first set of code instructions of a target program is emulated to generate a first set of emulated instructions that emulate a first component on the host system. A second set of code instructions is emulated to generate a second set of emulated instructions that emulate a second component of the target system on the host system. The first set is executed based on a first clock (which may be a fixed clock) and the second set is executed based on a second clock (which may be a variable clock). The host system adjusts the first or second clock, execution of the first or second sets of instructions or a memory access to maintain a desired synchronization between the first and second sets of instructions. | 11-04-2010 |
| 20100306570 | ASYNCHRONOUS INTERFACE CIRCUIT AND DATA TRANSFER METHOD - An asynchronous interface circuit for transferring a data stream between different clock domains, the asynchronous interface circuits includes a data holding circuit for sequentially receiving and transferring data of the data stream in synchronism with a first clock signal, and holding the received data until an input of a next data, an asynchronous memory for sequentially receiving the data held in the data holding circuit in synchronism with the first clock signal and for outputting the data in the order of inputting in synchronism with a second clock signal. The asynchronous interface circuit further includes a monitor for detecting an operating state of the asynchronous memory, and a selector for selecting one of the data output from the asynchronous memory and the data output from the data holding circuit on the basis of a detecting result of the monitor. | 12-02-2010 |
| 20100318831 | GLOBAL CLOCK VIA EMBEDDED SPANNING TREE - In some embodiments, the present invention relates to a method of maintaining a global clock within a multiprocessor system having a plurality of nodes that are connected in a network via links. A virtual spanning tree is mapped onto the network and the nodes and the links are configured such that each node is in a parent-child relationship with one or more other nodes in the virtual spanning tree. A global clock is generated in a root of the virtual spanning tree and global clock signals are communicated down the virtual spanning tree to each of the nodes. | 12-16-2010 |
| 20100325468 | Memory Unit Access - A system comprises a control unit and a circuit. The circuit comprises an input clock connection for receiving a clock signal from the control unit, a first output clock connection for providing the clock signal to a first memory unit, a second output clock connection for providing the clock signal to a second memory unit, a control connection for receiving a control signal from the control unit. The circuit further comprises multiplexer circuitry connected to the input clock connection, the first and the second clock connections and the control connection. The multiplexer circuitry is configured to react to the control signal from the control unit by providing the clock signal to the first memory unit or the second memory unit. In other words, a clock signal is multiplexed in such a way that only one memory unit at a time receives the clock signal. An effect of this is that in a system having two or more memory units, unique access is provided to one memory unit at a time. | 12-23-2010 |
| 20100325469 | CLOCK CONTROL DEVICE, CLOCK CONTROL METHOD, CLOCK CONTROL PROGRAM AND INTEGRATED CIRCUIT - An instruction detecting section ( | 12-23-2010 |
| 20110010576 | MICROCODE CONFIGURABLE FREQUENCY CLOCK - A microcode configurable frequency clock that may be used to control the speed of high speed comparison in an operational optical transceiver. The frequency clock includes a memory and a logic circuit. The memory receives microcode generated data relating to the desired speed of comparison. The logic circuit is configured to receive an input clock signal and to produce an output clock signal by frequency dividing the input signal based on the microcode generated data. The output clock is used to control the speed of comparison in the optical transceiver. | 01-13-2011 |
| 20110022878 | Configuring Multi-Bit Slave Addressing on a Serial Bus Using a Single External Connection - Unique addresses for a plurality of devices may be programmed through a single external connection (pin) on each device by using a one of a plurality of different analog voltage or current values on the single external pin in combination with a serial clock of a serial data bus for each device requiring a unique binary address. The unique binary address is stored in the device after detection of certain number of clocks on the serial data bus. Once the unique binary address has been stored in the device, the single external connection may be used for another purpose such as a multifunction external connection. This unique binary address may be retained by the device until a power-on-reset (POR) or general reset condition occurs. Address detection and address load commands on the serial bus may also perform the same address definition and storage functions. | 01-27-2011 |
| 20110055617 | Hybrid Single and Dual Channel DDR Interface Scheme by Interleaving Address/Control Signals During Dual Channel Operation - A memory structure is described. In one embodiment, the memory structure comprises a memory controller configured to receive a clock signal and to be coupled to a plurality of memory modules via a single address/control bus. The memory controller couples to each of the plurality of memory modules via a separate chip select signal for each memory module. The memory controller issues commands across the address/control bus to the memory modules in an interleaved fashion in accordance with the timing supplied by the clock. During a waiting period after issuance of a command to one memory module, the memory controller can issue commands to a different memory module. | 03-03-2011 |
| 20110055618 | MEMORY CONTROLLING METHOD - A memory controlling method adapted for driving a memory within a computer system is disclosed. When the computer system is booted, the memory is driven and tested via the BIOS. The memory controlling method performs tests on multiple controlling signals of the memory. The memory controlling method includes steps of: detecting an active window of each controlling signal; determining whether the active windows is larger than a predetermined window; performing a parameter adjustment on the controlling signals if one of the active windows is smaller than the predetermined window; performing a phase range test between two of the control signals if the active windows are larger than the predetermined window; performing a phase adjustment on the active windows of the controlling signals if the controlling signals fails in the phase range test; and driving the memory according to the adjusted controlling signals. | 03-03-2011 |
| 20110078485 | Increasing Memory Bandwidth in Processor-Based Systems - The amount of data that may be transferred between a processing unit and a memory may be increased by transferring information during both the high and low phases of a clock. As one example, in a graphics processor using a general purpose register file as a memory and a mathematical box as a processing unit, the amount of data that can be transferred can be increased by transferring data during both the high and low phases of a clock. | 03-31-2011 |
| 20110078486 | DYNAMIC SELECTION OF EXECUTION STAGE - Methods and apparatus relating to dynamic selection of execution stage are described. In some embodiments, logic may determine whether to execute an instruction at one of a plurality of stages in a processor. In some embodiments, the plurality of stages are to at least correspond to an address generation stage or an execution stage of the instruction. Other embodiments are also described and claimed. | 03-31-2011 |
| 20110087914 | I2C BUFFER CLOCK DELAY DETECTION METHOD - Systems and methods are disclosed that promote communication in an I2C Bus. These systems and methods include establishing a connection between at least two units within coupled together in a I2C bus, transmitting a message from a master to a slave, transitioning the slave to below a threshold during communications, and delaying additional messages from the master to the slave. | 04-14-2011 |
| 20110099411 | USB Device and Correction Method Thereof - A universal serial bus (USB) device for receiving data from a link partner is provided. An electrical physical unit receives a series of data from the link partner via a cable and generates a symbol string corresponding to the series of data, wherein the symbol string includes a plurality of symbols. A correction unit receives the symbol string, determines whether each symbol of the received symbol string is a first type symbol and counts a quantity of the received first type symbol, wherein when the counted quantity is odd and a next received symbol is a second type symbol, the next received symbol is replaced with the first type symbol by the correction unit. | 04-28-2011 |
| 20110107133 | SYSTEM AND METHOD FOR IMPLEMENTING A CLOUD COMPUTER - One embodiment is a clocking system for a computing environment. The system comprises a first set of processes executing in a first computing environment; a first local clock mechanism associated with the first set of processes; and a first communications channel for connecting the first local clock mechanism with the first set of processes. The first local clock mechanism stores clock rates of the first set of processes, wherein each clock rate is specified by function and source and destination combination, the first local clock mechanism further coordinating the clock speeds of the first set of processes as necessary. | 05-05-2011 |
| 20110107134 | INFORMATION RECORDING MEDIUM, METHOD FOR RECORDING INFORMATION ON INFORMATION RECORDING MEDIUM, METHOD FOR REPRODUCING INFORMATION FROM INFORMATION RECORDING MEDIUM, AND METHOD FOR MANUFACTURING INFORMATION RECORDING MEDIUM - The present invention provides a measure for getting read/write control information stored within a space of a predetermined size in a format that ensures compatibility with media of a lower order or an older generation even if the size of the read/write control information increases significantly as the storage densities of information storage media rise in the near future. On an information storage medium, a data sequence is writable as a combination of marks and spaces. The medium has at least one information storage layer, which has an information storage area to store information and a control information area for use to perform a read/write operation on the at least one information storage layer. The control information area stores at least one set of control information, which includes a first kind of write pulse information including information to be used as a reference value and a second kind of write pulse information including information to be used as an offset value. If the pulse width or pulse position of a write pulse is definable with a precision of 1T/n (where T is a channel clock pulse width and n is a positive integer), the size of the offset value is large enough to define at least an n/2 range. | 05-05-2011 |
| 20110119522 | ELECTRONIC DEVICE WITH REDUCED POWER CONSUMPTION IN EXTERNAL MEMORY - An electronic device for data processing is disclosed having a CPU ( | 05-19-2011 |
| 20110138217 | SEMICONDUCTOR DEVICE - An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result. | 06-09-2011 |
| 20110145624 | SYSTEM AND METHOD FOR ASYNCHRONOUSLY AND INDEPENDENTLY CONTROLLING CORE CLOCKS IN A MULTICORE CENTRAL PROCESSING UNIT - A method of controlling core clocks in a multicore central processing unit is disclosed and may include executing a zeroth dynamic clock and voltage scaling (DCVS) algorithm on a zeroth core and executing a first DCVS algorithm on a first core. The zeroth DCVS algorithm may operable to independently control a zeroth clock frequency associated with the zeroth core and the first DCVS algorithm may be operable to independently control a first clock frequency associated with the first core. | 06-16-2011 |
| 20110145625 | MULTI-CORE CLOCKING SYSTEM WITH INTERLOCKED 'ANTI-FREEZE' MECHANISM - A clocking system, comprises a plurality of clocked data processing devices and a clock control circuit controlling a generation of a plurality of clock signals and an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices. A method for clocking a plurality of clocked data processing devices comprises controlling a generation of a plurality of clock signals and controlling an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices. | 06-16-2011 |
| 20110161718 | Command Decoding Method and Circuit of the Same - A decoding circuit for decoding a command is provided. The received command is transmitted during at least two clock periods of a clock signal, and the received command is divided to a former encoded data and a latter encoded data. The decoding circuit includes a pre-trigger signal generating unit, a comparing unit, and a starting signal generating unit. The pre-trigger signal generating unit receives the former encoded data and generates a pre-trigger signal when the former encoded data of the received command matches the corresponding former encoded data of a predetermined command. The comparing unit generates a match signal when the latter encoded data of the received command is the same with the latter encoded data of the predetermined command. The starting signal generating unit outputs a starting signal according to the pre-trigger signal and the match signal. The starting signal starts a corresponding operation of the predetermined command. | 06-30-2011 |
| 20110161719 | PROCESSING DEVICES - An embodiment of a processing device includes a function unit and a control unit. The function unit receives input data and performs a specific operation to the input data to generate result data. The control unit receives the result data and generates an output signal. The control unit latches the result data according to a first clock signal to generate first data and latches the result data according to a second clock signal to generate second data. The control unit compares the first data with the second data to generate a control signal and selects the first data or the second data to serve as data of the output signal according to the control signal. The second clock signal is delayed from the first clock signal by a predefined time period. | 06-30-2011 |
| 20110173481 | FREQUENCY ADAPTER UTILIZED IN HIGH-SPEED INTERNAL BUSES - A frequency adapter for synchronizing data transfers between a low-frequency module and a high-frequency module connected to an internal bus. The frequency adapter includes a low-to-high synchronization unit for synchronizing data transfers from the low frequency module to the high-frequency module, wherein the low-to-high synchronization unit is clocked by a low frequency clock; and a high-to-low synchronization unit for synchronizing data transfers from the high frequency module to the low-frequency module, wherein the high-to-low synchronization module is clocked by a low frequency clock. | 07-14-2011 |
| 20110185219 | MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS - A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode. | 07-28-2011 |
| 20110197089 | DATA PROCESSING APPARATUS AND CONTROL METHOD THEREOF - A data processing apparatus includes: a plurality of processing units adapted to process data according to input operation clocks; and a control unit adapted to measure response times of the plurality of processing units when the operation clocks of a common frequency are supplied to the plurality of processing units, and to control a frequency of the operation clocks to be supplied to at least one of the plurality of processing units so that a plurality of measured response times become closer to each other. | 08-11-2011 |
| 20110202788 | METHOD AND DEVICE FOR CLOCK GATE CONTROLLING - A method and an activity tracking device for controlling clock gating of a data processing block is provided. The processing block is one of a plurality of data processing blocks of a circuitry system interconnected by a streaming data bus. The activity tracking device receives a busy indication from processing units and streaming data bus segments of the data processing block to keep track of the data transfer and processing activity therein, and has an output connected to a clock gate at the root of the local clock distribution network of the data processing block to gate off the clock of the data processing block when an idle condition is detected, and to recover the clock when a wake-up condition is detected. This provides a low complexity way of automatic clock gating in SoC designs, and generally a way to reduce power consumption of electronic devices. | 08-18-2011 |
| 20110208991 | MEMORY DEVICE, BOARD, LIQUID CONTAINER, HOST DEVICE, AND SYSTEM - A memory device includes a memory unit, a memory control unit that controls an access of the memory unit, a control unit that performs a communication process with a host device, a data terminal, a reset terminal, and a clock terminal. The control unit outputs a response signal for reporting the connection of the memory device to the host device through the data terminal in an m-th clock cycle (m is at least an integer of 1≦m≦n) corresponding to ID information of the memory device among first to n-th clock cycles (n is an integer of 2 or more) of clocks input to the clock terminal. | 08-25-2011 |
| 20110219257 | IDLE-STATE DETECTION CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND IDLE-STATE DETECTION METHOD - An idle-state detection circuit detects that the processor repeats every predetermined number of clocks an operation to load data satisfying a preset idle-state condition from a particular address, and determines that the processor is in an idle state if the number of iterations is greater than a preset specified number of loops. | 09-08-2011 |
| 20110225444 | MEMORY INTERFACE HAVING EXTENDED STROBE BURST FOR WRITE TIMING CALIBRATION - Methods and systems for calibrating parameters for communication between a controller and a memory device. A memory controller may be configured to calibrate one or more of the write latency and/or the latency window of a memory device such that a data signal and a data strobe signal are received by the memory device within the latency window of the memory device. | 09-15-2011 |
| 20110225445 | MEMORY INTERFACE HAVING EXTENDED STROBE BURST FOR READ TIMING CALIBRATION - Methods and systems for calibrating parameters for communication between a controller and a memory device. A memory controller may be configured to calibrate one or more of the read latency and/or the latency window of a memory controller such that a data signal and a data strobe signal are received by the memory controller within the latency window of the memory controller. | 09-15-2011 |
| 20110239036 | WAVE PIPELINE WITH SELECTIVELY OPAQUE REGISTER STAGES - A selectively synchronous wave pipeline segment and an integrated circuit (IC) including the segment. The segment includes a normally opaque input stage and output stage and multiple internal stages that are normally transparent. A programmable local clock control circuit provides internal stage clock selection control to internal stages. The internal clock selection control determines whether each internal pipeline stage is gated opaque by a local clock. The programmable local clock control circuit is programmed to allows data items to propagate as data waves in a wave pipeline until each wave reaches a point where beyond, a race condition is likely to exist. Multiple pipeline data items pass as data waves between input and said output stage selectively unclocked. | 09-29-2011 |
| 20110258477 | SELECTIVE LIMITS ON PROCESSOR TURBO MODES - A method, computer program product and system for controlling the maximum turbo mode of a processor in a turbo boost state. The method comprises limiting a maximum turbo mode available to the processor by over-reporting the amount of current drawn by the processor to the current monitoring feedback line to the processor, wherein the processor uses the over-reported current to maintain operation of the processor within performance specifications of the processor. An automatic calibration routine may be used to determine nominal amounts of current over-reporting that may be used to prevent the processor performance from exceeding the maximum turbo mode. In one embodiment, a digital potentiometer is included in the voltage regulator circuit to over-report the current as instructed. | 10-20-2011 |
| 20110271135 | DATA MANAGEMENT METHOD AND NODE APPARATUS - When receiving a predetermined command regarding an assigned key to a node apparatus, a history element is registered, which includes a first Logical Clock Value (LCV) at a first time the predetermined command was received, and a data value at a second time represented by the first LCV. When receiving a reference request to reference a data value at a third time represented by a specific LCV, a first marker is registered, which includes, as the specific LCV, a second LCV at a time when the reference request was received or a third LCV designated by the reference request, and further includes information concerning the reference request. When a fixed LCV in a system becomes not less than the specific LCV, a data value corresponding to the assigned key at the third time is identified from the history elements including first LCVs that are not greater than the specific LCV. | 11-03-2011 |
| 20110289341 | CLOCK AND DATA RECOVERY (CDR) METHOD AND APPARATUS - Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed. | 11-24-2011 |
| 20110314324 | Variable latency interface for read/write channels - A variable latency interface and method for managing variable latency. An apparatus includes a storage device controller and a read/write channel coupled to the storage device controller by a variable latency interface. The variable latency interface includes a media control component configured for read and write operations. The variable latency interface also includes a data transfer component configured for read and write operations. A read or write operation in the media control component is offset from a respective read or write operation in the data transfer component by a latency period. | 12-22-2011 |
| 20110320854 | Inter-clock domain data transfer FIFO circuit - The inter-clock domain data transfer FIFO circuit provides a circuit that transfers data between two clock domains of unrelated frequencies. The gate count is kept relatively low, thereby allowing data transfer between the two clock domains at one data item per cycle of the lower of the two frequencies. Depending on the frequency difference between the data producer and consumer, the initial latency could be as low as a fraction of a cycle and no more than two cycles of the consumer's clock. The operation of the data transfer FIFO circuit has been verified using gate-level simulations for several ratios of clock frequencies. | 12-29-2011 |
| 20120011389 | SELECTIVELY INCREASING THROUGHPUT OF A CPU CORE - In a computing system having a multi-core central processing unit (CPU) having at least two cores, it is determined that a task to be scheduled meets clock acceleration criteria such as requiring a number of threads less than or equal to a pre-defined threshold and/or having tasks that will run above a pre-determined amount of time. Thereafter, a clock speed of a first core of the CPU is increased and a clock speed of a second core of the CPU is decreased. Once the clock speeds have been adjusted, the task is scheduled to be executed by the first core. Related apparatus, systems, techniques and articles are also described. | 01-12-2012 |
| 20120060046 | SYSTEMS AND METHODS FOR SYNCHRONIZING OPERATIONS AMONG A PLURALITY OF INDEPENDENTLY CLOCKED DIGITAL DATA PROCESSING DEVICES THAT INDEPENDENTLY SOURCE DIGITAL DATA - In a system for distributing data, distribution device is configured to distribute timestamp, offset and source location information for a digital data stream to an execution device, and the execution device is configured to seek digital data corresponding to the received information. The execution device is further configured to execute the digital data relative to a clock rate maintained by the distribution device. Related methods include receiving timestamp, offset and source location information for the digital data stream and seeking digital data corresponding to the received offset and source location information. | 03-08-2012 |
| 20120066538 | USING PULSES TO CONTROL WORK INGRESS - The present invention extends to methods, systems, and computer program products for using pulses to control work ingress. Generally, embodiments of the invention use a variable-speed clock for accepting work for lower-priority services. A clock rate is controlled by a load monitor. The load monitor periodically collects sensor measurements of resources available after allocations by higher-priority services. Based on the sensor measurements, the load monitor adjusts the clock speed up or down (i.e., depending on the amount of resources available after allocations by higher-priority services). At the boundary of the lower-priority service (e.g., where work enters the system), work requests are enqueued to be associated with a future pulse of the clock. Work is accepted or rejected based on a determination of whether the work request can be allocated a clock pulse within a defined period of time. | 03-15-2012 |
| 20120066539 | INTERCHANGEABLE LENS AND CAMERA BODY - An interchangeable lens that can be detachably fitted to a camera body includes: a clock signal reception unit that receives a clock signal outputted from the camera body; a control command reception unit that receives a control command and data signal from the camera body, the control command and data signal being in synchrony with the clock signal, specifying a control command for the interchangeable lens and including type data specifying a type of the control command; a response generation unit that generates a response data signal including the type data on the basis of the control command and data signal; and a response transmission unit that transmits the response data signal to the camera body in synchrony with the clock signal received by the clock signal reception unit when a control command and data signal is received from the camera body in a next communication cycle. | 03-15-2012 |
| 20120072761 | Device and method for implementing clock transparent transmission - The present invention discloses a device and method for implementing a transparent clock. The device comprises: a clock module, a data identification module and a data correction module, wherein the clock module is connected with the data identification module and the data correction module respectively, and used for providing clock information to the data identification module and the data correction module; the data identification module is used for receiving data and acquiring current time information from the clock module; and the data correction module is connected with the data identification module, and is used for accumulating a positive or negative value of the current time information with the time information included in the data according to an outputting direction of the data and outputting the accumulated time information together with the data. By adopting the present invention, the residence time information of the data in the switching node is acquired by a hardware device, and the time information included in the data is corrected according to the residence time information, so that the transparent clock of the data can be effectively implemented, and the acquired residence time information is of a high precision and is acquired stably. | 03-22-2012 |
| 20120089858 | CONTENT PROCESSING APPARATUS - A content processing apparatus includes a plurality of takers. Each of a plurality of takers runs with reference to any one of N (N: an integer of two or more) of clocks, and the plurality of takers respectively take a plurality of contents. A mixer mixes the plurality of contents respectively taken by the plurality of takers so as to create equal to or less than N of output contents. A changer changes the clock referred to by each of the plurality of takers corresponding to a mode switching. An adjuster adjusts a mixing manner of the mixer in association with a change process of the changer so that a mixing process is executed for every contents corresponding to a common clock. | 04-12-2012 |
| 20120096302 | FIELD DEVICE HAVING A REAL TIME CLOCK - A field device includes a real time clock, and at least one communication interface for at least unidirectionally, receiving and transmitting data. The real time clock is detachably connected to the at least one receiving communication interface of the field device, and includes a power supply. | 04-19-2012 |
| 20120159230 | Mechanism for Updating Memory Controller Timing Parameters During a Frequency Change - A mechanism for updating memory controller timing parameters during a frequency change includes a memory controller that controls memory transactions to a memory unit. The integrated circuit may also include a power manager unit that is coupled to the memory controller and may be configured to provide an indication that a memory clock frequency is changing to a new frequency. The integrated circuit also includes a storage that includes a number of entries. Each entry may store a predetermined set of timing values that corresponds to a respective memory clock frequency. In response to receiving the indication, the memory controller may access a given entry of the storage that corresponds to the new frequency, and may generate new timing values that correspond to the new frequency based upon the predetermined set of timing values stored within the given entry. | 06-21-2012 |
| 20120159231 | DATA PROCESSING APPARATUS, DATA PROCESSING METHOD AND RECORDING MEDIUM - A data processing apparatus comprising: a gate unit connected to an input or an output of a processing unit and configured to cut off the data input and output; a control unit configured to control a supply of clock to the processing unit; and an instruction unit configured to give an instruction for the clock control to the control unit, wherein the control unit controls the gate unit and controls the clock supplied to the processing unit based on an instruction from the instruction unit, whereby securing a higher power saving effect. | 06-21-2012 |
| 20120179931 | DATA PROCESSING MODULE PROVIDING UNIFORM POWER CONSUMPTION FOR DIGITAL LOGIC - A microcontroller that includes logic to provide a uniform overall power consumption current of parts of the microcontroller generated by sequential element switching is disclosed. For example, the number of sequential elements switching at the triggering edge of the clock is calculated to determine a number of switching elements. The number of switching elements is compared to the number of sequential elements of the circuitry. Additional sequential elements are added in the circuitry and are forced to switch so that the overall number of switching elements equals the number of sequential elements, excluding the additional sequential elements. | 07-12-2012 |
| 20120198267 | System and Method for Facilitating Data Transfer Between a First Clock Domain and a Second Clock Domain - System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination. | 08-02-2012 |
| 20120239963 | TIMING UNINTERRUPTIBLE PROCESSES - A method for controlling the execution of a process in a user device, such as a set-top-box is provided. An instruction is received at an input of the user device from the user and this instruction causes an uninterruptible process to begin or commence in the user device after a time delay, measured preferably from receipt of the initial instruction. The input, or inputs, of the device is/are monitored to determine whether a subsequent instruction is received from the user within a time period. Based on this determination, the time delay applied to future processes is adjusted. By adjusting the time delay in response to input from the user, the time delay can be automatically matched to a user's preferences. By adjusting the time delay in response to input from the user, the time delay can be automatically matched to a user's preferences. A corresponding apparatus and computer program are also provided. | 09-20-2012 |
| 20120284554 | DATA PROCESSING DEVICE AND MOBILE DEVICE - A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card. | 11-08-2012 |
| 20130019121 | Synchronization of Data Streams with Associated Metadata StreamsAANM Ben-David; ShayAACI HaifaAACO ILAAGP Ben-David; Shay Haifa ILAANM Hazanovich; EvgenyAACI HaifaAACO ILAAGP Hazanovich; Evgeny Haifa ILAANM Mandel; ZakAACI NesherAACO ILAAGP Mandel; Zak Nesher IL - Synchronizing a data stream with an associated metadata stream by receiving a data stream and a metadata stream having a plurality of metadata events associated with the data stream, identifying within the data stream a plurality of data events, matching each of the data events to one of the metadata events in accordance with a matching criterion, and synchronizing the data stream with the metadata stream by effecting a relative time shift between the metadata stream and the data stream in accordance with a time shift adjustment value that results in the smallest sum of absolute differences between time indices of each matched data event and metadata event. | 01-17-2013 |
| 20130024716 | STORING EVENT DATA AND A TIME VALUE IN MEMORY WITH AN EVENT LOGGING MODULE - Example embodiments disclosed herein relate to storing event data and a time value in memory with an event logging module. Example embodiments of the event logging module include event command storage, clock command storage, and memory command storage. | 01-24-2013 |
| 20130024717 | Double Data Rate Output Circuit and Method - A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock. | 01-24-2013 |
| 20130080820 | Minimizing the Use of Chip Routing Resources When Using Timestamped Instrumentation Data - A timestamp generator generates a timestamp value having a predetermined number of most significant bits and a predetermined number of least significant bits. The least significant bits are transmitted to a client via a parallel data bus. The most significant bits are transmitted to the client sequentially via a series data bus. Each client receives the parallel least significant bits and the series most significant bits and assembles a complete time stamp value. | 03-28-2013 |
| 20130103971 | COMPUTER SYSTEM AND METHOD OF CONFIGURING CLOCK THEREOF - The present invention relates to a computer system and a clock configuring method. The computer system comprises at least two nodes, wherein each of the at least two nodes includes a selecting module and a CPU, inputs to the selecting module of any node comprise a clock of the node and a clock output from other node, and an output terminal of the selecting module is connected to the CPU and an input terminal of the selecting module of other node; the computer system further comprises a clock controlling module, whose output terminal is connected to a control terminal of the selecting module to control the clocks of the at least two nodes to be the same clock. When clocks of plural nodes are abnormal, the computer system can still normally operate as long as there is a normal clock in the computer system. | 04-25-2013 |
| 20130173951 | CONTROLLING COMMUNICATION OF A CLOCK SIGNAL TO A PERIPHERAL - A method of communicating in an electronic system or apparatus is disclosed. The method includes using a processor to communicate with a peripheral. The method further includes using the peripheral to request a clock signal. The method also includes selectively control communication of the clock signal to the peripheral in response to the request. | 07-04-2013 |
| 20130179721 | USING PULSES TO CONTROL WORK INGRESS - The present invention extends to methods, systems, and computer program products for using pulses to control work ingress. Generally, embodiments of the invention use a variable-speed clock for accepting work for lower-priority services. A clock rate is controlled by a load monitor. The load monitor periodically collects sensor measurements of resources available after allocations by higher-priority services. Based on the sensor measurements, the load monitor adjusts the clock speed up or down (i.e., depending on the amount of resources available after allocations by higher-priority services). At the boundary of the lower-priority service (e.g., where work enters the system), work requests are enqueued to be associated with a future pulse of the clock. Work is accepted or rejected based on a determination of whether the work request can be allocated a clock pulse within a defined period of time. | 07-11-2013 |
| 20130198555 | SYSTEM AND METHOD FOR REDUCING CROSSTALK IN ON-CHIP NETWORKS - A data connector includes two different sets of wires that transport data between components of a computer system. A first set of wires transports data from a first component to a second component. A second set of wires transports data from the second component to the first component. The first set of wires is interlaced with the second set of wires so that each wire in the data connector transports data in the opposite direction of one or more neighboring wires. | 08-01-2013 |
| 20130219209 | ELECTRONIC DEVICE WITH AN OVERCLOCKING MODE AND METHOD - An electronic device with an overclocking mode includes a processor, a memory storing a first range and a second range, and a digital controller which includes a first register, a second register, a monitor module, a determining module, a first writing module, an implementing module, and a second writing module. The monitor module monitors a value of current of the processor. The determining module determines whether the current is within the first range. The first writing module writes the current value in the first register. The implementing module reduces a value from the current value to acquire a new current value. The second writing module writes the new current value in the second register. The processor reads the new current value, detects whether the new current value is within the second range, and keeps itself in the overclocking mode when the new current value is within the second range. | 08-22-2013 |
| 20130219210 | Flat Panel Display Driver Method and System - Methods and systems are described for enabling display system data transmission during use. An integrated circuit package includes input interface circuitry configured to receive an audio-video data stream having a video signal and timing information and timing extraction circuitry that can identify blanking patterns for the video signal. The package includes input processing circuitry for receiving audio-video signal and converting the audio-video data stream input into a low voltage differential signal (LVDS). The package includes a timing controller having timing extraction circuitry, a set of symbol buffers, a scheduler, and timing control circuitry. All configured to implement LVDS data transfer and in some implementation enable point to point data transfer from data buffers to associated column drivers. | 08-22-2013 |
| 20130227331 | Modular Structure for Processing Data - A circuit arrangement for a data processing system is configured to process data in a plurality of modules. The circuit arrangement is configured such that each module is provided with at least one clock pulse, a time base and a base of at least one additional physical variable. The circuit arrangement also comprises a central routing unit to which the plurality of modules are coupled and via which the plurality of modules can periodically exchange data amongst themselves, based on the time base and/or the base of other physical variables. Each module is configured independently and parallel to other modules of the plurality of modules in order to process data. The circuit arrangement is employed in a corresponding method. | 08-29-2013 |
| 20130246836 | COMMAND DECODING METHOD AND CIRCUIT OF THE SAME - A decoding circuit includes a pre-trigger signal generating unit, a comparing unit, and a starting signal generating unit. The pre-trigger signal generating unit receives the former encoded data and generates a pre-trigger signal when the former encoded data of the received command matches the corresponding former encoded data of a predetermined command. The comparing unit generates a match signal when the latter encoded data of the received command is the same with the latter encoded data of the predetermined command. The starting signal generating unit outputs a starting signal according to the pre-trigger signal and the match signal. The starting signal starts a corresponding operation of the predetermined command. | 09-19-2013 |
| 20130275799 | CIRCUIT, SYSTEM AND METHOD FOR SELECTIVELY TURNING OFF INTERNAL CLOCK DRIVERS - The present invention includes a circuit, system and method for selectively turning off internal clock drivers to reduce operating current. The present invention may be used to reduce power consumption by reducing operating current in a memory device. Operating current may be reduced by turning off internal clock drivers that deliver a clock signal during selected periods of time. According to an embodiment of clock control circuitry of the present invention, an internal clock is disabled if a no operation command is detected during periods of time when no read or write burst operation is taking place. Methods, memory devices and computer systems including the clock control circuitry and its functionality are also disclosed. | 10-17-2013 |
| 20130290769 | SYSTEMS AND METHODS FOR HANDLING RACE CONDITIONS DURING DATA TRANSFER IN AN IMPLANTABLE MEDICAL DEVICE - The accuracy of data processing operations in implantable medical devices is improved through reductions in errors associated with data acquisition, reading, and transmission. In one embodiment, two or more circuit modules of the device are operated at different clock speeds and a voting scheme is utilized to obtain a valid data value from one of the modules. The disclosure describes methods, devices and systems that utilize the voting schemes to eliminate errors induced by race conditions in obtaining the valid data values by obtaining a plurality of data samples during operation of the circuit modules at the different clock speeds and selecting from among the data samples the valid data value. | 10-31-2013 |
| 20130339778 | COMMUNICATION BETWEEN DOMAINS OF A PROCESSOR OPERATING ON DIFFERENT CLOCK SIGNALS - Implementations of the present disclosure involve an apparatus and/or method for communicating between domains of a computing system, where at least one of the domains operates on a skipped clock signal. Communication from a skipped clock domain to a non-skipped clock domain, or free running domain, may include a valid signal component configured to indicate when a new data packet is available and one or more counters associated with the domains to count received data packets for acknowledgement or credit purposes. The free running domain may receive data packets from any number of skipped clock domains through the communication scheme described herein. Communication from a free running domain to a skipped clock domain may include delaying transmitted data packets to correspond with the cycles of the skipped clock signal to ensure that transmitted data packets arrive at the skipped clock domain to be properly read on a skipped clock cycle. | 12-19-2013 |
| 20140013151 | I2C MULTIPLEXER SWITCHING AS A FUNCTION OF CLOCK FREQUENCY - In accordance with one embodiment of the invention, an I2C bus multiplexing circuit for use in an I2C bus interface can be provided. The I2C bus multiplexing circuit can facilitate multiplexer switching in an I2C bus interface by detecting a start command from an I2C master device via an I2C bus, buffering data from the I2C master device, detecting a clock frequency of a bus serial clock (SCL) line of the I2C master device, holding the serial data (SDA) line of the I2C master device in a clock stretch state and selecting a port based on the detected clock frequency of the SCL of the I2C master device. The method further can include sending the buffered data to an I2C slave device on the selected port. The method further can include receiving an acknowledgement from the I2C slave device on the selected port. | 01-09-2014 |
| 20140040654 | TIMEBASE PERIPHERAL - A microcontroller has a programmable timebase, wherein the timebase has a trigger input to start a timer or counter of the timebase and wherein the timebase can be configured to operate upon receiving a trigger signal in a first mode to generate a plurality of timer/counter event signals until a reset bit in a control register is set and in a second mode to generate a single timer/counter event signal and wherein the timebase can be configured to operate in a third mode to generate a predefined number of timer/counter event signals, wherein the predefined number is defined by a plurality of bits of a register. | 02-06-2014 |
| 20140082405 | EMBEDDED MULTIMEDIA CARD (eMMC), HOST CONTROLLING eMMC, AND METHOD OPERATING eMMC SYSTEM - An embedded multimedia card (eMMC) includes a clock channel that receives a clock signal from a host, a command channel that receives a command from the host, a plurality of data channels that transmit data to the host, and a return clock channel that transmits a return clock synchronized with the data to the host. | 03-20-2014 |
| 20140089723 | SEMICONDUCTOR DEVICE, CONTROL METHOD FOR THE SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - The core chips each include a timing control circuit that outputs a timing signal synchronized with the outputting of parallel data to the interface chip. The interface chip includes a data input circuit that captures parallel data in synchronization with the timing signal. With this arrangement, the timing to output the parallel data and the timing to capture the parallel data are both synchronized with the timing signal generated in the core chips. Therefore, even if there is a difference in operation speed between each core chip and the interface chip, the parallel data can be accurately captured on the interface chip side. | 03-27-2014 |
| 20140101478 | Processor Clocking Policies for Mobile Computing Devices - In one embodiment, a processor of a computing device executes a sequence of instructions that depends on one or more external operations. Software of the computing device determines a clocking policy for the processor during execution of the sequence of instructions. The clocking policy is based at least in part on a pattern of execution involving the sequence of instructions and the external operations, and the clocking policy modifies a clock speed of the processor. The software of the computing device applies the clocking policy to the processor during execution of at least a portion of the sequence of instructions. | 04-10-2014 |
| 20140122917 | ELECTRONIC DEVICE AND CLOCK RATES CONTROLLING METHOD OF OVERCLOCKING OPERATION - An electronic device and a method for controlling over clocking of CPU are provided. A temperature sensing element is coupled with the CPU and used for sensing the temperature of the CPU. A control circuit is coupled with the temperature sensing element and the CPU used for determining whether the temperature of the CPU is higher than a first threshold temperature. When the temperature of the CPU is higher than the first threshold temperature, the control circuit controls the CPU to enter an idle mode and determines whether the temperature of the CPU is lower than a second threshold temperature. When the temperature of the CPU is lower than the second threshold temperature, the CPU is controlled to return to a normal mode. The first threshold temperature is higher than the second threshold temperature, and the clock rate of the CPU is maintained at same clock rate. | 05-01-2014 |
| 20140136877 | GENERATION AND DISTRIBUTION OF A SYNCHRONIZED TIME SOURCE - An apparatus comprising a first oscillator, a time source controller coupled with the first oscillator and corrected time interval counters coupled with the time source controller. The first oscillator is configured to transmit a raw time interval pulse at regular or near regular intervals. The time source controller is configured to receive an indication of time that indicates at least one of the current day and the current time and to determine that the raw interval pulse should be adjusted based on the indication of time. The time source controller is also configured to generate a steered time interval pulse based, at least partly, on the raw time interval pulse and the indication of time, and distribute the steered time interval pulse to a plurality of hardware components. The time interval counters are configured to host a time value based on the output from the time source controller. | 05-15-2014 |
| 20140143586 | Timing Optimized Implementation of Algorithm to Reduce Switching Rate on High Throughput Wide Buses - A dynamic bus inversion (DBI) circuit disposed between a transmitter and a receiver for generating an inversion control signal that is communicated to the receiver and used to perform inversion control on data communicated along a data path between the transmitter and the receiver includes a delay data setup circuit to receive the data from the transmitter. A majority vote function circuit is used to perform majority voting for consecutive bits of data output by the delay data setup circuit to generate majority data output. An inversion control circuit receives the majority data output, retrieves feedback data from a preceding inversion control output and interprets the two data to generate inversion control signal, which is used to perform inversion control on data along the data path before being communicated to the receiver. The inversion control signal is used by the receiver to interpret the data received from the data path. | 05-22-2014 |
| 20140143587 | INDIRECT CLOCK MEASURING AND MEDIA ADJUSTMENT - A method for indirectly measuring the clock rate of a media rendering subsystem, in a media rendering device that has a separate hardware clock for rendering the media, by using the rate at which data requests are made of the CPU in the media rendering device and using the CPU clock to provide additional accuracy in measuring the clock rate. | 05-22-2014 |
| 20140189415 | MEDIA PERIPHERAL INTERFACE, ELECTRONIC DEVICE WITH MEDIA PERIPHERAL INTERFACE, AND COMMUNICATION METHOD BETWEEN PROCESSOR AND PERIPHERAL DEVICE - A media peripheral interface for communication between a processor and a peripheral device includes a clock port, a plurality of data I/Os, and a data strobe port. The clock port is operative to transfer a clock signal to the peripheral device. The data I/Os are provided for command transfer to the peripheral device and for data transfer to and from the peripheral device. The data strobe port is operative to transfer a data strobe signal to or from the peripheral device according to an instruction that the processor issues to the peripheral device. According to the clock signal, command information transferred via the data I/Os is captured. According to rising edges and falling edges of the data strobe signal, data transferred via the data I/Os are captured. | 07-03-2014 |
| 20140189416 | PREDICTIVE SEQUENTIAL CALCULATION DEVICE - A calculation device is provided that executes calculations within real-time restrictions. The calculation device implements a step of predicting a processing time of a calculation related to the amount and property of input data based on a prediction model; a step of adjusting the processing time by decreasing the amount of data used for the calculation or decreasing the number of iterative calculations when the processing time exceeds a time slice allocated to the calculation; a step of executes the calculation using the adjusted processing time; a step of updating, as required, the prediction model used for predicting the processing time according to the result of the calculation which is executed in a period where the calculation is not performed while implementing a change of the amount of data or the number of iterative calculations or change to an approximation. | 07-03-2014 |
| 20140201562 | SYSTEMS AND METHODS FOR OPTIMIZING DATA STORAGE AMONG A PLURALITY OF SOLID STATE MEMORY SUBSYSTEMS - A solid state storage device includes an interface system configured to communicate with an external host system over an aggregated multi-channel interface to receive data for storage by the solid state storage device. The solid state storage device also includes a storage processing system configured to communicate with the interface system to receive the data, process the data against storage allocation information to parallelize the data among a plurality of solid state memory subsystems, and transfer the parallelized data. The interface system is configured to receive the parallelized data, apportion the parallelized data among the plurality of solid state memory subsystems, and transfer the parallelized data for storage in the plurality of solid state memory subsystems, where each of the plurality of solid state memory subsystems is configured to receive the associated portion of the parallelized data and store the associated portion on a solid state storage medium. | 07-17-2014 |
| 20140258768 | CHANGING SETTINGS FOR A TRANSIENT PERIOD ASSOCIATED WITH A DETERMINISTIC EVENT - Disclosed embodiments relate to a system that changes transmitter and/or receiver settings to deal with reliability issues caused by a predetermined event, such as a change in a power state or a clock start event. One embodiment uses a first setting while operating a transmitter during a normal operating mode, and a second setting while operating the transmitter during a transient period following the predetermined event. A second embodiment uses similar first and second settings in a receiver, or in both a transmitter and a receiver employed on one side of a bidirectional link The first and second settings can be associated with different swing voltages, edge rates, equalizations and/or impedances. | 09-11-2014 |
| 20140298075 | Serial-to-Parallel Converter - A method for converting serial data having a certain word size to parallel data, comprises the steps of: generating segments from the serial data using one or more serially-connected first stages, wherein the segments have a predetermined bit size; storing each of the segments into a selectively turned-on flip-flop of a final stage, wherein the final stage is serially connected to the first stages, wherein the final stage has a plurality of flip-flops and each of the flip-flops has a bit size equaling to the bit size of the segments; and outputting the stored segments in parallel from the final stage. | 10-02-2014 |
| 20140310553 | HARDWARE AND SOFTWARE FOR SYNCHRONIZED DATA ACQUISITION FROM MULTIPLE DEVICES - A computer may assign a master device and at least one slave device. A program may direct the master device to broadcast counts based on its data acquisition clock. Then at least one slave device may receive the broadcast count and determine the difference between the clock count of the slave and the clock count of the master. The slave may use the difference of the counts to control the slave's voltage-controlled crystal oscillator. | 10-16-2014 |
| 20140337659 | DUAL-DOMAIN DYNAMIC MULTIPLEXER AND METHOD OF TRANSITIONING BETWEEN ASYNCHRONOUS VOLTAGE AND FREQUENCY DOMAINS - A dual-domain dynamic multiplexer and a method of transitioning between asynchronous voltage and frequency domains. One embodiment of the dual-domain dynamic multiplexer includes: (1) a first domain having a first voltage and a first clock, and a second domain having a second voltage and a second clock, (2) a plurality of data and data select input pairs wherein a data input of an input pair is in the first domain and a data select input of an input pair is in the second domain, and (3) a pre-charge stage in the second domain that is energized upon an edge of the second clock, whereby one data and data input pair is enabled and data latched in the second domain upon another edge of the second clock. | 11-13-2014 |
| 20140337660 | Trigger Circuits and Event Counters for an IC - Some embodiments provide an integrated circuit (“IC”). The IC includes multiple configurable circuits that configurably perform operations of a user design based on configuration data. The IC also includes a configurable trigger circuit that receives a set of configuration data that specifies an operational event. The configurable trigger circuit also determines whether the operational event has occurred during implementation of the user design of the IC. Additionally, the operational trigger event outputs a trigger signal upon determining that the operational trigger event has occurred. | 11-13-2014 |
| 20150039928 | DATA PROCESSING METHOD AND APPARATUS - A data processing method and apparatus are provided. The data processing apparatus includes a converter module and a control module. The converter module receives a clock signal through a pin, and decides a bit value of the first data according to a length of a corresponding period of the clock signal. The control module determines whether to perform a bit writing operation for writing the bit value into a memory according to the clock signal and the first data. | 02-05-2015 |
| 20150058657 | ADAPTIVE CLOCK THROTTLING FOR EVENT PROCESSING - Methods, apparatuses, and computer program products for adaptive clock throttling for event processing are provided. Embodiments include an event processing system receiving a plurality of events from one or more components of the distributed processing system. Embodiments also include the event processing system determining that an arrival attribute of the plurality of events exceeds an arrival threshold. Embodiments also include the event processing system, adjusting, in response to determining that the arrival attribute of the plurality of events exceeds the arrival threshold, a clock speed of at least one of the event processing system and a component of the distributed processing system. | 02-26-2015 |
| 20150082076 | DYNAMIC CLOCK REGULATION - A clock frequency is controlled by determining a cumulative duty cycle according to a ratio of a cumulative time, during an interval, that the clock frequency has a frequency greater than or equal to a design frequency threshold value to a duration of the interval. A frequency of the clock frequency is controlled to be a first frequency value when the cumulative duty cycle is less than a first duty cycle threshold; and controlled to be a second frequency value substantially less than the first frequency value when the cumulative duty cycle is greater than a second duty cycle threshold. The second duty cycle threshold is greater than or equal to the first duty cycle threshold. | 03-19-2015 |
| 20150121119 | PLURAL CIRCUIT SELECTION USING ROLE REVERSING CONTROL INPUTS - Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits. | 04-30-2015 |
| 20150149809 | SYNCHRONOUS BRIDGE CIRCUITRY AND A METHOD OF TRANSFERRING DATA USING ASYNCHRONOUS BRIDGE CIRCUITRY - Asynchronous bridge circuitry provides data communication between source circuitry | 05-28-2015 |
| 20150316951 | EDP INTERFACE AND CONTROL METHOD OF TRANSMISSION RATE OF EDP INTERFACE - The present invention discloses an eDP interface, including: a determination module, a clock signal generating module, a clock signal adjusting module, a first eDP data processing chip and a second eDP data processing chip. When the determination module determines that a target transmission rate is not equal to a protocol rate, the clock signal generating module generates a first clock signal and a second clock signal. The clock signal adjusting module adjusts the frequency of the second clock signal. The first and second eDP data processing chips process data according to the first and second clock signals, respectively. | 11-05-2015 |
| 20150316953 | Information Processing Device, Printing Device, and Control Method of an Information Processing Device - Efficient power conservation is enabled using a configuration having multiple processors. A printing device has a first processor unit that runs a program stored in a first memory, and a second processor unit that runs a program stored in a second memory, and has operating modes including a normal mode in which the first processor unit and the second processor unit operate according to a normal clock, and a first power conservation mode in which, after going to a state enabling the first processor unit to execute some processes of the second processor unit, the first processor unit operates according to the normal clock, and the second processor operates according to a slow clock having an operating frequency lower than the normal clock. | 11-05-2015 |
| 20150323956 | GENERATING A TIMEOUT SIGNAL BASED ON A CLOCK COUNTER ASSOCIATED WITH A DATA REQUEST - Various aspects provide for generating a timeout signal based on a clock counter associated with a data request. An interface component is configured for receiving a data request from a master device and forwarding the data request to a slave device. A timeout component is configured for maintaining a clock counter associated with the data request and generating a timeout signal in response to a determination that a threshold level associated with the clock counter is reached before receiving a data response associated with the data request from the slave device. | 11-12-2015 |
| 20150338878 | ARITHMETIC UNIT AND ARITHMETIC PROCESSING METHOD FOR OPERATING WITH HIGHER AND LOWER CLOCK FREQUENCIES - There is a need for providing a battery-less integrated circuit (IC) card capable of operating in accordance with a contact usage or a non-contact usage, preventing coprocessor throughput from degrading despite a decreased clock frequency for reduced power consumption under non-contact usage, and ensuring high-speed processing under non-contact usage. A dual interface card is a battery-less IC card capable of operating in accordance with a contact usage or a non-contact usage. The dual interface card operates at a high clock under contact usage and at a low clock under non-contact usage. A targeted operation comprises a plurality of different basic operations. The dual interface card comprises a basic arithmetic circuit group. Under the contact usage, the basic arithmetic circuit group performs one basic operation of the targeted operation at one cycle. Under the non-contact usage, the basic arithmetic circuit group sequentially performs at least two basic operations of the targeted operation at one cycle. | 11-26-2015 |
| 20150346763 | APPARATUS MANAGEMENT DEVICE, CLOCK SPEED CONTROL METHOD, AND PROGRAM - An apparatus manager monitors and controls respective apparatus connected via a network. A learner learns load periods when a significant load is imposed on a processor, on the basis of a utilization condition of the processor, and stores load period information indicating the learned load periods in auxiliary storage. The clock speed controller references the load period information, and controls the operating clock speed of the processor to be a normal level clock speed if the current time is during a load period, and a low level clock speed if the current time is during a time period other than a load period. | 12-03-2015 |
| 20160018844 | SHIFT REGISTER - A shift register is configured by connecting unit circuits | 01-21-2016 |
| 20160098059 | CIRCUITS FOR AND METHODS OF PROCESSING DATA IN AN INTEGRATED CIRCUIT DEVICE - A circuit for processing data in an integrated circuit device comprises a selection circuit; a first register coupled to a first output of the selection circuit; a second register implemented as a latch and coupled to a second output of the selection circuit; and a signal line coupled between the output of the first register and an input of the selection circuit. The selection circuit enables the coupling of an output signal of the first register to an input of the second register. A method of processing data in an integrated circuit device is also disclosed. | 04-07-2016 |
| 20160098061 | SCALABLE 2.5D INTERFACE ARCHITECTURE - Systems and methods for interface block. The interface block includes input/output modules distributed along the interface block and a mid-stack module interspersed within the input/output modules. The input/output modules include at least one data module and at least one command module. At least one of the input/output modules is shared by an adjacent pair of channels. Each of the input/output modules is configured to interface with a memory device via a silicon interposer or equivalent. The mid-stack module is in communication with the input/output modules via programmable logic circuitry. The mid-stack module may include independent clock quadrants. Each clock quadrant is configured to operate at different phases where each phase is aligned to a respective core clock. | 04-07-2016 |
| 20160116938 | Clock Generation for Timing Communications with Ranks of Memory Devices - A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device. | 04-28-2016 |
| 20160139622 | AUTOMATIC DATA RATE MATCHING - Pacing of a producer, operating in a producer clock domain, may be based on at least one heuristic of a credit wire that is used to return credits to the producer. The returned credits may indicate that a consumer, operating in a consumer clock domain, has consumed data produced by the producer. The at least one heuristic may be a rate at which the credits are returned to the producer. Pacing the producer based on the rate at which the credits are returned to the producer may reduce latency of the data, flowing from the producer clock domain to the consumer clock domain, by minimizing an average number of entries in use in a First-In-First-Out (FIFO) operating in a pipeline between the producer and the consumer. | 05-19-2016 |
| 20160190986 | INTEGRATED CIRCUIT COMPRISING FRACTIONAL CLOCK MULTIPLICATION CIRCUITRY - Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO. | 06-30-2016 |
| 20160253151 | CROSSING PIPELINED DATA BETWEEN CIRCUITRY IN DIFFERENT CLOCK DOMAINS | 09-01-2016 |
