Entries |
Document | Title | Date |
20080209251 | Method and Device for Clock Changeover N a Multi-Processor System - A unit and method for clock changeover in a system having at least two processing units, in which switchover device(s) are provided by which a switchover between at least two operating modes of the system is able to be implemented in which a clock pulse changeover is carried out in at least one processing unit in a switching of the operating mode. | 08-28-2008 |
20080235530 | FILE INFORMATION GENERATING METHOD, FILE INFORMATION GENERATING APPARATUS, AND STORAGE MEDIUM STORING FILE INFORMATION GENERATION PROGRAM - A method and apparatus for generating file information including setting clock information regarding a clock condition and a clock speed to be used by a speed conversion circuit block, reconstructing the clock circuit block including a new clock for accommodating insertion of the speed conversion circuit block, and associating connection terminal information indicating a connection relationship of connection terminals with speed conversion object information having set, as a speed conversion object, a connection terminal requiring connection speed conversion. The connection terminal information of the connection terminal set as the speed conversion object is extracted, speed conversion circuit information indicating a connection relationship of the connection terminals in the speed conversion circuit block and connection terminal information having the connection relationship of the connection terminals reconstructed is generated, and file information in which the speed conversion circuit block is inserted between the clock circuit block and the interface block is generated. | 09-25-2008 |
20080256381 | METHOD AND SYSTEM FOR ANALOG FREQUENCY CLOCKING IN PROCESSOR CORES - A method of and system for frequency clocking in a processor core are disclosed. In this system, at least one processor core is provided, and that at least one processor core has a clocking subsystem for generating an analog output clock signal at a variable frequency. Digital frequency control data and an analog signal are both transmitted to that at least one processor core; and that processor core uses the received analog signal and digital frequency control data to set the frequency of the output clock signal of the clocking subsystem. In a preferred implementation, multiple cores are asynchronously clocked and the core frequencies are independently set. | 10-16-2008 |
20080256382 | METHOD AND SYSTEM FOR DIGITAL FREQUENCY CLOCKING IN PROCESSOR CORES - Disclosed are a method of and system for digital frequency clocking in a processor core. At least one-processor core is provided, and that processor core has a clocking subsystem for generating an output clock signal, which may be an analog signal at a variable frequency. Digital frequency control data are transmitted or distributed to the processor core; and that one processor core receives the digital frequency control data transmitted to the core, and uses that received digital frequency control data to set the frequency of the output clock signal of the clocking subsystem of the processor core. Preferably, multiple cores are asynchronously clocked and the core frequencies are independently set, and, there is no phase relationship between the core clocks. | 10-16-2008 |
20080263382 | METHOD AND APPARATUS FOR ON-DEMAND POWER MANAGEMENT - An apparatus for on-demand power management including a system controller, a clock domain manager coupled to the system controller and a power distribution manager coupled to the system controller. The system controller monitors a processing demand in a processing system. The clock domain manager provides one or more clock frequencies and, in response to the processing demand, switches between a first set of clock frequencies and a second set of clock frequencies without halting the processing system. The power distribution manager provides one or more operating voltages and, in response to the processing demand, switches between a first set of voltages and a second set of voltages without halting the processing system. | 10-23-2008 |
20080263383 | FREQUENCY MODIFICATION TECHNIQUES THAT ADJUST AN OPERATING FREQUENCY TO COMPENSATE FOR AGING ELECTRONIC COMPONENTS - A number of performance parameters for the electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. Operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters may be predetermined (such as through reliability and burn-in testing), determined during the life of the electronic system, or some combination of these. Performance parameters can comprise prior operating frequencies, hours of operation, ambient temperature, and supply voltage. Performance parameters can comprise performance statistics determined using age-monitoring circuits, where an aged circuit is compared with a circuit enabled only for comparison. Performance statistics may also be determined though error detection circuits. If an error is detected, the operating frequency can be reduced. | 10-23-2008 |
20080276115 | Power Optimization When Using External Clock Sources - Logic circuits of a digital device may be biased to operate over specific external clock frequency ranges by programming a desired clock oscillator frequency range into a configuration memory of the digital device. In addition, clock source selection may also be programmed into the configuration register. Bias circuits are then configured so that the internal logic of the digital device will operate over the desired clock oscillator frequency range. Non-volatile memory may be used to store the contents of the configuration memory so as to retain the configuration during power down of the digital device. The non-volatile memory may be programmable fuse links, electrically erasable and programmable memory (EEPROM), FLASH memory, etc. | 11-06-2008 |
20080276116 | Method and an Apparatus for Providing Timing Signals to a Number of Circuits, an Integrated Circuit and a Node - A method of providing or transporting a timing signal between a number of circuits, electrical or optical, where each circuit is fed by a node. The nodes forward timing signals between each other, and at least one node is adapted to not transmit a timing signal before having received a timing signal from at least two nodes. In this manner, the direction of the timing skew between nodes and circuits is known and data transport between the circuits made easier. | 11-06-2008 |
20090019303 | Clock frequency adjustment for semi-conductor devices - A method and apparatus are provided for clocking data processing modules, which require differing average clock frequencies, and for transferring data between the modules. This comprises a means for providing a common clock signal to modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. Clock pulses are applied to modules between which data is to be transferred at times consistent with the data transfer. | 01-15-2009 |
20090024864 | AUDIO PROCESSOR HAVING DYNAMIC AUTOMATIC CONTROL FUNCTION OF OPERATING FREQUENCY - A data processing system includes a processor for writing data processed based on a clock signal in a buffer for storing and outputting written data, and the processor changes a frequency of the clock signal supplied to the processor in accordance with an amount of data stored in the buffer. | 01-22-2009 |
20090037759 | Clock shifting and prioritization system and method - A clock shifting and prioritization method comprising adjusting a frequency for a plurality of clocks corresponding to a plurality of respective components of an electronic device based on a desired user configuration setting for operating the electronic device. | 02-05-2009 |
20090037760 | CIRCUIT ARRANGEMENT HAVING A PLURALITY OF COMMUNICATION INTERFACES - A circuit arrangement including at least two communication interfaces, a clock input, a frequency divider, and a frequency comparator configured to compare a frequency applied to the clock input with a reference frequency, and to output a comparison signal, wherein based on the comparison signal, the circuit arrangement is configured to divide the frequency applied to the clock input and to activate a communication interface of the at least two communication interfaces. | 02-05-2009 |
20090044038 | APPARATUS AND METHOD FOR DYNAMIC CLOCK CONTROL IN A PIPELINE SYSTEM - An apparatus and method for dynamically controlling a clock signal in a pipeline system are provided. In the apparatus and method, a clock generator outputs the clock signal at every period, a PDR is included with each stage for outputting information about a processing speed of each stage, and a CCU controls the delay of the clock signal using the processing time of each stage received from the PDR and providing the clock signal with the controlled delay to a register between stages. Accordingly, the clock signal is dynamically controlled to provide higher operating speeds. | 02-12-2009 |
20090055676 | Apparatus and method for redundant and spread spectrum clocking - An apparatus and method for fault-tolerant and spread spectrum clocking. In one embodiment a master clock synthesizer circuit generates an output clock signal of varying frequency within a predetermined range of frequencies. A slave clock synthesizer circuit is provided to track the output clock signal generated by the master clock synthesizer circuit. If the master clock synthesizer circuit fails or generates an invalid output clock signal, the slave clock synthesizer circuit takes over and functions as the master clock synthesizer circuit. In one embodiment a method of fault-tolerant spread spectrum clocking includes generating a first digital data stream; receiving the first digital data stream, a first input reference signal and a first clock signal in a master clock synthesizer circuit; generating an first output clock signal of varying frequency by the master clock synthesizer circuit in response to the first digital data stream and the first clock signal. | 02-26-2009 |
20090063888 | METHOD AND APPARATUS FOR CLOCK CYCLE STEALING - A method for producing a plurality of clock signals. The method includes generating a reference clock signal using a phase locked loop (PLL). The reference clock signal is then provided to each of a plurality of clock divider units which each divide the received reference clock signal to produce a corresponding divided clock signal. The method then removes one or more clock cycles (per a given number of cycles) in order to produce a plurality of domain clock signals each having an effective frequency based on a frequency and a number of cycles removed from the correspondingly received divided clock signal. | 03-05-2009 |
20090083567 | APPARATUS AND METHOD FOR CLOCK GENERATION WITH PIECEWISE LINEAR MODULATION - An apparatus and method for generating a clock using piecewise linear modulation are provided. The apparatus includes: a modulation profile generator for outputting an M-bit digital profile obtained by quantizing a piecewise linear modulation profile consisting of two or more linear signals; a delta-sigma modulator for receiving the M-bit digital profile and outputting a K-bit profile obtained by delta-sigma modulating the M-bit digital profile, K being a smaller number than M; a phase-frequency comparator for outputting up and down pulses having the same phase difference as that between a reference clock and a feedback clock; a charge pump for outputting a predetermined current for a time corresponding to the phase difference between the up and down pulses; a loop filter for outputting a control voltage corresponding to the predetermined current; a voltage controlled oscillator (VCO) for outputting a multi-phase clock having a frequency corresponding to a level of the control voltage; and a fractional divider for receiving the multi-phase clock of the VCO, selecting a divider according to the K-bit profile, and outputting a divided clock as the feedback clock. Therefore, it is possible to minimize electromagnetic interference (EMI) using piecewise linear modulation, and to readily implement the apparatus and method on a chip due to the modulation profile consisting of two or more linear signals. In addition, the delicate fractional divider using a multi-phase clock of the VCO and a phase interpolator allows precise frequency interpolation. Furthermore, unnecessary power consumption can be reduced by preventing application of a clock to an unused block. | 03-26-2009 |
20090094476 | DERIVING CLOCKS IN A MEMORY SYSTEM - A computer program product and a hub device for deriving clocks in a memory system are provided. The computer program product includes a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for facilitating a method. The method includes receiving a reference oscillator clock at the hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface. | 04-09-2009 |
20090100286 | METHODS AND DEVICES FOR TREATING AND PROCESSING DATA - A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell. | 04-16-2009 |
20090106576 | METHODS AND SYSTEMS FOR DIGITALLY CONTROLLED MULTI-FREQUENCY CLOCKING OF MULTI-CORE PROCESSORS - A method and system for digitally controlled multi-frequency clocking are provided. The method includes receiving a system reference oscillator clock frequency at a microprocessor including multiple cores. The system reference oscillator clock frequency provides a reference frequency to a local oscillator. The local oscillator supplies a core clock frequency to at least one of the cores. The method further includes adjusting the local oscillator to output the core clock frequency at a frequency greater than the system reference oscillator clock frequency as a function of digital frequency characteristic data associated with the core or cores. The method supports extendibility to larger systems and may support enhanced power management through frequency adjustments at the core level. | 04-23-2009 |
20090113231 | DATA PROCESSING DEVICE AND MOBILE DEVICE - A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card. | 04-30-2009 |
20090119534 | SYSTEM AND METHOD FOR EMPLOYING A CONTROLLED MODIFICATION CURRENT TIME VALUE - A method for employing a controlled-modification current time value is presented. In the method, the current time value is maintained. Also, requests for modification of the current time value are received. The requests are processed so that the requested modification associated with one of the requests is immediately incorporated into the current time value, and so that the requested modification associated with another one of the requests is not immediately incorporated into the current time value. | 05-07-2009 |
20090125749 | Method and device for controlling a computer system - A method and a device for controlling a computer system having at least two execution units, in particular for controlling a multiprocessor system having a switchover means via which a switchover is possible between at least two different operating modes of the computer system, a switchover of the clock frequency of the computer system also being performed when switching over between the operating modes. | 05-14-2009 |
20090138745 | Electronic devices with radio-frequency collision resolution capabilities - Electronic devices such as portable electronic devices contain electronic components. The electronic components may include radio-frequency transceiver circuitry. The radio-frequency transceiver circuitry may be used for handling data communications and cellular telephone voice communications. One or more adjustable clock sources may be provided within the electronic device. The adjustable clock sources may be based on phase-locked-loop circuits. A clock manager may determine which frequencies are being used by the radio-frequency transceiver circuitry and other components in the electronic device. The clock manager may use this information to compute a list of safe fundamental clock signal frequencies. Based on the list of safe clock signal frequencies, the clock manager may dynamically adjust the clock sources to avoid collisions between harmonics of the clock signals from the clock sources and the frequencies used by the transceiver circuitry and other components. | 05-28-2009 |
20090164828 | NETWORK OVERCLOCK CONTROL CIRCUIT - A network overclock control circuit for a computer includes an RC circuit, first and second comparator circuits, and first and second switch circuits. A signal pin of a network indicating lamp is connected to input terminals of the first and second comparator circuits via the RC circuit. Output terminals of the first and second comparator circuits are respectively connected to first and second clock pins of a clock chip via the first and second switch circuits. When network has little traffic, the first and second comparator circuits control the first and second switch circuits to output low level signals. When network has medium to high traffic, the first and second comparator circuits control the first and second switch circuits to output high and low level signals. When network is overloaded, the first and second comparator circuits control the first and second switch circuits to output high level signals. | 06-25-2009 |
20090199036 | LSSD compatibility for GSD unified global clock buffers - A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal. | 08-06-2009 |
20090228734 | Electronic device and system start method - An electronic device and a system start method that reduce electric power consumption and improves convenience. A state check section detects that an information processing section is being booted and that a telephone conversation is being carried out by the use of an information processing section (portable telephone). When the state check section detects this state, the state check section outputs instructions to a clock control section to lower a frequency of an operation clock of a processing circuit included in the information processing section. When the clock control section accepts the instructions from the state check section to lower the frequency of the operation clock of the processing circuit, the clock control section lowers the frequency of the operation clock of the processing circuit. | 09-10-2009 |
20090240971 | OPTIMIZED PERFORMANCE AND POWER ACCESS TO A SHARED RESOURCE IN A MULTICLOCK FREQUENCY SYSTEM ON A CHIP APPLICATION - A request from a first processor for access to a shared resource in a computing system is received, and access is provided to the shared resource by the first processor at a first clock frequency. A request from a second processor for access to a shared resource in a computing system is received, and access is provided to the shared resource by the second processor at a second clock frequency that is lower than the first clock frequency. | 09-24-2009 |
20090259876 | COMPUTER SYSTEM AND METHOD FOR AUTOMATICALLY OVERCLOCKING - A computer system for automatically overclocking includes an overclocking element, a detecting circuit and a basic input/output system (BIOS). The overclocking element has a signal standard. The detecting circuit is used for acquiring an I/O signal of the overclocking element. The BIOS is used for comparing the signal standard with the I/O signal to obtain a comparing result. The BIOS is further used for adjusting a reference signal according to the comparing result. The reference signal is an input signal of the overclocking element. | 10-15-2009 |
20090282280 | Memory System for seamless switching - Provided is a memory system for seamless switching. The memory system includes first through mth chips, where m is a natural number, connected in the form of a daisy chain and configured to transmit at least one of signals and data, a (k−1)th chip of the first through mth chips, where k is a natural number and 2≦k≦m, configured to output a (k−1)th detection signal corresponding to a phase difference between (k−1)th test data of the (k−1)th chip and kth test data of a kth chip of the first through mth chips, and the kth chip including a clock phase control unit configured to control a phase of a received clock signal and to output the phase-controlled clock signal as a kth clock signal, where the clock phase control unit of the kth chip outputs the kth clock signal in response to the (k−1)th detection signal. | 11-12-2009 |
20090307518 | ASYNCHRONOUS COUNTER BASED TIMING ERROR DETECTION - A method for estimating a timing difference between a first clock signal and a second clock signal is disclosed. The estimating method comprising: generating an edge signal by detecting an edge of the second clock signal by sampling the second clock signal using the first clock signal; generating a delayed edge signal by a further sampling of the second clock signal using the first clock signal; generating a first intermediate code by counting a number of clock edges of the first clock signal within a duration defined by the edge signal using an asynchronous counter; generating a second intermediate code to represent a timing difference between the second clock signal and the delayed edge signal using a time-to-digital converter; and generating an output code using a weighted sum of the first intermediate code and the second intermediate code. | 12-10-2009 |
20090319818 | METHOD AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE - A method is provided for operating an interface between a first unit and a second unit supplying its data. The method includes switching control between LSSD_B and LSSD_C clocks and system clock (CLK) to provide a test mode of operation and a functional mode of operation to optimize setup and hold times depending on conditions under which the unit is operating. In the test mode, data is launched by the LSSD_C clock. In the functional mode, the data is launched by the system clock (CLK) to RAM. A method is also provided to determine which memory inputs should use a circuit that provides adequate setup and hold margins. | 12-24-2009 |
20090327792 | BUS FREQUENCY ADJUSTMENT CIRCUITRY FOR USE IN A DYNAMIC RANDOM ACCESS MEMORY DEVICE - The present disclosure relates to clock divider circuitry for use in a dynamic random access memory device. In accordance with at least one embodiment the disclosure includes a method having a number of operations. Some operations may include receiving a clock input signal having a first frequency from a clock input receiver at clock divider circuitry, the clock divider circuitry including a flip-flop configured to generate an output signal, based at least in part, on an inverted output signal and the clock input signal. The output signal may have a second frequency that is a fraction of the first frequency. The method may further include receiving said clock input signal and said output signal at a multiplexer and generating a multiplexed output. The method may additionally include receiving said multiplexed output at a first bus configured to receive said multiplexed output and to reduce an operational frequency of said first bus in response to an increase in an operational frequency of a second bus associated with said memory device. | 12-31-2009 |
20090327793 | FINITE IMPULSE RESPONSE (FIR) FILTER WITHOUT DECIMATION - Provided is a discrete signal finite impulse response (FIR) filter and a filter set in which a plurality of FIR filter units are connected in a cascade structure to remove down-sampling by decimation, in order to improve the attenuation characteristics of a FIR filter, such as, for example, a switched capacitor filter. The FIR filter includes a clock generator generating a plurality of clock signals that are different from each other; and N+2 sub blocks each including N sample storage units, each sample storage unit storing a received sample. Each sub block being in a state among a number of possible states including N charging states for storing the received sample, a transfer state for outputting the stored sample and a reset state for operation initialization. The N charging states, the transfer state and the reset state are changed sequentially in response to the clock signals. | 12-31-2009 |
20100042864 | SYSTEM AND METHOD FOR MANAGING APPLICATION - A system for managing an application includes a clock unit for generating a plurality of predetermined time signals, a counting unit, a storage unit and a processing unit. The counting unit tracks an invoking count when the application has been executed between two predetermined time signals. The storage unit stores an aging table. The aging table includes a collection of ordered logical pointers and a collection of age values, where each logical pointer is associated with an age value. The application includes a logical pointer. The age values have a predetermined increment when the logical pointer is changed forward. The processing unit increases the logical pointer by a small value if the invoking count is bigger than a predetermined value and increases a larger value otherwise when the later predetermined time signal of the two predetermined time signals comes. | 02-18-2010 |
20100070792 | SYSTEM AND METHOD FOR TESTING OVERCLOCKING CAPABILITY OF CPU - A test system for overclocking capability of a central processing unit (CPU) includes a basic input and output system (BIOS), a frequency generator, and a watchdog timer. The BIOS includes an input module, a watchdog control module, and a frequency increasing module. The input module inputs an initial frequency of a CPU to the frequency generator to adjust a real-time frequency of the CPU. The watchdog control module sends a counter signal to the watchdog timer in a preset time interval. The watchdog timer receives the counter signal. If the watchdog timer does not receive the counter signal within the preset time, the watchdog timer outputs a reset signal to restart the computer. The frequency increasing module adds a preset increment to the real-time frequency to obtain a newly adjusted frequency, and provides the newly adjusted frequency to the frequency generator to adjust the real-time frequency. | 03-18-2010 |
20100070793 | Clock supply device - Provided is a clock supply device that variably adjusts a frequency of a clock supplied to each module, as needed. The clock supply device includes a clock output unit that switches between clocks having different frequencies and output the clocks; a clock distribution unit that distributes and supplies the clocks from the clock output unit to the plurality of modules; and a clock switching control unit that causes the frequencies of the clocks from the clock output unit to be switched. The clock switching control unit includes a clock request pattern determination unit. The clock request pattern determination unit outputs a control signal for decreasing a clock frequency to a slow frequency, to the clock output unit, when a pattern of a clock request signal output from a monitoring target module satisfies a predetermined condition pattern. | 03-18-2010 |
20100106996 | SerDes double rate bitline with interlock to block precharge capture - An embodiment of the invention provides a method of separating an early clock pulse and a late clock pulse into two different latches, wherein the early clock pulse is generated through a bit line. In response to the early clock pulse rising, a first data waveform is sent to a fourth data waveform. In response to a third data waveform rising, an early precharge is turned off. In response to the turning off of the early precharge and in response to a fifth data waveform dropping, an eighth data waveform rises if the first data waveform has a value of 1. In response to a sixth data waveform rising, a first pulse latch is opened | 04-29-2010 |
20100169698 | RECORDING MEDIUM CONTROL ELEMENT, RECORDING MEDIUM CONTROL CIRCUIT BOARD, AND RECORDING MEDIUM CONTROL DEVICE - A recording medium control element includes: an input/output module configured to input/output a command and data to/from a recording medium; a first control module configured to control the input/output of the command and data performed by the input/output module; a buffer holding the data input/output to/from the input/output module; a second control module configured to control writing and reading data to/from the buffer; a clock generating module configured to generate a first clock signal and a second clock signal whose frequency is lower than a maximum operating frequency of the recording medium; and a signal supply module configured to supply the first clock signal to the recording medium and the input/output module, and supplying the second clock signal to the first and second control modules. | 07-01-2010 |
20100174937 | Method and System for a Message Processor Switch for Performing Incremental Redundancy in Edge Compliant Terminals - Certain embodiments of the invention may be found in a method and system for processing messages. Aspects of the method may comprise receiving at least one signal on a chip that controls switching from a core processor to a DSP. At least a first bus that couples the core processor to a message processor and at least a first clock signal that clocks the core processor may be switched. At least a second bus that couples the DSP to the message processor and at least a second clock signal that clocks the DSP may be switched. When a loss of clock signal from the core processor or the DSP to the message processor is detected, a third clock signal for clocking the message processor may be generated. The message processor switch significantly reduces the amount of bandwidth utilized for transfer of data between the core processor and the DSP and provides incremental redundancy (IR) without high hardware cost and software MIPS, thereby providing significant improvement in system performance. | 07-08-2010 |
20100223489 | OVERCLOCKING CONTROL DEVICE AND OVERCLOCKING CONTROL METHOD - An overclocking control method cooperates with an overclocking application of a computer system when the overclocking application is started. The overclocking control method includes the steps as follows. A BIOS enters an overclocking mode according to an executing state of the overclocking application. The BIOS receives a first triggering signal outputted from a south bridge chip, and the first triggering signal is generated by the south bridge chip according to a first button of the computer system. The BIOS selects a piece of corresponding overclocking information from a look-up table and loads the overclocking information into a register of the BIOS according to the first triggering signal to control the overclocking of the computer system. | 09-02-2010 |
20100250998 | METHODS AND APPARATUSES FOR CONTROLLING THREAD CONTENTION - An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold. | 09-30-2010 |
20100275052 | LOAD ADAPTIVE EMI REDUCTION SCHEME FOR SWITCHING MODE POWER SUPPLY - The present invention relates to a frequency jittering device and method, and a switching power supply employing such frequency jittering device. Said method comprises: S1 generating a variable logic number; S2 generating a delay signal; S3 generating a PWM control signal according to the variable logic number and the delay signal; S4 generating an output signal according to the PWM control signal; and S5 generating a clock signal with variable frequency according to the output signal; wherein, the clock signal is fed back to update the variable logic number, and a jittering clock signal modified in each clock cycle is produced. The benefit of the present invention is not only can apply small low cost EMI filter but also can keep the noise floor level low enough at light load condition. | 10-28-2010 |
20110016344 | AUDIO CLOCKING IN VIDEO APPLICATIONS - A method of operating an electronic video device such as a DVD player, wherein video clock signals and audio clock signals are derived from a system clock signal using two phase-lock loops, and these video and audio clock signals are used to process encoded video data and encoded audio data, but digital-to-analog conversion of the audio data stream is controlled by the system clock signal rather than the audio clock signals. By using the system clock signal to control the audio digital-to-analog converter (DAC), the DAC avoids the poor performance issues that can arise from jitter introduced into the audio clock signals by the PLL. The system clock signal may be divided by an integer to generate the sampling clock for the audio DAC. In the illustrative embodiment, the system clock signal has a rate which is not an integer multiple of the sample rate of the audio data stream. | 01-20-2011 |
20110016345 | SEMICONDUCTOR DEVICE AND DATA PROCESSOR - Synchronization between command and address signals commonly coupled to a plurality of memory devices to be operated in parallel and a clock signal coupled to the memory devices is achieved, while suppressing an increase in the clock wiring length. A semiconductor device has a data processing device mounted on a wiring substrate and a plurality of memory devices accessed in parallel by the data processing device. The data processing device outputs the command and address signals as a first frequency from command and address terminals, and outputs a clock signal as a second frequency from a clock terminal. The second frequency is set to multiple times of the first frequency, and an output timing equal to or earlier than a cycle starting phase of the clock signal output from the clock terminal can be selected to the command and address signals output from the command and address terminals. | 01-20-2011 |
20110022876 | COMPUTER SYSTEM AND OPERATING METHOD THEREOF - A computer system is provided with an event counter, a CPU, a memory, an external device, a hub M | 01-27-2011 |
20110047402 | DYNAMIC PROGRAMMABLE DELAY SELECTION CIRCUIT AND METHOD - A controller may include a measurement circuit configured to generate a proxy signal representing delay variations in the controller. The measurement circuit may also generate a measurement value from the proxy signal. A control circuit may be configured to convert the measurement value into a control value. A delay circuit may be adjusted by the control value to alter an amount of delay of a signal. | 02-24-2011 |
20110078484 | MOTHERBOARD WITH OVERCLOCKING AND OVERVOLTING FUNCTIONS - A motherboard with overclocking and overvolting functions is provided. The motherboard with an overvolting function includes a specified component, a voltage regulator and a micro-controller. The specified component receives an operating voltage. The voltage regulator generates the operating voltage according to a reference voltage. The micro-controller is electrically connected to an external input device for receiving a control signal issued by the external input device and adjusting the reference voltage according to the control signal. | 03-31-2011 |
20110126039 | MEMORY CONTROLLER WITH REDUCED POWER CONSUMPTION, MEMORY DEVICE, AND MEMORY SYSTEM - A memory device comprising: at least one bank of memory cells that receives a first clock for clocking commands and a second clock for clocking data, wherein the second clock is activated based on a first command and deactivated based on a second command. The memory device further including a clock activation circuit configured to generate an enable signal based on the first command and a disable signal based on the second command, and a clock generator configured to generate the second clock based on a reference clock upon receipt of the enable signal. | 05-26-2011 |
20110131441 | SYSTEM INCLUDING PLURALITY OF STORAGE DEVICES AND DATA TRANSMISSION METHOD FOR THE SAME - A system includes a plurality of storage devices and a controller. The plurality of storage devices are bus-connected to one clock signal line and one data signal line connected to the controller. Each of the plurality of storage devices stores identification information in advance to distinguish the storage devices from each other. The controller transmits data using an identification information transmission period in which one storage device is selected from the plurality of storage devices by transmitting the identification information of the one storage device to the plurality of storage devices via the data signal line and a data transmission period in which the data is transmitted to the one selected storage device. A frequency of a clock signal during the identification information transmission period is set to be lower than a frequency of the clock signal during the data transmission period. | 06-02-2011 |
20110131442 | TRACING APPARATUS AND TRACING SYSTEM - A tracing apparatus for tracing operational information that is output from a plurality of processing units in relation to data processing operations, the tracing apparatus comprising for each of the processing units: a counting unit configured to obtain and output a counter value for the corresponding processing unit, the counter value obtained by counting clock signals that are input to the processing unit at an operating frequency thereof; a counter value conversion unit configured to obtain and output a converted counter value for the corresponding processing unit, the converted counter value obtained by converting the counter value based on the assumption that the processing unit has a given reference operating frequency; and an adding unit configured to acquire an operational information set from the corresponding processing unit, and to add the converted counter value to the operational information set. | 06-02-2011 |
20110154089 | PROCESSOR CORE CLOCK RATE SELECTION - Techniques described herein generally relate to multi-core processors including two or more processor cores. Example embodiments may set forth devices, methods, and computer programs related to calculating a clock rate for one or more of the processor cores in the multi-core processor. One example method may include determining a first estimated workload for a first processor core and a second estimated workload for a second processor core within a scheduling interval in a periodic scheduling environment. In addition, a first clock rate for the first processor core may be calculated based on one or more of the first estimated workload, a maximum clock rate supported by the multi-core processor and/or the scheduling interval. Similarly, a second clock rate for the second processor core may also be calculated based on one or more of the second estimated workload, the maximum clock rate, and/or the scheduling interval. | 06-23-2011 |
20110191621 | DYNAMIC FREQUENCY ADJUSTMENT FOR INTEROPERABILITY OF DIFFERENTIAL CLOCK RECOVERY METHODS - A system and method for dynamic frequency adjustment for interoperability of differential clock recovery, including one or more of the following: a frequency generator for receiving a frequency reference clock signal and generating a plurality of frequency signals by operating on the frequency reference clock signal, the plurality of frequencies signals being output from the frequency generator and each having a different frequency; a flexible distributor for receiving the plurality of frequency signals from the frequency generator and selecting ones of said plurality of frequency signals and transmitting said selected ones of said plurality of frequency signals; and a plurality of differential units, each for receiving one of said selected ones of said plurality of frequency signals, each for applying a differential signal to said selected ones of said plurality of frequency signals, and each for adding time stamps to the selected ones of said plurality of frequency signals and outputting respective time stamped differential selected frequency signals. | 08-04-2011 |
20110197087 | MEMORY DEVICE INCLUDING A MEMORY BLOCK HAVING A FIXED LATENCY DATA OUTPUT - A memory block includes a memory circuit and a clock generation unit. The memory circuit may output read data in response to being clocked by a clock signal having a selectable delay that may be dependent upon a time taken for the read data to be output by a memory core after the read command is received at the memory block. The clock generation unit may cause the read data to be provided as an output of the memory block in response to being clocked by a selected data clock signal. The data clock signal may be selected from one of several clock edges generated by one of several clock edges of a system clock such that regardless of the frequency of the system clock, the read data is provided by the memory block a predetermined amount of time after the read command is received at the memory block. | 08-11-2011 |
20110208989 | Command Protocol for Adjustment of Write Timing Delay - A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal. | 08-25-2011 |
20110208990 | Regulation of Memory IO Timing - This disclosure provides for adjustment of memory IO timing using a voltage controlled oscillator (VCO) and a register that generates a VCO control voltage directly used to vary memory IO timing. The register may be externally programmable by a controller and may be located on a memory device (IC, module or other device) or on an external voltage generator, which then provides an adjustable voltage to the memory device. This structure may be used to adjust memory timing so as to achieve a minimum target bitrate and thus minimize frequency of operation to minimize power. In one embodiment, each of several memory devices may be independently adjusted in this way to achieve a mesochronous memory system; in another embodiment, memory devices may be have their timing adjusted in parallel, with all memory devices equal to or greater than a target bitrate. Teachings presented herein provide a way to relax overdesign requirements and “tune” fast-fast and slow-slow devices to effectively operate as typical devices. | 08-25-2011 |
20110231695 | DIGITAL FORCED OSCILLATION BY DIRECT DIGITAL SYNTHESIS - An opportunity is apparent to develop alternative circuitry. Simplified circuitry without artifacts tied to the clock that drives a digital frequency generator (DFG) is useful in a variety of tunable electronic devices. The present invention relates to digital frequency generation. In particular, it relates to a method and apparatus for the digital generation of a pulse stream having a desired frequency relative to a reference clock signal and the ratio of two integers. The method applies generally to integers whose ratio is not an integer. The DFG as a device can be integrated onto a simple chip, without need for an off-chip filter. | 09-22-2011 |
20110246810 | CLOCK SIGNALS FOR DYNAMIC RECONFIGURATION OF COMMUNICATION LINK BUNDLES - In at least some embodiments, an electronic device includes a processor and a memory coupled to the processor. The electronic device also includes a serial communication link controller coupled to the processor, the serial communication link controller supporting dynamic reconfiguration of a plurality of communication link bundles. The serial communication link controller receives an input clock and generates first and second clock signals based on the input clock, the first and second clock signals having different clock rates and being provided to each of a plurality of communication link bundles. | 10-06-2011 |
20110252267 | POWER MANAGEMENT COORDINATION IN MULTI-CORE PROCESSORS - Systems and methods of managing power provide for issuing a first operating requirement from a first processor core and issuing a second operating requirement from a second processor core. In one embodiment, the operating requirements can reflect either a power policy or a performance policy, depending upon the factor that is currently most important to software. Hardware coordination logic is used to coordinate a shared resource setting with the operating requirements. The hardware coordination logic is also able to coordinate the shared resource setting with independent resource settings of the first and second processor cores based on the operating requirements. | 10-13-2011 |
20110264946 | MODULAR INTEGRATED CIRCUIT WITH CLOCK CONTROL CIRCUIT - A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The hub module includes a clock control circuit, coupled to the plurality of hub interfaces, that selectively supplies a plurality of clock signals to the plurality of spoke modules by receiving a clock request signal from a corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces, generating at least one of the plurality of clock signals in response to the clock request signal; and sending the at least one of the plurality of clock signals to the corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces. | 10-27-2011 |
20120042193 | CLOCK FREQUENCY SELECTION SCHEME - Systems and methods for selecting and setting clock frequencies for an electronic device are disclosed. Specifically, clock frequencies may be adjusted to avoid interference with input electromagnetic energy, often in radio frequency bands. Clock frequencies may be chosen to minimize signal interference and improve device performance. In some embodiments, clock frequency information is stored in one or more lookup tables in device memory. In certain embodiments, a system processor can access the information stored in the lookup table and instruct system circuitry to adjust clock frequency as needed based on lookup table entries. | 02-16-2012 |
20120047390 | APPARATUS AND METHOD OF CONTROLLING A PROCESSOR CLOCK FREQUENCY - An apparatus and a method of controlling a processor clock frequency are provided. The apparatus comprises a hardware counter to count write accesses to a memory buffer during a predetermined period of time, a hardware comparator to compare a number of write accesses counted by the hardware counter with at least one predetermined threshold value, the hardware comparator further to generate a control signal, the control signal being dependent on a result of a comparison of a number of write accesses counted by the hardware counter with at least one predetermined threshold value performed by the hardware comparator, and a clock frequency setting circuit to set a clock frequency of a processor depending on the control signal. | 02-23-2012 |
20120084594 | USB DEVICE WITH A CLOCK CALIBRATION FUNCTION AND METHOD FOR CALIBRATING REFERENCE CLOCKS OF A USB DEVICE THEREOF - A USB device with a clock calibration function and a method for calibrating reference clocks of a USB device are provided. A USB 2.0 initial calibration is performed on the USB device in order to control an embedded oscillator (EMOSC) of the USB device to output a first reference clock compliance USB 2.0 specification and USB 3.0 specification during the initialization phase. After that, a USB 3.0 on-line calibration is performed on the USB device in order to control the EMOSC of the USB device to calibrate a second reference clock during a super-speed mode of USB 3.0 specification. | 04-05-2012 |
20120102354 | TIMER UNIT CIRCUIT HAVING PLURALITY OF OUTPUT MODES AND METHOD OF USING THE SAME - A timer unit includes a first selector that receives a fixed value and a first enable signal, a second selector that receives the fixed value and a count cycle signal, a third selector that receives an output of the second selector, the count cycle signal, and a second enable signal, a first counter circuit that starts counting in response to an output of the first selector, and that generates the count cycle signal and a first counter circuit output signal indicating that a count value approaches a predetermined value, a second counter circuit that starts counting in response to an output of the third selector, and that generates a second counter circuit output signal, a first output signal generator that receives the first counter circuit output signal and the second counter circuit output signal to generate a first output signal, and a second output signal generator. | 04-26-2012 |
20120110365 | METHOD FOR LOCKING FREQUENCY OF USB DEVICE AND USB FREQUENCY LOCKING DEVICE - A method for locking the frequency of a USB device includes the following steps. Receive a USB data signal and generate multiple reference clock signals. Compare the frequency of the reference clock signals with a bit rate of the USB data signal to generate a control signal. Adjust the operating frequency of an output clock of the USB device according to the control signal. | 05-03-2012 |
20120110366 | CLOCK CONTROL DEVICE, CLOCK CONTROL METHOD, CLOCK CONTROL PROGRAM AND INTEGRATED CIRCUIT - An instruction detecting section ( | 05-03-2012 |
20120117413 | METHOD AND INFRASTRUCTURE FOR CYCLE-REPRODUCIBLE SIMULATION ON LARGE SCALE DIGITAL CIRCUITS ON A COORDINATED SET OF FIELD-PROGRAMMABLE GATE ARRAYS (FPGAs) - A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom. The plurality of local clock control state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided. | 05-10-2012 |
20120124408 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus may comprise: a first chip ID generation unit configured to receive an enable signal through a first through-silicon via and a clock signal through a second through-silicon via and generate a first chip ID signal and a delayed enable signal; a second chip ID generation unit configured to receive the delayed enable signal through a third through-silicon via from the first chip ID generation unit and the clock signal and generate a second chip ID signal; a first chip selection signal generation unit configured to receive the first chip ID signal and a main ID signal and generate a first chip selection signal; and a second chip selection signal generation unit configured to receive the second chip ID signal and the main ID signal and generate a second chip selection signal. | 05-17-2012 |
20120131374 | JITTER REDUCTION METHOD AND APPARATUS FOR DISTRIBUTED SYNCHRONISED CLOCK ARCHITECTURE - A method of reducing jitter in a local clock of a synchronised USB device attached to a USB Hub, the USB Hub having a local clock and repeater circuitry, comprising: observing a USB data stream with the USB Hub, the data stream having a data stream bit rate; the USB Hub decoding a periodic signal structure in the USB data stream; the USB Hub generating an event signal in response to decoding of the periodic signal structure; and the USB Hub locking a frequency of the local clock of the USB Hub to the periodic event signal. The local clock of the USB Hub is adapted to be a clocking source for the repeater circuitry of the USB Hub at substantially an integer multiple of a frequency of the data stream bit rate. | 05-24-2012 |
20120137161 | METHOD AND APPARATUS FOR GENERATING A PHASE DEPENDENT CONTROL SIGNAL - A computer system with a phase detector that generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having duty cycles corresponding to the phase relationship between the clock edges of the first and second clock signals. The phase detector also includes a charge pump that receives select signals from the phase detector circuits and produces an increasing or decreasing control signal when the first and second clock signals do not have the predetermined phase relationship, and a non-varying control signal when the first and second clock signals do have the predetermined phase relationship. The delay value of a voltage-controlled delay circuit and the phase relationship between the first and second clock signals to a predetermined phase relationship are thereby adjusted. | 05-31-2012 |
20120166859 | METHOD AND APPARATUS FOR GENERATING A SYSTEM CLOCK SIGNAL - An apparatus includes a processor, a clock recovery circuit and a frequency locked loop. The processor receives a system clock signal to clock operations of the processor; and the clock recovery circuit recovers a clock signal from data communication occurring over a bus. The frequency locked loop receives the clock signal from the clock recovery circuit as a reference clock signal, and the frequency locked loop is adapted to lock onto the clock signal provided by the clock recovery circuit to provide the system clock signal. | 06-28-2012 |
20120166860 | SEQUENTIAL ON-CHIP CLOCK CONTROLLER WITH DYNAMIC BYPASS FOR MULTI-CLOCK DOMAIN TESTING - A controller includes a clock control unit configured to provide a first output to test circuitry and a bypass unit configured to provide a second output to a further controller. The controller is configured to cause the bypass unit to output the second output and to optionally cause the clock control unit to output the first output. | 06-28-2012 |
20120166861 | METHOD FOR ADJUSTING CLOCK FREQUENCY OF A PROCESSING UNIT OF A COMPUTER SYSTEM AND RELATED DEVICE - A method for adjusting clock frequency of a processing unit of a computer system includes calculating a busyness ratio of the processing unit according to a status signal provided by the processing unit, determining whether the busyness ratio is in a busyness ratio range, when the busyness ratio is not in the busyness ratio range, determining whether a calculation result generated according to a clock frequency of the processing unit and a frequency difference is in a frequency range, and when the calculation result is in the frequency range, adjusting the clock frequency of the processing unit according to the calculation result and outputting the adjusted clock frequency to a clock generator, wherein the busyness ratio range, the frequency range and the frequency difference are decided according to an operation state of a peripheral unit of the computer system. | 06-28-2012 |
20120173915 | Clock Generation Circuit and Semiconductor Device Including the Same - Objects of the invention are to provide a clock generation circuit and to provide a semiconductor device including the clock generation circuit. The clock generation circuit includes an edge detection circuit, a reference clock generation circuit, a reference clock counter circuit, and a frequency-divider circuit. The reference clock counter circuit is a circuit which outputs a counter value, which is obtained by counting the number of waves of a reference clock signal outputted from the reference clock generation circuit, in a period of time from when the edge detection circuit detects an edge of a signal which is externally inputted to the edge detection circuit to when the edge detection circuit detects the next edge, to the frequency-divider circuit. The frequency-divider circuit is a circuit which frequency-divides the reference clock signal based on the counter value. | 07-05-2012 |
20120173916 | Apparatus and Method for Redundant and Spread Spectrum Clocking - An apparatus and method for fault-tolerant and spread spectrum clocking. In one embodiment a master clock synthesizer circuit generates an output clock signal of varying frequency within a predetermined range of frequencies. A slave clock synthesizer circuit is provided to track the output clock signal generated by the master clock synthesizer circuit. If the master clock synthesizer circuit fails or generates an invalid output clock signal, the slave clock synthesizer circuit takes over and functions as the master clock synthesizer circuit. In one embodiment a method of fault-tolerant spread spectrum clocking includes generating a first digital data stream; receiving the first digital data stream, a first input reference signal and a first clock signal in a master clock synthesizer circuit; generating an first output clock signal of varying frequency by the master clock synthesizer circuit in response to the first digital data stream and the first clock signal. | 07-05-2012 |
20120198266 | Bus Clock Frequency Scaling for a Bus Interconnect and Related Devices, Systems, and Methods - Bus clock frequency scaling for a bus interconnect and related devices, systems, and methods are disclosed. In one embodiment, the bus interconnect comprises an interconnect network configurable to connect a master port(s) to a slave port(s). A bus interconnect clock signal clocks the interconnect network. The controller is configured to receive bandwidth information related to traffic communicated over the master port(s) and the slave port(s). The controller is further configured to scale (e.g., increase or decrease) the frequency of the bus interconnect clock signal if the bandwidth of the master port(s) and/or the slave port(s) meets respective bandwidth condition(s), and/or if the latency of the master port(s) meets a respective latency condition(s) for the master port(s). The master port(s) and/or slave port(s) can also be reconfigured in response to a change in frequency of the bus interconnect clock signal to optimize performance and conserve power. | 08-02-2012 |
20120221883 | DEVICE CONFIGURED TO SWITCH A CLOCK SPEED FOR MULTIPLE LINKS RUNNING AT DIFFERENT CLOCK SPEEDS AND METHOD FOR SWITCHING THE CLOCK SPEED - A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports. | 08-30-2012 |
20120233489 | CIRCUITRY FOR ACTIVE CABLE - Circuits, methods, and apparatus that allow signals that are compliant with multiple standards to share a common connector on an electronic device. An exemplary embodiment of the present invention provides a connector that provides signals compatible with a legacy standard in one mode and a newer standard in another mode. | 09-13-2012 |
20120272088 | DYNAMIC BUS CLOCK RATE ADJUSTING METHOD AND DEVICE - A dynamic bus clock rate adjusting method is to be executed by a bus controller and a CPU. The bus controller is coupled with a bus that is coupled with a plurality of slave devices. The method comprises the steps of: configuring the bus controller to generate, upon receipt of a request signal from one of the slave devices, an access instruction including an address from which the request signal is sent; and configuring the CPU to determine which of the slave devices the address of the access instruction corresponds so as to obtain a working clock rate thereof, and to set the bus controller to adjust an operating clock rate of the bus according to the working clock rate, and to perform the access instruction on the slave device via the bus. | 10-25-2012 |
20120272089 | INTERFACE - The present invention relates to methods and apparatus for data transfer. A data interface is described with at least a first data terminal for either outputting or receiving a data signal. In bi-directional embodiments there may be one terminal for receiving data and one terminal for outputting data. A bit clock terminal outputs or receives a bit clock signal; and a frame clock terminal for outputs or receives a frame clock signal. Interface control circuitry is configurable to associate data outputted or received in each frame with time slots (1-8) of a predetermined number of bits (x, y, z) wherein the control circuitry is adapted such that the frequency of the bit clock signal can be changed at any time so as to vary the number of time slots in a frame. | 10-25-2012 |
20120290866 | METHOD AND SYSTEM FOR CORRECTING TIMING ERRORS DUE TO THERMAL CHANGES WITHIN A PORTABLE COMPUTING DEVICE - A method and system for correcting timing errors due to thermal changes within a portable computing device are disclosed. The system and method may include calculating an estimate of frequency for a first clock compared to a second clock. The first clock may comprise a crystal oscillator while the second clock comprises a system clock. Next, a sleep state may be calculated for a hardware device, such as radio access technology (“RAT”) module, based on the estimate of frequency for the first clock. An error in the frequency of the first clock that may occur during the sleep state of the hardware device may be calculated. Subsequently, a magnitude of time that corresponds to an actual length of the sleep state relative to the second clock may be calculated so that an internal clock of the hardware devices may be synchronized with the second clock. | 11-15-2012 |
20120311371 | TIME MULTIPLEXING AT DIFFERENT RATES TO ACCESS DIFFERENT MEMORY TYPES - A memory controller accesses different types of memory devices running at different native rates through the use of a time division multiplexed bus. Data is transferred over the bus at one rate when accessing one type of memory device and at a different rate when accessing another type of memory device. In addition, the memory controller may provide control information (e.g., command and address information) to the different types of memory devices at different rates and, in some cases, time multiplex the control information on a shared bus. | 12-06-2012 |
20120317435 | APPARATUS FOR DETECTING PRESENCE OR ABSENCE OF OSCILLATION OF CLOCK SIGNAL - A semiconductor apparatus includes an arithmetic circuit that executes a program based on an operating clock signal input through a clock transfer node, an internal oscillator that generates an internal clock signal to be used internally, a watch dog timer that counts the internal clock signal, detect that a count value reaches a predetermined value of an execution time of the program in the arithmetic circuit and output a notification signal, and a clock monitor circuit that detects presence or absence of the operating clock signal in response to the notification signal. | 12-13-2012 |
20130007500 | HIGH-SPEED I/O DATA SYSTEM - In embodiments of a high-speed I/O data system, a first computer chip includes a data transmission system, and a second computer chip includes a data reception system. A data channel communicates an NRZ data signal, and a clock channel communicates a forwarded clock signal, from the data transmission system to the data reception system. The data transmission system includes a first differential serializing transmitter to generate the NRZ data signal from pulsed data, and further includes a second differential serializing transmitter to generate a forwarded clock signal. A first multi-phase transmit clock generator generates transmit clock signals for the first and second differential serializing transmitters. The data reception system includes a data receiver and a de-serializer to receive and de-serialize the NRZ data signal, and includes a multi-phase receive clock generator to generate receive clock signals from the forwarded clock signal for the de-serializing data receiver. | 01-03-2013 |
20130024715 | Thermal Protection Method for Computer System and Device Thereof - A thermal protection method for a computer system including at least a processor includes monitoring the temperature and loading of the processor via a system firmware in the computer system, obtaining the current performance state level and at least an operable performance state levels of the processor when the system firmware determines that the temperature and loading of the processor exceeds a predetermined value respectively, wherein the performance state level is associated to the frequency of the processor, and setting the processor to one of the operable performance state levels, wherein the frequency of the performance state level is lower than the frequency of the current performance state level, according to the current performance state level and the operable performance state levels. | 01-24-2013 |
20130042137 | METHODS AND DEVICES FOR TREATING AND PROCESSING DATA - A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell. | 02-14-2013 |
20130055004 | HARDWARE-BASED AUTOMATIC CLOCK GATING - A system and method for automatically updating with hardware clock tree settings on a system-on-a-chip (SOC). A SOC includes a hardware clock control unit (HCCU) coupled to a software interface and a clock tree. The SOC also includes multiple integrated circuit (IC) devices, wherein each IC device receives one or more associated core clocks provided by one or more phase lock loops (PLLs) via the clock tree. The HCCU receives a software-initiated request specifying a given IC device is to be enabled. The HCCU identifies one or more core clocks used by the given IC device. For each one of the identified core clocks, the HCCU configures associated circuitry within the clock tree to generate an identified core clock. The HCCU may also traverse the clock tree and disable clock generating gates found not to drive any other enabled gates or IC devices. | 02-28-2013 |
20130055005 | METHOD AND APPARATUS FOR REDUCING ELECTROMAGNETIC WAVES IN MOBILE DEVICE - A method and an apparatus for reducing electromagnetic waves in a mobile device are provided. According to the method, in a mobile device having the first and second modules with different functions, the apparatus operates the first module at the first operating frequency. If there is a request for operating the second module while the first module is operated, the apparatus changes the first operating frequency to a second operating frequency which is different from the first operating frequency, and operates the first module at the second operating frequency. The apparatus reduces a total magnitude of electromagnetic waves caused by a simultaneous operation of two or more modules, thereby enhancing the quality of the mobile device and minimizing any undesirable impact upon the human body. | 02-28-2013 |
20130086410 | FREQUENCY SYNTHESIS METHODS AND SYSTEMS - Multi-tier methods and systems to synthesize a reference frequency, and control one or more tiers in view of multiple prioritized criteria. A first tier of a frequency synthesizer may include a first phase locked loop (PLL), which may include an inductive-capacitive voltage-controlled oscillator (LC VCO). One or more subsequent tiers may each include a second PLL, which may include a self-biased (SB) VCO PLL or a digitally-controlled oscillator (DCO) PPL. A subsequent tier may be controllable with respect to multiple parameters. Parameters may be evaluated and selected based on multiple criteria, which may be prioritized. Parameters may be selected, for example, to minimize a frequency error equal relative to a permissible deviation from a desired frequency as a first priority, reduce jitter as a second priority, and minimize a frequency error relative to the desired frequency as a third priority. | 04-04-2013 |
20130097453 | APPARATUS AND METHOD FOR CONTROLLING CPU IN PORTABLE TERMINAL - The present disclosure relates to an apparatus and a method for controlling a central processing unit in a portable terminal The method includes: operating a first core among multiple cores included in the central processing unit within a range of pre-designated limited clock frequencies; identifying the number of work queues corresponding to the number of processings being delayed by the central processing unit; comparing the identified number of work queues with a pre-designated reference value; and operating the first core and a second core among the multiple cores at a maximum clock frequency when a result of the comparison shows that the identified number of work queues exceeds the reference value. | 04-18-2013 |
20130111256 | DRIFT DETECTION IN TIMING SIGNAL FORWARDED FROM MEMORY CONTROLLER TO MEMORY DEVICE | 05-02-2013 |
20130173948 | Frequency And Voltage Scaling Architecture - A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others. | 07-04-2013 |
20130191678 | IN SITU PROCESSOR RE-CHARACTERIZATION - A re-characterization process is provided that adjusts one or more operating parameters of a processor to improve the health (e.g., reduce errors) of the processor. The parameters include voltage and/or clock frequency, as examples. The processor can be an inactive or active processor for which the re-characterization process is performed. It is performed, in one instance, by a hardware controller in real-time. | 07-25-2013 |
20130246834 | PSEUDO-STATIC DOMINO LOGIC CIRCUIT AND APPARATUSES INCLUDING SAME - A domino logic circuit includes a plurality of domino logic stages connected in series between a latch and a flip-flop and a clock signal generator generating a clock signal having a first duty cycle and a flip-flop clock signal having a second duty cycle. The latch and the domino logic stages respectively operate in response to a domino clock signals derived from the first clock signal. The flip-flop operates in response to the flip-flop clock signal. | 09-19-2013 |
20130262907 | APPARATUS AND METHOD FOR A REDUCED PIN COUNT (RPC) MEMORY BUS INTERFACE INCLUDING A READ DATA STROBE SIGNAL - A method and apparatus for a memory bus interface including a read data strobe. The interface includes a chip select for delivering a chip select signal that indicates when a peripheral device is activated, wherein said bus interface provides communication between a host device and said peripheral device. The interface also includes a differential clock pair for delivering a differential clock signal. A read data strobe is included in the interface for delivering a read data strobe signal from the peripheral device. The interface includes a data bus for delivering command, address, and data information. The read data strobe indicates when valid data is present on the data bus. | 10-03-2013 |
20130262908 | PROCESSING DEVICE AND METHOD FOR CONTROLLING PROCESSING DEVICE - A processing device includes: a clock generating circuit that outputs a clock; an instruction executing circuit that is capable of a state change between an instruction executing state where an instruction is executed and an instruction stop state where an instruction is stopped; a first circuit that inhibits the supply of the clock to an internal circuit when a first clock inhibition signal is input; a second circuit that inhibits the supply of the clock to an internal circuit when a second clock inhibition signal is input; and a control circuit, and the control circuit outputs the second clock inhibition signal to the second circuit after outputting the first clock inhibition signal to the first circuit, when the instruction executing circuit changes from the instruction executing state to the instruction stop state. | 10-03-2013 |
20130262909 | CLOCK RECOVERY, RECEIVER, AND COMMUNICATION SYSTEM FOR MULTIPLE CHANNELS - Disclosed are various exemplary embodiments of a clock recovery apparatus for recovering clock signals of multiple data channels. In one exemplary embodiment a clock recovery apparatus for a plurality of data channels may include a plurality of channel blocks, where each channel block may include a frequency detection block configured to generate an intermediate signal based on a respective data signal received from a respective data channel and a global signal, and a recovery block configured to recover a clock signal for the respective data channel in response to the respective data signal and the global signal. The apparatus may also include a global signal generation block configured to receive and combine the intermediate signals from the plurality of channel blocks to generate the global signal. | 10-03-2013 |
20130290767 | COMMAND PROTOCOL FOR ADJUSTMENT OF WRITE TIMING DELAY - Apparatuses are provided for adjusting the write timing. For instance, the apparatus can include an address/control bus, a write clock data recovery (WCDR) signal bus, and a timing adjustment module. The address/control bus can be configured to concurrently enable a WCDR mode of operation and an active mode of operation. The WCDR signal bus can be configured to transmit WCDR data to a memory device during the WCDR mode of operation. And the timing adjustment module can be configured to adjust a timing based on a phase shift in the WCDR data. | 10-31-2013 |
20130311816 | CIRCUIT AND METHOD FOR CONTROLLABLY DELAYING AN INPUT SIGNAL, AND MICROSCOPE, AND METHOD FOR CONTROLLING A MICROSCOPE - A circuit for delaying an input signal includes first and second delay units. The input signal is switched to the first delay unit which is configured to delay the input signal by k cycles of a first clock signal so as to generate a value x | 11-21-2013 |
20130311817 | SCALABLE, COMMON REFERENCE-CLOCKING ARCHITECTURE USING A SEPARATE, SINGLE CLOCK SOURCE FOR BLADE AND RACK SERVERS - Scalable, common reference-clocking architecture and method for blade and rack servers. A common reference clock source is configured to provide synchronized clock input signals to a plurality of blades in a blade server or servers in a rack server. The reference clock signals are then used for clock operations related to serial interconnect links between blades and/or servers, such as QuickPath Interconnect (QPI) links or PCIe links. The serial interconnect links may be routed via electrical or optical cables between blades or servers. The common reference clock input and inter-blade or inter-server interconnect scheme is scalable, such that the plurality of blades or servers can be linked together in communication. Moreover, when QPI links are used, coherent memory transactions across blades or servers are provided, enabling fine grained parallelism to be used for parallel processing applications. | 11-21-2013 |
20130332766 | METHOD AND SYSTEM FOR CALCULATING A CLOCK FREQUENCY OF A CLOCK SIGNAL FOR AN IC CARD - A clock frequency of a clock signal is calculated, with the clock signal being received by an IC card from a terminal or an internal clock within the IC card. A first time-stamp is received from the terminal, and a first value of the timer is set. The timer of the IC card is started when the first time-stamp is received. A second time-stamp is received, and a second value of the timer is read when the second time-stamp is received. The frequency is calculated by comparing a difference between the second and the first timer values, and a difference between the second and the first time stamps. | 12-12-2013 |
20140006838 | DYNAMIC INTELLIGENT ALLOCATION AND UTILIZATION OF PACKAGE MAXIMUM OPERATING CURRENT BUDGET | 01-02-2014 |
20140006839 | APPARATUS AND METHOD USING FIRST AND SECOND CLOCKS | 01-02-2014 |
20140019792 | TIMING CALIBRATION FOR MULTIMODE I/O SYSTEMS - Integrated circuit devices that operate in different modes. In a low data rate mode, data is transferred between the integrated circuit devices at a low data rate, or no data is transferred at all. In a high data rate mode, data is transferred between integrated circuit devices at a high data rate. A transition mode facilitates the transition from the low data rate mode to the high data rate mode. During the transition mode data is transferred between the integrated circuit devices at an intermediate data rate greater than the low data rate but lower than the high data rate. Also during the transition mode, parameters affecting the transmission of data between the integrated circuit devices are calibrated at the high data rate. | 01-16-2014 |
20140019793 | STRICTLY INCREASING VIRTUAL CLOCK FOR HIGH-PRECISION TIMING OF PROGRAMS IN MULTIPROCESSING SYSTEMS - The present invention relates to a method of building virtual clocks that guarantee strictly increasing and high precision timekeeping of programs executed on multiprocessor systems. Specifically, a multiprocessor system is defined as a computing system composed of multiple processing units, where a processing unit is formed of multiple processor cores which operate asynchronously with each other. In addition each processor core has a time counter and operates with one of multiple operating frequencies and can change the operating frequency dynamically. The method builds a high-precision Strictly Increasing Virtual Clock (SIVC) on top of a computer system's time counter which is used as the reference time counter to which a control layer is implemented for capturing the system events that can advance or delay the elapsed time count of system clocks. In this way, SIVC can provide to the computer system a time counter which produces strictly increasing and high-precision values. A program will access SIVC information by using either an operating system call or a hardware instruction. A computer program will create a SIVC on top of a selected computer system's time counter and by isolating it from differences in time count caused by internal changes of the computer system such as internal replacements of a time counter by the system. The present invention guarantees that the SIVC values are strictly increasing and highly precise. | 01-16-2014 |
20140025981 | DUAL RAIL POWER SUPPLY SCHEME FOR MEMORIES - A dual rail memory operable at a first voltage and a second voltage includes an input circuit, an output circuit and a clock generator circuit coupled with the input circuit. The input circuit is operable to receive at least a first input signal referenced to the first voltage and to generate a second input signal referenced to the second voltage. The output circuit is operable to receive at least a first output signal referenced to the second voltage and to generate a second output signal referenced to the first voltage. The clock generator circuit is operable to receive a first clock signal referenced to the first voltage and to generate a second clock signal referenced to the second voltage, a logic state of the second clock signal being a function of a logic state of the first clock signal. | 01-23-2014 |
20140025982 | INFORMATION PROCESSING EQUIPMENT AND CONTROL METHOD - Information processing equipment that has one or plurality of partitions further includes: a detection unit configured to detect switching of a clock unit from a first clock unit for counting a time used by an operating system in the partition to a second clock unit; a first setting unit configured to set a time obtained from the first clock unit to a third clock unit for counting a time used in the partition when switching of the clock unit is not detected, and to set a time obtained from the third clock unit to the second clock unit when switching of the clock unit is detected; and a second setting unit configured to set a time that is set to the first clock unit by the operating system to the third clock unit when time setting to the first clock unit performed by the operating system is detected. | 01-23-2014 |
20140059374 | METHOD AND APPARATUS FOR SETTING A FREQUENCY OF A CLOCK SIGNAL FOR A BUS BASED ON A NUMBER OF REQUESTS ASSERTED TO TRANSFER DATA ON THE BUS - An integrated circuit includes a generator. The generator, based on a summation signal, generates a clock signal having a frequency. Multiple devices generate respective requests. Each of the requests requests transfer of data on a bus. Each of the devices is configured to, based on the frequency of the clock signal, transfer the data for the corresponding request on the bus. A summer receives the requests and based on a number of the requests being in an asserted state during a first period of time, generates the summation signal. A first module, based on the summation signal, increases a second period of time that a first request is in an asserted state. The second period of time is increased to include or overlap the first period of time. The summer, as a result of the increase, generates the summation signal further based on the first request. | 02-27-2014 |
20140075237 | MEMORY SYSTEM USING ASYMMETRIC SOURCE-SYNCHRONOUS CLOCKING - The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant. | 03-13-2014 |
20140082401 | USB3.0 CLOCK FREQUENCY GENERATION DEVICE WITHOUT CRYSTAL OSCILLATOR - The present invention discloses a USB3.0 clock frequency generation device without crystal oscillator, that is, the crystal oscillator used in the USB3.0 device (or apparatus) is removed and replaced with an oscillator circuit module in the present invention, in which a simple circuit module is added to the controller circuit of the USB3.0 device to provide accurate and proper timing signals needed. The oscillator circuit module includes an oscillator block, a frequency divider block, a delta-sigma modulator block, and a preset number block. | 03-20-2014 |
20140082402 | EMBEDDED MULTIMEDIA CARD (eMMC), HOST FOR CONTROLLING eMMC METHOD OPERATING eMMC SYSTEM - An embedded multimedia card (eMMC) includes a clock channel receiving a clock from a host, a complementary clock channel receiving a complementary clock from the host, a command/response channel exchanging commands/responses with the host, a plurality of data channels exchanging data between the host and the eMMC, a return clock channel sending a return clock to the host synchronously with data, a complementary return clock channel sending a complementary return clock to the host, and a reference voltage channel that either receives a reference voltage from the host or communicates a reference voltage to the host. | 03-20-2014 |
20140089720 | APPARATUS AND METHODS FOR DETERMINING LATENCY OF A NETWORK PORT - One embodiment relates to a method for determining a latency of a network port. Read and write pointers for a FIFO are sampled at the same time. An average difference between a plurality of samples of the read and write pointers is determined. Another embodiment relates to an apparatus for providing timestamps to packets at a network port. Registers sample read and write pointers of a FIFO using a sampling clock. Logic circuitry determines an average difference between the read and write pointers, and timestamping circuitry receives the average difference and inserts timestamps into packets. Other embodiments and features are also disclosed. | 03-27-2014 |
20140089721 | BACKPLANE COMMUNICATION SYSTEM - The invention relates to an improved backplane communication system. In one embodiment this is accomplished by a central data processing card including at least one master central card and a plurality of slave central card, wherein each master central card and the slave central card having a first SerDes (serializer-deserializer), a first clock and a first faster local clock, a line card including a second SerDes (serializer-deserializer), a clock selection module and a second faster local clock and a serial communication channel coupling the central data processing card and the line card, wherein the master central card uses the first faster local clock to transmits the data at a rate higher than actually required, wherein the transmitted data includes a stuff data to adjust to the link data rate between the central data processing card and line card. | 03-27-2014 |
20140095919 | CLOCK CONTROL METHOD FOR PERFORMANCE THERMAL AND POWER MANAGEMENT SYSTEM - A control method for a clock signal for a CPU contained in a CMOS circuit includes: when a load current for the CMOS circuit is enabled, generating a first clock signal; in a first period, selectively gating certain cycles of the first clock signal to generate a second clock signal which has a clock rate less than a clock rate of the first clock signal; and in a second period, dithering in the gated cycles to increase the clock rate of the second clock signal to be equal to that of the first clock signal. The second clock signal is continuously input to the CMOS circuit during the first period and the second period. | 04-03-2014 |
20140095920 | Variable clocked serial array processor - A serial array processor may have an execution unit, which is comprised of a multiplicity of single bit arithmetic logic units (ALUs), and which may perform parallel operations on a subset of all the words in memory by serially accessing and processing them, one bit at a time, while an instruction unit of the processor is pre-fetching the next instruction, a word at a time, in a manner orthogonal to the execution unit. | 04-03-2014 |
20140108848 | PROCESSOR AND CONTROL METHOD FOR PROCESSOR - A processor includes a plurality of processing units. A plurality of first arbitration units each arbitrate request signals output from at least two of the processing units to generate a first arbitration signal. A second arbitration unit arbitrates first arbitration signals output from the first arbitration units to generate a second arbitration signal. A plurality of clock controllers, arranged in correspondence with the first arbitration units, each generate a clock signal supplied to a corresponding first arbitration unit and the processing units coupled to the corresponding first arbitration unit. A control unit determines whether or not to operate each processing unit in accordance with an operation state of the processor and generates control information according to the determination result. Each of the clock controllers supplies or stops the clock signal or changes a frequency of the clock signal in accordance with the control information. | 04-17-2014 |
20140108849 | METHOD, APPARATUS, AND SYSTEM FOR OPTIMIZING FREQUENCY AND PERFORMANCE IN A MULTIDIE MICROPROCESSOR - With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status. | 04-17-2014 |
20140115375 | MULTI-LEVEL ENCODED DATA TRANSFER - Multi-level encoded data transfer is disclosed. 2 | 04-24-2014 |
20140129868 | SELECTABLE PHASE OR CYCLE JITTER DETECTOR - Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit. | 05-08-2014 |
20140136875 | APPARATUS AND METHOD OF CONTROLLING CLOCK SIGNALS - An apparatus and a method of controlling clock signals for a master device and a slave device are disclosed. The controlling apparatus includes: a first connection port coupled to a first clock line of the master device; a second connection port coupled to a second clock line of the slave device; and a control module receiving a first clock signal from the master device via the first connection port, producing a second clock signal according to the first clock signal, and transmitting the second clock signal to the slave device via the second connection port; wherein when the first clock signal is switched from a first logic level to a second logic level, the control module controls the first connection port to maintain the second logic level in a time interval. | 05-15-2014 |
20140136876 | Complementary Output Generator Module - A complementary output generator (COG) module generates at least two complementary outputs determined by rising and falling event sources. In a simple configuration of the COG module, the rising and falling event sources are the same signal which is a signal having the desired period and duty cycle. The COG module converts this single signal input into dual complementary outputs. The frequency and duty cycle of the dual outputs substantially match those of the single input signal. Blanking and deadband times may be introduced between the complementary outputs, and the dual complementary outputs may also be phase delayed. In addition the COG module may provide up to four outputs for controlling half and full-wave bridge power applications. | 05-15-2014 |
20140173324 | AUTOMATIC SELECTION OF ON-CHIP CLOCK IN SYNCHRONOUS DIGITAL SYSTEMS - Embodiments of a synchronous digital system are disclosed that may include generation of clock and synchronization signals. Any of a plurality of available clock signals may be selected for use as a primary clock, without causing clock-induced errors in the synchronous digital system. A clock signal generated on-chip with the synchronous digital system may be automatically selected in response to detecting a condition indicating that use of a local clock may be necessary. Such conditions may include detection of tampering with the synchronous digital system. If an indication of tampering is detected, security measures may be performed. | 06-19-2014 |
20140181570 | SIGNAL PROCESSING CIRCUITRY WITH FRONTEND AND BACKEND CIRCUITRY CONTROLLED BY SEPARATE CLOCKS - An apparatus comprises read channel circuitry and associated signal processing circuitry comprising frontend processing circuitry and backend processing circuitry. The frontend processing circuitry comprises a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal. The backend processing circuitry comprises a backend detector, an interleaver, a backend decoder, and a de-interleaver configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal. The frontend processing circuitry is controlled by a first clock having an associated first clock rate and the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate determined at least in part by the first clock rate and a maximum clock rate. | 06-26-2014 |
20140181571 | MANAGING FAST TO SLOW LINKS IN A BUS FABRIC - Systems and methods for managing fast to slow links in a bus fabric. A pair of link interface units connect agents with a clock mismatch. Each link interface unit includes an asynchronous FIFO for storing transactions that are sent over the clock domain crossing. When the command for a new transaction is ready to be sent while data for the previous transaction is still being sent, the link interface unit prevents the last data beat of the previous transaction from being sent. Instead, after a delay of one or more clock cycles, the last data beat overlaps with the command of the new transaction. | 06-26-2014 |
20140223220 | CLOCK SELECTION CIRCUIT AND METHOD - The invention provides a clock select circuit and method which uses feedback arrangements between latches in different branches, with each branch for coupling an associated clock signal to the circuit output. An override circuit is provided in one of the feedback arrangements for preventing a latching delay in that feedback arrangement. This enables rapid switching between clocks in both directions. | 08-07-2014 |
20140258765 | CPU Current Ripple and OCV Effect Mitigation - High frequency current transients, due to logic switching inside the CPU, are reduced by applying clock signals having different relative phases to different parts of the CPU. This reduces the amplitude of current variations, and hence noise induced onto the power supply voltage. In some embodiments, different CPU cores within multi-core CPUs are clocked with a different clock phases. Additionally a method and circuit for low-latency communication in the presence of large OCV effects is provided. The low-latency communication may be based on a FIFO. Strobes are used to indicate safe points in time to update and read signals between transmitter and receiver. The strobes are generated in a central clock generation module. The strobe mechanism is used to transfer the read and write pointers between the transmitter and receiver, while the payload data is transferred using a FIFO data array that allows data writes to be asynchronous to corresponding data reads. | 09-11-2014 |
20140281656 | Global Synchronous Clock - Processor clock signals are generated for each processor in a HPC system, such that all the processor clock signals are of the same frequency. Furthermore, as part of a startup (boot) procedure, a process sets all time stamp counters (TSCs) of the processors, such they indicate identical times. Each blade of the HPC system recovers a recovered clock signal from a synchronous communication network, to which the blade is coupled. The blade generates a processor clock from the recovered clock signal and provides the processor clock to processor(s) on the blade. Each chassis is coupled to a second, system-wide, synchronous communication network, and each chassis synchronizes its chassis synchronous communication network with the system-wide synchronous communication system. Thus, all the processor clock signals are generated with the same frequency. | 09-18-2014 |
20140281657 | PROCESSOR CORE CLOCK RATE SELECTION - Techniques described herein generally relate to multi-core processors including two or more processor cores. Example embodiments may set forth devices, methods, and computer programs related to calculating a clock rate for one or more of the processor cores in the multi-core processor. One example method may include determining a first estimated workload for a first processor core and a second estimated workload for a second processor core within a scheduling interval in a periodic scheduling environment. In addition, a first clock rate for the first processor core may be calculated based on one or more of the first estimated workload, a maximum clock rate supported by the multi-core processor and/or the scheduling interval. Similarly, a second clock rate for the second processor core may also be calculated based on one or more of the second estimated workload, the maximum clock rate, and/or the scheduling interval. | 09-18-2014 |
20140317433 | CLOCK CONTROL CIRCUIT AND METHOD - This invention provides a clock control circuit, which can be added to any pipeline-processor to solve timing problems arising from variations due to process outcome and environmental conditions. Critical instructions are detected (instructions that exercise critical paths) in conjunction with environmental sensing (such as process, temperature and voltage). This information is used to control cycle stealing. | 10-23-2014 |
20140337657 | DESIGN SUPPORT DEVICE, DESIGN SUPPORT METHOD, AND COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN DESIGN SUPPORT PROGRAM - When a sequential circuit to which a clock signal distributed by a first buffer included in a clock distribution circuit is input is added, in a case where a plurality of other sequential circuits are connected to the first buffer, a processor determines whether or not a distance between the sequential circuit to be added and the first buffer is between a maximum value and a minimum value of distances between the first buffer and the plurality of other sequential circuits based on the physical design data stored in the memory, and, as a result of the determination, in a case where the distance between the sequential circuit to be added and the first buffer is between the maximum value and the minimum value, the processor performs wiring processing of the clock signal supplied from the first buffer for the sequential circuit to be added. | 11-13-2014 |
20140344614 | Specifying and Implementing Relative Hardware Clocking in a High Level Programming Language - System and method for specifying and implementing relative hardware clocking in a high level programming language. User input specifying a program may be received. The program is specified for deployment to a programmable hardware element (PHE), and includes first and second code portions configured to communicate with each other during execution. The user input may further specify a rational ratio of respective execution rates for the first and second code portions. A hardware configuration program (HCP) implementing the specified program is automatically generated, including automatically determining a respective clock rate for at least one of the first and second code portions based on the rational ratio. The HCP may be deployable to the PHE, including implementing first and second clocks for controlling execution of the first and second code portions in accordance with the rational ratio and the automatically determined respective clock rate for the at least one code portion. | 11-20-2014 |
20140344615 | CIRCUITRY FOR ACTIVE CABLE - Circuits, methods, and apparatus that allow signals that are compliant with multiple standards to share a common connector on an electronic device. An exemplary embodiment of the present invention provides a connector that provides signals compatible with a legacy standard in one mode and a newer standard in another mode. | 11-20-2014 |
20140372785 | HIGH-SPEED I/O DATA SYSTEM - In embodiments of a high-speed I/O data system, a first computer chip includes a data transmission system, and a second computer chip includes a data reception system. A data channel communicates an NRZ data signal, and a clock channel communicates a forwarded clock signal, from the data transmission system to the data reception system. The data transmission system includes a first differential serializing transmitter to generate the NRZ data signal from pulsed data, and further includes a second differential serializing transmitter to generate a forwarded clock signal. A first multi-phase transmit clock generator generates transmit clock signals for the first and second differential serializing transmitters. The data reception system includes a data receiver and a de-serializer to receive and de-serialize the NRZ data signal, and includes a multi-phase receive clock generator to generate receive clock signals from the forwarded clock signal for the de-serializing data receiver. | 12-18-2014 |
20140380082 | INTEGRATED CIRCUIT COMPRISING FRACTIONAL CLOCK MULTIPLICATION CIRCUITRY - Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO. | 12-25-2014 |
20150033061 | Harmonic Detector of Critical Path Monitors - A system for monitoring a clock input signal including a reference clock to be monitored, a flip-flop, a plurality of delay logic blocks, a sampling unit, and a comparison unit. The reference clock may have an expected maximum frequency. The flip-flop may be configured to generate a corresponding clock signal at a reduced frequency compared to the reference clock. The plurality of delay logic blocks may be configured to receive the reduced frequency clock signal and delay the signal for various amounts of time, each less than an expected period of the reference clock. The sampling unit may be configured to sample the signals output from the plurality of delay logic blocks. The comparison unit may be configured to receive the outputs of the flip-flop and the sampling unit and use these outputs to determine if the reference clock is running at an acceptable frequency compared to the expected frequency. | 01-29-2015 |
20150033062 | APPARATUS AND METHOD FOR CONTROLLING CONTROLLABLE CLOCK SOURCE TO GENERATE CLOCK SIGNAL WITH FREQUENCY TRANSITION - A clock generator includes a controllable clock source and a frequency hopping controller. The controllable clock source generates a clock signal to a clock-driven device. The frequency hopping controller controls the controllable clock source to make the clock signal have at least one frequency transition from one clock frequency to another clock frequency, wherein the controllable clock source stays in a frequency-locked state during a time period of the at least one frequency transition. | 01-29-2015 |
20150052378 | CONNECTING INTERFACE UNIT AND MEMORY STORAGE DEVICE - A connecting interface unit and a memory storage device without a crystal oscillator are provided and include a frequency detector, a phase detector, an oscillator, a sampling circuit and a transmitter circuit. The frequency detector and the phase detector respectively detect frequency difference and phase difference between an input signal from a host system and a reference signal to generate a frequency signal and a phase signal. The frequency signal and the phase signal that have passed through a filter are transmitted to the oscillator to generate the reference signal for generating a clock signal. The sampling circuit generates an input data signal according to the reference signal. The transmitter circuit modulates an output data signal according to the clock signal to generate and transmit an output signal to the host system. Accordingly, the connecting interface unit conforms to the specification of a transmission stand. | 02-19-2015 |
20150052379 | SPREAD SPECTRUM CLOCK GENERATION CIRCUIT, CLOCK TRANSFER CIRCUIT, INTEGRATED CIRCUIT, AND IMAGE READING APPARATUS - A spread spectrum clock generation circuit includes a generation unit configured to generate and output a spread spectrum clock based on an input reference clock, a monitoring unit configured to monitor a difference between the number of pulses of a reference clock input to the generation unit after a reference time and the number of pulses of a spread spectrum clock output from the generation unit after the reference time, and a control unit configured to control a frequency of a spread spectrum clock to be generated by the generation unit so as to make the difference fall within a predetermined range. | 02-19-2015 |
20150074444 | DATA PROCESSING DEVICE AND METHOD FOR DETERMINING A CLOCK RELATIONSHIP - A data processing device is described comprising a first clock generator configured to generate a first clock signal with a first frequency; a second clock generator configured to generate a second clock signal with a second frequency, wherein the second frequency is higher than the first frequency; and a processing circuit configured to sample a clock cycle number of the second clock signal at a plurality of sample times given by the first clock signal and determine a relationship between the first frequency and the second frequency based on a minimization of a measure of a deviation of the sampled clock cycle numbers from the clock cycle numbers of the second clock signal at the plurality of sample times expected according to the determined relationship. | 03-12-2015 |
20150082074 | TECHNIQUE FOR SCALING THE BANDWIDTH OF A PROCESSING ELEMENT TO MATCH THE BANDWIDTH OF AN INTERCONNECT - A transmitter is configured to scale up a low bandwidth delivered by a first processing element to match a higher bandwidth associated with an interconnect. A receiver is configured to scale down the high bandwidth delivered by the interconnect to match the lower bandwidth associated with a second processing element. The first processing element and the second processing element may thus communicate with one another across the interconnect via the transmitter and the receiver, respectively, despite the bandwidth mismatch between those processing elements and the interconnect. | 03-19-2015 |
20150082075 | TECHNIQUE FOR SCALING THE BANDWIDTH OF A PROCESSING ELEMENT TO MATCH THE BANDWIDTH OF AN INTERCONNECT - A transmitter is configured to scale up a low bandwidth delivered by a first processing element to match a higher bandwidth associated with an interconnect. A receiver is configured to scale down the high bandwidth delivered by the interconnect to match the lower bandwidth associated with a second processing element. The first processing element and the second processing element may thus communicate with one another across the interconnect via the transmitter and the receiver, respectively, despite the bandwidth mismatch between those processing elements and the interconnect. | 03-19-2015 |
20150106649 | DYNAMIC SCALING OF MEMORY AND BUS FREQUENCIES - Systems and methods for controlling a frequency of system memory and/or system bus on a computing device are disclosed. The method may include monitoring a number of read/write events occurring in connection with a hardware device during a length of time with a performance counter and calculating an effective data transfer rate based upon the amount of data transferred. The method also includes periodically adjusting a frequency of at least one of the system memory and the system bus based upon the effective data transfer rate and dynamically tuning a threshold number of events that trigger an interrupt based upon a history of the number of read/write events. In addition, the method includes receiving the interrupt from the performance counter when the threshold number of read/write events occurs and adjusting the frequency of at least one of the system memory and the system bus when the interrupt occurs. | 04-16-2015 |
20150121118 | METHOD AND DEVICES FOR CONTROLLING OPERATIONS OF A CENTRAL PROCESSING UNIT - Control circuitry controls the operations of a central processing unit, CPU, which is associated with a nominal clock frequency. The CPU is further coupled to an I/O range and configured to deliver input to an application. The control circuitry controls the CPU to poll the I/O range for input to the application. The control circuitry also monitors whether or not each poll results in input to the application and adjusts a clock frequency at which the CPU operates to a clock frequency lower than the nominal clock frequency if a pre-defined number of polls resulting in no input is detected. Methods and a central computer server of an automated exchange system are also provided. | 04-30-2015 |
20150134999 | METHOD AND APPARATUS FOR ATOMIC FREQUENCY AND VOLTAGE CHANGES - A method and apparatus for atomic frequency and voltage changes in the processor. In one embodiment of the invention, the atomic frequency and voltage changes in the processor is feasible due to the enabling technology of fully integrated voltage regulators (FIVR) that are integrated in the processor. FIVR allows independent configuration of each core in the processor and the configuration includes, but is not limited to, voltage setting, frequency setting, clock setting and other parameters that affects the power consumption of each core. | 05-14-2015 |
20150149808 | FREQUENCY CALIBRATION METHOD APPLICABLE IN UNIVERSAL SERIAL BUS DEVICE AND RELATED UNIVERSAL SERIAL BUS DEVICE - A frequency calibration method applied to a Universal Serial Bus (USB) device includes: coupling the USB device to a USB host, wherein the USB device at least comprises a programmable oscillator; utilizing the USB device to extract a low frequency periodic signal from the USB host; and calibrating the programmable oscillator of the USB device according to the low frequency periodic signal, to make the programmable oscillator generate an oscillating signal having a predetermined frequency. | 05-28-2015 |
20150323957 | Method for Stabilizing the Clock Frequency of a Microcontroller - A method for stabilizing the clock frequency of a microcontroller associated with a field device of automation technology. The field device as a function of application is exposed to different process conditions, wherein the clock frequency of the microcontroller is ascertained at at least two different temperature values, and/or at at least two different voltage values. Based on the ascertained values, the dependence of the clock frequency of the microcontroller on temperature over a predetermined temperature- and/or frequency range and/or the dependence of the clock frequency of the microcontroller on voltage over a predetermined voltage- and/or frequency range is ascertained. The ascertained values are stored, and the influence of temperature and/or voltage on the clock frequency of the microcontroller is at least approximately compensated taking into considerating the ascertained temperature dependence and/or the ascertained voltage dependence. | 11-12-2015 |
20160004273 | Clock generator, communication device and sequential clock gating circuit - The present invention discloses a clock generator comprising: an oscillator operable to generate a reference clock; a multi-phase clock generating circuit operable to generate a plurality of output clocks of the same frequency but different phases according to the reference clock and stop or start outputting the output clocks according to a power control signal; a sequential clock gating circuit operable to sequentially stop or start outputting a plurality of gated clocks according to a gate control signal and maintain an output cycle number relation between the gated clocks even though the multi-phase clock generating circuit stops and then starts outputting the output clocks; and a clock operation control circuit operable to provide the power control signal and the gate control signal. | 01-07-2016 |
20160011623 | PROCESSOR STATE CONTROL BASED ON DETECTION OF PRODUCER/CONSUMER WORKLOAD SERIALIZATION | 01-14-2016 |
20160011624 | DYNAMIC SYSTEM MANAGEMENT BUS | 01-14-2016 |
20160013779 | MULTI-RATE CLOCK BUFFER | 01-14-2016 |
20160048154 | APPARATUS AND METHOD USING FIRST AND SECOND CLOCKS - Receiving an indication of a frequency ratio of first and second clocks; generating an indication of a number of clock pulses of the second clock occurring between first and second clock pulses of the first clock; and generating an indication of a time offset between (1) a clock pulse of the second clock occurring between the second clock pulse and a third clock pulse of the first clock, and (2) the second clock pulse of the first clock. Also, receiving an input data word representing a fractional number, a first part of the input data word comprising an integer portion of the fractional number and a second part comprising a decimal portion of the fractional number; providing a first output data word that is either the first part of the input data word or an increment by one of the first part; and providing a second output data word that is an integer multiple of the second part. | 02-18-2016 |
20160098060 | CRUM UNIT MOUNTABLE IN CONSUMABLE UNIT OF IMAGE FORMING APPARATUS AND IMAGE FORMING APPARATUS USING THE SAME - A customer replacement unit monitor (CRUM) unit that can be mounted in an image forming apparatus includes a decoder which receives first clock signals from the image forming apparatus and converts the first clock signals into second clock signals, a memory which stores data related with a consumable unit, and a controller which manages the memory based on data signals transmitted from the image forming apparatus and the second clock signals. The first clock signals are divided into a data section in which the data signals are transmitted and received and an idle section in which the data signals are not transmitted and received. The first clock signals have a first frequency on the data section while having a second frequency on the idle section, and the second clock signals are clock signals maintaining a high value or a low value on the idle section. | 04-07-2016 |
20160147249 | Apparatus and Method to Provide Multiple Domain Clock Frequencies In A Processor - In an embodiment, a processor includes at least one core, a first domain to operate at a first clock frequency, and a second domain to operate at a second clock frequency that is lower than the first clock frequency. The processor also includes phase locked loop (PLL) logic to generate a first signal having a first frequency corresponding to the first clock frequency and to provide the first signal to the first domain. The processor also includes a first clock to produce a first squash signal that is determined based at least in part on the second clock frequency, and also first logic to generate a second signal having a second frequency corresponding to the second clock frequency by gating the first signal with the first squash signal and to provide the second signal to the second domain. Other embodiments are described and claimed. | 05-26-2016 |
20160147251 | SIGNAL GENERATOR FOR A MEASURING APPARATUS AND MEASURING APPARATUS FOR AUTOMATION TECHNOLOGY - The invention relates to a signal generator for producing periodic signals for a measuring apparatus ( | 05-26-2016 |
20160202722 | TRANSMISSION DEVICE AND METHOD FOR CONTROLLING FIFO CIRCUIT | 07-14-2016 |