Entries |
Document | Title | Date |
20080201596 | Clock buffer circuit of semiconductor device - A clock buffer circuit of a semiconductor device is disclosed which receives an external clock signal and generates an internal clock signal with no duty distortion. The clock buffer circuit includes a first clock buffer for receiving and buffering a normal-phase clock signal, a second clock buffer for receiving and buffering a reverse-phase clock signal, and an internal clock generator for generating an internal clock signal in response to output signals from the first and second clock buffers. | 08-21-2008 |
20080201597 | WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES - Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device. | 08-21-2008 |
20080201598 | Device and Method For Preventing Lost Synchronization - A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses. | 08-21-2008 |
20080201599 | COMBINED ALIGNMENT SCRAMBLER FUNCTION FOR ELASTIC INTERFACE - An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state transitions. The busy interface alignment pattern can be used for scrambling and unscrambling operational data. The interface alignment pattern has a unique timing sequence for determining the location of a data bit's first data beat. | 08-21-2008 |
20080215906 | Method for Fault Tolerant Time Synchronization Mechanism in a Large Scaleable Multi-Processor Computer - Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips. | 09-04-2008 |
20080222442 | CIRCUIT FOR GENERATING OUTPUT ENABLE SIGNAL IN SEMICONDUCTOR MEMORY APPARATUS - A circuit for generating an output enable signal in a semiconductor memory apparatus which can include an interval setting unit capable of delaying a burst length signal in synchronized with a clock, thereby generating an interval setting signal, and a signal generating unit for generating an output enable signal in response to a read command signal and the interval setting signal. | 09-11-2008 |
20080244299 | Data processing apparatus and method for translating a signal between a first clock domain and a second clock domain - The present invention provides a data processing apparatus and method for translating a signal between a first clock domain and a second clock domain. The data processing apparatus may comprise a first component for generating a signal, the first component operating in the first clock domain having a first clock period, and a second component for receiving the signal, the second component operating in the second clock domain having a second clock period. In one embodiment, the second clock period is synchronous with but slower than the first clock period. Interface circuitry is provided for translating the signal between the first clock domain and the second clock domain, the interface circuitry operating in the first clock domain and comprising a storage element for temporarily buffering the signal generated by the first component before outputting that signal to the second component. Further, enable circuitry is used to control output of the signal from the storage element having regard to a specified input delay value identifying an input delay time of the second component expressed in terms of the first clock period. Hence, such a data processing apparatus controls translation of a signal from a fast clock domain to a slow clock domain where the input delay time of the component in the slower clock domain is configured in terms of the fast clock period, thereby enabling the latency to be tuned having regard to the slow clock domain input delay constraints. In an alternative embodiment, a similar arrangement is used to control translation of a signal from a slow domain to a fast clock domain, with the output delay time of the component in the slow clock domain being configured in terms of the fast clock period. | 10-02-2008 |
20080244300 | Fault Tolerant Time Synchronization Mechanism in a Scaleable Multi-Processor Computer - Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips. | 10-02-2008 |
20080250263 | Integrated Circuit Input/Output Interface with Empirically Determined Delay Matching - An integrated circuit input/output interface with empirically determined delay matching is disclosed. In one embodiment, the integrated circuit input/output interface uses empirical information of signal traces coupled to the integrated circuit to adjust a transmit/receive clock of each pin of the interface so as to compensate for delay mismatches caused by differences in signal trace lengths. In one embodiment, values representative of the empirical information are stored for use by the integrated circuit to generate trace-specific signals so as to compensate for delay differences that are at least partially caused by unmatched signal trace lengths. The empirical information, in one embodiment, includes signal flight time of each signal trace, which can be pre-measured or pre-calculated from known signal trace lengths. The empirical information, in another embodiment, includes trace-specific phase offset values calculated from pre-calculated or pre-measured signal flight times or signal trace lengths. | 10-09-2008 |
20080276112 | SEMICONDUCTOR INTEGRATED CIRCUIT - A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay. | 11-06-2008 |
20080313485 | DATA PIPELINE WITH LARGE TUNING RANGE OF CLOCK SIGNALS - The invention relates to a data pipeline comprising a first stage with a data input for receiving a digital data input signal, a clock input and a data output, and a first bi-stable element being adapted to be switched in response to an edge of a first clock signal, and a dynamic latch stage comprising an input transfer element, and a second bi-stable element coupled between the input transfer element and a dynamic latch data output, wherein the input transfer element is adapted to be switched by a second clock signal and a delayed second clock signal, which is delayed with respect to the second clock signal by a first period of time being shorter than half a period of the second clock signal, such that the input transfer element allows signal transfer only during the first period of time. | 12-18-2008 |
20080320324 | Data recovery (CDR) architecture using interpolator and timing loop module - The present invention provides a method and mechanism for data recovery with phase synchronized clock using interpolator and timing loop module and a data latching circuit. The interpolator can be considered as a programmable delay circuit with a specified delay resolution over the clock period. | 12-25-2008 |
20080320325 | DLL phase detection using advanced phase equalization - A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an On1x mode (i.e., left shifting on each clock cycle). The feedback clock that tracks the phase of the reference clock (which, in turn, is derived from the system clock) is initially delayed in a coarse phase detector prior to applying it to the coarse phase detection window. Two delayed versions of the feedback clock are sampled by the reference clock to generate a pair of phase information signals, which are then used to establish an advanced phase equal (APHEQ) signal. The APHEQ signal advances onset of the PHEQ (phase equalization) phase and is used to terminate the ForceSL and On1x modes, thereby preventing wrong ForceSL exit due to clock jitter or feedback path overshooting during On1x exit. The avoidance of wrong ForceSL exit and On1x overshooting problems further results in faster DLL locking time. | 12-25-2008 |
20090019302 | Calculating Apparatus Having A Plurality of Stages - A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e., hundreds, of stages arranged in parallel sub-arrays, the clocking conductor is snaked alongside the sub-arrays. In individual stages it is arranged that the shortest of the two calculations taking place in a stage, takes place in the return path. An array can be divided into separate sections for independent processing. | 01-15-2009 |
20090031158 | Method and apparatus for providing symmetrical output data for a double data rate dram - An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal. | 01-29-2009 |
20090037758 | USE OF T4 TIMESTAMPS TO CALCULATE CLOCK OFFSET AND SKEW - Disclosed are a method and system for calculating clock offset and skew between two clocks in a computer system. The method comprises the steps of sending data packets from a first processing unit in the computer system to a second processing unit in the computer system, and sending the data packets from the second processing unit to the first processing unit. First, second, third and fourth time stamps are provided to indicate, respectively, when the packets leave the first processing unit, arrive at the second processing unit, leave the second processing unit, and arrive at the first processing unit. The method comprises the further steps of defining a set of backward delay points using the fourth time stamps, and calculating a clock offset between clocks on the first and second processing units and clock skews of said clocks using said set of backward delay points. | 02-05-2009 |
20090055675 | Adjustable Byte Lane Offset For Memory Module To Reduce Skew - Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for such skew, an on-chip delay is added to the data out paths of those bits in the byte lane with otherwise would arrive early to their destinations. Such on-chip delay is provided delay circuits preferably positioned directly before the output buffers/bond pads of the integrated circuit or module. By intentionally delaying some of the outputs from the integrated circuit or module, external skew is compensated for so that all data in the byte lane arrives at the destination at substantially the same time. In a preferred embodiment, the delay circuits are programmable to allow the integrated circuit or module to be freely tailored to environments having different skew considerations, such as different styles of connectors. | 02-26-2009 |
20090063887 | MEMORY MODULE WITH TERMINATION COMPONENT - A memory component having a first and second interface. The first interface is provided to sample address information in response to a first clock signal. The first interface includes inputs to sample at least two bits of the address information in succession during a clock cycle of the first clock signal. The second interface is provided to sample data in response to a second clock signal, having a frequency that is at least twice the frequency of the first clock signal. The second interface includes inputs to sample at least two bits of data in succession during a clock cycle of the second clock signal. | 03-05-2009 |
20090077409 | CIRCUITS TO DELAY A SIGNAL FROM A MEMORY DEVICE - A circuit for delaying an input control signal, comprises a clock circuit to generate a clock signal having a frequency different from an input clock signal to delay and including a clock signal input, a derivative clock signal output, an input to program a frequency ratio between its input clock frequency and its output clock frequency. A clock capturing circuit provides a determined number of delay elements required to provide a delay of an amount of the period of the signal provided by the clock circuit. A delay calculation circuit receives the determined number of delay elements and calculates a number of delay elements needed to delay the input control signal by an amount of time. A delay circuit includes a control signal input, a select input for receiving the number of delay elements provided by the delay calculation circuit. | 03-19-2009 |
20090119532 | Method and system for a free running strobe tolerant interface - A method of receiving data. A plurality of data signals and clocking signals are received over a source synchronous communication channel. The plurality of data signals is strobed with the clocking signal at a plurality of coarse time offset delays (e.g., time offset delays spanning over a data bit period). The plurality of error rates associated with the strobing at the plurality of coarse time offset delays is determined. Strobing design of a transmitting component (e.g., edge-strobed, center-strobed, etc.) may be determined based on the plurality of error rates. The error rates of the plurality of data signals strobed with a plurality of time offset delays close to the determined strobing design of the transmitting component is calculated. A time offset delay is selected based on the error rates. The plurality of data signals can be strobed with the selected time offset delay to recover the transmitted data signals. | 05-07-2009 |
20090119533 | Digital delay locked loop circuit using mode register set - A semiconductor memory device includes a mode register set for establishing information on a delay time, a delay time calculator for calculating an I/O path delay time of a data clock on a basis of a unit period of a system clock, and a delay locked clock generator for reflecting in the data clock a value of subtracting an output of the delay time calculator from the information established in the mode register set. | 05-07-2009 |
20090138744 | MULTIPLIER DEVICE WITH SUPPRESSION OF HIGHER-ORDER DISTORTION - A multiplier device is configured to include first to n | 05-28-2009 |
20090150707 | MESOSYNCHRONOUS DATA BUS APPARATUS AND METHOD OF DATA TRANSMISSION - A memory system is described, where the transmission time of data between memory modules is managed so that the overall time delay between specified points in the memory system is maintained a constant. Each lane of a multilane bus may be separately managed, and a data frame evaluated at the destination module, without a need for deskewing at intermediate modules. The time delay in propagation of the data through a module, which may have a switch to route the data, is reduced by operating the data path through the module at one or more submultiples of the bus serial data rate, and selecting the sampling point of the received data so that variations in time delay due to temperature changes or ageing are accommodated. | 06-11-2009 |
20090217074 | TIME SYNCHRONIZATION IN UNITS AT DIFFERENT LOCATIONS - To synchronize units of a formation evaluation/drilling operation evaluation system, a time delay associated with a communications link between a master unit and a slave unit of the formation evaluation/drilling operation evaluation system is determined. The master unit has a master time clock that provides universal time. The time delay associated with the communications link is used to enable synchronization of time provided by a slave time clock in the slave unit to the universal time. | 08-27-2009 |
20090240968 | METHOD FOR CALIBRATING READ OPERATIONS IN A MEMORY SYSTEM - A method of calibrating read operations in a memory system is disclosed. The method involves placing a memory controller in a calibration mode, and performing a series of dummy read operations. Each of the read operations performs a read of pre-specified data stored in at least one memory component while using different ones of delayed enable signals. Data read from respective dummy read operations is compared to identify successful read operations while the timing information from successful read operations is compared to identify a suitable delayed enable signal. | 09-24-2009 |
20090240969 | System and Method to Facilitate Deterministic Testing of Data Transfers between Independent Clock Domains on a Chip - A system and method of deterministically transferring data across a first clock domain to a second clock domain includes receiving a resynchronize command, initiating a corresponding one of a plurality of read delays in each one of a second plurality of devices in the second clock domain, counting down the plurality of read delays to zero, receiving a training pattern after the plurality of read delays count down to zero in each one of the second plurality of devices, recovering a clock data in each of the second plurality of devices, receiving a synch byte by each of the second plurality of devices, selecting one of a plurality of serial lanes as a reference lane, wherein the plurality of serial lanes couple the first clock domain to the second clock domain, initiating a write pointer, writing n bytes of serial data to a buffer and converting the n bytes of data from serial data to parallel data in a serial to parallel converter such that the serial n byte data in the buffer are aligned in time. | 09-24-2009 |
20090259872 | PROGRAMMABLE DATA SAMPLING RECEIVER FOR DIGITAL DATA SIGNALS - Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture includes a linear receiver portion having a first input node for a data (DQ) signal, a second input node for a reference voltage, and output nodes for a differential output signal. The linear receiver portion is configured to compare the DQ signal to the reference voltage, and to generate the differential output signal in response to the comparison. A sense amplifier portion is coupled to the linear receiver portion. The sense amplifier portion has input nodes connected to the output nodes of the linear receiver portion, and an output node for a binary output signal having voltage characteristics compatible with the computer processor. The sense amplifier portion is configured to transform the differential output signal into the binary output signal. The receiver architecture also includes a programming architecture coupled to the linear receiver portion, the programming architecture being configured to set operating characteristics of the linear receiver portion. | 10-15-2009 |
20090259873 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH POWER SAVING FEATURE - A non-volatile semiconductor memory device, comprising: an interface for receiving commands issued by a controller, the commands including an erase command; a functional entity with circuit components and having a terminal; a node; switchable circuitry capable of controllably switching between a first operational state in which the terminal is electrically connected to the node and a second operational state in which the terminal is electrically decoupled from the node, the node being configured to have a signal for the functional entity communicated through it when the switchable circuitry is in the first operational state; and a command processing unit configured to recognize the commands issued by the controller and, in response to recognizing the erase command, to cause the switchable circuitry to switch from the first operational state to the second operational state. | 10-15-2009 |
20090307516 | Asynchronous circuit insensitive to delays with time delay insertion circuit - The asynchronous circuit insensitive to delays comprises at least one time delay insertion circuit on the propagation path of a signal. The delay insertion circuit comprises, between an input and an output of the signal, a Muller C-element and a plurality of delay circuits connected in series to an output of the Muller C-element. The outputs of the delay circuits are connected to corresponding inputs of a multiplexing circuit having an output constituting the output of the delay insertion circuit. The Muller C-element comprises an input connected to the output of the last delay circuit via an inverter gate, and an input constituting the input of the signal to the delay insertion circuit. The multiplexing circuit control circuit preferably comprises a random generator. | 12-10-2009 |
20090319816 | INFORMATION PROCESSING APPARATUS AND TIME MEASUREMENT METHOD - An information processing apparatus includes a versatile Operating System (OS) that performs a time measurement process in response to a request from an application, a storage unit that stores a process load of the versatile OS and a delay time of the time measurement process in combination, a detecting unit that detects a process load of the versatile OS when the application requests the time measurement process, an acquiring unit that acquires a delay time that corresponds to the process load, which is detected by the detecting unit, as an expected delay time from the storage unit, and a requesting unit that requests the versatile OS to measure a requested measurement time that is obtained by subtracting the expected delay time, which is acquired by the acquiring unit, from a measurement time that is requested by the application. | 12-24-2009 |
20100023793 | APPARATUS AND METHOD FOR GENERATING A DELAYED CLOCK SIGNAL - An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal. | 01-28-2010 |
20100042863 | MEMORY REGISTER HAVING AN INTEGRATED DELAY-LOCKED LOOP - A memory device is provided. The memory device includes a plurality of memory chips coupled in series, and a register serially coupled to the memory chips. The register includes an integrated delay-locked loop. The memory device may be included in a processing system. Moreover, a method for improving timing budgets in a registered dual in-line memory module (RDIMM) may be implemented using the memory device having a register with an integrated delay-locked loop. | 02-18-2010 |
20100058100 | DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS - A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function. | 03-04-2010 |
20100064163 | DOMAIN CROSSING CIRCUIT OF A SEMICONDUCTOR MEMORY APPARATUS - A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal. | 03-11-2010 |
20100115324 | Memory interface and operating method of memory interface - A memory interface circuit includes a clock signal supply buffer configured to send a system clock signal which is supplied through a reference node, to a memory through a transmission line; a data strobe buffer configured to receive a data strobe signal supplied from the memory; a system clock synchronizing circuit configured to supply a data read from the memory to a logic circuit in synchronization with the system clock signal; and a delay detecting circuit provided at a front stage to the system clock synchronizing circuit and configured to detect a transmission delay from the clock signal supply buffer to the data strobe buffer. The delay detecting circuit generates a phase difference data indicating the transmission delay based on a difference between a phase of the system clock signal and a phase of the data strobe signal outputted from the data strobe buffer, and supplies the phase difference data to the system clock synchronizing circuit. The system clock synchronizing circuit generates a read clock signal by shifting the system clock signal based on the phase difference data, and controls a supply timing at which the data is supplied to the logic circuit, based on the read clock signal. | 05-06-2010 |
20100122104 | APPARATUS AND METHOD FOR INTERFACING TO A MEMORY - In a memory interface, a delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow. Physical design of the solidified drive and receive logic blocks permits simple fit within ASIC place and route flows for increased ease of implementation and ease of reuse. | 05-13-2010 |
20100146320 | Memory Access Time Measurement Using Phase Detector - Methods and systems for determining a memory access time are provided. A first phase skew is measured between a first clock signal used by a memory and a second clock signal used as a reference clock signal. Then, a second phase skew is measured between a delayed version of the first clock signal output by the memory when the memory completes a given read operation and the second clock signal. The memory access time is determined based on the first and second phase skews. | 06-10-2010 |
20100153766 | MEMORY CONTROLLER AND DEVICE WITH DATA STROBE CALIBRATION - A memory controller comprises a DQ path, a DQS path, a delay element, a flip flop, and an adjustment unit. The DQ path receives and passes a data signal, and outputs a delayed data signal. The DQS path receives and passes a data strobe signal. The delay element is coupled to the DQS path, receiving the data strobe signal to generate a compensated data strobe signal having a calibrated latency. The calibrated latency is determined by an adjustment signal. The flip flop is coupled to the data signal path and the delay element, sampling the delayed data signal by the compensated data strobe signal to generate an output data. The adjustment unit generates the adjustment signal according to the output data. The adjustment unit performs a calibration to adjust the adjustment signal, thus the calibrated latency is adjusted. | 06-17-2010 |
20100169696 | PROCESSOR SYSTEM EMPLOYING A SIGNAL ACQUISITION MANAGING DEVICE AND SIGNAL ACQUISITION MANAGING DEVICE - A processor system having a processor core configured to control an external apparatus in accordance with a control algorithm; a signal acquisition managing device configured to receive state signals provided by the apparatus, perform corresponding actions, and generate corresponding synchronized command signals; and a peripheral module structured to receive the synchronized command signals and generate output signals to be processed by the processor core in accordance with the control algorithm. | 07-01-2010 |
20100180141 | METHOD OF DYNAMICALLY ADJUSTING SIGNAL DELAY TIME OF CIRCUIT SYSTEM - A circuit system periodically checks a system-environment monitor value, and then obtains a system-environment monitor value index corresponding to the system-environment monitor value in the environment-adjustment look-up table. Finally, the circuit system adjusts a signal delay time according to a delay adjustment value corresponding to the system-environment monitor value index. | 07-15-2010 |
20100199117 | TIMING SYNCHRONIZATION CIRCUIT WITH LOOP COUNTER - An apparatus for synchronizing an output clock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter. The first timing synchronization circuit is operable to generate a delay to synchronize a reference clock signal representative of the input clock signal with a feedback clock signal representative of the output clock signal responsive a strobe signal. The control logic is operable to generate an enable signal based on the reference clock signal and generate the strobe signal based on the feedback clock signal. The counter is operable to count cycles of the reference clock signal occurring between the enable signal and the strobe signal to generate a loop count for the first timing synchronization circuit. | 08-05-2010 |
20100250995 | SPLIT DELAY-LINE OSCILLATOR FOR SECURE DATA TRANSMISSION - A split delay-line oscillator for secure data transmission is disclosed. In one embodiment, an apparatus for a split delay-line oscillator for secure data transmission includes a first modulator/demodulator block in a first device, the first modulator/demodulator block operable to insert a first variable delay to modulate a frequency of a shared carrier signal passing through the first modulator/demodulator block, and a second modulator/demodulator block in a second device, the second modulator/demodulator block operable to insert a second variable delay to modulate the frequency of the shared carrier signal passing through the second modulator/demodulator block, wherein the first and second devices create a shared secret by contributing data on the frequency-modulated shared carrier signal. | 09-30-2010 |
20100293405 | INTEGRATED CIRCUIT WITH REDUCED ELECTROMAGNETIC INTERFERENCE INDUCED BY MEMORY ACCESS AND METHOD FOR THE SAME - The invention provides an integrated circuit with reduced electromagnetic interference induced by memory access. The integrated circuit includes a random code generator, a request receiver and a memory unit. The random code generator generates a plurality of random codes according to a predetermined delay parameter. The request receiver obtains an input clock signal according to a plurality of data requests and spreads the spectrum of the input clock signal based on the random codes to derive a non-periodic output clock signal. The memory unit accesses image data to be displayed in response to the data requests and the output clock signal. | 11-18-2010 |
20100293406 | METHOD TO CALIBRATE START VALUES FOR WRITE LEVELING IN A MEMORY SYSTEM - A memory controller performs a read test for each of a plurality of memory devices to generate a read delay time of each memory device. There is a prime memory device and a subset of memory devices. For each memory device of the subset, the read delay time for the prime memory device is compared with the read delay time of each memory device of the subset of memory devices to generate a differential delay for each memory device of the subset. For each subset memory device, a write test start time of the prime memory device is combined with a differential delay of each memory device to generate a write test start time for the each memory device. A write test for each memory device uses the write test start time for each subset memory device to generate a write launch time for each subset memory device. | 11-18-2010 |
20110022872 | Apparatus for and method of generating a time reference - In one embodiment, a system is configured to generate a time reference where the system includes a bi-directional loop configured to have a first propagation speed in a first direction and a second propagation speed in a second direction, wherein the first propagation speed is substantially equal to the second propagation speed. In one embodiment, the system further includes a plurality of system elements coupled to the bi-directional loop, wherein each respective system element of the plurality of system elements is configured to determine a time reference common to each as an average arrival time at the respective system element of a first signal transmitted in the first direction over the bi-directional loop and a second signal transmitted in the second direction over the bi-directional loop. | 01-27-2011 |
20110022873 | SYSTEM WITH POWER SAVING DELAY LOCKED LOOP CONTROL - The delay locked loop (“DLL”) delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL is associated to the system clock. This is achieved by adding logic sensing when a DRAM device will not imminently be called upon to output data and when the device has stabilized. Waiting for the DLL delay interval to stabilize before locking the delay interval still allows the DLL to immediately and effectively resume operations when the DLL is needed to synchronize the output of the DRAM device with the system clock. The DLL delay interval can be locked, together with the DLL clock, after the DRAM device is deselected by the chip select control line, after a number of no operation commands have been received, and/or after any command issued to the DRAM device has been completed. | 01-27-2011 |
20110040997 | SYNCHRONIZATION OF CLOCKS IN AUTONOMOUS COMPONENTS OF AN MR SYSTEM AND SYNCHRONOUS EXECUTION OF COMMANDS IN THOSE COMPONENTS - In a device and a method to execute commands in components of an imaging system, in particular of a magnetic resonance tomography system, local clocks in the components are temporally synchronized, commands, including a respective command execution time specification which respectively specifies at which point in time a command should be executed, are sent to the components, the commands are received by the components, commands and command execution time specifications that are received by components are stored in these components, and a stored command is respectively executed when a time indicated by the local clock coincides with the stored command execution time specification regarding the command. | 02-17-2011 |
20110060934 | METHODS AND APPARATUS FOR CLOCK SIGNAL SYNCHRONIZATION IN A CONFIGURATION OF SERIES-CONNECTED SEMICONDUCTOR DEVICES - A system includes a system controller and a configuration of series-connected semiconductor devices. Such a device includes an input for receiving a clock signal originating from a previous device, and an output for providing a synchronized clock signal destined for a succeeding device. The device further includes a clock synchronizer for producing the synchronized clock signal by processing the received clock signal and an earlier version of the synchronized clock signal. The device further includes a device controller for adjusting a parameter used by the clock synchronizer in processing the earlier version of the synchronized clock signal. The system controller has an output for providing a first clock signal to a first device, and an input for receiving a second clock signal from a second device. The second clock signal corresponds to a version of the first clock signal that has undergone processing by a clock synchronizer in at least one of the devices. The system controller further includes a detector for processing the first and second clock signals to detect a phase difference therebetween; and a synchronization controller for commanding an adjustment to the clock synchronizer in at least one of the devices based on the phase difference detected by the detector. | 03-10-2011 |
20110072296 | INFORMATION PROCESSING APPARATUS, DATA RECEPTION DEVICE AND METHOD OF CONTROLLING THE INFORMATION PROCESSING APPARATUS - A clock adjustment circuit delays a phase of a clock signal on the basis of a TAP value so as to output an adjusted clock signal. By synchronizing transmission data with the adjusted clock signal, reception data is generated. A data adjustment circuit delays the transmission data on the basis of a TAP2 value. By synchronizing the delayed transmission data with the adjusted clock signal, adjusted reception data is generated. A data adjustment control circuit generates the TAP2 value on the basis of a result of a comparison between the reception data and the adjusted reception data, and outputs to a clock adjustment control circuit an instruction to update the TAP value. | 03-24-2011 |
20110099409 | DELAYING ONE-SHOT SIGNAL OBJECTS - A device may include a processor to execute a thread. The processor may be further configured to execute a set of wrappers that are called from within the thread to invoke a set of one-shot signal objects to generate delayed signals. Each of the set of wrappers may be configured to detect whether different ones of one-shot signal objects that were invoked from within the thread have generated signals at periodic time intervals, determine a delay to be used for invoking one of the set of one-shot signal objects, and invoke the one of the set of one-shot signal object to generate one of the delayed signals based on the delay when the different ones of one-shot signal objects have generated signals at periodic time intervals. The processor may be further configured to receive the delayed signals generated from the set of one-shot signal objects over a time period. | 04-28-2011 |
20110119518 | METHOD FOR PROVIDING A GUARANTEED PLAYOUT RATE - A method for delivering data to first and second processes comprising: identifying a first process communicatively connected to a first data access port; identifying a second process communicatively connected to a second data access port; identifying a data-throughput requirement of the first process via the first data access port; identifying a current data-throughput being delivered to the first process via the first data access port; identifying a data-throughput difference representing a difference between the data-throughput requirement of the first process and the current data-throughput being delivered to the first process; and delivering data to the first process via the first data access port at a rate that meets the data-throughput requirement at an expense, if necessary, of a data rate delivered to the second process via the second data access port. | 05-19-2011 |
20110119519 | METHOD AND APPARATUS FOR PROVIDING SYMMETRICAL OUTPUT DATA FOR A DOUBLE DATA RATE DRAM - An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal. | 05-19-2011 |
20110126038 | TIME DELAY COMPENSATION IN POWER SYSTEM CONTROL - A method and controller are provided for the compensation of time delays in remote feedback signals in power system control. The method includes converting the time delay into a phase shift and calculating four compensation angles from the phase shift. The optimal compensation angle is determined and applied to the remote feedback signals. A technique of equipping a controller with a global clock is also disclosed. | 05-26-2011 |
20110131439 | Jitter Precorrection Filter in Time-Average-Frequency Clocked Systems - Synchronous circuitry for processing digital data in which the data are filtered to compensate for expected jitter in time-average frequency clock signals. Time-average frequency synthesis circuitry generates internal clock signals of a desired frequency, for example as based on a recovered clock signal from an input data stream, in a manner in which not all periods of the clock signal are of uniform duration. A jitter precorrection filter is inserted into the data path to apply a variable delay to pre-correct for distortion caused by jitter in the clock cycle. In embodiments of the invention using a flying-adder architecture to generate the clock signal, coefficients of the digital filer realizing the jitter precorrection filter are calculated according to the currently-selected oscillator phase and according to a fractional portion of a digital frequency control word. | 06-02-2011 |
20110131440 | SEMICONDUCTOR DEVICE INCLUDING ANALOG CIRCUIT AND DIGITAL CIRCUIT - A semiconductor device includes an analog circuit with a first delay variation in response to a variation in a power supply potential, and a digital circuit with a second delay variation smaller than the first delay variation. The analog circuit is connected to a first power supply potential. The digital circuit includes a detecting circuit detecting a first delay caused by a first circuit connected to the first power supply potential, and a second circuit generating a control signal to control the analog circuit, the second circuit being connected to a second power supply potential whose potential variation is smaller than the first power supply potential. A second delay caused by the second circuit is controlled in correlation to the first delay. | 06-02-2011 |
20110161715 | INFORMATION PROCESSING APPARATUS OR INFORMATION PROCESSING METHOD - According to the present invention, a phase shift of data received by an external device controller is delayed and corrected, and a control signal used for the data load control on the external device controller side is delayed period-by-period. Further, the phase shift is adjusted and then the control signal is adjusted. The adjustment can beneficially be performed very quickly. Moreover, the present invention is also beneficial for preventing a failure to load data. | 06-30-2011 |
20110185215 | Single-Wire Serial Interface - A circuit comprising a single-wire serial interface (SWSI), a delay module coupled to the SWSI and operable to introduce a delay during a data transmission, the delay being dependent on a local clock (LC) associated with the circuit, wherein the delay enables the circuit to synchronize the data transmission with a device coupled to the SWSI based on the LC. | 07-28-2011 |
20110185216 | Time Synchronization Method and System for Multicore System - A time synchronization method and system for a multi-core system are provided. The time synchronization method comprises: establishing at least one clock synchronization domain, and respectively allocating each core to each clock synchronization domain; selecting a core with a lowest load in each clock synchronization domain as a master clock synchronization source in the clock synchronization domain, and selecting the clock synchronization domain having the master clock synchronization source with a lowest load as a master clock synchronization domain, while other clock synchronization domains as slave clock synchronization domains; the master clock synchronization domain sending a synchronization deviation detection message to each slave clock synchronization domain, and calculating a time deviation value; when the time deviation value is greater than a permitted deviation value, the master clock synchronization domain calculating a time adjustment quantity and releasing to each slave clock synchronization domain, making adjustment based on its time adjustment quantity. | 07-28-2011 |
20110202786 | Stalling synchronisation circuits in response to a late data signal - A data processing circuitry for processing data is disclosed. The data processing circuitry comprises: a plurality of synchronisation circuits for capturing and transmitting the data in response to a clock signal and a plurality of combinational circuits arranged between the synchronisation circuits for processing the data, the plurality of synchronisation circuits being arranged in at least two groups; an error detecting circuit for determining if the data input to one of the plurality of synchronisation circuits is stable during a predetermined time and for signalling an error if the data input is not stable, the predetermined time being less than a half cycle of the clock signal; control circuitry responsive to said error detecting circuit signalling said error to transmit a control signal to at least one of said groups of synchronisation circuits that contains a subsequent synchronisation circuit that said synchronisation circuit with said unstable input is configured to transmit said data to; each of said group of synchronisation circuits being configured to respond to receipt of said control signal to stall for a clock cycle and to transmit a stall signal to at least one further group of synchronisation circuits that said group of synchronisation circuits is configured to transmit data to or receive data from; each of said group of synchronisation circuits being configured to respond to receipt of said stall signal provided they have not stalled in a preceding clock cycle to stall for a clock cycle and to transmit a stall signal to said at least one further group of synchronisation circuits. | 08-18-2011 |
20110219256 | SYNCHRONIZATION DEVICES HAVING INPUT/OUTPUT DELAY MODEL TUNING ELEMENTS IN SIGNAL PATHS TO PROVIDE TUNING CAPABILITIES TO OFFSET SIGNAL MISMATCH - Apparatus for synchronizing signals. For memory devices, such as SDRAMs, implementing a synchronization device to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, tuning elements may be provided at various points in the signal path of the synchronization device. The tuning elements are designed to be identical, such that a single design may be used to a signal mismatch that is produced in either direction, using a single design. The tuning elements may be implemented to provide uniformity in the access time through a range of conditions, such as drain voltages and temperatures. | 09-08-2011 |
20110246809 | Synchronization of Converters Having Varying Group-Delays in a Measurement System - An analog-to-digital-converter (ADC) timing engine may simplify the use of Delta-Sigma ADCs by compensating for the group-delay of the ADC. The compensation may render the group-delay corresponding to the ADC largely transparent to the end-user of the ADC. Therefore, multiple ADCs may be easily synchronized with each other, even if they have different group-delays, and they may further be synchronized with other types of ADCs that do not have group-delays. The data from the ADCs may also be synchronized with external events. The ADC timing engine (ATE) may be programmed with a number of parameters to set proper delays taking into account not only the group-delays corresponding to the various ADC, but delays stemming from a variety of other sources. Multiple ATEs may be synchronized with each other to ensure that data acquisition by the participating ADCs is started and/or stopped at the same point in time. | 10-06-2011 |
20110252265 | DELAY CONTROLLER, CONTROL METHOD, AND COMMUNICATION SYSTEM - A delay controller includes an acquiring section that acquires synchronization timings indicating timings when a plurality of controllers, which control via a line a plurality of transmitters that transmit data, synchronously control the transmitters, a determining section that determines a reference synchronization timing serving as a reference for synchronization between the controllers, on the basis of the synchronization timings acquired by the acquiring section, and a synchronization information transmitting section that transmits synchronization information to the controllers, the synchronization information being used when the controllers receive data from each of the transmitters at the reference synchronization timing determined by the determining section. | 10-13-2011 |
20110258475 | Dynamically Calibrated DDR Memory Controller - A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is typically calibrated during a power on the initialization sequence in concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and increasing both device and system yield. An additional embodiment also includes programmably delaying the incoming dqs signal. To compensate for voltage and temperature variations over time during normal operation, a runtime dynamic calibration mechanism and procedure is also provided. | 10-20-2011 |
20110271133 | ADDRESS OUTPUT TIMING CONTROL CIRCUIT OF SEMICONDUCTOR APPARATUS - Various embodiments of a control circuit for controlling an address output timing of a semiconductor device are disclosed. In one exemplary embodiment, the circuit may include: a timing signal generation unit configured to decode operation specification information of a semiconductor device and generate a timing signal by delaying a read command or a write command based on a decoding result of the operation specification information; a storage control signal generation unit configured to generate a storage control signal in response to the read command or the write command; an output control signal generation unit configured to generate an output control signal in response to the timing signal; and a storage/output unit configured to store an address in response to the storage control signal, and output the stored address as a timing-adjusted address in response to the output control signal. | 11-03-2011 |
20110289339 | Semiconductor device - A semiconductor device performs operation in synchronization with a certain clock signal. The semiconductor device includes a control unit for outputting operation control information, a storage unit for storing data, a first operation unit for performing operation on first data in accordance with first operation control information, and a second operation unit for performing operation on second data in accordance with second operation control information. The first operation unit includes a plurality of operation circuits. The number of logic gates constituting the entire operation circuits is m. The second operation unit includes at least one operation circuit in which the number of logic gates is n (n>m). Each of the total delay of the operation unit or the total delay of the operation unit is set at a value equal to or less than the cycle of the clock signal. | 11-24-2011 |
20110320851 | PORT ENABLE SIGNAL GENERATION FOR GATING A MEMORY ARRAY DEVICE OUTPUT - A method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock signal; generating a programmable trailing edge clock signal derivation of the input dynamic clock signal, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; and gating the generated programmable leading and trailing edge clock signal derivations with a static input enable signal so as to generate the port enable signal such that, when inactive, the port enable signal prevents early memory array data from being coupled to the output node. | 12-29-2011 |
20120047388 | Adjustable Byte Lane Offset For Memory Module to Reduce Skew - Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for such skew, an on-chip delay is added to the data out paths of those bits in the byte lane with otherwise would arrive early to their destinations. Such on-chip delay is provided delay circuits preferably positioned directly before the output buffers/bond pads of the integrated circuit or module. By intentionally delaying some of the outputs from the integrated circuit or module, external skew is compensated for so that all data in the byte lane arrives at the destination at substantially the same time. In a preferred embodiment, the delay circuits are programmable to allow the integrated circuit or module to be freely tailored to environments having different skew considerations, such as different styles of connectors. | 02-23-2012 |
20120047389 | NON-VOLATILE MEMORY DEVICES FOR OUTPUTTING DATA USING DOUBLE DATA RATE (DDR) OPERATIONS AND METHODS OF OPERATING THE SAME - A non-volatile memory device is operated by outputting data in response to an alternating sequence of first and second edges of a read control signal, respectively. A determination is made whether the read control signal and a write control signal are in synchronization at one of the first edges. Output of the data is stopped at the second edge that follows the one of the first edges of the read control signal if the read control signal and the write control signal are in synchronization at the one of the first edges. | 02-23-2012 |
20120072759 | Timing Error Correction System and Method - A timing error correction method used at the transmitting end in high-speed serial data transmission system comprises inputting a predefined parallel data training sequence and a clock signal, converting the training sequence into serial data, counting the number of the rising or falling edges of the serial data within a certain period, sending an adjustment signal for adjusting the time delay of the clock signal, obtaining a reasonable serialization timing, so that the number of the rising edges or falling edges of the serial data being equal to a predefined correct number. The corresponding timing error correction system comprises a data path, an adjustable delay clock path, a serialization unit for converting the parallel data into serial data, a driver unit, and a counting judging unit for counting the number of the rising or falling edges of the serial data and sending an adjustment signal to the adjustable delay clock path so as to control the timing of the serialization unit. | 03-22-2012 |
20120173914 | Methods and Apparatus for Trimming of CDR Clock Buffer Using Histogram of Clock-Like Data Pattern - Methods and apparatus are provided for trimming of one or more CDR clock buffers using a histogram of clock-like data patterns. One or more clock buffers in a clock and data recovery system are trimmed by receiving a first transmitted clock-like data pattern in a reduced rate mode, wherein the first transmitted clock-like data pattern is transmitted using a first rate mode and wherein the reduced rate mode divides the first rate mode by an integer value that is greater than one; locking the clock and data recovery system using the received version of the first transmitted clock-like data pattern in the reduced rate mode; receiving a second transmitted clock-like data pattern, wherein the second transmitted clock-like data pattern has a run-length that is an integer division of a run-length of the first transmitted clock-like data pattern, wherein the integer division is greater than one; and adjusting a phase of the one or more clock buffers using the second transmitted clock-like data pattern. The first and second transmitted clock-like data patterns can be transmitted by a local transmitter in a loopback mode. Generally, the received version of the first transmitted clock-like data pattern has edges that correspond to only positive or negative edges of the first transmitted clock-like data pattern. | 07-05-2012 |
20120198264 | PSEUDO SYNCHRONOUS SERIAL INTERFACE SYNCHRONIZATION METHOD - Primary serial interface logic is synchronized by cycling through a plurality of delays upon power up of the serial interface until a synchronization bit pattern is located. A minimum delay and a maximum delay are determined for the primary serial interface logic, and a delay is set to a midpoint between the minimum delay and the maximum delay. Secondary serial interface logic is synchronized by cycling through a plurality of delays until the output of the secondary serial interface logic equals the output of the primary serial interface logic. A minimum delay and a maximum delay are determined for the secondary serial interface logic, and a delay is set to a midpoint between the minimum delay and the maximum delay. | 08-02-2012 |
20120198265 | CIRCUIT - An embodiment of a circuit comprises an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer. | 08-02-2012 |
20120204055 | SYSTEM AND METHOD FOR MULTIPLE BACKPLANE TIME SYNCHRONIZATION - A system and method for synchronizing multiple backplanes within an information handling system are disclosed. An information handling system includes a first controller that may be operable to generate a time command at a predetermined time interval. A backplane including a second controller is communicatively coupled to the first controller. The second controller may be operable to receive the time command from the first controller and calculate a skew for the time command based at least on a location of the backplane. The second controller may further be operable to adjust a time domain of the backplane based on the calculated skew for the time command to synchronize the backplane. | 08-09-2012 |
20120204056 | Power Signature Obfuscation - A data processing apparatus is configured to perform a data processing operation on at least one data value in response to a data processing instruction. The data processing apparatus comprises a delay unit situated on a path within the data processing apparatus, wherein the delay unit is configured to apply a delay to propagation of a signal on the path and propagation of that signal forms part of the data processing operation. The data processing apparatus is configured to determine a result of the data processing operation at a predetermined time point, wherein the predetermined time point following an initiation of the data processing operation by a predetermined time interval. The delay unit is configured such that a time for the data processing operation to be performed plus the delay is less than the predetermined time interval. | 08-09-2012 |
20120239961 | SYNCHRONOUS DATA PROCESSING SYSTEM AND METHOD - A synchronous data processing system includes a memory module to store data and a memory controller coupled to the memory module. The memory controller includes a clock inverter to receive an input clock signal and to transmit an inverted clock signal to the memory module. The inverted clock signal incurs a first propagation delay prior to reaching the memory module as a memory clock signal. A write data buffer is coupled to the memory module. The write data buffer transmits data to the memory module in response to the input clock signal. An asynchronous first-in-first-out (ASYNC FIFO) buffer is coupled to the memory module. The ASYNC FIFO buffer reads data from the memory module in response to a feedback signal generated by feeding back the memory clock signal to the ASYNC FIFO buffer. | 09-20-2012 |
20120254650 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a synchronized signal generation circuit, a serial-to-parallel data conversion unit and a data storage region. The synchronized signal generation unit outputs one of a data input/output strobe signal and a delay locked clock signal as synchronized signals in response to a control signal in a write operation. The serial-to-parallel data conversion unit converts serial data into parallel data in response to the synchronized signals. The parallel data is stored in the data storage region. | 10-04-2012 |
20120266009 | INFORMATION PROCESSING APPARATUS OR INFORMATION PROCESSING METHOD - If data received by the an information processing apparatus from an external device is delayed by one cycle or more with respect to a clock of the information processing apparatus, the information processing apparatus may require an additional process for adjusting a data latch timing. | 10-18-2012 |
20120278647 | Reducing Memory Used To Store Totals In Static Timing Analysis - A system and a method are disclosed for reducing memory used in storing totals during static timing analysis. Totals are stored at various points along paths analyzed in static timing analysis. Some totals may not be merged for reasons including differing clock re-convergence pessimism removal (CRPR) dominators, exceptions, or clocks. Totals at a point may be stored in a super-tag mapping table and replaced at the point with a super-tag. The super-tag includes a super-tag ID referencing the totals stored in the super-tag mapping table. The super-tag also includes a time delay value. The time delay value allows the super-tag ID to be reused in other super-tags at other points while still storing total time delays at the other points. Therefore, the memory used to store totals is reduced in many situations. | 11-01-2012 |
20120331326 | APPARATUS AND METHOD FOR ADVANCED SYNCHRONOUS STROBE TRANSMISSION - An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a core clocks generator, and a synchronous strobe driver. The resistor network is configured to provide a ratio signal that indicates an amount to advance a synchronous data strobe associated with a data group. The core clocks generator is coupled to the ratio signal, and is configured to advance a data strobe clock by the amount. The synchronous strobe driver is configured to receive the data strobe clock, and is configured to employ the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the amount. | 12-27-2012 |
20120331327 | OPTIMIZED SYNCHRONOUS STROBE TRANSMISSION MECHANISM - An apparatus that compensates for misalignment on a synchronous data bus, including a resistor network, a transmitting device, and a receiving device. The resistor network indicates an amount to advance a synchronous data strobe associated with a data group. The transmitting device has a core clocks generator and a synchronous strobe driver. The core clocks generator advances a data strobe clock by the amount. The synchronous strobe driver employs the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe is advanced also by the amount. The receiving device has a composite delay element and delay-locked loops (DLLs). The composite delay element equalizes delay paths within the receiving device, where the delay paths correspond to the synchronous data strobe that is received from the transmitting device. | 12-27-2012 |
20120331328 | APPARATUS AND METHOD FOR DELAYED SYNCHRONOUS DATA RECEPTION - An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network and a delay-locked loop (DLL). The resistor network is configured to provide a ratio signal that indicates an amount to delay a data bit signal associated with a data group. The DLL is coupled to the ratio signal, and is configured generate a delayed data bit signal, where the DLL adds the amount of delay to the data bit signal to generate the delayed data bit signal. | 12-27-2012 |
20120331329 | OPTIMIZED SYNCHRONOUS DATA RECEPTION MECHANISM - An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a composite delay element, and delay-locked loops (DLLs). The resistor network is configured to provide a ratio signal that indicates an amount to delay data bit signals associated with a data group. The composite delay element is configured to equalize delay paths within a receiving device, where the delay paths correspond to a data strobe signal that is received from a transmitting device. The DLLs are coupled to the ratio signal and disposed within the receiving device, and are configured to generate delayed data bit signals, where the DLLs add the amount of delay to the data bit signals to generate the delayed data bit signals. | 12-27-2012 |
20120331330 | PROGRAMMABLE MECHANISM FOR OPTIMIZING A SYNCHRONOUS DATA BUS - An apparatus including a JTAG interface, synchronous bus optimizer, core clocks generator, synchronous strobe driver, and a DLL. The JTAG interface receives control information indicating a first amount to advance a synchronous data strobe associated with a first data group and a second amount to delay a data bit signal associated with a second data group. The synchronous bus optimizer receives the control information, and develops a first value on a first ratio bus that indicates the first amount and a second value on a second ratio bus that indicates the second amount. The core clocks generator advances a data strobe clock by the first amount. The synchronous strobe driver employs the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the first amount. The DLL generates a delayed data bit signal, delayed by the second amount. | 12-27-2012 |
20130031401 | Systems, Methods, and Computer Program Products Providing Output Sample Frequency Determinism - A computer-implemented method for performing processing including setting a timer associated with a first processing event, scheduling an expected time for the processing event using wall clock time, at the timer, using the expected time to calculate a delay associated with the timer, performing the first processing event in response to the timer, and setting a subsequent timer to compensate for the delay. | 01-31-2013 |
20130080816 | OPERATING SYSTEM SYNCHRONIZATION IN LOOSELY COUPLED MULTIPROCESSOR SYSTEM AND CHIPS - Methods, systems and devices configured to add synchronization to the entry and exit from low power modes in asynchronous operating systems on a multiprocessor system. A synchronizing agent tracks the requested sleep and wake up times of the different asynchronous operating systems executing on different cores of the same system on chip or multicore processor. The sleep/wake up times of some cores/operating systems may be delayed in order to synchronize the sleep/wake up times of two or more of the asynchronous operating systems executing on the multiprocessor system. | 03-28-2013 |
20130080817 | Systems and Methods of Network Synchronization - An exemplary method of synchronizing a master clock and a slave clock comprises transmitting a plurality of packets between a master device and a slave device, calculating a first skew between a first pair of the plurality of packets at the slave device and a second skew between the first pair at the master device, calculating a ratio between the first skew and the second skew, providing a slave clock frequency correction to the slave device, calculating a first packet trip delay using a time that the master device initiates sending a packet to the slave device, a time the master device receives a response from the slave device, a corrected time the slave device receives the packet, and a corrected time the slave device initiates sending the response, calculating a first offset based on the first packet trip delay, and providing the first offset to the slave device. | 03-28-2013 |
20130111254 | Multi-Path Power Switch Scheme for Functional Block Wakeup | 05-02-2013 |
20130124904 | MEMORY SUBSYSTEM AND METHOD - One embodiment of the present invention sets forth an interface circuit configured to combine time staggered data bursts returned by multiple memory devices into a larger contiguous data burst. As a result, an accurate timing reference for data transmission that retains the use of data (DQ) and data strobe (DQS) signals in an infrastructure-compatible system while eliminating the cost of the idle cycles required for data bus turnarounds to switch from reading from one memory device to reading from another memory device, or from writing to one memory device to writing to another memory device may be obtained, thereby increasing memory system bandwidth relative to the prior art approaches. | 05-16-2013 |
20130159759 | Signal Conditioning By Combining Precursor, Main, and Post Cursor Signals Without A Clock Signal - Embodiments of an apparatus for signal conditioning, a serial data interface, and a method for a programmable delay filter are disclosed. In an embodiment of an apparatus for signal conditioning, a wave shaping circuit has a precursor signal, a post cursor signal, and a main signal combined to provide an output signal. The precursor signal, the post cursor signal, and the main signal are provided for combination independently of a clock signal. The main signal is delayed relative to the precursor signal, and the post cursor signal is delayed relative to the main signal. | 06-20-2013 |
20130159760 | Synchronizing Compute Node Time Bases In A Parallel Computer - Synchronizing time bases in a parallel computer that includes compute nodes organized for data communications in a tree network, where one compute node is designated as a root, and, for each compute node: calculating data transmission latency from the root to the compute node; configuring a thread as a pulse waiter; initializing a wakeup unit; and performing a local barrier operation; upon each node completing the local barrier operation, entering, by all compute nodes, a global barrier operation; upon all nodes entering the global barrier operation, sending, to all the compute nodes, a pulse signal; and for each compute node upon receiving the pulse signal: waking, by the wakeup unit, the pulse waiter; setting a time base for the compute node equal to the data transmission latency between the root node and the compute node; and exiting the global barrier operation. | 06-20-2013 |
20130179720 | MULTIPLE PROCESSOR DELAYED EXECUTION - A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input. | 07-11-2013 |
20130254584 | SEQUENCER SYSTEM AND CONTROL METHOD THEREFOR - A sequencer system includes a plurality of units, a backplane on which the units are mounted, bus communication lines for data transmission and reception among the units, a clock generation unit that generates a fixed-cycle clock signal having an arbitrary cycle, and an electric signal line provided separately from the bus communication lines, to transfer the fixed-cycle clock signal from the clock generation unit to the units via the backplane. Each of the units includes a processor that controls the unit, and an interrupt-signal control unit that generates an interrupt signal corresponding to the fixed-cycle clock signal. The processor uses the interrupt signal to synchronize control timings of the units. | 09-26-2013 |
20130297961 | Systems And Methods For DQS Gating - Systems and methods for timing read operations with a memory device are provided. A timing signal is received from the memory device at a gating circuit. The timing signal is passed through as a filtered timing signal during a gating window. The gating window is configured to open the gating window based on a control signal and to close the gating window based on a falling edge of the timing signal. The falling edge is determined based on a counter that is triggered to begin counting by the control signal. The control signal is generated at a timing control circuit after receiving a read request from a memory controller. The timing control circuit is configured to delay generation of the control signal to cause the gating window to open during a preamble portion of the timing signal. | 11-07-2013 |
20130311814 | CONSTANT FREQUENCY ARCHITECTURAL TIMER IN A DYNAMIC CLOCK DOMAIN - Implementations of the present disclosure involve an apparatus and/or method for providing a constant frequency timer signal for a microprocessor that operates with varying core clock signals. The apparatus and/or method utilizes a code generator, such as a gray code generator, operating on a reference clock signal that allows the constant frequency timer signal to be either faster or slower than the core clock frequency. More particularly, the apparatus and/or method may compute a difference between previous gray code samples and add the calculated difference to a software visible reference clock signal such that constant frequency timer signal may be faster or slower than the core clock signal. Through the use of the apparatus and/or method, a core clock signal may be reduced as needed to provide operational power savings to the microprocessor and the computing system employing the techniques described herein, while maintaining synchronization between the executing programs of the computing system. | 11-21-2013 |
20130346785 | CALIBRATION FOR SOURCE-SYNCHRONOUS HIGH FREQUENCY BUS SYNCHRONIZATION SCHEMES - Embodiments provide bus synchronization system including a source module, a plurality of destination modules, and a data alignment controller. The source module is configured to synchronize a plurality of data segments of a data bus with a source clock signal, and transmit respective synchronized data segments to individual destination modules. The source module is further configured to transmit the source clock signal to the destination modules contemporaneously with the synchronized data segments. The source module thereafter receives feedback clock signals from the individual destination modules, the feedback clock signals being delayed versions of the source clock signal. The data alignment controller adjusts an output delay time for the individual destination modules, based on the received feedback clock signals, to temporally align output signals of the destination modules. | 12-26-2013 |
20140013149 | Dynamically Calibrated DDR Memory Controller - A method for calibrating a DDR memory controller is described. The method provides an optimum delay for a core clock delay element to produce an optimum capture clock signal. The method issues a sequence of read commands so that a delayed version of a dqs signal toggles continuously. The method delays a core clock signal to sample the delayed dqs signal at different delay increments until a 1 to 0 transition is detected on the delayed dqs signal. This core clock delay is recorded as “A.” The method delays the core clock signal to sample the core clock signal at different delay increments until a 0 to 1 transition is detected on the core clock signal. This core clock delay is recorded as “B.” The optimum delay value is computed from the A and B delay values. | 01-09-2014 |
20140075235 | Switch for Clock Synchronization Over A Switched Fabric - Devices and methods for synchronizing devices over a switched fabric. A switch receives a request packet from a device, transmits a completion packet to the device, determines an in-switch delay, and stores the in-switch delay. Another switch receives a packet from a first device, forwards the packet to a second device, determines an in-switch delay of the packet, and stores the in-switch delay. Storing of in-switch delays may include adding an in-switch delay to values in one or more transaction delay fields of a packet. Storing of in-switch delays may include storing the delays in a storage element of a switch. In-switch delay may be determined as a difference between a receiving time corresponding to reception of a packet and a forwarding or transmittal time corresponding to forwarding or transmitting of a packet. | 03-13-2014 |
20140082397 | EMBEDDED MULTIMEDIA CARD USING UNIDIRECTIONAL DATA STROBE SIGNAL, HOST FOR CONTROLLING THE SAME, AND RELATED METHODS OF OPERATION - An embedded multimedia card (eMMC) comprises a clock channel configured to receive a clock signal from a host, a command channel configured to receive a command from the host, a plurality of data channels configured to transmit data to the host, a data strobe channel configured to transmit a data strobe signal synchronized with the data to the host, and a data strobe control unit configured to selectively enable or generate the data strobe signal according to a protocol control signal. | 03-20-2014 |
20140082398 | EMBEDDED MULTIMEDIA CARD (eMMC), HOST CONTROLLING eMMC, AND METHOD OPERATING eMMC SYSTEM - An embedded multimedia card (eMMC) is provided. The eMMC includes a clock channel receiving a clock output from a host, data channels receiving data signals from the host, and a command channel receiving a SWITCH command including delay offset values from the host so as to adjust a delay of at least one of the data signals, which are received, in response to the delay offset values. | 03-20-2014 |
20140082399 | DATA BUS PART AND METHOD FOR SYNCHRONIZING DATA BUS PARTS - A data bus part ( | 03-20-2014 |
20140089717 | AD-HOC SYNCHRONIZATION OF INDUSTRIAL CONTROL NETWORKS - A method and apparatus are disclosed to provide ad-hoc synchronization in industrial networks between a programmable logic controller and each I/O device without any specific protocol extensions or distributed clock scheme. An embodiment of an industrial control network comprising a Programmable Logic Controller (PLC), a network coupled to the PLC, and a plurality of networked input/output (I/O) devices coupled to the network is provided. Each I/O device comprises: inputs coupled to the network to receive data from the PLC as device input data; and outputs coupled to the network to transmit output data from the I/O device to the PLC. The embodiment further comprises a programmable timer initiating an I/O cycle for the device on a periodic basis. The I/O device is operable to determine a first time period starting at the time at which specific output data arrives from the PLC and ending when the period of the timer ends. The first time period is compared to a predetermined time period. The I/O device is operable to adjust the period of the timer such that the first period approaches the predetermined time period and ad-hoc synchronization is provided between production time of the PLC and timing of the I/O device. | 03-27-2014 |
20140157035 | Bit-Timing Symmetrization - A bus interface, for allowing a plurality of devices to communicate with one another via the bus, includes a bit timing symmetrization component for symmetrizing the bit stream. For an incoming bit stream, the bit timing symmetrization component further includes an input delay filter for delaying recessive to dominant edges for a given received bit stream and sampling the delayed input signal at the sample point. In one embodiment, bit timing synchronization may still be performed with the undelayed recessive to dominant edges. For an outgoing bit stream, the bit timing symmetrization component transmits a recessive bit, that followed a previously transmitted dominant bit, before the start of the next bit time, and transmits a dominant bit, that followed a previously transmitted recessive bit, with a delay of a configurable amount of time. | 06-05-2014 |
20140181568 | INTERFACE FOR CONTROLLING THE PHASE ALIGNMENT OF CLOCK SIGNALS FOR A RECIPIENT DEVICE - Interface circuitry transmitting transactions between an initiator and a recipient includes: a clock input receiving a clock signal; a transaction input receiving transactions; clock outputs for outputting the clock signal; transaction outputs outputting the transactions to the recipient; and synchronising circuits clocked by the clock signal and transmitting the transactions to the transaction output in response to the clock signal. A controllable delay circuit is provided between the clock input and the synchronising circuits. A further synchronising circuit configured to provide a similar delay. Phase detection circuitry is arranged to detect alignment of the received clock signals. Calibration control circuitry adjusts a delay of the controllable delay circuit during calibration until the phase detection circuitry detects alignment. The calibration control circuitry controls the controllable delay circuit to generate a delay to the clock signal in dependence upon the delay that generated the alignment detected during calibration. | 06-26-2014 |
20140208147 | APPARATUS AND METHOD FOR LOCALLY OPTIMIZING SOURCE SYNCHRONOUS DATA STROBES - An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a bit lag control element and a synchronous lag receiver. The bit lag control element is configured to measure a propagation time beginning with assertion of a strobe and ending with assertion of a first one of a plurality of radially distributed strobes corresponding to the strobe, and is configured to generate a value on a lag bus that indicates the propagation time. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive the first one of the plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the propagation time. | 07-24-2014 |
20140208148 | AUTOMATIC SOURCE SYNCHRONOUS BUS SIGNAL ALIGNMENT COMPENSATION MECHANISM - An apparatus including a Joint Test Action Group (JTAG) interface and a bit lag control element. The JTAG interface receives information that indicates an amount to adjust a propagation time. The bit lag control element measures the propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and generates a value indicating an adjusted propagation time. The bit lag control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control selects one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and generates a second value indicating the propagation time. The adjust logic adjusts the second value by the amount prescribed by the JTAG interface to yield a third value. The gray encoder gray encodes the third value to generate the value on the lag bus. | 07-24-2014 |
20140208149 | APPARATUS AND METHOD FOR DYNAMICALLY ALIGNED SOURCE SYNCHRONOUS RECEIVER - An apparatus including a synchronous lag receiver that receives one of a plurality of radially distributed strobes and a data bit, and that delays registering of the data bit by a propagation time. The synchronous lag receiver has a first plurality of matched inverters, a first mux, and a bit receiver. The first plurality of matched inverters generates successively delayed versions of the data bit. The first mux receives a value on a lag bus that indicates the propagation time, and selects one of the successively delayed versions of the data bit that corresponds to the value. The bit receiver receives the one of the successively delayed versions of the data bit and one of a plurality of radially distributed strobe signals, and registers the state of the one of the successively delayed versions of the data bit upon assertion of the one of a plurality of distributed strobe signals. | 07-24-2014 |
20140258764 | TIMING SYNCHRONIZATION CIRCUIT WITH LOOP COUNTER - An apparatus for synchronizing an output dock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter. The first timing synchronization circuit is operable to generate a delay to synchronize a reference clock signal representative of the input clock signal with a feedback dock signal representative of the output clock signal responsive a strobe signal. The control logic is operable to generate an enable signal based on the reference clock signal and generate the strobe signal based on the feedback clock signal. The counter is operable to count cycles of the reference clock signal occurring between the enable signal and the strobe signal to generate a loop count for the first timing synchronization circuit. | 09-11-2014 |
20140289550 | Integrated Clock Architecture for Improved Testing - A computer system includes a first on-chip controller and a second on-chip controller, both connected to a control element. In normal operation, the first and second on-chip controllers operate in different clock domains. During testing, the control element causes each on-chip controller to generate a substantially similar clock signal. The substantially similar clock signals are used to test substantially similar test circuitry connected to each on-chip controller, thereby reducing overhead associated with testing. A delay may be incorporated into the path of the clock signal of one of the on-chip controllers to reduce instantaneous power draw during testing. | 09-25-2014 |
20140304543 | FABRIC MULTIPATHING BASED ON DYNAMIC LATENCY-BASED CALCULATIONS - In one embodiment, a system for determining latency in paths includes logic integrated with and/or executable by a processor, the logic being adapted to synchronize clocks of two devices connected via two or more link aggregation (LAG) ports and/or multiple devices within paths through a network fabric, determine a transit delay for each LAG port and/or path, store the transit delay for each LAG port to a LAG structure along with an identifier for the LAG port and/or for each path to an equal cost multi-path (ECMP) structure along with an identifier of the path, sort the LAG ports according to each LAG port's transit delay and mark a LAG port having the lowest latency, and sort the paths according to each path's transit delay and mark a path having the lowest latency, wherein each path has an equal path cost factor. | 10-09-2014 |
20140344612 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE TESTING METHOD, AND DATA PROCESSING SYSTEM - To provide a semiconductor device including an interface chip and a core chip and a measurement-target signal line and a reference signal line each including a through silicon via provided in the core chip and electrically connecting the interface chip and the core chip. The interface chip outputs a test clock generated by a first signal generation circuit to the core chip. The core chip includes a second signal generation circuit that generates a predetermined measurement signal from the test clock, and outputs the predetermined measurement signal to the measurement-target signal line and the reference signal line in a simultaneous manner. Further, the interface chip detects a phase difference of a plurality of predetermined measurement signals input via the measurement-target signal line and the reference signal line by an operational amplifier, and outputs a test result to a determination circuit. | 11-20-2014 |
20140365809 | SEMICONDUCTOR CIRCUIT APPARATUS AND ELECTRONIC APPARATUS - A semiconductor circuit apparatus includes a controller configured to output a control signal, an outputting part configured to output the control signal outside of the semiconductor circuit apparatus, a condition holding part configured to hold a generating condition and an output condition of a trigger signal, a trigger signal generator configured to generate the trigger signal, if the control signal satisfies the generating condition, a delay controller configured to give a delay to the trigger signal based on the output condition, and a selector configured to be disposed between the controller and the outputting part and to selectively output the trigger signal delayed at the delay controller to the outputting part instead of the control signal output from the controller based on the output condition. | 12-11-2014 |
20150012773 | INFORMATION PROCESSING APPARATUS AND DISTRIBUTION METHOD - An apparatus transmits data to terminal devices. The apparatus includes a storage unit, a transmitting unit, an obtaining unit, a calculating unit, and a controlling unit. The storage unit stores time differences between times clocked by the terminal devices and a time clocked by the apparatus. The transmitting unit transmits the data to the terminal devices. The obtaining unit obtains information indicating a time the terminal device has received the data. The calculating unit calculates a delay amount of a path to the terminal device, by using a subtraction result between a time the transmitting unit transmitted the data and the time indicated by the obtained information, and the stored time difference. The controlling unit identifies a delay amount difference of the calculated delay amounts. The controlling unit further controls a data amount transmitted/received to/from the terminal devices in accordance with the identified delay amount difference. | 01-08-2015 |
20150106647 | Method and a Device for Maintaining a Synchronized Local Timer Using a Periodic Signal - A method is provided for maintaining a synchronized local timer by using a periodic signal which comprises: providing a value of a clock cycle, and values for a first and second timer-parameters, wherein the first timer-parameter is less than the clock cycle value and the second timer-parameter is higher therefrom; providing values for a first (“a”) and second (“b”) arbitration parameters associated with the first and second timer-parameters respectively; upon receiving a periodic signal, adding to the local timer, at least once the first and/or the second timer-parameter, so that on average over one second, the first timer-parameter is added “a” times and the second timer-parameter is added “b” times, thereby ensuring that a value of the local timer essentially overlaps the period frequency of the periodic signal; upon receiving a subsequent periodic signal, setting the value of the local timer to a propagation delay of the periodic signal. | 04-16-2015 |
20150121116 | APPARATUS AND METHOD TO RECOVER A DATA SIGNAL - Embodiments of the present invention disclose an apparatus and method for recovering a data signal in a digital transmission. A computer processor receives a data signal from a data signal input wire. The computer processor receives an external clock signal. The computer processor samples a binary bit of the data signal multiple times per clock cycle. The computer processor determines, for each sampling group, a sample and a quality measurement. The computer processor stores, for each sampling group, the sample and the quality measurement into a set of memory elements. The computer processor stores the sample from each sampling group into a first and a second delay chain. The computer processor determines a current sampling point. The computer processor transmits output corresponding to a content of the current sampling point to a data signal output wire. | 04-30-2015 |
20150121117 | SIGNAL CONTROL CIRCUIT, INFORMATION PROCESSING APPARATUS, AND SIGNAL CONTROL METHOD - An EVEN component selecting unit and an ODD component selecting unit acquire a first signal from a DQ signal based on a rising edge of a DQS signal and a second signal from the DQ signal based on a falling edge of the DQS signal. Variable delay adding units give the first signal a first delay based on a phase difference between an internal clock signal and the rising edge of the DQS signal and give the second signal a second delay based on a phase difference between the internal clock signal and the falling edge of the DQS signal. Data capturing units capture, based on the internal clock signal, data from the first signal to which the first delay is given and the second signal to which the second delay is given. | 04-30-2015 |
20150143155 | DATA STORAGE APPARATUS - A data storage apparatus includes a controller including a controller input/output unit suitable for receiving a ready/busy delay signal and generating a ready/busy output signal in response to a first control signal, and a memory chip including a memory input/output unit suitable for receiving a chip enable delay signal and generating a chip enable output signal in response to a second control signal. The ready/busy delay signal and the chip enable delay signal are transmitted through a substantially same transmission line. | 05-21-2015 |
20150293557 | DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS - A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal. | 10-15-2015 |
20150309529 | MEMORY MIRRORING - Memory system enabling memory mirroring in single write operations. The memory system includes a memory channel which can store duplicate copies of a data element into multiple locations in the memory channel. The multiple locations are disposed in different memory modules and have different propagation times with respect to a data signal transmitted from the memory controller. In a write operation, the relative timings of the chip select, command and address signals among the multiple locations are adjusted according to the data propagation delay. As a result, a data element can be written into the multiple locations responsive to a data signal transmitted from the memory controller in a single transmission event. | 10-29-2015 |
20150346761 | COMMUNICATION APPARATUS AND METHOD FOR CONTROLLING COMMUNICATION APPARATUS - There is provided a communication apparatus. A communication unit transmits data to a communication module, which communicates with an external device, according to a clock signal, and receives data from the communication module in accordance with a timing corresponding to a timing signal generated by delaying the clock signal. An adjustment unit adjusts an amount of the delay. A control unit controls the communication unit to repeatedly perform first processing for transmitting a first command to the communication module, second processing for receiving a first response that is sent from the communication module, and third processing for transmitting a packet to the communication module according to the first response. In a predetermined mode, the control unit controls the communication unit to perform processing for transmitting data of the packet regardless of contents of the first response. | 12-03-2015 |
20150355673 | METHODS AND SYSTEMS WITH DELAYED EXECUTION OF MULTIPLE PROCESSORS - A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input. | 12-10-2015 |
20160133309 | CIRCUITS AND METHODS FOR DQS AUTOGATING - In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer. The method includes, after a period when the values of both the first and second components are at a first logic state, but before receiving a burst of clock edges in the differential strobe signal, detecting a transition in the first component from the first logic state to a second logic state, and in response to the detected transition, asserting an enable signal. The method further includes receiving, by a gating logic block, the enable signal and the output of the first buffer, and, when the enable signal is asserted, un-gating the output of the first buffer. | 05-12-2016 |
20160139625 | DISTRIBUTED TIMER SUBSYSTEM ACROSS MULTIPLE DEVICES - Multiple ARM devices, each having multiple processing elements, linked together by an interconnect to form a coherent memory fabric in which each device has access to all of the processing elements located on all of the devices that are part of the coherent memory fabric. In order to comply with the ARM architecture, the system must have a global timer that is accessible to all of the ARM devices so that each of the devices can maintain the same timer value. The devices, systems, and methods disclosed herein provide for initial synchronization between multiple ARM devices that are joined together to form a coherent memory fabric. The initial synchronization is achieved by determining an offset between the timers of each ARM device and then minimizing the offset. The synchronization may be periodically checked and adjusted, as necessary, to maintain proper synchronization. | 05-19-2016 |
20160139626 | REAL TIME PROTOCOL GENERATION - A storage device may include a memory; and a controller. The controller may be configured to: maintain, for each respective type of command segment of a plurality of types of command segments, a respective timer of a plurality of timers that indicates an amount of time elapsed since the controller last output a command segment of the respective type of command segments to the memory; determine, based on the plurality of timers, whether a command segment of a particular type of command segment of the plurality of types of command segments may be output to the memory at a current time; and responsive to determining that the command segment of the particular type of command segment may be output at the current time, permit output of the command segment of the particular type of command segment to the memory at the current time. | 05-19-2016 |
20160147250 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor package may include a first die, a second die disposed adjacent to the first die, and configured to share an address with the first die. The semiconductor package may include a first address pin included with the first die, and configured for receiving the address. The semiconductor package may include a second address pin included with the second die, and configured for receiving the address. The first die and the second die may output data corresponding to the address. Timings of the address in the first die and the second die may be aligned according to delay signals applied from a controller. | 05-26-2016 |
20160170439 | METHOD AND DEVICES FOR TIME TRANSFER USING PEER-TO-PEER TRANSPARENT CLOCKS | 06-16-2016 |
20160170441 | FEED-FORWARD TIME TRANSFER MECHANISM FOR TIME SYNCHRONIZATION | 06-16-2016 |