| Entries |
| Document | Title | Date |
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| 20080201593 | Storage control device - The storage control device of the present invention reduces the power consumption amount by stopping the transmission of power to enclosures that are not accessed. A plurality of additional enclosures are switch-connected via backend switches to a base enclosure. Drives that have not been accessed for a predetermined time or more undergo spin-down. When all of the drives in the enclosure enter a spin-down state, the supply of power from the power supply in the enclosure to the respective drives is stopped. The base enclosure that manages the system constitution of the storage control device turns OFF the switch connected to the enclosure when all of the drives in a certain enclosure have spun down. The transmission of power to this enclosure is accordingly stopped. | 08-21-2008 |
| 20080201594 | ELECTRONIC APPLIANCE, METHOD OF SETTING RETURN INTERFACE, RETURN COMMUNICATION METHOD AND COMPUTER PROGRAM - An electronic appliance designed for low power consumption mode having a plurality of hardware interfaces mounted thereon for communication with an external device is disclosed. The electronic appliance includes a return interface setting part configured to variably set a part of the plurality of the hardware interfaces as a return interface that waits for receiving a return signal. | 08-21-2008 |
| 20080229132 | Image Processing Apparatus and Control Method, and Program and Storage Medium Thereof - An object is to provide an image processing apparatus which can reduce power consumption during the power saving standby mode. The starting factor monitor unit and the power saving standby mode voltage control unit are driven with the USB bus power can be supplied during a shift to the power saving standby mode and the starting factor monitor unit and the power saving standby mode voltage control unit are driven by voltage from the main power supply when the USB bus power cannot be supplied during a shift to the power saving standby mode. | 09-18-2008 |
| 20080229133 | POWER REDUCTION DEVICE FOR DATA BACKUP - A power reducer for data backup stops a power supply one after another for each memory whose backup has been completed, thereby reducing power consumption for battery during the backup lengthening a data backup time. The power reducer for data backup in a device includes an external power supply unit supplying power to the device, auxiliary power supply unit charging based upon the power supply from the external power supply unit and supplying auxiliary power to the device when the power from the external power supply unit is stopped, a cache memory having first and second memory units and recording a part of data stored in a storage medium, and a controller controlling power from the auxiliary power supply unit to the device and stopping power to the first or second memory unit one after another. | 09-18-2008 |
| 20080235528 | PROGRESSIVE POWER CONTROL OF A MULTI-PORT MEMORY DEVICE - A method and system for progressively reducing the power consumption of a serial memory device is provided, called the power control system. The power control system monitors the ports of a multi-port serial memory so that they can be enabled or disabled on a per-port basis. When data is not being transmitted or received on a port, a series of steps are taken to progressively de-power portions of the port and cause the port to enter into a low-power state. By disabling certain ports and placing ports in a low-power state, the power consumption of the overall serial port memory is significantly reduced. | 09-25-2008 |
| 20080235529 | Information processing apparatus and cellular phone - According to an aspect of the invention, there is provided an information processing apparatus including: a control unit configured to allow a device to perform an operation consuming a first amount of electrical power when the processing unit uses the device and allow the device to perform an operation consuming a second amount of electrical power less than the first amount of electrical power when the device is not used for a predetermined period of time after the device use, the control unit configured to determine the predetermined period of time in accordance with a request of the processing unit; and a plurality of processing units configured to use the device and request a length of the predetermined period of time to the control unit. | 09-25-2008 |
| 20080244293 | Methods, Systems, And Computer Program Products For Providing For Automatically Closing Application Widgets Based On Markup Language Elements - Methods and systems are described for providing for automatically closing application widgets based on markup language elements. In one embodiment, a markup element defined in a markup language to specify a condition for automatically closing the first widget is detected while processing a resource for presentation in a widget. It is determined without using executable code included in the resource whether the condition for automatically closing the widget is satisfied. The widget is automatically closed responsive to the condition for automatically closing the widget being satisfied. In another embodiment, a resource including a markup element defined in a markup language to specify a condition for automatically closing a widget that presents the resource is provided by a first network entity to a second network entity that is one of a client and a server. | 10-02-2008 |
| 20080244294 | Dynamic power reduction - Some embodiments of the invention include systems, apparatuses, and methods for dynamically reducing requested supply voltage based on idle functional blocks. | 10-02-2008 |
| 20080244295 | Method of saving power consumed by a storage system - Provided is a method of saving power consumed by a storage system that is connected to a host computer via a network, including a disk device for storing to be written data requested by the host computer, and controllers that control access to the disk device, in which the controllers each have an interface connected to the network, a processor connected to the interface, and a memory connected to the processor, in which the processor measures a load of the storage system, and in which the processor controls power to the controllers in accordance with the measured load of the storage system. | 10-02-2008 |
| 20080250260 | INFORMATION PROCESSING APPARATUS, SCHEDULER, AND SCHEDULE CONTROL METHOD OF INFORMATION PROCESSING APPARATUS - According to one embodiment, an information processing apparatus includes a CPU including a plurality of instruction processors, a monitoring unit which monitors an operating power supplying environment, and a power saving unit which controls the number of operating instruction processors provided in the CPU in accordance with the operating power supplying environment obtained by the monitoring with the monitoring unit. | 10-09-2008 |
| 20080256375 | SYSTEM OF INTEGRATED ENVIRONMENATLLY HARDENED ARCHITECTURE FOR SPACE APPLICATION - An environmentally hardened architecture comprises a hybrid processor, a high speed bus having environmentally-sensitive interfaces, an environmentally hardened bus having environmentally-hardened interfaces, and an environmentally-hardened processor communicatively coupled to an environmentally-sensitive interface of the high speed bus and communicatively coupled to an environmentally-hardened interface of the environmentally hardened bus. The hybrid processor includes an environmentally-hardened processing section and an environmentally-sensitive processing section. At least one environmentally-sensitive interface is configured to pass data to and from the environmentally-sensitive processing section and another environmentally-sensitive interface is configured to pass data to and from the environmentally-hardened processing section of the hybrid processor. An environmentally-hardened interface is configured to pass data to and from the environmentally-hardened processing section of the hybrid processor. The environmentally-hardened processor processes critical applications in the environmentally-hardened processing section of the at least one hybrid processor during an environmental event. | 10-16-2008 |
| 20080256376 | MULTI-THREAD POWER-GATING CONTROL DESIGN - The invention relates to a multi-thread power gating control design, setting idle components into a sleep mode to reduce power consumption due to current leakage. Based on compiler techniques, the invention arranges predicted-power-gating instructions into every thread of a may-happen-in-parallel region. A predicted-power-on instruction determines whether the corresponding component has been powered on, and powers on the component when it has not been powered on yet. A predicted-power-off instruction determines whether the component is required in the rest of the may-happen-in-parallel region, and powers off the component when it is required later. | 10-16-2008 |
| 20080256377 | Power Management for Buses in Cmos Circuits - The invention relates to a controlled shut-down of an electronic circuit or circuits such that the electrical power consumption of that circuit or circuits is minimized and that each said circuit is at a status which is a pre-determined state ( | 10-16-2008 |
| 20080270815 | DEVICE CONTROL APPARATUS AND DEVICE CONTROL METHOD - A device control apparatus includes: an interface connectable to at least one device having a power-saving function of stopping an action of a storage unit when a state that the storage unit is not accessed continues for more than a given time; a test data writing unit transmitting a writing command of test data to the storage unit through the interface in an interval shorter than the given time, when the device is connected to the interface; and a test data deleting unit transmitting to the device a deleting command to delete the test data in correspondence with a reception of a response to the writing command, the response being indicating writing completion and sent back from the device. | 10-30-2008 |
| 20080288801 | Information Processing Apparatus and Power Supply Control Method for Information Processing Apparatus - An information storage device ( | 11-20-2008 |
| 20080288802 | METHOD AND APPARATUS FOR OPERATING AN ELECTRONIC DEVICE IN A LOW POWER MODE - An electronic device, such as a hand-held portable computer, is provided with capability to operate an application during a low power mode. During the low power mode, portions of hardware, software, services, and/or other components of the portable computer that are not necessary to the operation of the application is suspended or otherwise deactivated. As each task is performed by the application, the components that are no longer needed for subsequent tasks to be performed by the application are also deactivated and reactivated as needed. The deactivation can be performed in sequence from the highest-level components to the lowest-level components to ensure that components that are needed by other components are not prematurely deactivated. A specific set of events transitions the portable computer out of the low power mode. | 11-20-2008 |
| 20080294922 | MATCHING SYSTEM OF ELECTRONIC DEVICE AND PERIPHERAL DEVICE AND MATCHING METHOD THEREOF - A matching system of an electronic device and a peripheral device and a matching method thereof are described. The system includes an electronic device, having an identification mechanism for identifying a specific identification code and generating a control signal or a control instruction according to an identification result; and a peripheral device, electrically coupled to the electronic device selectively. The peripheral device includes an identification code unit for storing a group identification code; and a power control unit, for controlling an operation state of the peripheral device according to the control signal or the control instruction, when the peripheral device is electrically coupled to the electronic device. If the identification result is that the specific identification code is consistent with the group identification code, the power control unit controls the entire peripheral device to work normally according to the control signal or the control instruction. | 11-27-2008 |
| 20080301483 | Surge-Protected Peripheral Devices - A computing system including: a host system; at least one device, mechanically connected to the host system, each device having an active state and an inactive state, wherein each device is conductively disconnected from the host system when the inactive state is enabled; and a mechanism for the host system to switch each device between the active state and the inactive state Preferably, at least one device is connected to the host system via a connector. Preferably, the device is hard-wired to the host system. Preferably, some wires of at least one device are isolated from the host system via a mechanical contactor. Preferably, some wires of at least one device are isolated from the host system via an optical isolator. Preferably, the system further includes: a switching battery; and a mechanism for charging the battery when at least one device is disconnected from the host system. | 12-04-2008 |
| 20080313482 | Power Partitioning Memory Banks - The present invention comprises a plurality of memory banks ( | 12-18-2008 |
| 20090013203 | Method and apparatus for power saving mode in hard disk drive - A method for implementing a power saving mode in a hard disk drive. The method includes the steps of flying a head over a data track of a disk that is covered with a lubricant. The speed of the disk is reduced. A voltage is applied to a heating element of the head to move the head closer to the disk. The fly height of the head is then determined. The voltage can be incrementally varied until the head makes contact with the disk. The voltage is terminated and the head is allowed to fly over the data track. The head is also moved to adjacent tracks on either side of the data track. A pressure gradient of the flying head moves the lubricant about the disk to mitigate a modulated wear pattern caused by the reduction in disk speed. The disk speed is then increased in a normal operating mode. | 01-08-2009 |
| 20090019300 | System and Method for Portable Power Source Management - A system is provided that includes a host system configured with a portable power source and a host power manager. The host power manager is configured to monitor an available power level of the portable power source and at least one power usage by one or more auxiliary devices. The host power manager is further configured to promote less than a full power usage by at least one of the auxiliary devices. | 01-15-2009 |
| 20090019301 | STORAGE APPARATUS - One aspect of the embodiments utilizes a storage apparatus includes a storage device through which data is input from and output to an external apparatus having an external interface. The storage apparatus includes a power supply control switch provided on a power supply line through which power is supplied to the storage device. A conversion control circuit converts signals mutually between a device interface of the storage device and the external interface, and performs control to turn off the power supply control switch so that supply of power to the storage device is stopped upon the storage device entering an idle state, the idle state being a state where input to and output from the external apparatus are absent. | 01-15-2009 |
| 20090024861 | PULSE LATCH CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - The disclosed invention is intended to decrease the power consumption of a pulse latch circuit. A pulse latch circuit that operates in sync with a pulsed clock signal, including a first operation mode in which shifting test pattern scan data is performed and a second operation mode in which shifting the test pattern scan data is not performed, comprises the following circuits: a first latch circuit that is able to latch input data in sync with the clock signal; a second latch circuit that is connected to the first latch circuit and is able to latch the test pattern scan data to be shifted in sync with the clock signal; and a control circuit that stops supply of the clock signal to the second latch circuit during the second operation mode. By thus stopping the supply of the clock signal to the second latch circuit, decrease the power consumption is achieved. | 01-22-2009 |
| 20090037757 | Method and Related apparatus for reducing CHIPSET power consumption - A method for reducing computer system power consumption. The computer system includes a memory module having a plurality of address pins, and a chipset having a plurality of driving units for driving the address pins. The method includes obtaining number of required address pins by detecting a capacity of the memory module, and disabling the driving units so as to make a number of the active driving units substantially equal to the number of the required address pins. | 02-05-2009 |
| 20090049320 | System and Method for Managing Storage Device Capacity Usage - Information handling system storage devices are managed to reduce power consumption by consolidating stored information to less than all of plural storage devices and powering down the storage devices that are no longer storing information. If a predetermined buffer of unused capacity is detected at the storage devices, then a powered down storage device is powered up to store additional information. The storage devices are consolidated to maintain desired performance parameters, such as by monitoring I/O performance for information stored on active storage devices. | 02-19-2009 |
| 20090049321 | CIRCUITS WITH TRANSIENT ISOLATION OPERABLE IN A LOW POWER STATE - An integrated circuit suitable for power conservation is disclosed. The circuit includes a core-logic providing a core-logic output, a latch in communication with the core-logic to store a state of the core-logic output, and an isolation circuit for selectively interconnecting the core-logic output to an input of the latch. The circuit also includes and a power consumption controller in communication with the core-logic, the latch and the isolation circuit, for controlling the latch to store a state of the core-logic output, and output a corresponding signal. The controller is further operable to signal the isolation circuit to isolate the core-logic output from the latch by providing an output corresponding to predetermined value and transition the core-logic from a high power state and a low power state. This prevents transient signals from propagating to interconnected circuit blocks and external devices. | 02-19-2009 |
| 20090063883 | STORAGE SYSTEM AND POWER CONSUMPTION REDUCTION METHOD FOR THE SAME - This invention achieves data capacity efficiency via data de-duplication and maximizes a power-saving effect by disk operation control. In a storage system, when data is received from a computer, a value representing the bit string for the data is calculated and whether or not a value identical to the calculated value is stored in a data management table is judged. If it is judged that an identical value is not stored, the received data is registered in the data management table and stored, based on a group management table, in disk device(s) associated with a logical unit number of a logical unit constituting an active group. Meanwhile, if it is judged that an identical value is stored, the received data is stored in disk device(s) based on the group information managed in the group management table and the management information managed in the data management table. | 03-05-2009 |
| 20090083563 | Power efficient data storage with data de-duplication - A storage system includes a first de-duplication scope comprising a first volume, a first table of hash values corresponding to first chunks of data stored on the first volume, and a first table of logical block addresses of where the chunks of data are stored on the first volume. A second de-duplication scope includes similar information for a second volume. The first scope is used for de-duplicating and storing first data from a first data source and the second scope is used for de-duplicating and storing second data from a second data source. First storage mediums that make up the first volume remain powered off while de-duplication and storage of the second data on the second volume takes place, and second storage mediums that make up the second volume remain powered off while de-duplication and storage of the first data takes place, thereby enabling data de-duplication while saving power. | 03-26-2009 |
| 20090094472 | Computer system and method for dynamically saving power thereof - A computer system and a method for saving power thereof are provided. The computer system includes a switch, a system power supply unit and an operation control unit. The switch is electrically connected to a peripheral component selectively. The system power supply unit is electrically connected to the switch. The operation control unit is electrically connected to the switch, and it detects whether an application program relative to the peripheral component is executed. Then, the operation control unit outputs the switch control signal to the switch to determine whether the system power supply unit provides the operation power for the peripheral component. | 04-09-2009 |
| 20090106573 | Power saving method - The present invention is to provide a power saving method which reduces the consumption of voltage of the notebook computer under a power saving mode. While the notebook computer enters the power saving mode, the configuration information of a south bridge chip of the notebook computer is read first, then said configuration information is stored in a non-volatile memory of the notebook computer, and then the voltage supply to the south bridge chip is cut. When the notebook computer is ordered to resume, voltage will be supplied to the south bridge chip, then the configuration information stored in the non-volatile memory will be retrieved, and then the south bridge chip will be set according to the configuration information to resume the notebook computer to the booted status. | 04-23-2009 |
| 20090119529 | CONFIGURATION OPTIMIZATION METHOD FOR A STORAGE SYSTEM - This invention provides, when optimizing a configuration of a storage system using a pool, an optimal configuration while ensuring a policy set by an administrator, the policy concerning a power saving performance, a response performance, or the like. The management computer sets, according to the set policy, priorities to volumes held by a storage subsystem, and reserves volumes satisfying the capacity of the pool, in descending order of the priority. Only some of the reserved volumes are registered for the pool in descending order of the priority. At this time, it can be guaranteed that a host computer makes no access to the volumes which have not been registered for the pool, and therefore the sleep state is set to physical drives forming the volumes or to a controller controlling the physical drives. | 05-07-2009 |
| 20090119530 | LOWER POWER DISK ARRAY AS A REPLACEMENT FOR ROBOTIC TAPE STORAGE - The present invention provides methods and systems for storage of data. In one aspect, the invention provides a data storage system that includes a plurality of storage devices, such as, disks, for storing data, and a controller that implements a policy for managing distribution of power to the storage devices, which are normally in a power-off mode. In particular, the controller can effect transition of a storage device from a power-off mode to a power-on mode upon receipt of a request for reading data from or writing data to that storage device. The controller further effects transition of a storage device from a power-on mode to a power-off mode if no read/write request is pending for that storage device and a selected time period, e.g., a few minutes, has elapsed since the last read/write request for that storage device. | 05-07-2009 |
| 20090125743 | Socket Assembly With Data Traffic Sensing - A power distribution apparatus for use with a suite of master and peripheral devices, comprising a master electrical outlet and at least one slave electrical outlet, both connectable to a common electrical power supply. The apparatus further comprising a monitoring means for monitoring data traffic, e.g. USB bus signals, associated with a master device such as a personal computer, and a controller for interrupting power to the at least one slave electrical outlet in response to the monitoring means detecting a prescribed change in the data traffic of the master device. | 05-14-2009 |
| 20090138739 | Circuitry for optimization of power consumption in a system employling multiple electronic components, one of which is always powered on - Circuitry for conserving power in a system employing multiple electronic components of which a first electronic component operates at a first frequency and is continuously powered on by a power source. The system further includes a second electronic component operating at a second frequency different than that of the first frequency of the first electric component, the second electronic component being maintained in a powered off state in which no energy whatsoever is consumed by the second electronic component until energized in response to a power enabling signal generated by the first electronic component based on demand of the particular function to be performed by the second electronic component. The first and second electronic components may be processors, wherein the frequency of the first processor is lower than that of the second processor. | 05-28-2009 |
| 20090144575 | CHARGING OF MOBILE DEVICES - A system which enables battery powered devices such as notebook computers to efficiently charge smaller mobile devices such as music players, cell phones and PDAs using the power signals provided over their data connections is made more efficient by ensuring that the power to the small mobile device is not interrupted should the notebook computer otherwise go into a standby or low-power state. The presence of the small mobile device is known and any power-down capabilities of the notebook computer are limited, at least for the period where the small mobile device is being recharged. This detection can be done at any of the levels of software present in the notebook computer. This charging and not powering down can be further optimized by determining the particular device and its charging requirements or by having the device provide feedback as to its charge state. | 06-04-2009 |
| 20090150700 | METHOD OF CONTROLLING POWER TO A PLURALITY OF SERVERS - A method of controlling power to a plurality of servers operating in a virtualization mode. The method includes monitoring a demand for resources from the plurality of physical servers. Upon sensing a decrease in demand for resources from the plurality of physical servers, select ones of the plurality of virtual servers are migrated from one or more of the plurality of physical servers to others of the plurality of physical servers. The physical severs from which the plurality of virtual servers have migrated are designated as inactive physical servers and powered off, and the others of the physical servers are designated as active physical servers. Upon sensing an increase in demand for resources from the plurality of active physical servers, the inactive physical servers are powered up and select ones of the plurality of virtual severs are migrated back to the powered-up inactive physical servers. | 06-11-2009 |
| 20090150701 | SHADOW WRITE AND TRANSFER SCHEMES FOR MEMORY DEVICES - Systems and methods for controlling memory devices are disclosed. In one embodiment, a memory system comprises a memory controller for forwarding a command signal and an address signal and for receiving and forwarding a data signal, and a first memory device for receiving the command signal and the address signal from the memory controller, where the first memory device comprises a first command judging circuit for receiving and forwarding the data signal and for decoding the command signal. The memory system further comprises a second memory device for receiving the command signal and the address signal from the memory controller, where the second memory device comprises a second command judging circuit for receiving and generating the data signal and for decoding the command signal. The command signal, the address signal and the data signal are commonly connected to the first memory device and the second memory device. | 06-11-2009 |
| 20090164822 | METHOD FOR MANAGING STORAGE, PROGRAM AND SYSTEM FOR THE SAME - A system including plural storage devices provides a technique for controlling storage devices in which files are located by a file system, and turning on or off the storage devices based on prediction of the start or end of access to the files. A program that manages power to the storage devices and data access to the storage devices via the files includes means or functions for allocating a storage device as an area in which a file is located, for selecting a storage device in which a file is located, for predicting that access to a file is started for commanding turning on power to a storage device based on the prediction that access to a file is started, for predicting that access to a file terminates, and for commanding turning off power to a storage device based on the prediction that access to a file terminates. | 06-25-2009 |
| 20090172449 | SYSTEM-DRIVEN TECHNIQUES TO REDUCE MEMORY OPERATING VOLTAGE - Disclosed herein are approaches to reducing a guardband (margin) used for minimum voltage supply (Vcc) requirements for memory such as cache. | 07-02-2009 |
| 20090172450 | Mobile systems with seamless transition by activating second subsystem to continue operation of application executed by first subsystem as it enters sleep mode - A computer system includes two or more subsystems. In one example, a first subsystem is executing a multimedia application using data stored in a first storage device. A copy of the data is also stored in a second storage device associated with a second subsystem. The second subsystem may be a dedicated multimedia player controller. When the first subsystem is to enter a sleep state, the second subsystem may continue to process the multimedia data stored in the second storage device. The second subsystem may also use the same audio port that the first subsystem was using before it enters the sleep state. Appropriate transition point may be determined by the second subsystem to ease audio disruption. | 07-02-2009 |
| 20090172451 | METHOD AND COMPUTER PROGRAM FOR CONTROLLING A STORAGE DEVICE HAVING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES - A method and computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device. | 07-02-2009 |
| 20090187780 | METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT TO MANAGE BATTERY NEEDS IN A PORTABLE DEVICE - A battery conservation component synchronizes with a user's schedule or calendar. The battery conservation component may disable functions or features to ensure that the device has sufficient battery life for selected calendar events. The battery conservation component may warn the user if a battery charge is necessary to make selected calendar events. The battery conservation component may be applied to a wide variety of portable devices with time-sensitive events. For example, the battery conservation component may be applied to a device with vehicle navigation and estimate time-sensitive events based on waypoints in the vehicle's route. The battery conservation component may synchronize with a user's travel itinerary. Alternatively, the battery conservation component may suggest alternative functions or features based on a time-sensitive event, such as suggesting a shorter movie on a flight or road trip. | 07-23-2009 |
| 20090210734 | WAKEUP OF A NON-POWERED UNIVERSAL SERIAL BUS - Universal serial bus wakeup when the bus is not powered. In one embodiment, a method of waking up a universal serial bus (USB) from a non-powered state, comprises: upon detection of a wakeup condition, a wakeup generation module associated with a USB device generating a wakeup signal on a power line of a USB bus coupled to the USB device, or on a single-wire sideband; and a host wakeup module detecting the wakeup signal and causing the USB bus that is coupled to the USB device to be supplied with power. | 08-20-2009 |
| 20090249102 | METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION IN MULTI-CHANNEL MEMORY CONTROLLER SYSTEMS - Disclosed is a method, apparatus and computer program product for reducing memory power consumption in a server system. The server system includes a memory controller and a plurality of Dual Inline Memory Modules (DIMMs). The method for reducing the memory power consumption includes determining a status of a channel of a plurality of channels of the memory controller. The plurality of channels is associated with the plurality of DIMMs of the server system. The status of the channel represents a presence of at least one scheduled transaction in the channel. The method further includes monitoring the status of the channel by checking whether the status of the channel is in an idle mode for a period of at least equal to a first threshold time. Thereafter, the method includes driving the channel into a power down state based on the monitoring of the status of the channel. | 10-01-2009 |
| 20090249103 | PLATFORM POWER MANAGEMENT BASED ON LATENCY GUIDANCE - Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described. | 10-01-2009 |
| 20090249104 | Storage system - A journal volume is created in a different power control unit of a normal mode, and the power saving mode is maintained by storing differential data in the journal until the corresponding power control unit is returned to a normal mode. A replication pair in a pair status in the power control unit is confirmed, set as a target to be switched to the power saving mode if it is of a constant value or less, and a management server is notified if there is an operation for creating a volume. | 10-01-2009 |
| 20090249105 | Hardware Controlled Power Management of Shared Memories - This invention manages power down and wakeup of shared memories in a multiprocessor system. A register for each shared memory has bits corresponding to each master. When a master wants to power down a memory, it sets its corresponding bit in the register. A hardware power down controller for the memory bank powers the memory bank if any processor signals powering the memory bank. The hardware power down controller for the memory bank powers down the memory bank only if all processor signal powering down the memory bank. waits for all masters to set their corresponding bits in the register before initiating power down of the memories. Software running on any processor has a view of the shared memory independent of the other processors and no inter-processor communication is needed. | 10-01-2009 |
| 20090249106 | Automatic Wakeup Handling on Access in Shared Memory Controller - A hardware based wake-up scheme initiates memory power-up upon a normal access to a powered down memory. The access that triggered the power-up is buffered. Further accesses are stalled until the memory is completely powered up. The buffered access then proceeds to the memory and the processor is brought out of stall. In cases where the software does not directly control access to the memory, such as on a cache miss, this scheme avoids undesirable conditions due to access to powered down memories. | 10-01-2009 |
| 20090259868 | INFORMATION PROCESSING APPARATUS, POWER MODE CONTROL METHOD, AND POWER MODE CONTROL PROGRAM PRODUCT - An information processing apparatus switches from a regular power mode to a power saving mode in the event that a first control unit does not process packets for a certain period of time. The information processing apparatus includes a packet table in which packets to be processed by the first control unit are registered, and a determining unit for determining whether the system of the information processing apparatus can switch to the power saving mode. In the event that the determining unit determines that the system can switch to the power saving mode, a network controller processes the packets based on the packet table. | 10-15-2009 |
| 20090265569 | POWER CONTROL METHOD FOR COMPUTER SYSTEM - Provided is a computer system comprising: an input/output switch coupled to a plurality of input/output devices; a server which is coupled to the input/output switch and, which uses the plurality of input/output devices; and a management computer coupled to the input/output switch and the plurality of input/output devices. The management computer manages pieces of management information including a port of the input/output switch coupled to the each of the plurality of input/output devices, an association of a device coupled to the each of the plurality of input/output devices, and a usage ratio of the each of the plurality of input/output devices; selects at least one of the input/output devices of which the usage ratio is smaller than a first predetermined threshold according to the pieces of management information; and processes, by another input/output device coupled to the input/output switch, a request for the selected input/output device. | 10-22-2009 |
| 20090271648 | INFORMATION PROCESSING DEVICE, DATA WRITING METHOD, AND PROGRAM FOR THE SAME - An information processing apparatus comprises: a creation unit creating a preset number of pieces of second data by duplicating first data, and holding the second data in a predetermined area or sending the second data to another information processing apparatus; a first writing unit for writing the first data in a first storage device; an activation unit activating power to a second storage device at a predetermined time, the second storage device being in a stopped state; a second writing unit for writing the second data in the second storage device activated by the activation unit by retrieving the second data from the predetermined area or another information processing apparatus after the second storage device is activated by the activation unit; a stop unit stopping power to the second storage device in which the second data is written by the second writing unit. | 10-29-2009 |
| 20090287948 | CONTEXT BASED POWER MANAGEMENT - According to some embodiments, context information associated with a processing system may be determined. It may then be automatically arranged for a power state associated with the processing system to transition from a first power state to a second power state based on the context information. | 11-19-2009 |
| 20090300394 | Reducing Power Consumption During Execution Of An Application On A Plurality Of Compute Nodes - Methods, apparatus, and products are disclosed for reducing power consumption during execution of an application on a plurality of compute nodes that include: executing, by each compute node, an application, the application including power consumption directives corresponding to one or more portions of the application; identifying, by each compute node, the power consumption directives included within the application during execution of the portions of the application corresponding to those identified power consumption directives; and reducing power, by each compute node, to one or more components of that compute node according to the identified power consumption directives during execution of the portions of the application corresponding to those identified power consumption directives. | 12-03-2009 |
| 20090300395 | POWER SAVING SYSTEM AND METHOD - A power saving system is provided, comprising a system chip, at least one controller and at least one corresponding switch. The system chip is coupled to the controller. The controller is coupled between the system chip and a connector. The switch is coupled between the controller and a power and is turned on or off according to a GPIO signal. When the switch is turned on, the controller is active. When there is no device through the connector and the controller coupled to the system chip, the controller is turned off for power saving. | 12-03-2009 |
| 20090300396 | INFORMATION PROCESSING APPARATUS - According to one embodiment, an information processing apparatus includes a power supply module, a connection bus, a processor connected to the connection bus and including a power supply control circuit module supplied with power from the power supply module and a arithmetic circuit module connected to the power supply control circuit module, a power supply control module configured to control supply of power from the power supply module to the arithmetic circuit module of the processor, and control module for sending, when the power supply control circuit module of the processor receives a predetermined notification, the predetermined notification to the power supply control module from the power supply control circuit module, and controlling, by the power supply control module which has received the predetermined notification, to stop power supply from the power supply module to the arithmetic circuit module. | 12-03-2009 |
| 20090300397 | METHOD, APPARATUS AND SYSTEM FOR REDUCING POWER CONSUMPTION INVOLVING DATA STORAGE DEVICES - The invention provides a method, apparatus and system for reducing power consumption involving data storage devices. One embodiment involves storing data in a first memory; in response to the first memory exceeding a first threshold, migrating the data from the first memory to a second memory; in response to the second memory exceeding a second threshold, then activating a third memory if the third memory is in active; and in response to the second memory exceeding a third threshold greater than the second threshold, migrating the data from the second memory to a third memory; wherein the second memory is sized and configured to store data targeted for the third memory to intelligently maintain a portion of the third memory in an inactive state. | 12-03-2009 |
| 20090307512 | System and Method for Managing Blades After a Power Supply Unit Failure - Systems and methods for managing blades in the event of a power supply unit failure are disclosed. A method may include determining whether a reduced power capacity of the non-failed power supply units is sufficient to provide an aggregate minimum power requirement of the resources in response to a failure of a particular power supply unit. The method may also include powering down a low-priority resource and not powering down a second resource having a higher priority than the low-priority resource if the reduced power capacity of the non-failed power supply units is not sufficient to provide the aggregate minimum power requirement of the resources. | 12-10-2009 |
| 20090307513 | ELECTRONIC DEVICE, POWER-ON METHOD FOR AN ELECTRONIC DEVICE, AND PROGRAM - An information processing unit and a storage unit are connected to each other through any one of a first interface, which is capable of interconnection in which the storage unit is powered on first, and after the storage unit is put into operation, the information processing unit is powered on, and a second interface, which is incapable of interconnection. The information processing unit has a PROM storing information on type of interface. The management unit reads out the type from the PROM upon reception of an instruction to power on the information processing unit. When the information processing unit is connected to the storage unit through the first interface, power-on is performed by predetermined control. When the information processing unit is not connected to the storage unit through the first interface, the storage unit is powered on, and then, the information processing unit is powered on. | 12-10-2009 |
| 20090319813 | METHOD AND SYSTEM FOR MANAGING POWER SUPPLY TO AT LEAST ONE DEVICE - A method of managing power supply to at least one device in a data processing system, the method comprising determining when the at least one device has been associated with no resources for a predetermined period of time; turning off the power supply to the at least one device; determining that the at least one device is required for use by the data processing system; and restoring the power supply to the at least one device. | 12-24-2009 |
| 20090327781 | METHOD AND SYSTEM FOR POWER MANAGEMENT IN A VIRTUAL MACHINE ENVIRONMENT WITHOUT DISRUPTING NETWORK CONNECTIVITY - A method for power management. The method includes gathering resource usage data for a first blade and a second blade on a blade chassis, migrating each virtual machine (VM) executing on the first blade to the second blade based on the resource usage data and a first migration policy, wherein the first migration policy defines when to condense the number of blades operating on the blade chassis, and powering down the first blade after each VM executing on the first blade is migrated from the first blade. | 12-31-2009 |
| 20100005329 | Storage System - There is provided a storage system including a file server connecting to a computer over a network and a storage apparatus connecting to the file server connecting over the network, wherein the file server includes a first controller, the storage apparatus includes multiple storage devices having multiple storage areas and a second controller that controls accesses to the multiple storage areas, each of the multiple storage areas has at least one power saving mode among multiple power saving modes with different shift times from the power saving modes to a ready mode, the first controller, in response to the reception of data from the computer, sets an indicator relating to the performance of response to an access from the computer to the data and refers to the indicator of the data and selects a first storage area having the power saving mode satisfying the indicator, and the second controller stores the data to the first storage area. | 01-07-2010 |
| 20100011235 | METHOD AND APPARATUS FOR POWER MANAGEMENT - An electronic device includes a processor configured to run a plurality of applications, a power supply coupled to the processor, and a database coupled to the processor The database is configured to store information identifying each of the plurality of applications as being in either a first set of applications or a second set of applications. The processor monitors the power level of the power supply and is configured to disable the first set of applications when the power level reaches a predetermined power level. | 01-14-2010 |
| 20100017638 | System and Method for Reducing Power Requirements of Microprocessors Through Dynamic Allocation of Datapath Resources - There is provided a system and methods for segmenting datapath resources such as reorder buffers, physical registers, instruction queues and load-store queues, etc. in a microprocessor so that their size may be dynamically expanded and contracted. This is accomplished by allocating and deallocating individual resource units to each resource based on sampled estimates of the instantaneous resource needs of the program running on the microprocessor. By keeping unused datapath resources to a minimum, power and energy savings are achieved by shutting off resource units that are not needed for sustaining the performance requirements of the running program. Leakage energy and switching energy and power are reduced using the described methods. | 01-21-2010 |
| 20100031073 | SYSTEMS AND METHODS FOR POWER MANAGEMENT IN ELECTRONIC DEVICES - Systems and methods are disclosed for managing power consumption in electronic devices. In certain embodiments, an integrated circuit for managing power consumption in an electronic device includes an input/output (I/O) interface, a first circuit block coupled to the I/O interface, and an interface circuit coupled between the I/O interface and the first circuit block, the interface circuit configured to provide a defined logic state to the first circuit block or a second circuit block external to the integrated circuit if one of the first circuit block or the second circuit block is powered down. By providing a defined logic state to the first circuit block or the second circuit block when one of the first circuit block or the second circuit block is powered down, power consumption of the electronic device may be reduced. | 02-04-2010 |
| 20100031074 | Storage device and control method for the same - In a storage device, any one of management sections respectively provided to a plurality of control modules is set to be in charge of collectively managing the modules, and a management user is allowed to collectively manage the modules via this management section through access thereto. Such a storage device is thus enabled, even if a control module is designed to be provided sequentially to a storage system, to manage the control modules as collective control resources with respect to a host device, and a method for controlling such a storage device is also provided. | 02-04-2010 |
| 20100037076 | METHOD AND APPARATUS FOR FACILITATING DEVICE HIBERNATION - One embodiment of the present invention provides a system that enables a computing device to save additional power by entering a “hibernation mode,” wherein the active state of the computing device is preserved in non-volatile storage while power to volatile storage is turned off. During operation, the system reanimates a computing device from a hibernation image by restoring reanimation code from the hibernation image and then executing the reanimation code. While executing this reanimation code, the system restores the rest of the hibernation image by, reading compressed data containing the rest of the hibernation image, and decompressing the compressed data using computational circuitry within the computing device. During this process, the decompression operations are overlapped with the reading operations to improve performance. | 02-11-2010 |
| 20100050007 | SOLID STATE DISK AND METHOD OF MANAGING POWER SUPPLY THEREOF AND TERMINAL INCLUDING THE SAME - A solid state disk and a method for managing power supply of the solid state disk and a terminal including the solid state disk. The solid state disk includes at least one data storage module for storing data, a management module for controlling data operation for said data storage module, controlling said data storage module as an operating power supply state when said data storage module is performing the data operation, and controlling said data storage module as a non-operating power supply state at other times. The data storage module may be enabled as the operating power supply state only when the data operation is performed for a certain data storage module, and the data storage module may be set as the non-operating power supply state when it is in the idle state or after the data operation is completed. Thus, the power consumption of the solid state disk is effectively saved, and the duration of the notebook computer which applies the solid state disk is prolonged. | 02-25-2010 |
| 20100058089 | MEMORY DEVICE HAVING A MEMORY SLEEP LOGIC AND METHODS THEREFOR - A memory device includes memory sleep logic operative to detect a repetitive pattern within at least one memory block, and place the memory block into a sleep mode in response to detecting the repetitive pattern. The memory device memory sleep logic may also provide a response to read commands to the memory block while it is in sleep mode, where the response is a constant output for any address location of the memory block. The memory device memory sleep logic may include pattern detection logic, associated with each memory block, to detect the repetitive pattern; and data port logic, coupled to the pattern detection logic, operative to receive an activation command from the pattern detection logic, and operative to return a constant output pattern in response to any read command to read data from the memory block. | 03-04-2010 |
| 20100058090 | STORAGE SYSTEM AND POWER SAVING METHOD THEREOF - A storage system and method are provided. The storage system includes, redundant disk arrays to which the same data is written and a write/read control section which controls writing and reading of data to and from the redundant disk arrays in response to a write request and a read request. The system includes disk rotation control section which continuously rotates disks of one of the disk arrays to perform a read process for written data and stops the rotation of disks of the other disk array when writing of data to the redundant disk arrays is completed, and further stops, when the write/read control section determines that the frequency of read requests from the host apparatus becomes less than a predetermined value after the completion of the writing of data, the rotation of the disks of the one of the disk arrays in accordance with the determination. | 03-04-2010 |
| 20100064160 | Circuit Having a Low Power Mode - Embodiments of the invention include an IC that includes a core used for ordinary operation and a thin power circuit. The thin power circuit can be configured to use very little power. The IC can also include a digital interface and a connection thereto. The IC can initiate transition to low power mode during which the core and various I/O pads can be shut down. However, the thin power circuit can be kept powered up. The thin power circuit can monitor the digital interface for a predefined wake up signal. When the wake up signal is detected, the thin power circuit can power up the core and any powered down I/O pads. The thin power circuit can also include a dedicated power on reset (POR) cell. This POR cell can be distinct than other POR cells used for the IC and can be specifically designed to for efficient operation. | 03-11-2010 |
| 20100064161 | Data Reserving Method for a Redundant Array of Independent Disks and Related Data Reserving Device and System - A data reserving method for a redundant array of independent disks (RAID) includes detecting an alternating-current (AC) power inputted to a power supply device used to transform the AC power into a direct-current (DC) power for the RAID, and storing data of a memory module of the RAID into a non-volatile storage device when the AC power is not inputted to the power supply device. | 03-11-2010 |
| 20100070789 | Storage control device - The storage control device of the present invention reduces power consumption by stopping the flow of power to enclosures that are not being accessed. A plurality of additional enclosures are connected to a base enclosure by means of a daisy-chain connection. The respective additional enclosures are divided into three levels, namely a low usage frequency level, a medium usage frequency level, and a high usage frequency level depending on the connection distance of the additional enclosures from the base enclosure. Drives that have not been accessed for a predetermined time are spun down. When all the drives in the enclosure are in the spindown state, the supply of power from the power supply to the respective drives is stopped. Further, when the flow of power to an additional enclosure located below the enclosure itself has stopped, the switch of the latter enclosure is turned OFF and the flow of power to the additional enclosure is stopped. | 03-18-2010 |
| 20100077244 | LOW POWER ELECTRONIC SYSTEM ARCHITECTURE USING NON-VOLATILE MAGNETIC MEMORY - A computing system includes at least one functional unit and a magnetic random access memory (MRAM) block coupled to the at least one functional unit. The MRAM block is configured to store a functional state of the at least one functional unit during a power down state of the at least one functional unit. | 03-25-2010 |
| 20100088532 | METHOD AND HANDHELD ELECTRONIC DEVICE HAVING A GRAPHIC USER INTERFACE WITH EFFICIENT ORIENTATION SENSOR USE - A method and handheld electronic device having a graphic user interface with efficient orientation sensor input use are provided. In accordance with one embodiment, there is provided a method of rendering a graphical user interface (GUI) on a portable electronic device, comprising: displaying a user interface screen of a foreground application on a display screen of the portable electronic device in a first screen orientation; receiving a device orientation event notification from an orientation sensor of the portable electronic device, the device orientation event notification specifying a device orientation; determining a preferred screen orientation associated with the device orientation; determining whether the preferred screen orientation matches a screen orientation rule for the foreground application; and re-displaying the user interface screen on the display screen in accordance with the preferred screen orientation when the preferred screen orientation matches the screen orientation rule for the foreground application only when it differs from the first screen orientation. | 04-08-2010 |
| 20100095145 | SYSTEM FOR REDUCING POWER CONSUMPTION IN AN ELECTRONIC CHIP - A system for reducing power consumption in an electronic device comprising at least one electronic chip comprises a plurality of local access network (LAN) ports, a transceiver coupled between the LAN ports and the electronic chip, a PLA device, and a central processing unit (CPU). The CPU is configured to power off the electronic chip in response to a period of inactivity on the LAN ports and power on the electronic chip in response to a signal from the PLA device. | 04-15-2010 |
| 20100095146 | PERSONAL COMPUTER POWER CONTROL METHOD AND DEVICE - The present invention describes a method for controlling electrical power supply to a personal computer installation, which may have a number of peripheral devices attached, such as printers, monitors etc. The method includes providing a first controlled power outlet adapted for supplying electrical power to a plurality of first devices and then monitoring, by use of software running on a personal computer, usage of at least one input device of the personal computer as well as a processor(s) associated with the computer, as well as the power level and power usage and then when the power usage mode is determined to be such that the first devices are not required to be powered, controlling the first controlled switch to remove power from the first controlled power outlet. | 04-15-2010 |
| 20100100755 | POWER MANAGEMENT METHOD FOR INPUT DEVICE - A power management method for an input device is provided, which includes the following steps: starting to count time and recording a trigger time of the input device after the input device enters a light-sleep mode; and dynamically updating a deep-sleep start time according to the trigger time. When the input device is idle over a standby time, the input device would enter the light-sleep mode and record the trigger time that the input device is restored from the light-sleep mode to an operation mode by a user operating the input device. The method dynamically updates the deep-sleep start time according to the recorded trigger time, and thus better power saving efficiency is achieved. | 04-22-2010 |
| 20100115319 | STORING DEVICE AND ELECTRONIC DEVICE HAVING THE SAME - A storing device includes a number of first storing unit, a second storing unit, and a control unit. The first storing units are capable of storing files therein. The second storing unit is capable of storing address information corresponding to the files stored in the first storing units. The control unit is electrically connected to each first storing unit and the second storing unit respectively. The control unit includes a data interface for communicating data with each first storing unit and a power port. The control unit is capable of selectively providing power for the first storing unit. | 05-06-2010 |
| 20100115320 | MOBILE SYSTEM ON CHIP (SoC) AND A MOBILE TERMINAL INCLUDING THE MOBILE SoC - A mobile System on Chip (SoC) including a central processing unit (CPU) and an audio out module that includes a buffer and an audio interface. A power mode of the audio out module is controlled separately from a power mode of the mobile SoC so that the audio out module operates when the mobile SoC is in a power down mode. | 05-06-2010 |
| 20100138680 | AUTOMATIC DISPLAY AND VOICE COMMAND ACTIVATION WITH HAND EDGE SENSING - Systems and methodologies for adapting input/output operation of an electronic device for in-hand and out-of-hand scenarios are provided herein. As described herein, sensors (e.g., capacitive, resistive, touch-sensitive, etc.) are applied to respective outer edges of a device to determine whether the device is in a user's hand. Subsequently, the determination can be utilized to automatically select an input/output mode for the device and to selectively activate one or more input/output mechanisms associated with the device. For example, if a device is determined to be in-hand, mechanical input/output mechanisms, such as a touch-screen or keypad, can be enabled. Alternatively, if a device is determined to be out-of-hand, a touch-screen at the device can be disabled to conserve power and alternative input/output mode, such as voice input/output, can be enabled. As further described herein, in- and/or out-of-hand behavior for a device can be specified on a per-application or per-application type basis. | 06-03-2010 |
| 20100138681 | SEMICONDUCTOR DEVICE - A semiconductor device capable of stabilizing power supply by suppressing power consumption as much as possible. The semiconductor device of the invention includes a central processing unit having a plurality of units and a control circuit, and an antenna. The control circuit includes a means for outputting, based on a power supply signal including data on power supply from an antenna (through an antenna) or a load signal obtained by an event signal supplied from each of the units, one or more of a first control signal for stopping power supply to one or more of the units, a second control signal for varying a power supply potential supplied to one or more of the units, and a third control signal for stopping supplying a clock signal to one or more of the units. | 06-03-2010 |
| 20100153763 | Method and apparatus to modulate multi-core usage for energy efficient platform operations - An energy efficient multi-core computing device and method are disclosed. According to embodiments of the invention, the processing load on a multi-core computing device may be monitored to determine whether one or more cores on the device may be dynamically shut down. Conversely, any core that is shut down may be dynamically powered up if the processing load on the device increases. Embodiments of the present invention therefore provide significant energy savings on multi-core platforms by minimizing the active cores on the device without affecting the device's processing capabilities. | 06-17-2010 |
| 20100153764 | Human Stimulus Activation and Deactivation of a Screensaver - Devices and methods are disclosed which relate to an electronic device having a human stimulus receptor which, when activated, suspends activation of a screensaver. The screensaver is activated to conserve the power and life of the electronic device. When latently viewing the electronic device, however, the human stimulus receptor is activated. A countdown starts counting down a pre-determined amount of time once the human stimulus receptor is inactive. At the expiration of the countdown, the screensaver is activated. The human stimulus receptor responds to skin conductivity, natural muscular twitch, pulse, skin temperature, and/or eye movement. Only when the electronic device no longer detects any of these human stimuli will the countdown begin. A user may set the predetermined amount of time. | 06-17-2010 |
| 20100162020 | Power Management of a Spare DRAM on a Buffered DIMM by Issuing a Power On/Off Command to the DRAM Device - A computer memory, having one or more of a semiconductor memory device having an internal memory array comprising a plurality of semiconductor dynamic random access memory (DRAM) cells arranged in a matrix of rows and columns, and provided as a memory module rank of such memory devices arranged in an array on a DIMM of one or more of said semiconductor memory device on a substrate which can be coupled via a memory device data interface to a memory system as a memory subsystem, each of said memory device having a low power shut-down state that can be activated using a common memory data interface. Control of power to a DRAM issues over the data interface two commands to a DRAM power control command decode, a power-state program signal and a power-state reset signal as a power-state control commands to control the power state of said DRAM, and to activate for READ/WRITE a memory cell as a normal active or spare device. | 06-24-2010 |
| 20100162021 | SYSTEM AND METHOD FOR EXTENDING THE BATTERY LIFE OF A MOBILE DEVICE - The present invention provides a system and method for extending the battery life of a mobile device. The method of extending the battery life of a mobile device can be broadly summarized by the following steps of determining if at least one component on the mobile device can be placed in a hibernation state for a predetermined time, setting a remote clock to the current time, and powering off the at least one component on the mobile device that can be placed in the hibernation state. The method further includes waiting a predetermined interval, re-activating the at least one component on the mobile device that was placed in the hibernation state, and synchronizing a system clock with the remote clock. | 06-24-2010 |
| 20100162022 | Apparatus and method for supporting selective suspend mode of USB network-device - A host computer equipment includes an apparatus configured to perform a method for supporting a selective suspend mode of a Universal Serial Bus (USB) network-device. The host includes a power manager, a status manager, and a USB driver. When there is a transition to a host suspend mode, the power manager delivers a host suspend mode notification message to the status manager. The status manager delivers a status transition message of instructing a normal status (D | 06-24-2010 |
| 20100169687 | DATA STORAGE DEVICE AND POWER-SAVING CONTROL METHOD FOR DATA STORAGE DEVICE - A data storage device includes a first nonvolatile memory, a second volatile memory that temporarily stores therein data to be transferred between a host device and the first memory, a first control unit that controls the second memory, a second control unit that controls data transfer between the first control unit and the first memory, a third control unit that controls data transfer between the host device and the first control unit, and a clock stop unit that stops a clock signal supplied to the first to third control units in conjunction with a power consumption control of the third control unit to perform a power saving control. | 07-01-2010 |
| 20100169688 | DISK ARRAY UNIT, AND METHOD AND PROGRAM FOR CONTROLLING POWER SOURCE IN DISK ARRAY UNIT - Intended is improvement in reliability of a disk array unit formed of a plurality of nodes at the time of start-up and stop. The disk array unit formed of a plurality of nodes, which includes a control unit which executes power source control of other node based on power source control information set at one of the nodes by inter-node communication executed through a common signal line which connects each node. | 07-01-2010 |
| 20100174933 | System and Method for Reducing Processor Power Consumption - A system and method for reducing active power in processors is disclosed. A method embodiment comprises the steps of determining when a particular logic block is inactive, determining the powered state of the particular logic block, isolating the particular logic block from a main processor core, and powering off the particular logic block. When the system needs the particular logic block, the method further comprises reactivating the block. A system embodiment comprises software and a processor coupled to a clock control module, an isolation control module and a header/footer module, operable to isolate a particular logic block and power off a particular logic block, thereby reducing power. Another embodiment comprises a logic module coupled to a clock by a clock gating module, an isolation module for isolating the logic module, a header/footer module for disabling power to the logic module, and a power and clock gating control module for controlling the clock gating module and the header/footer module. | 07-08-2010 |
| 20100174934 | Hibernation or Suspend Using a Non-Volatile-Memory Device - This disclosure describes techniques for using a non-volatile-memory device such as flash memory to store memory data during hibernation or suspend. By so doing, hard drives and/or data are safer, and less power may be used. | 07-08-2010 |
| 20100174935 | IMAGE FORMING APPARATUS AND METHOD OF CONTROLLING POWER CONSUMPTION THEREOF - A method of controlling power consumption of an image forming apparatus includes outputting information regarding power consumption of a plurality of operation units if a power consumption check mode is set, performing power save operation in which at least one operation unit from among the plurality of operation units is turned on and the remaining operation units are turned off if a power save mode is set. Accordingly, on/off of the plurality of operation units may be controlled in the power save mode based on power consumption of each of the operation units. | 07-08-2010 |
| 20100180136 | Ultra Low Power Wake-On-Event Mode For Biometric Systems - An apparatus for reducing power consumption in fingerprint-sensing circuits is disclosed in one embodiment of the invention as including a fingerprint sensing area onto which a user can apply a fingerprint. An integrated circuit communicates with the fingerprint sensing area and is configured to detect finger activity over the fingerprint sensing area. The integrated circuit includes a primary logic portion configured to assume control of the integrated circuit when finger activity is detected over the fingerprint sensing area. The integrated circuit also includes a secondary logic portion configured to assume control of the integrated circuit and shut off power to the primary logic portion when finger activity is not detected over the fingerprint sensing area. | 07-15-2010 |
| 20100180137 | CONTROL DEVICE - A control device performs the reading of data from a recording medium that is authenticated mutually or the writing of data into the recording medium. The control device includes an interface section which interfaces with the recording medium, a storing section which stores key information and authentication information produced in an authentication operation, and a controlling section which controls a supply of power based on whether or not the control device performs either the reading of data from the recording medium or the writing of data into the recording medium. While the control device performs neither the reading of data from the recording medium nor the writing of data into the recording medium, the controlling section controls so as to supply only to the storing section. Therefore, in the control device, a reduction in the number of times of mutual authentication with a recording medium is compatible with low power consumption. | 07-15-2010 |
| 20100180138 | POWER SWITCHING CIRCUIT OF PORTABLE ELECTRONIC DEVICE - A power switching circuit of a portable electronic device is disclosed. The portable electronic device can be coupled to an expansion device. The power switching circuit includes a first power terminal, a second power terminal, a first switch module, a second switch module, and a power pin. The first switch module is coupled to the first power terminal. The second switch module is coupled to the second power terminal. The power pin is coupled to the first switch module and the second switch module, respectively. When the portable electronic device is not coupled to the expansion device, the first switch module and the second switch module are turned off, such that first power provided by the first power terminal and second power provided by the second power terminal fail to be provided for the power pin via the first switch module and the second switch module. | 07-15-2010 |
| 20100185887 | APPARATUS AND METHOD FOR SAVING POWER IN PORTABLE TERMINAL USING ETHERNET - A method for saving power in a portable terminal includes determining whether an Ethernet cable is communicatively connected to an Ethernet modem; and when the Ethernet cable is not in communication with the Ethernet modem, intermittently supplying power to the Ethernet modem. | 07-22-2010 |
| 20100199116 | MULTIPATH POWER MANAGEMENT - Disclosed is a method of controlling power. Multiple paths via multiple I/O ports couple a server to a storage array. When I/O loads are low, it is determined if an I/O port may be deactivated and placed in a power saving mode. An I/O port may not be deactivated if deactivating that I/O port will affect a high-availability requirement or a performance requirement. Requests are stopped from being sent to an I/O port to be deactivated. When the port to be deactivated becomes idle, the I/O port is placed in a power saving mode. When I/O loads increase to a point where it is necessary to reactivate the I/O port, the I/O port is activated. | 08-05-2010 |
| 20100205469 | POWER BUDGETING FOR A GROUP OF COMPUTER SYSTEMS - Power consumption of a group of computer systems is managed based on a maximum power consumption for the group. A power budget is determined from the power consumption of each computer system and the maximum power consumption for the group. The power budget identifies a power cap for each computer system in the group. The power caps in the power budget are distributed to the computer systems in the group. | 08-12-2010 |
| 20100211810 | POWER SUPPLY AND DATA CENTER CONTROL - Systems and methods for data center power supply control are provided that identify a parameter of at least one of a plurality of servers that form at least part of a data center that includes an uninterruptable power supply. An estimated parameter of a virtual server can be identified, and one of the plurality of servers can be selected based at least in part on the parameter and the estimated parameter. The virtual server can be provided to the selected server, and the power provided to at least one of the plurality of servers can be reduced, shut down, or otherwise adjusted. | 08-19-2010 |
| 20100218024 | INPUT DEVICE AND METHOD, INFORMATION PROCESSING SYSTEM, AND PROGRAM - An input device includes an operation unit, a sending unit, and a power control unit. The operation unit is configured to be held by a user and to be operated in a three-dimensional free space so as to remotely operate an information processing apparatus. The sending unit is configured to send a command that disables display of a graphical user interface of the information processing apparatus when the operation unit is placed, and to send a command that enables display of the graphical user interface of the information processing apparatus when a button of the operation unit is operated. The power control unit is configured to cause the input device to enter a low power consumption state when the operation unit is placed. | 08-26-2010 |
| 20100218025 | PRINTING DEVICE CONTROLLER AND PRINTING DEVICE - A printing device controller provided with a first computational processing unit that performs overall control of the device as a whole and a second computational processing unit that consumes less power than the first computational processing unit, the printing device controller including: a RAM (Random Access Memory) having a self-refresh mode; a main control unit whose main processing constituent is the first computational processing unit; and a sub control unit whose main processing constituent is the second computational processing unit. When an instruction to enter a power-saving state is inputted, the main control unit causes the first computational processing unit to store information necessary for returning from the power-saving state into a storage unit and then causes the RAM to enter the self-refresh mode, and the sub control unit then powers off the first computational processing unit. | 08-26-2010 |
| 20100218026 | INTERFACE CONTROL DEVICE - An interface control device includes a first interface, a second interface, a third interface, an interface controller and a clock supplying unit. The first interface is used to communicate with a first information processing device and obtain a first clock signal from the first information processing device. The second interface is used to communicate using a second clock signal with a second information processing device different from the first information processing device. The third interface is used to communicate with a controller of a data-storage medium. The interface controller performs an interface control for the first, second and third interfaces. Moreover, the clock supplying unit supplies the first clock signal to the third interface while communications through the second interface have not been established. | 08-26-2010 |
| 20100223484 | DARK WAKE - Exemplary embodiments of methods, apparatuses, and systems for powering up select components of a computer from a sleep state, maintaining a network state, and powering down the select components of the computer to return the computer to the sleep state are described. For one embodiment, a network interface and a fan controller receive power during the network state maintenance but a display or audio components do not receive power during the network state maintenance. | 09-02-2010 |
| 20100235669 | MEMORY POWER CONSUMPTION REDUCTION SYSTEM, AND METHOD AND PROGRAM THEREFOR - Disclosed is a memory power consumption reduction system that includes a memory allocation section, which allocates an area of a plurality of physical memories included in a physical information processing device to a process of a virtual machine when the virtual machine is to be controlled with a VMM; a memory compaction section, which performs memory compaction when the physical memory area allocated to the process by the memory allocation section is deallocated upon termination of the process; and a power supply control section, which exercises control so as to shut off the power supply to a physical memory that is unused as a result of memory compaction by the memory compaction section. | 09-16-2010 |
| 20100235670 | Fast L1 Flush Mechanism - In one embodiment, a processor comprises a data cache configured to store a plurality of cache blocks and a control unit coupled to the data cache. The control unit is configured to flush the plurality of cache blocks from the data cache responsive to an indication that the processor is to transition to a low power state in which one or more clocks for the processor are inhibited. | 09-16-2010 |
| 20100241888 | INFORMATION PROCESSING APPARATUS AND POWER-SAVING SETTING METHOD - According to one embodiment, an information processing apparatus having a power-saving function includes a monitoring module and a power-saving setting presenting module. The monitoring module monitors a usage pattern of the information processing apparatus, and stores log information indicative of the usage pattern in a storage device. The power-saving setting presenting module determines recommended values of power-saving parameters for specifying content of the power-saving function, based on the stored log information, and to display the determined recommended values. | 09-23-2010 |
| 20100241889 | POWER MANAGEMENT SYSTEM AND METHOD - In one embodiment, provided is a method that includes detecting disconnect of a link at a Universal Serial Bus (USB) device coupled to a USB host via a USB bus, disconnecting the USB device from the USB bus, and modifying a power state of the USB device to a reduced power state. Disconnecting the USB device from the USB bus includes configuring the USB device such that the USB host recognizes the USB device as being disconnected from the USB bus. The reduced power state allows the USB device to monitor a status of the link such that the USB device is able to detect a reconnect of the link. | 09-23-2010 |
| 20100250990 | ELECTRONIC DEVICE, AND METHOD OF CONTROLLING THE ELECTRONIC DEVICE - An electronic device including an external-memory-medium installing portion in which an external memory medium storing contents data, a display portion for displaying the contents data, a sound generating portion for generating a sound, a power-shut-down-requirement receiving portion for receiving a requirement for shutting-down a power supply to the electronic device, a monitoring portion for determining whether the external memory medium is installed in the external-memory-medium installing portion, a sound-generation commanding portion for commanding command the sound generating portion to generate an alarming sound when the monitoring portion has determined that the external memory medium is not installed in the external-memory-medium installing portion while the contents data are displayed, and a power supply control portion for inhibiting an operation to shut down the power supply to the electronic device when the power-shut-down-requirement receiving portion has received the requirement for shutting down the power supply while the contents data are displayed. | 09-30-2010 |
| 20100262855 | Uncore Thermal Management - A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value. | 10-14-2010 |
| 20100262856 | Operating Mode For Extreme Power Savings When No Network Presence Is Detected - Drivers which control hardware devices in a network adapter chip are disabled prior to reducing power to a first portion of circuits in the network adapter chip. Power is received by a second portion of circuits which are utilized for detecting network activity and communicating the activity to processors. Upon network activity detection, the first portion of circuits receives power. Drivers are enabled subsequent to detection. Drivers are enabled after receiving power by the first portion of circuits. Processors control hardware devices, disable devices before power reduction, enable devices after network activity detection and enable devices after receiving power. The network adapter chip is reset for power reception. A power reduction mode is selected where drivers are disabled after reducing power. Drivers are enabled after hardware devices are enabled. A first state is characterized by no signal before disabling drivers. A second state is characterized by signal detection before receiving power. | 10-14-2010 |
| 20100275049 | POWER CONSERVATION IN VERTICALLY-STRIPED NUCA CACHES - Embodiments that dynamically conserve power in non-uniform cache access (NUCA) caches are contemplated. Various embodiments comprise a computing device, having one or more processors coupled with one or more NUCA cache elements. The NUCA cache elements may comprise one or more banks of cache memory, wherein ways of the cache are vertically distributed across multiple banks. To conserve power, the computing devices generally turn off groups of banks, in a sequential manner according to different power states, based on the access latencies of the banks. The computing devices may first turn off groups having the greatest access latencies. The computing devices may conserve additional power by turning of more groups of banks according to different power states, continuing to turn off groups with larger access latencies before turning off groups with the smaller access latencies. | 10-28-2010 |
| 20100275050 | DATA STORAGE DEVICE INCLUDING CURRENT DETECTOR - Provided is a data storage device including a current detector. The data storage device includes a plurality of memory devices, a detector, and a power manager. The detector detects a current inputted from a power source. The power manager manages consumption power of the plurality of memory devices according to a result of the detection provided from the detector. | 10-28-2010 |
| 20100281284 | Methods and Systems for Providing Indirect Voltage Detection in a Power Supply - A method is provided for providing indirect voltage detection in a power supply of an IHS. The method may include providing output current and voltage to an IHS via a power cable and monitoring the output current within the power supply. Furthermore, the method may include adjusting the output voltage if the output current reaches a threshold value. | 11-04-2010 |
| 20100281285 | Managing under-utilized resources in a computer - A method, and a corresponding system, for managing under-utilized resources in a computer system includes the steps of monitoring performance of workloads executing on the computer system, where the workloads consume resources, determining resource demand and utilization by the workloads, comparing the workload performance to user-defined performance targets and resource utilization by the workloads to user-defined utilization targets, using the comparison results, determining if one or more resources may be assigned to a free resource pool, and assigning the determined resources to the free resource pool. | 11-04-2010 |
| 20100281286 | METHOD, COMPUTING SYSTEM, AND COMPUTER PROGRAM FOR REDUCING POWER CONSUMPTION OF A COMPUTING SYSTEM BY RELOCATING JOBS AND DEACTIVATING IDLE SERVERS - In a computing system where multiple servers are connected through a network and one or more jobs are run, a power reduction facility of a supervisory server relocates jobs according to predetermined conditions, thereby reducing the amount of power consumed by the computing system. For relocating the jobs, the power reduction facility obtains server-related information such as the power properties of the servers constituting the computing system and job-related information such as performance requirements for the jobs which are run in the computing system, and searches for one or more jobs to be relocated and destination servers, based on these server-related information and job-related information, to the extent that the performance requirements for each job are fulfilled. Based on the search results, the jobs are relocated to the destination servers, and servers on which no job is running, as a result of the relocation, are powered off. | 11-04-2010 |
| 20100287397 | Method of a Full Coverage Low Power Mode for Storage Systems Storing Replicated Data Items - A novel and useful method of implementing a full coverage low power mode in a storage system comprised of one or more memory storage devices storing replicated data items. A subset of the memory storage devices is chosen whose replicated data items require the least amount of storage. If the chosen subset stores uncovered data items, these data items are copied to an auxiliary memory storage device. The storage system can enter a full coverage low power mode by powering down the chosen subset of memory storage devices. | 11-11-2010 |
| 20100293404 | System and Method for Dynamic Energy Efficient Ethernet Control Policy Based on User or Device Profiles and Usage Parameters - A system and method for dynamic energy efficient Ethernet (EEE) control policy based on user or device profiles and usage parameters. The analysis by an EEE control policy can consider user or device related EEE profile information that is either network propagated or retrieved from a network database. This EEE profile information can be used in combination with static settings established by an IT manager and the properties of the traffic on the link itself. | 11-18-2010 |
| 20100299547 | POWER-SAVING CONTROL APPARATUS AND METHOD - A power-saving control apparatus and method capable of power-saving and prevention of decrease in the speed of accessing files of a high level of importance is suggested. | 11-25-2010 |
| 20100306565 | INFORMATION PROCESSOR AND POWER SUPPLY METHOD - According to one embodiment, an information processor capable of supplying power to an external device includes a connector, a storage module, a receiver, a selector, and a power supply controller. The connector connects the external device to the information processor. The storage module stores identification information that identifies the external device and a power supply mode in association with each other. The power supply mode defines a condition of each element of the information processor to cause the external device to be chargeable. The receiver receives the identification information from the external device connected to the information processor. The selector selects the power supply mode stored in the storage module in association with the identification information. The power supply controller sets the element of the information processor according to the condition defined by the power supply mode. | 12-02-2010 |
| 20100313052 | CONTROL APPARATUS - This invention improves the access efficiency of each of a plurality of memory devices mounted on a semiconductor chip. The invention provides a memory control circuit including a queue buffer unit, a management unit to set the CKE signal at High for a memory device to which a determination target access command is to be issued when it is determined that the determination target access command has shifted to the head position of the queue buffer unit, a command generating unit to issue an access command, and a data interface unit to execute processing specified by an access command. The management unit performs control to set the CKE signal to Low for the memory device to which the determination target access command is to be issued based on the state of the queue buffer unit when it is determined that the processing by the data interface unit is complete. | 12-09-2010 |
| 20100318827 | ENERGY USE PROFILING FOR WORKLOAD TRANSFER - Embodiments of energy profiling for workload transfer are disclosed. In accordance with at least one embodiment, the energy profiling for workload transfer includes determining a baseline wattage of a first server. Further, a load wattage of a workload is derived using a difference between the baseline wattage consumption and an overall wattage consumption. The workload is transferred to a second server when the load wattage is less than an available wattage on the second server. | 12-16-2010 |
| 20100325461 | STORAGE APPARATUS - A storage apparatus connectable to an external apparatus through a connection line for data communication includes: a storage for storing data; a system controller for controlling data communication with the external apparatus through the connection line so as to allow the external apparatus to access the storage; and a power controller for controlling power supply to the storage, wherein the system controller controls the power controller to initiate supply of a power to the storage after establishing a communication linkage with the external apparatus through the connection line. | 12-23-2010 |
| 20100325462 | INFORMATION PROCESSING APPARATUS CAPABLE OF BEING INSTRUCTED TO POWER OFF BY A COMMAND FROM EXTERNAL APPARATUS, METHOD OF CONTROLLING THE SAME, AND STORAGE MEDIUM - An image processing apparatus that is capable of being instructed to power off, by a power switch or a command from an external apparatus, and is capable of executing the restart thereof under appropriate conditions. When power-off is instructed, shutdown is started. Upon completion of the shutdown, if the power switch is on, and at the same time the power-off has been instructed by the power switch of the apparatus, the restart of the apparatus is executed, whereas upon completion of the shutdown, if the power-off has been instructed by a command from the external apparatus, the restart of the apparatus is not executed. | 12-23-2010 |
| 20100332882 | MINIMIZING STORAGE POWER CONSUMPTION - Techniques for minimizing storage power consumption are provided. The techniques include generating one or more physical storage volumes and one virtual storage volume for each physical storage volume, creating a mapping from virtual storage volumes to physical storage volumes, determining input/output (I/O) access behavior of one or more applications using statistical analysis, and re-mapping the virtual to physical volume mapping based on the determined I/O access behavior of the one or more applications to minimize storage power consumption while meeting a required performance. | 12-30-2010 |
| 20100332883 | METHOD AND SYSTEM FOR EVENT-BASED MANAGEMENT OF RESOURCES - A system for dispatching a thread to a resource obtains a thread and utilization data for all resources. The system determines if there is a thread-resource affinity. The system uses thread-resource affinity to identify a resource and a timestamp for when the thread last completed executing on the resource. The system determines if the resource qualifies under a dispatch policy. The system uses utilization data to determine a timestamp for when the resource last transitioned to a not powered state. When the second timestamp precedes the first timestamp, the system dispatches the thread to the resource and generates a power management event. The system determines if the power management event satisfies a throttle policy. The system discards the power management event when throttle policy is unsatisfied and determines whether to adjust the current power state of the resource based on the power management event when throttle policy is satisfied. | 12-30-2010 |
| 20100332884 | STORAGE CONTROL APPARATUS AND METHOD - A storage control apparatus includes a controller for receiving an access command from a host computer and controlling an access to a storage device and a monitoring period obtaining section for obtaining a monitoring period corresponding to the access command. The storage device is capable of operating in one of a power saving state and a normal state. The controller causes the storage device to return from the power-saving state to the normal state if the storage device corresponding to the access command is in the power saving state, and sends the host computer a response for preventing a timeout corresponding to the access command if the storage device have not yet returned to the normal state when the monitoring period elapses from receiving the access command. | 12-30-2010 |
| 20100332885 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD FOR INFORMATION PROCESSING APPARATUS, AND COMPUTER-READABLE STORAGE MEDIUM - An information processing apparatus decreases power supply to a processing unit if a predetermined condition is satisfied. If a waiting time has elapsed during a power saving state in which power supply to the processing unit is decreased, the information processing apparatus cancels the power saving state. The information processing apparatus executes a head retraction in response to the cancellation of the power saving state. The information processing apparatus stops power supply to the storage unit in response to completion of the head retraction. | 12-30-2010 |
| 20100332886 | METHOD AND APPARATUS FOR REGULATING TRANSCEIVER POWER CONSUMPTION FOR A TRANSCEIVER IN A COMMUNICATIONS NETWORK - A method and apparatus for regulating transceiver power consumption for a transceiver in a communications network. Data received by the transceiver is monitored to detect the presence or absence of a received data signal. A transceiver state machine is controlled to regulate transceiver power consumption in response to the presence of absence of the data received. | 12-30-2010 |
| 20110004778 | Method for Controlling Power on a Computer System Having a Network Device and a Wakeup Function - A method for controlling power in a computer system having a network device and a wakeup function is disclosed. A determination is made whether or not the network device is in an associated state at the time when the computer system moves into a power saving mode. In response to a determination that the network device is not in the associated state, power supply is turned off from a power source to the network device. In response to a determination that the network device is in the associated state, power supply is continually provided from the power source to the network device. | 01-06-2011 |
| 20110022869 | DEVICE HAVING MULTIPLE INSTRUCTION EXECUTION MODULES AND A MANAGEMENT METHOD - A multiple instruction execution modules device that comprises a first instruction execution module and a second instruction execution module and a context switch controller; wherein the first instruction execution module is logically identical to the second instruction execution module but substantially differs from the second instruction execution module by at least one power consumption characteristic; wherein the context switch controller controls a context switch between the first instruction execution module and the second instruction execution module; wherein an instruction execution module that its context has been transferred is shut down. | 01-27-2011 |
| 20110029797 | MANAGING MEMORY POWER USAGE - Methods of method of managing memory power usage in a computing device having two or more memory modules. By monitoring a system working set size of the computing device, a determination can be made if all active memory modules are needed for the system working set size. If not all active memory modules are needed for the system working set size, one or more of the active memory modules can be selected for power down. By evacuating data from the selected one or more memory modules, placing the evacuated one or more memory modules in a power-down state, and removing the powered-down memory modules from the active memory of the computing device, memory power usage can be reduced. | 02-03-2011 |
| 20110040994 | Two-Level Guarded Predictive Power Gating - A mechanism is provided for two-level guarded predictive power gating of a set of units within the data processing system. A success determines whether a unit within the set of units is power gated during a monitoring interval. If the unit is power gated, the success monitor determines whether a count of idle cycles for the unit is below a breakeven point. If the count is above the breakeven point, the success monitor increments a success efficiency counter. If the count is below the breakeven point, the success monitor determines whether the unit needs to be woke up. If the unit needs to be woke up, the success monitor increments a harmful efficiency counter. If the value of the harmful efficiency counter is less than the value from the success efficiency counter, the success monitor enables power gating for the unit via a first-level power-gating mechanism. | 02-17-2011 |
| 20110040995 | Predictive Power Gating with Optional Guard Mechanism - A mechanism is provided for predictively power gating a set of units within the data processing system. A second-level power gating controller monitors a set of events for each unit in a set of units within the data processing system. The second-level power gating controller identifies idle sequences of a predetermined set of cycles within the events from each unit where the unit is idle. The second-level power gating controller determines preceding sequences of a predetermined length that precede the idle sequences. The second-level power gating controller determines an accuracy of the preceding sequences. Responsive to the accuracy being above a threshold, the second-level power gating controller sends a permit command to a first-level power gating mechanism associated with the unit to permit power gating of the unit. | 02-17-2011 |
| 20110047397 | POWER GATING DEVICE - A power gating device may include a control unit that generates a first interrupt signal based on a mode change signal when a mode of a system is changed from a normal operation mode to a stand-by mode, and generates a second interrupt signal based on the mode change signal when the mode is changed from the stand-by mode to the normal operation mode, a memory unit that stores data of a function block based on the first interrupt signal, and restores the stored data to the function block based on the second interrupt signal, and a power source unit that provides a normal operation power to the function block and the memory unit based on a power down signal in the normal operation mode, and provides a stand-by power to the memory unit based on the power down signal in the stand-by mode. | 02-24-2011 |
| 20110055610 | PROCESSOR AND CACHE CONTROL METHOD - A processor and a cache control method are provided herein. The processor includes a plurality of caches and a control unit. The caches are respectively controlled by a plurality of cache enable signals to be activated. The control unit generates the cache enable signals according to a power mode for selecting and accessing a subset of the caches in response to the power mode, wherein the number of the subset of the caches is determined by the power mode. Therefore, the processor can activate the caches as requirement according to the power mode for reducing power consumption of the caches. | 03-03-2011 |
| 20110055611 | SYSTEM FOR CONTROLLING POWER CONSUMPTION OF A NETWORK - A system for controlling power consumption of a network includes at least one terminal to receive a plurality of requests to route data from a plurality of data sources to a plurality of data sinks, where the data sources and the data sinks are connected to each other through a plurality of network nodes forming the network, and a network configuration unit. The network configuration unit includes a selection module configured to select a configuration of the network nodes that allows the network to have a lowest overall power consumption of the network among a plurality of configurations of the network, and an output module configured to output a plurality of instruction signals to the network nodes to perform the network configuration. A network path for transmitting a network flow is selected that does not allow the network flow to be split and flow through another network path. | 03-03-2011 |
| 20110055612 | COMPUTER SYSTEM AND CONTROL METHOD THEREOF - A computer system and a control method thereof reduce power to devices not in use. The system typically includes a device unit; a switching unit which switches supply of power to the device unit; and a control unit which checks whether or not the device unit is in use, and controls the switching unit to prevent power from being supplied to the device unit if the device unit is not in use. Wasteful power consumed by devices which are not in use is minimized. In addition, if a user wants to reuse a device with supply of power cut off, it is possible to reuse the device by resuming the supply of power to the device in a simple manner. | 03-03-2011 |
| 20110060930 | Power-saving management method for computer peripheral device and system thereof - A power-saving management method for a computer peripheral device and a system thereof are described, which are applicable to stop the operation of at least one functional electronic element of the computer peripheral device, when the computer peripheral device enters a power-saving mode. The method includes the following steps. A sensor is activated to detect an environmental parameter value of the computer peripheral device. If the environmental parameter value is changed, the functional electronic element is activated to enter an operating mode, and an operation state of the functional electronic element is detected within a counting time. If the functional electronic element does not perform any operation, the sensor is reset and records the finally changed environmental parameter value, and the functional electronic element is made to enter the power-saving mode once again. | 03-10-2011 |
| 20110066869 | Memory Array Power Cycling - In a non-volatile memory system, physically separate power rails are provided from a host system to a NVM device for independently power cycling a controller and memory array in the NVM device. The controller of the NVM device can send a power cycle request signal to the host system over a host channel, or updates a status register in the NVM device. The host system receives and decodes the power cycle request signal, or reads the status register, and performs the power cycle request, which can include power cycling the controller or the memory array in the NVM device, or both. The power cycle request can be based on a power state of the non-volatile memory system, which can be managed by the controller or the host system, or both. | 03-17-2011 |
| 20110066870 | PERIPHERAL CAPABLE OF CONNECTING WITH A HOST AND POWER CONTROL METHOD THEREOF - A peripheral connected with a host via a transmission interface, and a power control method applied to the peripheral includes the steps of: receiving signal data from the host via the transmission interface; generating a power control signal when determining that the host and the peripheral are indifferent statuses; and selectively switching on or switching off an input power of the peripheral according to the power control signal, so as to make the peripheral change its status. | 03-17-2011 |
| 20110072289 | METHOD AND APPARATUS FOR DISCOVERY AND DETECTION OF RELATIONSHIP BETWEEN DEVICE AND POWER DISTRIBUTION OUTLET - For the discovery and detection of the relationships between power consuming devices and power distribution outlets, an aspect of the invention is directed to a system including at least one power consuming device and a plurality of outlets for supplying power, and a method for discovering a relationship between a target device of the at least one power consuming device and at least one outlet of the plurality of outlets which supplies power to the target device. The method comprises applying an external action to the target device to change power consumption of the target device; monitoring power consumption at each of the plurality of outlets; and correlating the applied external action and the monitored power consumption to obtain the relationship between the target device and the at least one outlet which supplies power to the target device. | 03-24-2011 |
| 20110072290 | AUXILIARY POWER SUPPLY, A METHOD OF PROVIDING POWER TO A DATA STORAGE SYSTEM AND A BACK-UP POWER SUPPLY CHARGING CIRCUIT - The invention provides a data storage system, comprising: one or more data storage media; a midplane to which the one or more data storage media are, in use, connected; at least one input/output module for providing control of data transfer between the or each of the data storage media and one or more hosts to which, in use, the data storage system is connected; and a back-up power supply to provide power to the input/output modules in the event of a failure of regular power sources therefor, the back-up power supply being provided separately from the at least one input/output module. | 03-24-2011 |
| 20110072291 | POWER EFFICIENT DATA STORAGE WITH DATA DE-DUPLICATION - A storage system includes a first de-duplication scope comprising a first volume, a first table of hash values corresponding to first chunks of data stored on the first volume, and a first table of logical block addresses of where the chunks of data are stored on the first volume. A second de-duplication scope includes similar information for a second volume. The first scope is used for de-duplicating and storing first data from a first data source and the second scope is used for de-duplicating and storing second data from a second data source. First storage mediums that make up the first volume remain powered off while de-duplication and storage of the second data on the second volume takes place, and second storage mediums that make up the second volume remain powered off while de-duplication and storage of the first data takes place, thereby enabling data de-duplication while saving power. | 03-24-2011 |
| 20110083029 | Controller - A first controller can provide system state information and a second controller can receive the system state information. The second controller can be programmed to control the state of a component. The state of the component can be based on information programmed in the second controller and the system state information. The component can include an off state and an operating state indicated by a signal from the second controller. | 04-07-2011 |
| 20110087911 | DYNAMIC TUNING OF COMPUTING SYSTEMS - Some embodiments of a system and a method to dynamically tune a computing system have been presented. In one embodiment, a processing device running in a computing system monitors usage of one or more hardware components of the computing system to determine a load on each hardware component. The processing device may tune each hardware component based on the load of a respective hardware component determined, and a respective weight associated with the respective hardware component. The hardware components may be tuned to reduce power consumption or to improve performance of the computing system. | 04-14-2011 |
| 20110087912 | POWER SAVING ARCHIVE SYSTEM - A power saving archive system includes a front storage system accessible by clients and one or more back storage systems connected to the front storage system. A client file received by the front storage system is written to one of the back storage systems, while the front storage system stores a reference to the file and deletes the file from the front storage system after a certain time period. Each back storage system enters an inactive state (e.g. a powered off state) after a period of unuse, and can become active again in response to a wakeup command (e.g. a Wake-on-LAN signal) from the front storage system. Upon receiving a file read request from a client, the front storage system wakes up the appropriate back storage system, restores the file from the back storage system, and provides the file to the client. | 04-14-2011 |
| 20110093730 | Portable Electronic Device and Power Management Method - A power management method is to be implemented by a portable electronic device. The portable electronic device is coupled to an expansion device having at least one expansion unit, and supplies power to the expansion device. The power management method includes: (A) configuring the portable electronic device to detect whether a control command is received thereby; (B) configuring the portable electronic device to transmit a control signal corresponding to the control command to the expansion device in response to the control command; and (C) configuring the expansion device to cease supplying power to the at least one expansion unit in accordance with the control signal, thereby saving power. | 04-21-2011 |
| 20110099405 | NONVOLATILE DEVICE - Apparatuses and methods may include receiving a power-down command at a first subsystem comprising a first processor, a first volatile memory, a first nonvolatile memory, a first compressor/decompressor, and a first power control circuit, the first volatile memory being configured to store state data relating to operating conditions of the first subsystem. In response to receipt of the power-down command, the apparatuses and methods may cause the first compressor/decompressor to compress the state data to generate compressed state data and to cause the compressed state data to be stored in the first nonvolatile memory. In response to storage of the compressed state data in the first nonvolatile memory, the apparatuses and methods may cause the first power control circuit to power down the first subsystem. | 04-28-2011 |
| 20110107132 | METHOD FOR DETECTING THE IMPROPER REMOVAL OF ELECTRONIC EQUIPMENT - A method for detecting an improper removal of the electronic equipment. In the method, having received a command from a higher-level device, the electronic equipment (card reader) executes processing operations in accordance with the command. The electronic equipment includes a first RAM for saving electronic information including the confidential data, a detection means (such as a switching circuit) for detecting the improper removal of the electronic equipment, a power supply control IC for shutting off a power supply to the RAM in accordance with a signal coming from the detection means, and a second RAM being separate from and independent of the first RAM. Data saved in the RAM is not deleted even if the power supply is shut off by the power supply control IC. Then, the detection means is activated after the confidential data saved in the first RAM is copied to the second RAM. | 05-05-2011 |
| 20110113275 | MICROCOMPUTER - IO buffers that operate with an IO power supply system and cut cells that isolate the IO buffers from each other are disposed on the periphery of an always-on power supply area and a power supply cut-off available area. A signal indicating the holding of an IO output(s) output from the always-on power supply area is wired so as to go round the IO buffers and the cut cells. The cut cell includes a level shifter that operates with an IO power supply system. The cut cell shifts the level of signal indicating the holding of IO output so that the signal level conforms to the power supply system of IO buffers, and outputs the resultant signal to the IO buffers. | 05-12-2011 |
| 20110131438 | Saving Power by Powering Down an Instruction Fetch Array Based on Capacity History of Instruction Buffer - Mechanisms for saving power by powering down an instruction fetch array based on capacity history information of an instruction buffer are provided. The mechanisms operate to receive a current access to an instruction buffer of a processor. The current access is a fetch of a group of one or more instructions to be stored in the instruction buffer. A determination is made, for one or more prior accesses occurring prior to the current access, if a predetermined pattern of capacity availability of the instruction buffer indicates that the instruction buffer is likely to have available capacity to store the group of one or more instructions of the current access. An instruction fetch unit array is powered down in response to a determination that the instruction buffer is not likely to have available capacity to store the group of one or more instructions of the current access. | 06-02-2011 |
| 20110138211 | APPARATUS AND METHOD FOR USING MULTIPLE MEMORIES IN A PORTABLE TERMINAL - An apparatus and method for using a plurality of memories in a portable terminal are provided. The method includes detecting insertion of a first memory card, determining whether a second memory card is inserted, and controlling power for the first memory card according to whether the second memory card is inserted. | 06-09-2011 |
| 20110154083 | Processor and Memory Folding for Energy Management - A method, system and computer-usable medium are disclosed for managing power consumption in information processing systems. Processing resources are successively folded, allowing them to be placed into deeper and deeper power saving states while maintaining the ability to respond to new processing loads without exposing the latency of the deeper power saving states as they are unfolded. Before a deeper power saving state can be used, there must be sufficient processing resources in the prior power saving state to mask the latency of bringing a processing resource out of the deeper power saving state. | 06-23-2011 |
| 20110154084 | EFFICIENT SERVICE ADVERTISEMENT AND DISCOVERY IN A PEER-TO-PEER NETWORKING ENVIRONMENT - A local device broadcasts a service advertisement in a wireless network, where the service advertisement includes one or more service identifiers (IDs) identifying one or more services being advertised and an availability schedule of the local device. Optionally, the local device reduces power to at least a portion of the local device and wakes up at a time according to the availability schedule. The local device listens in the wireless network according to the availability schedule of the local device. In response to a service request received from a remote device during the availability window, the local device transmits a service response to the remote device. The service request includes one or more service IDs identifying one or more services being inquired by the remote device and the service response includes detailed information associated with one or more services identified by the one or more service IDs. | 06-23-2011 |
| 20110161710 | LAPTOP COMPUTER AND HINGE MODULE WITH ANGLE DETECTOR THEREOF - A laptop computer includes a main body, a display device, a hinge module and an angle detector. The hinge module is pivotally interconnected between the display device and the main body such that the display device is swiveled relative to the main body to be folded against or unfolded away from the main body. The hinge module includes a first hinge component and a second hinge component. The first hinge component is secured to the main body. The second hinge component is pivotally connected with the first hinge component and includes an end secured to the display device. The angle detector is coupled with an opposite end of the second hinge component for measuring a rotation angle of the second hinge component. | 06-30-2011 |
| 20110161711 | Control Device, Control Method, and Recording Medium - Power consumption by an external device can be reduced while controlling the external device by a generic device driver even when the generic device driver does not have a power management function for the external device. When a command generated by operation of a POS application | 06-30-2011 |
| 20110167288 | Information processing apparatus and controlling method thereof - An information obtaining unit provided inside a system controller obtains operation states of processing units and processing units respectively of cabinets, calculates an average utilization of CPUs of the processing units, and determines whether or not any processing unit can be disconnected. When a hardware resource can be disconnected as a result of the determination, an electric power control determining unit calculates possible combinations of hardware resources to be disconnected and performs a disconnection by a cabinet unit when there is a combination enabling a disconnection by a cabinet unit. | 07-07-2011 |
| 20110173478 | Scheduler with voltage management - There is provided a method of scheduler assisted power management for semiconductor devices. By accessing and analyzing workload data for tasks to be completed, a scheduler may provide finer grained control for determining and implementing an efficient power management policy. In this manner, tasks with completion deadlines can be allocated sufficient resources without wasteful power consumption resulting from ramping up of performance through overestimating of voltage or frequency increases. Additionally, power management may be planned for longer periods, rather than looking only at immediate data to be processed and constantly fluctuating voltage and frequency. In this manner, power management can run more smoothly and efficiently compared to conventional means of power management that ignore data from a scheduler when determining power management policy. | 07-14-2011 |
| 20110173479 | DATA PROCESSING APPARATUS - A data processing apparatus according to the present invention is capable of writing video and/or audio data to a storage medium. The data processing apparatus includes: a power controller for controlling powering on or off; a signal processing circuit for generating data; and a drive section for writing the generated data to the storage medium. In response to a powering-off instruction, the power controller stops supplying power to the drive section but continues to supply power to the signal processing circuit and the power controller itself. Since hardware elements remain energized, they do not need to perform initialization operations when the apparatus is powered on. Similarly, corresponding software elements are also in an operable state, and therefore do not need to perform initialization processes. Therefore, the signal processing circuit can immediately start processing thereafter. | 07-14-2011 |
| 20110185210 | Method and Arrangement for Saving Energy In Microprocessors - The invention relates to a method for operating an electronic system, wherein the energy consumption of at least parts of the system is regulated such that on the basis of at least a time-related curve of the current (IFE | 07-28-2011 |
| 20110213997 | VIRTUAL MACHINE POWER CONSUMPTION MEASUREMENT AND MANAGEMENT - Embodiments of the virtual machine power metering system and method measure the power consumption of individual virtual machines. Power meter measurements for a physical host server are converted into individual virtual machine power meters that measure the power consumption of each individual virtual machine residing on the host server. The virtual machine power consumption is computed by generating a power model using the total power consumption of the host server and resource utilization for a virtual machine. Optimal power model coefficients are computed using the power model. The energy used by the virtual machine is computed using one of two embodiments. Embodiments of the system and method also can be used to obtain the power consumption for a specific activity (such as a service, request, or search query). In addition, the virtual machine power metering can be used for virtual machine power capping to allow power oversubscription in virtualized environments. | 09-01-2011 |
| 20110213998 | System and Method for Power Optimization - A technique for reducing the power consumption required to execute processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and second set of cores comprising one or more slow cores. A processing mode of the processing complex can switch between a first mode of operation and a second mode of operation based on one or more of the workload characteristics, performance characteristics of the first and second sets of cores, power characteristics of the first and second sets of cores, and operating conditions of the processing complex. A controller causes the processing operations to be executed by either the first set of cores or the second set of cores to achieve the lowest total power consumption. | 09-01-2011 |
| 20110213999 | SYSTEM AND METHOD OF SUPPLYING AN ELECTRICAL SYSTEM WITH DIRECT CURRENT - A system for supplying an electrical system with direct current, the system including at least two direct current power supply devices each having means of electrical connection to an alternating current power supply source and an AC/DC converter of alternating current into direct current, a module for managing the power supply of the electrical system which, after reception of an information of failure of a first active power supply device, transmits a command to start up a second inactive power supply device and a back up electrical energy storage device electrically by-pass connected between the power supply devices and the electrical system. The management module also receives the information of failure from the back up device and/or from the electrical system and transmits the command to start up the second power supply device during a discharge phase of the back up device. | 09-01-2011 |
| 20110219252 | Methods and Systems for Power Management in a Data Processing System - Methods and systems for managing power consumption in data processing systems are described. In one embodiment, a data processing system includes a general purpose processing unit, a graphics processing unit (GPU), at least one peripheral interface controller, at least one bus coupled to the general purpose processing unit, and a power controller coupled to at least the general purpose processing unit and the GPU. The power controller is configured to turn power off for the general purpose processing unit in response to a first state of an instruction queue of the general purpose processing unit and is configured to turn power off for the GPU in response to a second state of an instruction queue of the GPU. The first state and the second state represent an instruction queue having either no instructions or instructions for only future events or actions. | 09-08-2011 |
| 20110219253 | System and Method for Portable Power Source Management - A host system is provided comprising including a power source configured to provide power to a first auxiliary device; and a host power manager configured to monitor an available power level of the power source; and direct the power source to reduce power provided to the first auxiliary device based upon the available power level, wherein the reduced power is greater than zero. | 09-08-2011 |
| 20110231686 | MANAGEMENT APPARATUS AND MANAGEMENT METHOD - Power savings for a storage apparatus while preventing a drop in response performance is achieved. When the storage area supplied by the memory apparatus groups is not accessed by the host apparatus for a predetermined period, stop operation is performed for each of the memory apparatuses configuring the memory apparatus groups. The management apparatus groups, among the resources, resources with overlapping time zones for which the number of accesses by the application is zero, in the same group, and maps each of the groups to the memory apparatus groups respectively. At this time, if the number of accesses in each of the time zones of the groups of resources mapped to the memory apparatus groups exceeds the reference value of the memory apparatus groups, the group is divided into a plurality of groups and each of the plurality of groups is mapped to the memory apparatus groups. | 09-22-2011 |
| 20110231687 | MEMORY SYSTEM AND SERVER SYSTEM - According to one embodiment, a memory system includes a NAND flash memory includes a memory cell array includes pages, and a volatile data register with a storage capacity of one page, and configured to write page data to the memory cell array through the data register, each of the pages includes nonvolatile memory cells and being a unit of data write, a volatile RAM, and a controller includes a power saving mode in which power consumption of the RAM is reduced, and configured to transfer data of the RAM to the data register before entering the power saving mode. | 09-22-2011 |
| 20110231688 | ARRANGEMENT AND METHOD FOR CONTROLLING POWER MODES OF HARDWARE RESOURCES - A circuit arrangement and method of executing program code which utilize power control instructions capable of dynamically controlling power dissipation of multiple hardware resources during execution of a program by a processor. The processor configured to process such power control instructions and to maintain the power modes of the multiple hardware resources to that specified in an earlier-processed power control instruction, such that subsequently-processed instructions will be processed while the power modes of the multiple hardware resources are set to that specified by the earlier-processed power control instruction. | 09-22-2011 |
| 20110239026 | POWER EFFICIENT WAY OF OPERATING MOTION SENSORS - Systems and methods are described for operating motion sensors in a power-efficient manner. An example technique described herein includes obtaining, at a motion sensor, first indications of sensed motion of a device associated with the motion sensor; integrating, at the motion sensor, the first indications of the sensed motion to obtain integrated motion information; generating, at the motion sensor, second indications of the integrated motion information; and sampling, at a processor disparate from the motion sensor, selective ones of the second indications. Another example technique includes obtaining a first indication of a motion state anomaly associated with motion of a mobile device and causing a gyroscope associated with the mobile device to transition between a first operating mode and a second operating mode in response to the first indication, where the first operating mode is a reduced-power mode compared to the second operating mode. | 09-29-2011 |
| 20110246803 | PERFORMING POWER MANAGEMENT BASED ON INFORMATION REGARDING ZONES OF DEVICES IN A SYSTEM - One or more target components of a system that are not associated with an active initiator are identified, where the identifying is based on information regarding zones of devices in the system. The devices in each of the zones include at least one initiator and at least one target component accessible by the initiator. The information describes accessibility of devices between the zones. A power management procedure is performed with respect to the identified one or more target components that are not associated with an active initiator to place the identified one or more target components in a reduced power state. | 10-06-2011 |
| 20110252260 | Reducing Power Requirements of a Multiple Core Processor - A mechanism is provided for reducing power consumed by a multi-core processor. Responsive to a number of properly functioning processor cores being more than a required number of processor cores in a multi-core processor, the power consumption measurement module determines a number of the properly functioning processor cores to disable. The power consumption measurement module initiates an equal amount of workload to be processed by each of the properly functioning processor cores. The power consumption measurement module determines power consumed by each of the properly functioning processor cores. The power consumption measurement module deactivates one or more of the properly functioning processor cores that have maximum power in order that the number of properly functioning processor cores deactivated is equal to the number of properly functioning processor cores to disable. | 10-13-2011 |
| 20110264940 | ADAPTIVE ENERGY-EFFICIENT LOCATION DETERMINATION - Managing use of a location sensor on a computing device for energy efficiency. The location sensor is briefly initialized to measure the signal quality. The measured signal quality is compared to pre-defined signal criteria values. The signal criteria values correspond to acceptable energy consumption, for example. If the signal criteria values are satisfied, location information for the computing device is obtained. Otherwise, the location sensor is disabled without obtaining the location information. In some embodiments, a lower-energy location sensor is used to obtain location information to determine whether to enable a higher-energy location sensor based on expected energy consumption. | 10-27-2011 |
| 20110264941 | APPARATUS AND METHOD FOR REDUCING POWER CONSUMPTION CAUSED BY COMMUNICATION BETWEEN PROCESSORS IN PORTABLE TERMINAL - An apparatus and method for reducing power consumption in a portable terminal are provided. The apparatus includes a display unit for displaying at least one indicator that indicates status information measured by a slave processor, a master processor for controlling one of ON and OFF of the display unit and for providing image data to the display unit, and the slave processor for transmitting to the master processor indicator update information for updating the at least one indicator, wherein transmission to the master processor of the indicator update information is discontinued if the status of the display unit is OFF. | 10-27-2011 |
| 20110264942 | Method and Apparatus for Controlling Standby Power - Reducing standby power of an information apparatus is described. In one aspect, a laptop PC is equipped with an Ethernet controller. The laptop PC operates in an intermittent manner and a DC/DC converter supplies power to the Ethernet controller. The laptop PC determines whether the Ethernet controller is connected to a network by a cable in a time Twake during which the converter is on. When it is determined that the Ethernet controller is connected, the laptop PC maintains operation of the DC/DC converter until the Ethernet controller is disconnected. When it is determined that the Ethernet controller is not connected, the laptop PC stops operation of the DC/DC converter during a time Tsleep and resumes the operation thereof when a setting time by a timer elapses. The DC/DC converter supplies power to the Ethernet controller when it is actually connected to the network. Other aspects are described. | 10-27-2011 |
| 20110264943 | STORAGE CONTROL DEVICE - The storage control device of the present invention reduces the power consumption amount by stopping the transmission of power to enclosures that are not accessed. A plurality of additional enclosures is switch-connected via backend switches to a base enclosure. Drives that have not been accessed for a predetermined time or more undergo spin-down. When all of the drives in the enclosure enter a spin-down state, the supply of power from the power supply in the enclosure to the respective drives is stopped. The base enclosure that manages the system constitution of the storage control device turns OFF the switch connected to the enclosure when all of the drives in a certain enclosure have spun down. The transmission of power to this enclosure is accordingly stopped. | 10-27-2011 |
| 20110276817 | MEMORY POWER MANAGER - Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits. | 11-10-2011 |
| 20110283128 | System and Method for Information Handling System Storage Device Power Consumption Management - A storage device, such as a hard disk drive or solid state drive, reduces energy consumption by entering a reduced power state after an inactivity time where the inactivity time is set based upon I/O commands received at the storage device. For example, where commands received at a storage device are characterized in a predetermined way in terms of read commands, such as a last received command as a read command or a ratio of read commands versus write commands, a first inactivity time is applied, while commands characterized in a predetermined way in terms of write commands have a second inactivity time applied. Using a greater inactivity time during read activities than during write activities provides improved performance with reduced power consumption. | 11-17-2011 |
| 20110283129 | SYSTEM AND METHOD FOR OPERATING AN ELECTRONIC DEVICE HAVING AN HDMI PORT THAT IS SHARED BETWEEN HDMI SOURCE FUNCTION AND AN HDMI SINK FUNCTION OF THE ELECTRONIC DEVICE - A system and method for operating an electronic device having a High-Definition Multimedia Interface port that is shared between an HDMI source function and an HDMI sink function of the electronic device utilizes detecting whether an external HDMI device that is attached to the HDMI port is one of an HDMI source and an HDMI sink. If the external HDMI device is detected as being an HDMI source, the HDMI sink function of the electronic device is enabled. If the external HDMI device is detected as being an HDMI sink, the HDMI source function of the electronic device is enabled. | 11-17-2011 |
| 20110296221 | METHOD AND SYSTEM FOR INTEGRATED CIRCUIT POWER SUPPLY MANAGEMENT - A method and system for power supply management in an integrated chip selectively manages the power supplied to the various circuits within the integrated circuit. The integrated circuit includes a combinational logic block, a memory block, a power supply block, and a control block. The power supply block includes multiple power regulators for generating power supply potentials of various magnitudes. The control block receives a power down signal, a clock disable signal, and a temperature threshold signal, and generates control signals for controlling the magnitude of the potential of the power supplied to the combinational logic block and the memory block by the power supply block. | 12-01-2011 |
| 20110296222 | DYNAMIC AND IDLE POWER REDUCTION SEQUENCE USING RECOMBINANT CLOCK AND POWER GATING - Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed. | 12-01-2011 |
| 20110296223 | Electronic Apparatus and Control Method of the Electronic Apparatus - According to one embodiment, an electronic apparatus includes a display, an operating module, a power saving module, a sensor and a controller. The power saving module is configured to turn off a screen of the display when a non-operating period of the operating module reaches a reference period. The sensor is configured to detect a vibration. The controller is configured to change the reference period from a first value given as the initial value to a second value longer than the first value when the sensor detects a vibration. | 12-01-2011 |
| 20110307730 | Power-Aware Thread Scheduling and Dynamic Use of Processors - Techniques and apparatuses for providing power-aware thread scheduling and dynamic use of processors are disclosed. In some aspects, a multi-core system is monitored to determine core activity. The core activity may be compared to a power policy that balances a power savings plan with a performance plan. One or more of the cores may be parked in response to the comparison to reduce power consumption by the multi-core system. In additional aspects, the power-aware scheduling may be performed during a predetermined interval to dynamically park or unpark cores. Further aspects include adjusting the power state of unparked cores in response to the comparison of the core activity and power policy. | 12-15-2011 |
| 20120005512 | METHOD, SYSTEM AND APPARATUS FOR DYNAMIC BUFFER MANAGEMENT FOR POWER SAVING - A method and apparatus may detect an event related to an external device communicating with a host controller. One or more external device characteristics of the external device may be determined. One or more physical memory cells for the host controller may be modified based on the one or more external device characteristics. | 01-05-2012 |
| 20120011387 | OPERATION METHOD FOR HOST APPARATUS TO SAVE POWER CONSUMPTION - An operation method for a host apparatus is provided. When a peripheral device connects to the host apparatus through a data transmission interface, the host apparatus is checked whether or not accessing data with the peripheral device. When the host apparatus doesn't access data with the peripheral device continuing a predetermined time, the peripheral device is shut down to make the peripheral device entering a power saving mode from a normal operation mode but an interrupt operation of the data transmission interface is still activated. When the host apparatus need to access data with the peripheral device being in the power saving mode, the interrupt operation is triggered for waking the peripheral device up to revive the peripheral device working under the normal operation mode. | 01-12-2012 |
| 20120030492 | SERVER SYSTEM - The present invention provides a server system comprising a first group of mainboard modules and a second group of mainboard modules, each of the first and second groups of mainboard modules including a plurality of mainboard modules. Each mainboard module includes a mainboard and a daughter board electrically connected to the mainboard; a first adaptor and a second adaptor; a hard disk array including a hard disk backplane and a plurality of hard disks, wherein the hard disk backplane is electrically connected to the first adaptor and the second adaptor; a first power control board and a second power control board respectively connected to at least one power supply, wherein the first power control board and the second power control board are electrically connected to the hard disk array; and a management board electrically connected to the first adaptor and the second adaptor. | 02-02-2012 |
| 20120030493 | Power Capping System And Method - A system, and a corresponding method, for temporarily capping power consumption includes a mechanism for determining total power consumption by a number of components, a mechanism for disconnecting and reconnecting power to one or more of the components, and a mechanism for determining when to disconnect and reconnect power to the components. | 02-02-2012 |
| 20120036383 | POWER SUPPLY FOR NETWORKED HOST COMPUTERS AND CONTROL METHOD THEREOF - A power supply is used in combination with networked first and second hosts with a virtual machine implemented on the first host. The power supply is comprised of: a memory; an outlet part linked with outlets respectively supplying electricity to the hosts; a communication interface linked with the hosts; a controller linked with the memory, the outlet part and the communication interface; a migration process located on the memory, wherein the migration process causes the communication interface to send a migration instruction to the first host, the migration instruction causing migration of the virtual machine to the second host; and a shut-down process located on the memory, wherein the shut-down process causes the communication interface to send a shut-down instruction to the first host, the shut-down instruction causing shut-down of the first host. | 02-09-2012 |
| 20120036384 | Reducing Power Consumption While Synchronizing A Plurality Of Compute Nodes During Execution Of A Parallel Application - Methods, apparatus, and products are disclosed for reducing power consumption while synchronizing a plurality of compute nodes during execution of a parallel application that include: beginning, by each compute node, performance of a blocking operation specified by the parallel application, each compute node beginning the blocking operation asynchronously with respect to the other compute nodes; reducing, for each compute node, power to one or more hardware components of that compute node in response to that compute node beginning the performance of the blocking operation; and restoring, for each compute node, the power to the hardware components having power reduced in response to all of the compute nodes beginning the performance of the blocking operation. | 02-09-2012 |
| 20120042188 | SEMICONDUCTOR DEVICE AND POWER SUPPLY CONTROL METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device includes an internal circuit, a power supply control circuit which controls supply of a power supply to the internal circuit upon receipt of a first control signal, and a control signal generation circuit which outputs the first control signal upon receipt of a second control signal. The control signal generation circuit does not deactivate the first control signal when an inactive period of the second control signal is equal to or less than a first period and deactivates the first control signal when the inactive period of the second control signal is more than the first period. | 02-16-2012 |
| 20120042189 | METHOD AND DEVICE FOR REDUCING THE ELECTRICAL CONSUMPTION OF AN ETHERNET INTERFACE - The present invention relates to a method for reducing the electricity consumption of an Ethernet interface involving switching to a low power mode when no activity is detected on the physical layer thereof for a first predetermined duration (T_L1_INACTIVE). The method is characterised in that the interface also switches to a low power mode when no activity is detected on the MAC layer thereof for a second predetermined duration (T_L2L). | 02-16-2012 |
| 20120042190 | PICTURE PROCESSING USING A HYBRID SYSTEM CONFIGURATION - A system is presented that is configured to reduce power consumption when performing processing tasks. The system includes a first processing entity capable of performing a set of operations, and a second processing entity configured to consume less power than the first processing entity and capable of performing a subset of operations that is part of the set of operations. During system operation, the second processing entity is configured to perform the subset of operations instead of the first processing entity. | 02-16-2012 |
| 20120047382 | Script engine for control of power management controllers - A power management IC (PMIC) and methods thereof have been achieved wherein the PMIC invented supports multiple applications while having a high degree of flexibility and allowing a small built and a low power consumption. An embedded script engine on an internal communication bus of the PMIC replaces hard-wired sequencers and control interfaces or using processors as utilized in prior art. The script engine reads instructions from a non-volatile memory as e.g. a one-time programmable (OTP) memory. Furthermore a RAM can be provided to store executable instructions loaded from a host. Moreover a FIFO process is provided if instructions or TAGs are received while a previous script is being exercised. Any type of power supplies, output GPIO or other function could be controlled also by the Script Engine. The invention is also applicable to any other kind of power management circuits. | 02-23-2012 |
| 20120047383 | Mechanism for Manager and Host-Based Integrated Power Saving Policy in Virtualization Systems - A mechanism for a manager and host-based integrated power saving policy in virtualization systems is disclosed. A method of the invention includes receiving configuration and power information of a host machine from a management agent on the host machine, performing a macro-level power saving scheduling algorithm that takes into consideration the received configuration and power information of the host machine, and requesting that the host machine alter a number of active running CPU cores as part of the macro-level power saving scheduling algorithm. | 02-23-2012 |
| 20120079303 | METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION IN A PROCESSOR BY POWERING DOWN AN INSTRUCTION FETCH UNIT - An apparatus and method are described for reducing power consumption in a processor by powering down an instruction fetch unit. For example, one embodiment of a method comprises: detecting a branch, the branch having addressing information associated therewith; comparing the addressing information with entries in an instruction prefetch buffer to determine whether an executable instruction loop exists within the prefetch buffer; wherein if an instruction loop is detected as a result of the comparison, then powering down an instruction fetch unit and/or components thereof; and streaming instructions directly from the prefetch buffer until a clearing condition is detected | 03-29-2012 |
| 20120079304 | PACKAGE LEVEL POWER STATE OPTIMIZATION - Methods and apparatus to optimize package level power state usage are described. In one embodiment, a processor control logic receives a request to enter a lower power consumption state (such as a package level deeper sleep state). The control logic determines the time difference or delta between a last entry into the lower power consumption state and the current time. The control logic then causes the flushing of a last level cache based on a comparison of the time difference and a threshold value corresponding to the lower power consumption state. Other embodiments are also claimed and disclosed. | 03-29-2012 |
| 20120084592 | POWER MANAGEMENT SYSTEM, METHOD THEREOF AND STORAGE MEDIUM - A power management method for a host computer, which is coupled to a USB hub, is provided. It prevents the USB hub from entering into a suspend mode while the host computer stays in a host active state. The method includes the following steps: a filter driver is loaded. When detecting a specified event, the filter driver issues a device sleep IRP request to control the USB hub enter into a suspend mode. Wherein the specified event represents that the host computer enters into a host sleep state. | 04-05-2012 |
| 20120096295 | METHOD AND APPARATUS FOR DYNAMIC POWER CONTROL OF CACHE MEMORY - The present invention provides a method and apparatus for dynamic power control of a cache memory. One embodiment of the method includes disabling a subset of lines in the cache memory to reduce power consumption during operation of the cache memory. | 04-19-2012 |
| 20120096296 | SYSTEM FOR REDUCING POWER CONSUMPTION IN AN ELECTRONIC CHIP - A system for reducing power consumption in an electronic device comprising at least one electronic chip comprises a plurality of local access network (LAN) ports, a transceiver coupled between the LAN ports and the electronic chip, a PLA device, and a central processing unit (CPU). The CPU is configured to power off the electronic chip in response to a period of inactivity on the LAN ports and power on the electronic chip in response to a signal from the PLA device. | 04-19-2012 |
| 20120102350 | Reducing Energy Consumption and Optimizing Workload and Performance in Multi-tier Storage Systems Using Extent-level Dynamic Tiering - Embodiments of the invention relate to reducing energy consumption and optimizing workload and performance in multi-tier storage systems using extent-level dynamic tiering. An aspect of the invention includes a receiving data access information of a storage extent stored in a storage system and utilization information of storage devices in the storage system. The storage system includes a plurality of storage tiers and each of the plurality of storage tiers is made up of a plurality of storage devices. Storage resources required for each of the plurality of the storage tiers to satisfy the storage extent's performance and capacity requirements are estimated based on the data access information. One storage tier that would incur the lowest power consumption to the storage system for satisfying the storage extent's performance and capacity requirements is determined. The one storage tier is determined by calculating the amount of power that would be consumed by the storage extent in each of the plurality of storage tiers based on the estimated storage resources. At least one storage device in the one storage tier that has available storage resources that would satisfy the storage extent's performance and capacity requirements is determined based on the data access information and utilization information. The storage extent is allocated to the one storage tier and to one storage device (among the at least one storage device) that has the least amount of available storage capacity. | 04-26-2012 |
| 20120110360 | APPLICATION-SPECIFIC POWER MANAGEMENT - An application-specific power management technique may establish a separate power-down interval for one or more applications based on user interaction with the one or more applications. In some implementations, during use of a particular application, when a management component determines that a period of user inactivity has become greater than or equal to the particular power-down interval established for the particular application, the management component may initiate a power down of one or more components, such as a display. | 05-03-2012 |
| 20120124405 | System and Method for Energy Savings on a PHY/MAC Interface for Energy Efficient Ethernet - A system and method for energy savings on a PHY/MAC interface for energy efficient Ethernet. Power savings for a PHY due to low-link utilization can also be realized in the higher layer elements that interface with the PHY. In one embodiment, subrating is implemented on a MAC/PHY interface to match a subrating of the PHY with a remote link partner. This subrating is less than the full capacity rate and can be zero. | 05-17-2012 |
| 20120137156 | CONTROLLING CIRCUIT WITH POWER SAVING MECHANISM AND ERRONEOUS WAKE-UP PREVENTING MECHANISM AND METHOD THEREOF - A controlling circuit supporting a power saving mechanism includes: a transmitting interface arranged to perform a signal transmission with a specific controlling circuit; and a setting unit coupled to the transmitting interface. The setting unit is arranged to control the specific controlling circuit to operate in the power saving mechanism. | 05-31-2012 |
| 20120137157 | DATA INTERFACE POWER CONSUMPTION CONTROL - Apparatus and techniques relating to data interface power consumption control are disclosed. Components of a data transfer module may be selectively moved between their normal operating states and reduced power states at times when the data transfer module is not to be used for transferring data. Decisions as to particular components that are to be moved to their reduced power states may be based on respective timing characteristics of the components and/or respective power consumption characteristics of the components, for example. In some embodiments, an action may be performed to reduce a powering up time of the data transfer module when normal operation of the data transfer module is to resume. In the case of a multiple-connection interface having respective data transfer modules for each connection, the interface may be partially shut down by moving a subset of the data transfer modules into reduced power states. | 05-31-2012 |
| 20120151236 | METHOD, APPARATUS AND SYSTEM FOR POWER MANAGEMENT THROUGH BACKLIGHT AND OTHER PERIPHERAL CONTROLS - A method, apparatus and system for power management in a mobile computing device is provided. In one aspect, the mobile computing device comprises a display with a backlight that is power by a power supply under the control of a processor. The mobile computing device is also configured to execute a web browser or other application that access a network resource. Activation of the backlight is controlled in coordination with the network resource in order to manage drain of power from the power supply. | 06-14-2012 |
| 20120151237 | ELECTRONIC DEVICE AND POWER MANAGEMENT METHOD THEREOF - A method for managing power of an electronic device receives a power signal of a peripheral device of the electronic device, determines if a data signal of the peripheral device is received at a preset time interval, and sends a time record command to a timer of the electronic device if the data signal is not received to obtain a recorded time of the electronic device. The method further displays an idle status of the peripheral device if the recorded time is greater than a first preset value, and stops supplying power to the peripheral device if the recorded time is greater than a second preset value. | 06-14-2012 |
| 20120151238 | REDUCING POWER CONSUMPTION IN MEMORY LINE ARCHITECTURE - A memory link architecture (MLA) comprises a multi-port memory device, a memory controller, and a nonvolatile memory. The MLA can perform a sleep switching control operation or a memory management operation to reduce power consumption based on commands received from a host processor and/or automatic control methods. | 06-14-2012 |
| 20120151239 | Power-Saving Device for Universal Serial Bus Modem Apparatus and Method Thereof - A power-saving apparatus for universal serial bus (USB) modem equipment is disclosed in the present invention, which includes: a personal computer and USB Modem equipment. Accordingly, a power-saving method for USB Modem equipment is provided in the present invention, which includes: regularly detecting whether selective suspending is allowed, if not allowed, processing a received request from an application program, and if allowed, transmitting an instruction for entering the selective suspending state to the USB Modem equipment; after receiving the instruction for entering the selective suspending state, the USB Modem equipment entering the selective suspending state. Thus, the present invention can realize that the USB Modem equipment enters the power-saving state in the idle period and resumes the work state when receiving a service request. | 06-14-2012 |
| 20120159224 | HARDWARE ASSISTED PERFORMANCE STATE MANAGEMENT BASED ON PROCESSOR STATE CHANGES - A processor is configured to support a plurality of performance states and idle states. The processor includes a first programmable location associated with a first idle state and configured to store first entry performance state (P-State) information. The first entry P-State information identifies a first entry P-State. The processor is configured to receive a request to enter the first idle state, retrieve the first entry P-State information and enter the first entry P-State. The processor may include a second programmable location associated with the first idle state and configured to store first exit P-State information. The first exit P-State information identifies a first exit P-State. The processor may be configured to receive a request to exit the first idle state, retrieve the first exit P-State information and enter the first exit P-State. | 06-21-2012 |
| 20120166851 | SYSTEMS AND METHODS FOR SHARING A WIRELESS ANTENNA IN A HYBRID ENVIRONMENT - Embodiments operating shared peripherals in a hybrid computing system are described. Embodiments control a shared wireless antenna variously between a primary system and a secondary system, where the secondary system is detachable from the primary system and operates as an independent computing device in the disconnected state, while operating as a display device in the connected state. | 06-28-2012 |
| 20120166852 | METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING IMPROVED PROCESSOR CORE DEEP POWER DOWN EXIT LATENCY BY USING REGISTER SECONDARY UNINTERRUPTED POWER SUPPLY - Embodiments of the invention relate to improving exit latency from computing device processor core deep power down. Processor state data may be maintained during deep power down mode by providing a secondary uninterrupted voltage supply to always on keeper circuits that reside within critical state registers of the processor. When these registers receive a control signal indicating that the processor power state is going to be reduced from an active processor power state to a zero processor power state, they write critical state data from the critical state register latches to the keeper circuits that are supplied with the uninterrupted power. Then, when a register receives a control signal indicating that a processor power state of the processor is going to be increased back to an active processor power state, the critical state data stored in the keeper circuits is written back to the critical state register latches. | 06-28-2012 |
| 20120173909 | CONTROLLING AUXILIARY POWER TO LOGIC DEVICES - A system may include multiple logic devices, a power input, and a logic controller. The power input may be configured to provide the auxiliary power to the logic devices. The logic controller may be configured to select a group of the logic devices for disabling the auxiliary power based, at least in part, on priority levels asserted by each of the logic devices, and disable the auxiliary power to the selected group of logic devices. | 07-05-2012 |
| 20120179928 | OPTIMIZED POWER SAVINGS IN A STORAGE VIRTUALIZATION SYSTEM - Various embodiments for optimized power savings in a storage virtualization system are provided. First meta data for physical resources which describes a power status of a storage resource in one of a powered-on/read-write, powered-on/read only, and powered-off power state is created. Second meta data for each of the physical storage resources which determines an actual performance of the physical storage resources and which supports optimization of a powering-on and a powering-off of the physical storage resources is created. A write request from one of a host and application to logical and virtual storage resource is executed. | 07-12-2012 |
| 20120185719 | POWER MANAGEMENT WITHIN AN INTEGRATED CIRCUIT - An integrated circuit can include a processor system configured to execute program code, wherein the processor system is hard-wired. The IC also can include programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system and can be configured to implement a power off procedure under the control of the processor system. | 07-19-2012 |
| 20120192002 | INFORMATION PROCESSING APPARATUS AND CONTROL METHOD THEREOF - One embodiment provides an information processing apparatus, including: a main controller; a sub controller configured to supply power to the main controller; a first operation input module configured to issue an operation signal to cause the sub controller to start power supply to the main controller, in a power-off state; and a second operation input module configured to accept an operation input, wherein the sub controller is switchable into a forcibly locked state where the power supply to the main controller is not started in response to the operation signal, the sub controller being switchable into the forcibly locked state, according to the operation input from the second operation input module. | 07-26-2012 |
| 20120204051 | POWER SAVING SYSTEM AND POWER SAVING METHOD - Devices and interior equipments that need not operate in a server room are stopped and thereby power saving can be achieved. More specifically, consolidation of virtual machines (VMs) providing a service is performed to concentrate processing in a server in a certain rack among a group of racks in the server room, a rack having no operating server is stopped, processing by an interior equipment controlling the rack and its circumference environment also is stopped or adjusted, and thereby power saving can be achieved. | 08-09-2012 |
| 20120210155 | STORING CONTEXT INFORMATION PRIOR TO NOT SUPPLYING POWER TO A PROCESSOR | 08-16-2012 |
| 20120216064 | HOT-PLUGGING OF MULTI-CORE PROCESSOR - A method of hot-plugging a multi-core processor comprises monitoring respective workload levels of multiple processor cores, hot-plugging off a first core among the processor cores upon determining that its workload level has fallen below a lower reference value, and hot-plugging on a second core among the processor cores upon determining that its workload level has risen above an upper reference value while the first core is hot-plugged off. | 08-23-2012 |
| 20120226928 | STORAGE DEVICE - The present invention makes is possible to appropriately set the power saving control of the storage device from the management device of the storage device. In addition, the storage device executes control of the power saving for the magnetic disk device after ensuring consistency between an instruction from the administrator and the operating state of the magnetic disk device in the storage device. | 09-06-2012 |
| 20120233484 | METHOD OF, AND APPARATUS FOR, POWER MANAGEMENT IN A STORAGE RESOURCE - There is provided a method and apparatus for power management in a storage resource. The storage resource comprises at least one RAID array including a plurality of physical drives. The method comprises: determining a reduced number of physical drives within a RAID array upon which data is to be concentrated; moving data stored on said RAID array and/or targeting data written to said RAID array to one or more of said reduced number of physical drives such that said data is concentrated on said reduced number of physical drives in said RAID array; and selectively applying power management logic to enable, based on at least one power management criterion, one or more physical drives in said RAID array to be powered down or to be supplied with reduced power. | 09-13-2012 |
| 20120246504 | ELECTRONIC DEVICE FOR DETECTING A TYPE OF A CHARGER DEVICE DURING A SLEEP MODE - An electronic device includes a microcontroller (MCU) and a central processing unit (CPU). The CPU enters a sleep mode. The MCU determines whether a charger device is inserted in the electronic device according to whether power is supplied from the charger device, and wakes up the CPU when the charger device is inserted in the electronic device. After being awakened, the CPU detects a type of the charger device, and adjusts charging current from the charger device to the electronic device according to the type of the charger device. | 09-27-2012 |
| 20120246505 | HSIC COMMUNICATION SYSTEM AND METHOD - A High Speed Inter Chip (HSIC) system and method for minimizing power consumption by controlling the state of the HSIC module through a control line are provided. The method between a host and a slave includes transitioning, when no communication request exists for a first reference time in an active state where all functions of the HSIC modules are enabled, to a suspend state where least functions used for maintaining a communication link of the HSIC modules and transitioning, when no communication request exists for a second reference time in the suspend state, to a power-off state where the HSIC modules turn off The HSIC communication method and apparatus are advantageous to minimize the electric current consumption of the HSIC consumption system. | 09-27-2012 |
| 20120254647 | DYNAMIC ALLOCATION OF PROCESSOR CORES RUNNING AN OPERATING SYSTEM - An apparatus and method for dynamic allocation of multiple processor cores in a computer running an operating system includes providing a program operable to halt a core from processing instructions from a respective ready queue. A next step includes establishing a maximum count of tokens available to allow the program execution, wherein the maximum count is less than a total number of cores. A next step includes obtaining tokens by the cores, wherein at least one core will not be able to obtain a token. If a token has been obtained by a core, executing the program by that core, or otherwise not executing the program by that core and remaining active to process instructions from the respective ready queue of that core. | 10-04-2012 |
| 20120254648 | PROGRAM PROCESSING APPARATUS - A program processing apparatus includes a detector. A detector detects a motion of a device. A first supplier supplies power to an internal memory in response to a detection of the detector. A loader loads a program executed by a processor into the internal memory, in association with a supplying process of the first supplier. A second supplier supplies the power to the processor in response to a power-on operation after a loading process of the loader. | 10-04-2012 |
| 20120260116 | EXTERNAL POWER-SAVING USB MASS STORAGE DEVICE AND POWER-SAVING METHOD THEREOF - An external power-saving USB mass storage device has a USB interface, a USB controller, an interface unit, a device controller and a memory unit. The USB controller has a sleep mode determination process embedded therein for predicting when a USB host plugged in by the USB mass storage device will not access the memory unit of the USB mass storage device for a prolonged time, and activates a sleep mode of the device controller through the interface unit so as to instruct the device controller and the memory unit to enter a power-down state for power-saving purpose. | 10-11-2012 |
| 20120266004 | CIRCUIT, ELECTRONIC DEVICE, AND IMAGE PROCESSING DEVICE - An SoC is connected to an SDRAM that is controlled by a memory controller and a memory PHY, and the SoC is operable in a normal mode and in a power saving mode. The SoC includes a block A to be powered off in the power saving mode and a block B not to be powered off in the power saving mode. A memory controller is included in the block A. A memory PHY and signal level holding cells are included in the block B. The signal level holding cells are provided between the memory controller and the memory PHY, and are configured to fix output signals from the memory controller at predetermined levels in the power saving mode. | 10-18-2012 |
| 20120266005 | METHOD AND DEVICE TO REDUCE POWER CONSUMPTION OF A PATTERN-RECOGNITION PROCESSOR - A device includes a pattern-recognition processor. The pattern recognition processor includes blocks, such that each of the blocks include a plurality of feature cells configured to analyze at least a portion of data to be analyzed and to selectively provide a result of the analysis. The pattern recognition processor also includes block deactivation logic configured to dynamically power-down the block. | 10-18-2012 |
| 20120272084 | INFORMATION PROCESSING APPARATUS CAPABLE OF UPDATING FIRMWARE THEREOF AND CONTROL METHOD AND STORAGE MEDIUM THEREFOR - An information processing apparatus capable updating firmware thereof, while reducing power consumption. In a case where an image forming apparatus as an information processing apparatus is in a power switch off mode in which a power switch operable by a user is kept turned off and where a setting to permit execution of firmware update has been set by the user, the image forming apparatus stops power supply for execution of processing other than processing performed by a network I/F. When a firmware update request is received by the network I/F, the image forming apparatus restores power supply for execution of firmware update. | 10-25-2012 |
| 20120284552 | Method, System and Computer Program Product for Reducing Consumption of Battery Power - An information handling system is powered by a battery. In response to determining that a remaining amount of power within the battery has fallen below a first threshold, power consumption of the information handling system is reduced by reducing at least one non-critical operation of the information handling system, while maintaining at least one critical operation of the information handling system. After reducing the at least one non-critical operation, it is increased in response to determining that the remaining amount of power within the battery has risen above a second threshold. | 11-08-2012 |
| 20120284553 | METHOD, APPARATUS AND SYSTEM FOR REDUCING POWER CONSUMPTION OF SERVICE SYSTEM - A method for reducing power consumption of a service system is disclosed in the present invention. The method includes: determining that a service utilization rate of the service system is smaller than a startup threshold for energy saving; determining, according to a preset condition, a board of the service system, where the board of the service system is required to be powered down; and triggering power-down of the board in the service system. A service system, an energy-saving system and a control system for reducing power consumption of a service system are also disclosed in the present invention. This present invention is capable of effectively reducing power consumption of the service system and achieving good energy-saving effects independent of a CPU. | 11-08-2012 |
| 20120303990 | POSTPONING SUSPEND - According to one general aspect, a method may include operating a computing device in a first power mode. The method may also include executing, by a processor of the computing device, at least one non-interactive task. The method may also include detecting, by a processor of the computing device, a request to place the computing device in a second power mode, wherein the second power mode consumes less system resources than the first power mode. The method may further include delaying the transition of the computing device to the second power mode until either the completion of the non-interactive task or an overriding triggering event. | 11-29-2012 |
| 20120303991 | METHOD AND APPARATUS FOR IMPROVED POWER MANAGEMENT OF MICROPROCESSORS BY INSTRUCTION GROUPING - A method of power gating a microprocessor having an instruction scheduling unit for receiving issued instructions from an instruction decoder; an execution unit receiving and sending signals from and to the instruction scheduling unit; and a state machine. The method comprises: obtaining a number of instructions per cycle being issued to the instruction scheduling unit; determining, if the number of instruction per cycle being issued to the instruction scheduling unit is less than a threshold level, and then determining if at least two of the instructions being issued to the instruction scheduling unit are independent of each other only when the instructions per cycle is less than the threshold level; determining when at least two of the instructions being issued to the instruction scheduling unit are independent of each other; and power gating the microprocessor to gate off power to idle macros with a signal from the state machine. | 11-29-2012 |
| 20120303992 | DISPLAY AND POWER MANAGEMENT METHOD THEREOF - A display and a power management method thereof are disclosed. The method includes: detecting a state of a Graphic Interface Card (GIC) in the display; turning off power supply to the GIC when the GIC is in a first state; and turning on power supply to the GIC when the GIC is in a second state. The method is capable of reducing power consumption of a display to satisfy environment protection requirements without sacrificing the functionality of the display's GIC. | 11-29-2012 |
| 20120311365 | PROGRAMMABLE LOGIC DEVICE - An object is to provide a programmable logic device configured to keep a connection state of logic circuits even while power supply voltage is stopped. The programmable logic device includes arithmetic circuits each of whose logic state can be changed; a configuration changing circuit changing the logic states of the arithmetic circuits; a power supply control circuit controlling supply of power supply voltage to the arithmetic circuits; a state memory circuit storing data on the logic states and data on states of the power supply voltage of the arithmetic circuits; and an arithmetic state control circuit controlling the configuration changing circuit and the power supply control circuit in accordance with the data stored in the state memory circuit. A transistor in which a channel formation region is formed in an oxide semiconductor layer is provided between the configuration changing circuit and each of the arithmetic circuits. | 12-06-2012 |
| 20120324268 | INFORMATION PROCESSING APPARATUS, METHOD, AND STORAGE MEDIUM - A novel information processing apparatus maintains file system information in a secondary storage device during power saving mode. The information processing apparatus keeps storing file information and mounting information in the secondary storage device without releasing it in shutdown process | 12-20-2012 |
| 20130007497 | APPARATUS FOR BLOCKING STANDBY POWER OF COMPUTER PERIPHERAL DEVICES - The present invention relates to an apparatus for blocking standby power of computer peripheral devices, comprising: a synchronization signal sensing control unit which senses the existence of horizontal and vertical synchronization signals provided to a monitor from a computer body, and outputs a switching control signal according to the sensed result; and a power switching unit which is provided with external power and situated on a power supply path for supplying power to the computer peripheral devices, and has a structure adapted for conducting or blocking the corresponding path according to the switching control signal. | 01-03-2013 |
| 20130031397 | INFORMATION PROCESSING APPARATUS - One embodiment provides an information processing apparatus including a processor; memory blocks; an internal voltage generator connected to the memory blocks; an input/output circuit connected to the memory blocks; switches each installed corresponding to the internal voltage generator, the input/output circuit, and the memory blocks, and configured to switch ON/OFF of the connection with a power source; a data register configured to store a data set that controls the ON/OFF of the switches; and a data management circuit configured to set the data set in the data register, wherein when a clock signal input to the processor is turned to OFF, the data management circuit generates a first type of the data set, which switches ON the switch connected to the internal voltage generator and switches OFF the switches connected to the memory blocks, and sets the first type of the data set in the data register. | 01-31-2013 |
| 20130042132 | IMAGE FORMING APPRATUS, MICROCONTROLLER, AND METHODS FOR CONTROLLING IMAGE FORMING APPARATUS AND MICROCONTROLLER - An image forming apparatus, a microcontroller, and methods for controlling the image forming apparatus and the microcontroller are provided. The microcontroller include: a memory controller which is connected to an external memory operating in a self-refresh mode if a normal mode changes to a low power mode, performs a control operation by using the external memory in the normal mode, and outputs a preset signal which is to cancel the self-refresh mode if the low power mode changes to the normal mode; a memory interface unit which transmits the preset signal to a main memory; and a signal detector which detects whether the preset signal has been output. Here, the memory controller powers off the memory interface unit if the normal mode changes to the low power mode and powers on the memory interface unit if the low power mode changes to the normal mode, and the output of the preset signal is detected by the signal detector. | 02-14-2013 |
| 20130047021 | MULTIPLE-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD - A multiple-core processor system includes a memory unit storing the number of time intervals within a time bin, a time interval being a time interval between two consecutive operations; and a processor configured to: update the number of time intervals, specify a time stretch during which the number of time intervals stays above a threshold, and set, based on the number of time intervals, a power supply mode in which the multiple-core processor is supplied with power. | 02-21-2013 |
| 20130061081 | THERMAL PROTECTION METHOD AND RELATED SYSTEM FOR A COMPUTER SYSTEM - A thermal protection method for a computer system comprising a thermal detector, a controller, and an input/output system, the thermal protection method including the thermal detector measuring the temperature of the computer system and generating a temperature value, the controller comparing the temperature value and a threshold value, the controller periodically transmitting an over-temperature indication signal to the input/output system when the temperature value is not lower than the threshold value, the input/output system executing a temperature-lowering process when receiving the over-temperature indication signal, and the controller executing a compulsory thermal protection process when determining that the temperature-lowering process is unsuccessfully executed. | 03-07-2013 |
| 20130061082 | BALANCING POWER CONSUMPTION AND HIGH AVAILABILITY IN AN INFORMATION TECHNOLOGY SYSTEM - A method is disclosed for balancing the requirements of high availability achieved by redundant active components and power saving achieved by less active components. The requirement for high availability can be expressed by the recovery time objective (RTO) which specifies the amount of time it takes to recover from a failure in the system. Based on the configured RTO, the system configures the most appropriate power mode. | 03-07-2013 |
| 20130073889 | Systems and Methods for Modular Power Management - Various systems and methods for power management. | 03-21-2013 |
| 20130080812 | CONTROL SYSTEM, CONTROL METHOD, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, a control system includes a processing device; a main storage device to store the data; a cache memory to store part of the data stored; a prefetch unit to predict data highly likely to be accessed and execute prefetch, reading out data in advance onto the cache memory; and a power supply unit. The system further includes: a detecting unit to detect whether the processing device is in an idle state; a determining unit that determines whether to stop the supply of power to the cache memory in accordance with the state of the prefetch when determined as idle state; and a power supply control unit that controls the power supply unit so as to stop the supply of power, or controls the power supply unit so as to continue the supply of power. | 03-28-2013 |
| 20130080813 | CONTROL SYSTEM, CONTROL METHOD, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, a control system includes a detector, an estimating unit, a determining unit, and a controller. The detector detects an idle state. The estimating unit estimates an idle period. When the idle state is detected, the determining unit determines whether a first power consumption when writeback of data which needs to be written back to a main storage device is performed and supply of power to a cache memory is stopped, is larger than a second power consumption when writeback of the data is not performed and supply of power is continued for the idle period. The controller stops the supply of power to the cache memory when the first power consumption is determined to be smaller than the second power consumption and continues the supply of power when the first power consumption is determined to be larger than the second power consumption. | 03-28-2013 |
| 20130086403 | METHOD OF REDUCING POWER CONSUMPTION IN A NETWORK - A method of reducing power consumption in a network. A first network device powers down or reduces the port speed of a port if said port is blocked by a loop mitigation protocol. | 04-04-2013 |
| 20130086404 | POWER REGULATION OF POWER GRID VIA DATACENTER - One or more techniques and/or systems are provided for regulating an amount of power on a power grid using a datacenter. This allows demand to be more closely brought into alignment with supply. For example, when supply exceeds demand by a predetermined level, the datacenter may increase consumption, causing demand to increase, and when demand exceeds supply and/or comes within a predetermined threshold of supply, the datacenter may decrease consumption, causing demand to decrease. In this way, the datacenter can be utilized as a regulatory tool on the grid. It may be appreciated that given the technology used by and/or operations performed by datacenters, datacenters are uniquely situated to achieve these ends as compared to other (large) energy consumers, such as manufacturing facilities that cannot shift around and/or shut-down operations swiftly. | 04-04-2013 |
| 20130086405 | SERVER CLUSTER AND CONTROL MECHANISM THEREOF - A server cluster including a network switch and multiple server nodes is provided. The network switch is connected to an external network. Each server node includes a network port, a network chip and a control unit. The network port is connected to the network switch via a cable. The network chip detects the cable to obtain a connection state with the external network at the server node after the network switch is started, and accordingly outputs a connection state signal. The control unit turns on or shuts down the server node according to the connection state signal and an on/off state of the server node. | 04-04-2013 |
| 20130086406 | System and Method for Portable Power Source Management - A battery monitoring apparatus that senses battery conditions such as low battery charge, end of battery capacity, and end of battery life, and responds by taking actions such as sending messages to a remote site and/or powering down. A rechargeable battery is coupled to one or more power-consuming electrical components, including battery monitoring equipment. The battery monitoring equipment senses battery charge. In response to a low-battery-charge condition, the battery monitoring equipment transmits a battery status message to a remote site and powers-down some of the electrical components. Whenever the battery nears the end of its capacity, the monitoring equipment powers down all electronic components and awaits the application of external power. The invention also tracks the time required for the battery charge to deplete. Charge duration decreases over time, and whenever it reaches a predetermined minimum, the battery monitoring equipment transmits a representative status message to the remote site. | 04-04-2013 |
| 20130091371 | SERVER CLUSTER AND CONTROL MECHANISM THEREOF - A server cluster including a network switch and multiple server nodes is provided. The network switch is connected to an external network. Each server node performs an operation system and respectively includes a network port, a network chip and a south bridge chip. The network port is connected to the network switch via a cable. The network chip outputs a power-off signal according to a received power-off packet after the network switch is started. The south bridge chip outputs a shutdown signal to shut down the server node according to the power-off signal when the server node is turned on and the operation system is working normally. | 04-11-2013 |
| 20130097449 | MEMORY UNIT, INFORMATION PROCESSING DEVICE, AND METHOD - A memory unit comprises at least two volatile memory elements, analyzing circuitry and power gate. The memory elements may for example be latches, flip-flops, or registers. Each of the memory elements has at least two different states including a predefined reset state. The analyzing circuitry generates a power-down enable signal in response to each of the memory elements being in its reset state. The power gate powers down the memory elements in response to the power-down enable signal. The memory elements may be arranged to assume their reset states upon powering up the memory unit. | 04-18-2013 |
| 20130111248 | Electronic Devices Having Integrated Reset Systems and Methods Thereof | 05-02-2013 |
| 20130111249 | ACCESSING A LOCAL STORAGE DEVICE USING AN AUXILIARY PROCESSOR | 05-02-2013 |
| 20130124897 | METHOD AND APPARATUS TO CONTROL POWER SUPPLY TO NETWORK DEVICE - An apparatus to control power of an electronic device includes a local area network (LAN) controller to control network communication of the electronic device, a communication interface connected to an external dongle to perform the network communication, a connection detector to detect whether a first signal for connection with the LAN controller is received from the external dongle, and a power controller to supply power to the LAN controller when the first signal is detected and to shut off power to the LAN controller when the first signal is not detected. | 05-16-2013 |
| 20130124898 | METHOD, SYSTEM AND APPARATUS FOR LOW-POWER STORAGE OF PROCESSOR CONTEXT INFORMATION - A method and system for saving and/or retrieving context information of a processor core for a power state transition. The processor core resides in a complex power domain variously transitioning between a plurality of power states. The processor core includes a local context storage area for storage and retrieval of processor core context information. A low power context storage resides in a nominal power domain external to the complex power domain. Context information of the processor core is stored to the low power context storage based on whether a power state transition of the complex power domain includes a transition to power down the processor core. | 05-16-2013 |
| 20130124899 | Method, Apparatus and System for Device Management - A method, apparatus and system for managing a device are provided by the present invention, which relate to the field of communication. The method includes: according to a preset power management rule, determining a power supply policy of each single board in the current device ( | 05-16-2013 |
| 20130132756 | ELECTRONIC CIRCUIT AND METHOD FOR STATE RETENTION POWER GATING - An electronic circuit includes a processor having a functional mode and a low power mode, said processor comprising state flip-flops and additional flip-flops; said state flip flips are arranged to store state information about a state of the processor when the processor is in the functional mode; said state flip-flops comprise non-reset flip-flops that are arranged to store at least one non-reset value when the processor exits the functional mode; a power management circuit for providing power to the processor when the processor is in the functional mode, and for preventing power from the processor when the processor is in the low power mode; a non-reset value identification module, coupled to the state flip-flops, said non-reset value identification module is arranged to identify the non-reset flip-flops and to generate non-reset information that identifies the non-reset flip-flops; and a recovery circuit, coupled to a memory module and to the state flip-flops. | 05-23-2013 |
| 20130159753 | APPARATUS, SYSTEMS AND METHODS FOR MODIFYING OPERATING STATES BASED ON MONITORED HDMI CEC COMMUNICATIONS - Systems and methods provide control of operating states of an electronic device. A first exemplary electronic device detects a consumer electronic control (CEC) communication sent from a second electronic device to a third electronic device, the CEC communication communicated over high-definition multimedia (HDMI) connectors communicatively coupling the first electronic device, the second electronic device and the third electronic device; determines, based on information in the CEC communication, whether the CEC communication is one of a first kind of CEC communication or a second kind of CEC communication; in response to determining that the CEC communication is one of the first kind of CEC communication, transitions the first electronic device to a predefined operating state; and in response to determining that the CEC communication is one of the second kind of CEC communication, maintains the first electronic device in a current operating state. | 06-20-2013 |
| 20130173944 | REDUCING POWER CONSUMPTION OF MEMORY - Described embodiments provide for a memory system having a transparent source bias (TSB) circuit. A monitor in the memory system monitors a process, temperature, and/or a leakage current of the memory. The system determines whether at least one of the monitored process, temperature, and leakage current reaches a corresponding threshold. The threshold is set based on a power budget of the memory. If the corresponding threshold is reached, the TSB is disabled and the memory operates at a relatively high speed. If the corresponding threshold is not reached, the TSB is enabled and the memory operates at a relatively law speed. | 07-04-2013 |
| 20130173945 | CONTROL METHOD, CONTROL DEVICE AND TERMINAL - A control method, a control apparatus and a terminal are provided according to embodiments of the present invention. The method includes: receiving a trigger event; determining from the trigger event whether the terminal enters a limited operation mode in which at least one component of the terminal is unusable; generating a first control instruction when it is determined that the terminal enters the limited operation mode; and controlling to turn off power supply to the at least one component terminal according to the first control instruction. With the present invention, it is possible to switch the terminal system between a limited operation mode and a normal operation mode in terms of hardware, thereby saving power and satisfying the low-carbon environmental preservation requirements. | 07-04-2013 |
| 20130179717 | ELECTRONIC SYSTEM WITH POWER SAVING FUNCTION - The present invention provides an electronic system with power saving function. In a first embodiment, the electronic system comprises a processing unit and a storage device. The storage device has a transmission interface, and the storage device is coupled to the processing unit via the transmission interface, wherein when the electronic system enters into a hibernate mode, the processing unit will turn off power supply of the storage device completely via the transmission interface. In a second embodiment, the electronic system comprises a processing unit and a storage device. The storage device has a transmission interface and an independent signal pin, and the storage device is coupled to the processing unit via the transmission interface and the independent signal pin, wherein when the electronic system enters into a hibernate mode, the processing unit will turn off power supply of the storage device completely via the independent signal pin. | 07-11-2013 |
| 20130191672 | User Generated Data Center Power Savings - Technologies are described herein for providing power savings in a data center. Some example technologies may identify some user-provided hardware independent power saving codes from multiple virtual machines within the data center. The technologies may convert at least a portion of the user-provided hardware independent power saving codes into a device power management message specific to a computing system in the data center. The technologies may provide the device power management message to the computing system. The computing system may be configured to enable or disable one or more devices within the computing system according to the device power management message. | 07-25-2013 |
| 20130191673 | SEMICONDUCTOR DEVICE - To individually control supply of the power supply voltage to circuits, a semiconductor device includes a CPU, a memory that reads and writes data used in arithmetic operation of the CPU, a signal processing circuit that generates an output signal by converting a data signal generated by the arithmetic operation of the CPU, a first power supply control switch that controls supply of the power supply voltage to the CPU, a second power supply control switch that controls supply of the power supply voltage to the memory, a third power supply control switch that controls supply of the power supply voltage to the signal processing circuit, and a controller that at least has a function of controlling the first to third power supply control switches individually in accordance with an input signal and instruction signals input from the CPU and the signal processing circuit. | 07-25-2013 |
| 20130198549 | AUTONOMOUS POWER-GATING DURING IDLE IN A MULTI-CORE SYSTEM - To preserve power and increase the overall efficiency of the CPU, the platform idle driver causes the power gate controller to cut power to the idle core. Such power gating is autonomous, i.e., the operating system and the other cores are not involved. In operation, the platform idle driver first prepares the core and the power gate controller for power gating the core. The platform idle driver then triggers the power gating. The power gate controller monitors interrupts released by the interrupt controller, and if any on the released interrupts are associated with the power gated core, the power gate controller resumes dispersing power to the core. | 08-01-2013 |
| 20130198550 | INFORMATION PROCESSING APPARATUS, POWER-SAVE CONTROL METHOD, AND POWER-SAVE CONTROL PROGRAM - An information processing apparatus includes a main storage unit and a primary computing unit. When a power-save mode is set, power supply to the main storage unit is being continued while power supply to the primary computing unit is stopped. The primary computing unit includes an operation status information processing unit to store operation status information of the primary computing unit when shifting to the power-save mode; a storing destination information processing unit to store storing-destination information indicating a storage area of the operation status information; a power-supply stop control unit to stop power supply to the primary computing unit after storing the operation status information and storing-destination information; a return operation identifying unit to confirm return operation identification information and to initialize the primary computing unit after power supply to the primary computing unit is resumed; and an operation status restoring unit to read the operation status information. | 08-01-2013 |
| 20130205156 | INFORMATION PROCESSING APPARATUS THAT PERFORMS USER AUTHENTICATION, METHOD OF CONTROLLING THE SAME, AND STORAGE MEDIUM - An information processing apparatus that improves the convenience of a user who performs authentication using an authentication medium. A communication system module acquires authentication information from an IC card. A sensor system module detects proximity of the IC card. A main circuit element group authenticates a user using the acquired authentication information. A power supply controller supplies power to those modules and the group. A power supply destination is controlled such that the apparatus is shifted to a power saving state in which power is supplied only to the sensor system module. In the power saving state, when the sensor system module detects proximity of the IC card, the power supply destination is controlled to cause the apparatus to shift to a normal power state in which power is supplied to the communication system module and the main circuit element group. | 08-08-2013 |
| 20130205157 | DATA TRANSFER OPERATION COMPLETION DETECTION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE PROVIDED THEREWITH - A data transfer operation completion detection circuit including a first counter for performing a shifting operation in response to the generation of a read initiation signal, a second counter for performing a shifting operation in response to the generation of a burst completion signal, and an SR latch circuit for generating a read enable signal in response to the burst completion signal being generated when the count value of the first counter matches the count value of the second counter. The completion of a read operation or another data transfer operation is thus detected based on a read initiation signal reception history; therefore, it is possible to detect whether all read operations are complete at a given time even if a new read command is received while a read operation or the like is in progress. | 08-08-2013 |
| 20130219205 | METHOD AND APPARATUS FOR SAVING POWER BY EFFICIENTLY DISABLING WAYS FOR A SET-ASSOCIATIVE CACHE - A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses. | 08-22-2013 |
| 20130227326 | APPARATUS AND METHOD FOR CONTROLLING POWER OF ELECTRONIC DEVICE HAVING MULTI-CORE - A method of controlling on/off of a core based on a used amount of an operating core and the number of tasks in an electronic device having a multi-core, and an apparatus thereof, includes confirming a load of an operating core and the number of executable tasks at a predetermined period, determining whether the load of the operating core and the number of executable tasks meet a defined on/off condition of the multi-core, and controlling on/off of the multi-core when the load of the operating core and the number of executable tasks meet the defined on/off condition of the multi-core. | 08-29-2013 |
| 20130232365 | SEMICONDUCTOR DEVICE - The semiconductor device includes a CPU core having functions of a control unit, an arithmetic unit, and a register; a first memory device including a plurality of blocks each including one or a plurality of rows of memory cells; a second memory device copying data that is to be treated in the CPU core from a first block selected by the CPU core from the plurality of blocks included in the first memory device, and storing the data; a plurality of switches controlling supply of power supply voltage to the respective blocks; a memory management unit recognizing an address of the first block; and a power controller turning off one of the plurality of switches using the address to stop supply of the power supply voltage to a second block of the plurality of blocks which is different from the first block. | 09-05-2013 |
| 20130232366 | MICROPROCESSOR AND METHOD FOR DRIVING MICROPROCESSOR - A microprocessor with low power consumption and a method for driving the microprocessor are provided. The microprocessor includes a processor core, a cache memory, an interrupt controller, and a power supply controller. As at least one of a plurality of memory cell arrays included in the cache memory, a memory cell array composed of a plurality of memory cells is used. At the time of switching to a low power consumption mode, data used by the processor core after supply of power is resumed is prefetched to the memory cell array; then supply of power to the cache memory is stopped. Then, the processor core fetches needed data from the memory cell array after supply of power to the cache memory is resumed. | 09-05-2013 |
| 20130232367 | Electronic Apparatus and Power Supply Control System - This electronic apparatus includes a plurality of functional blocks, a storage portion storing and accumulating use states of the plurality of functional blocks, and a control portion. The control portion is configured to perform control of disconnecting power supplied to a functional block whose usage rate is not more than a prescribed usage rate, tending to be disused, of the plurality of functional blocks in a state where power is supplied to at least one functional block. | 09-05-2013 |
| 20130232368 | MANAGING POWER CONSUMPTION IN A MULTI-CORE PROCESSOR - A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3 | 09-05-2013 |
| 20130246825 | METHOD AND SYSTEM FOR DYNAMICALLY POWER SCALING A CACHE MEMORY OF A MULTI-CORE PROCESSING SYSTEM - A system and method of power scaling cache memory ( | 09-19-2013 |
| 20130246826 | METHOD AND SYSTEM FOR CONTROLLING POWER - A method and system for controlling power is provided. The system is configured to selectively control a plurality of power control domains. The system may be configured to process audio data in at least one of the domains. The system may be configured to output audio data, while one or more of the power control domains is suspended. | 09-19-2013 |
| 20130254575 | ELECTRONIC DEVICE HAVING MEMORIES AND METHOD FOR MANAGING MEMORIES THEREOF - A method for managing memories in an electronic device includes the following steps. Detecting a change in status of all the applications installed in the electronic device, wherein the change in status of each application may include at least one start-to-run application or at least one stop-running application. If the at least one stop-running application is detected, obtaining memories occupied by the stop-running application, and powering off each obtained memory occupied by other running application. If the at least one start-to-run application is detected, determining a memory size required to enable each start-to-run application to run, determining whether a working condition of the memories needs to be changed according to the determined memory size required, and powering on the memories that are needed to enable the start-to-run application to run. | 09-26-2013 |
| 20130254576 | MULTIPROCESSOR SYSTEM AND METHOD OF CONTROLLING POWER - According to one embodiment, a multiprocessor system includes a plurality of processors, a power supply device and a shared memory. The shared memory includes a thread pool and a thread queue. In the thread pool, threads each having waiting events are registered in association with the numbers of the waiting events. In the thread queue, threads having no waiting event are registered. One or more first processors acquire first thread from the thread queue and execute the first thread. A second processor updates the number of waiting events of a second thread, which is registered in the thread pool, having completion of required procedure for the second thread by the first thread as a waiting event. A third processor operates supply of power to the first processors individually based on the number of threads in the thread queue and the number of waiting events. | 09-26-2013 |
| 20130254577 | ELECTRONIC DEVICE AND METHOD FOR SUPPLYING POWER TO AT LEAST TWO DIFFERENT LOADS BY SINGLE POWER SUPPLY - An electronic device and a method for supplying power are provided. The electronic device includes a power supply, a central processing module, at least two load power supply circuits including a capacitor, at least one switch and at least one feedback resistor unit. The switch is connected with the power supply and the central processing module, configured to be turned on or off according to a control signal output by the central processing module; the feedback resistor unit is connected with the switch and a load, configured to sample the load when the switch is turned on and feed back a sampled voltage, to the power supply through the switch, the power supply supplies power to the load; the capacitor is connected with the switch and the load, configured to be charged when the switch is turned on, or supply power to the load when the switch is turned off. | 09-26-2013 |
| 20130268795 | CACHE SYSTEM AND INFORMATION-PROCESSING DEVICE - According to one embodiment, a cache system includes a tag memory includes a volatile memory device, the tag memory includes ways and storing a tag for each line, a data memory includes a nonvolatile memory device including sense amplifiers for reading data, the data memory includes ways and storing data for each line, a comparison circuit configured to compare a tag included in an address supplied from an external with a tag read from the tag memory, and a controller configured to turn off a power of a sense amplifier for a way which is not accessed based on a comparison result of the comparison circuit. | 10-10-2013 |
| 20130275795 | STORAGE CONTROL SYSTEM WITH POWER DOWN MECHANISM AND METHOD OF OPERATION THEREOF - A storage control system and method of operation thereof includes: a control unit for initiating a hardening process beginning at a power-down signal; a counter module, coupled to the control unit for tracking a recorded time beginning at the power-down signal; a completion module, coupled to the counter module, for generating a work-complete entry in memory devices at a conclusion of the hardening process; and a calculation module, coupled to the completion module, for calculating a power down margin by determining the recorded time between the work-complete entry and a complete power loss of a hold-up power. | 10-17-2013 |
| 20130283080 | APPARATUS AND METHOD FOR CONTROLLING POWER OF EXTERNAL MEMORY IN MOBILE TERMINAL - An external memory power control apparatus and method capable of controlling power of an external memory inserted into a mobile terminal. The external memory power control apparatus includes an external memory power switch for switching between a power supply and an external memory to supply or block power for the external memory; and a controller, when ‘power-on’ is selected on the mobile terminal, for checking and notifying operability of the external memory inserted into the mobile terminal after completing booting while the external memory power switch turned off, wherein the controller may selectively turn on/off the external memory power switch depending on operability of the external memory. | 10-24-2013 |
| 20130283081 | Memory Array Power Cycling - In a non-volatile memory system, physically separate power rails are provided from a host system to a NVM device for independently power cycling a controller and memory array in the NVM device. The controller of the NVM device can send a power cycle request signal to the host system over a host channel, or updates a status register in the NVM device. The host system receives and decodes the power cycle request signal, or reads the status register, and performs the power cycle request, which can include power cycling the controller or the memory array in the NVM device, or both. The power cycle request can be based on a power state of the non-volatile memory system, which can be managed by the controller or the host system, or both. | 10-24-2013 |
| 20130283082 | APPARATUS AND METHOD FOR MANAGING POWER IN A COMPUTING SYSTEM - A disable module may be coupled to an analog circuit of an electronic circuit. The disable module may detect an input voltage that is supplied to the analog circuit, and may disable (such as by powering off) the analog circuit if the input voltage is below a reference value. The reference value may be set at a voltage level at or below a maximum voltage that may be present across a transistor in the analog circuit. Accordingly, the analog circuit may be disabled without damage to the transistors of the analog circuit. The disable module may detect whether the input voltage is below the reference value level by comparing the input voltage to a reference voltage. The electronic circuit may include a voltage regulator, and the voltage regulator may include the analog circuit. | 10-24-2013 |
| 20130305073 | CONTROLLING METHODS OF OPTICAL DISC DRIVE AND COMPUTER SYSTEM - A controlling method of an optical disc drive includes the following steps. After an optical disc is loaded into the optical disc drive, a start-up procedure is performed to acquire a disc parameter and a disc information of the optical disc. Then, the optical disc drive enters a ready state. If a command from the computer system is received within a predetermined time interval, the command is executed and the optical disc drive enters the ready state again. If no command is received within the predetermined time interval, the optical disc drive enters an idle state corresponding to the presence of the optical disc. Then, the disc parameter, the disc information and a power index tag are written into a non-volatile memory, and a power-interruptible event is issued to the computer system. | 11-14-2013 |
| 20130305074 | PROTOCOL FOR MEMORY POWER-MODE CONTROL - In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command. | 11-14-2013 |
| 20130311810 | BROWSING TERMINAL, CHARGING TERMINAL, AND COMMUNICATION SYSTEM AS WELL AS TRANSMITTING/RECEIVING SYSTEM USING THE SAME - To provide a browsing terminal and the like with high security, which can effectively prevent contents data stored in a terminal from being stolen unlawfully by a third party even if the terminal is accidentally lost. The browsing terminal includes: a receiving part for receiving contents data; a volatile memory for storing the received contents data; a display device with a memory function, which displays the contents data stored in the volatile memory; and a secondary battery for supplying power to the volatile memory and the display device. | 11-21-2013 |
| 20130318387 | DISTRIBUTED POWER DELIVERY SCHEME FOR ON-DIE VOLTAGE SCALING - A high-speed low dropout (HS-LDO) voltage regulation circuit suitable to enable a power gate unit to produce a variable voltage signal based on the load of a processor is disclosed herein. In various embodiments, selection logic may dynamically enable or disable the HS-LDO circuit to allow the power gate unit to operate under a fully-on or fully-off mode. Other embodiments may be disclosed or claimed. | 11-28-2013 |
| 20130332763 | POWER-GATED MEMORY DEVICE WITH POWER STATE INDICATION - A memory device comprises one or more power gates and state signaling circuitry. Each of the one or more power gates is configurable such that a respective portion of the memory device is powered down. The state signaling circuitry is operative to produce a power state output signal indicative of when the one or more power gates are configured such that the memory device is fully powered up. | 12-12-2013 |
| 20130332764 | INTELLIGENT INTER-PROCESSOR COMMUNICATION WITH POWER OPTIMIZATION - One embodiment of the present invention provides a system that facilitates intelligent inter-processor communication with power optimization. The system comprises a memory, a first router, a second router, a first physical link coupled between the first router and the second router, and a second physical link coupled between the first router and the second router. Furthermore, the system comprises a first communication bus implemented on the first physical link, as well as a second communication bus implemented on the second physical link. Note that the second communication bus provides lower power consumption and lower bandwidth than the first communication bus. During operation, the system receives a packet at the first router, wherein the packet is destined for the second router. Next, the system selects either the first communication bus or the second communication bus over which to route the packet. Finally, the system routes the packet according to the selection. | 12-12-2013 |
| 20130346781 | Power Gating Functional Units Of A Processor - In one embodiment, the present invention includes an apparatus having a core including functional units each to execute instructions of a target instruction set architecture (ISA) and a power controller to control a power mode of a first functional unit responsive to a power identification field of a power instruction of a power region of a code block to be executed on the core. Other embodiments are described and claimed. | 12-26-2013 |
| 20130346782 | STORAGE SYSTEM AND POWER CONSUMPTION CONTROL METHOD FOR STORAGE SYSTEM - A storage system that functions as one or more logical volumes includes a control unit and a plurality of storage units connected to the control unit, wherein the control unit includes a memory that stores allocation status information that indicates status of allocation of the plurality of storage units to a logical volume; an access request responding unit that controls at least one storage unit among the plurality of storage units in response to a request for access to each logical volume from a host device; and a power saving controller that identifies an unused storage unit not allocated to any logical volume among the plurality of storage units on the basis of the allocation status information and performs power saving control on the identified unused storage unit. | 12-26-2013 |
| 20140006830 | USER BEHAVIOR ADAPTIVE SENSING SCHEME FOR EFFICIENT POWER CONSUMPTION MANAGEMENT | 01-02-2014 |
| 20140006831 | DYNAMIC LINK SCALING BASED ON BANDWIDTH UTILIZATION | 01-02-2014 |
| 20140006832 | POWER SUPPLY CIRCUIT AND HARD DISK BACKPLANE USING SAME | 01-02-2014 |
| 20140025980 | POWER SUPPLY SYSTEM - A power supply system supplies power includes a single power supply unit to supply power for a number of motherboards. A number of power management chips are provided corresponding to the motherboards, to monitor a real-time power consumption of each motherboard. A microcontroller is connected to each of the motherboards through a data line, to control a total power consumption of the motherboards to control power consumption to remain within a nominal power of the power supply unit. | 01-23-2014 |
| 20140032956 | ULTRA-DEEP POWER-DOWN MODE FOR MEMORY DEVICES - A memory device includes a voltage regulator, whose output provides a voltage supply for various other components of the memory device, including a command user interface. The memory device is placed into an ultra-deep power-down mode by providing to the memory device a software command, which causes the output of the voltage regulator to be disabled. To bring the memory device out of the ultra-deep power-down mode, a chip select signal is provided to the memory device, which includes a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode. Receipt of the chip select signal while the memory device is in the ultra-deep power-down mode causes the output of the voltage regulator to be enabled, thereby providing power to the components that were completely powered down. | 01-30-2014 |
| 20140040650 | SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR CONTROLLING THE SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a nonvolatile memory, memory controller storing control information, a switch between the nonvolatile memory/memory controller and a power supply terminal, a second memory, an interpreter interprets a command, a switch controller, and a third memory stores an address of the control information in the second memory. The memory controller instructs the switch controller to open the switch after writing the control information into the second memory and reads the control information from the second memory based on the address stored in the third memory when the memory controller is electrically connected to the first power supply terminal. | 02-06-2014 |
| 20140047257 | POWER MANAGEMENT TECHNIQUES FOR USB INTERFACES - Power management techniques for a Universal Serial Bus (USB) include determining an idle period on one or more USB ports by a main controller circuit of a USB host controller. The main controller circuit signals a suspend to a Power Management Controller (PMC) sub-circuit of the USB host controller, in response to the determined idle period. The PMC sub-circuit stores one or more operating parameters of the one or more USB ports in response to the suspend signal. The PMC sub-circuit also maintains the idle state on the one or more USB ports in response to the suspend signal. Thereafter, the main controller circuit is placed in a low energy state while the PMC sub-circuit maintains the idle state. | 02-13-2014 |
| 20140047258 | AUTONOMOUS MICROPROCESSOR RE-CONFIGURABILITY VIA POWER GATING EXECUTION UNITS USING INSTRUCTION DECODING - In an embodiment, a functional unit control system includes an instruction decoder of a processor comprising a pipeline, the instruction decoder being configured to decode an instruction to be performed by the processor. The system further includes a power controller unit coupled to the instruction decoder, and a functional unit which may operate during execution stages of the processor's pipeline coupled to the power controller unit and the instruction decode stage. The power controller unit is configured to determine whether the functional unit should be used to perform at least part of the instruction based on data of the instruction decoder. The power controller unit is further configured to perform at least one of activating and deactivating the functional unit in accordance with the determination of whether the functional unit should be used. | 02-13-2014 |
| 20140047259 | Methods and Apparatus for Mobile Device Power Management Using Accelerometer Data - A computer-implemented method for power management in a portable device includes receiving sensor information from a sensor in the portable device, associating the sensor information with one of a plurality of states of the portable device, and reducing electrical power consumption in one or more parts in the portable device according to the associated state of the portable device. In some embodiments, the method also includes collecting, from the accelerometer in the portable device, electrical signals associated with a plurality of known motion states of the portable device, and analyzing the collected electrical signals. The method also includes identifying attributes of the electrical signal with the known motion states of the portable device. | 02-13-2014 |
| 20140047260 | NETWORK MANAGEMENT SYSTEM, NETWORK MANAGEMENT COMPUTER AND NETWORK MANAGEMENT METHOD - A network management system comprising: a network including a plurality of packet relay apparatuses; wherein the plurality of packet relay apparatuses include first packet relay apparatuses, second packet relay apparatuses, and third packet relay apparatuses located downstream of the first packet relay apparatuses and the second packet relay apparatuses, wherein each of the third packet relay apparatuses has a first path coupled to one of the first packet relay apparatuses to send and receive traffic and a second path coupled to one of the second packet relay apparatuses and being in a blocking state, a management computer includes: a state information collection unit for acquiring state information on the first to the third packet relay apparatuses; and a power management unit for selecting a candidate packet relay apparatus to be deactivated satisfying predetermined conditions based on the state information. | 02-13-2014 |
| 20140068309 | ELECTRONIC DEVICE AND METHOD FOR CONTROLLING STARTUP CURRENT OF STORAGE SERVER - In a method for controlling a startup current of a storage server, a current of each storage nodes of the storage server is detected by a current sensor when the storage server is turned on. The method calculates a power of each storage node, and a total power of the storage server. When the total power of the storage server is greater than a threshold value, one or more storage nodes are turned off, and the storage nodes are grouped according to the calculated powers. The method further determines a startup sequence of groups of the storage nodes, and controls the groups of the storage nodes to start up according to the startup sequence, to avoid inrush current when a power supply provides power to all of the storage nodes simultaneously. | 03-06-2014 |
| 20140075231 | MICROCONTROLLER INPUT/OUTPUT CONNECTOR STATE RETENTION IN LOW-POWER MODES - A microcontroller is operable in a low-power mode and includes one or more I/O connectors, as well as an I/O controller operable to provide control signals for controlling a state of a particular one of the I/O connectors. The I/O controller is powered off or deactivated during the low-power mode. The microcontroller also includes I/O connector state control logic operable to control the state of the particular one of the I/O connectors in accordance with the control signals from the I/O controller. The I/O connector state control logic includes I/O connector state retention logic that retains states of the control signals and maintains the particular I/O connector in a corresponding state in accordance with the retained control signals while the microcontroller is in the low-power mode. | 03-13-2014 |
| 20140075232 | Nonvolatile Logic Array Based Computing Over Inconsistent Power Supply - Input power quality for a processing device is sensed. In response to detection of poor power quality, input power is disconnected, and the processing device backs up its machine state in non-volatile logic element arrays using available stored charge. When power is restored, the stored machine state is restored from the non-volatile logic element arrays to the volatile logic elements whereby the processing device resumes its process from the state immediately prior to power loss allowing seamless processing across intermittent power supply. | 03-13-2014 |
| 20140075233 | Customizable Backup And Restore From Nonvolatile Logic Array - Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics. | 03-13-2014 |
| 20140082394 | ELECTRONIC DEVICE - An electronic device comprises a main battery used as a drive power source for driving the electronic device, a secondary battery used as a drive power source instead of the main battery when the main battery cannot be used, a battery detection unit that detects an event of removal of the main battery from the electronic device, and a power control unit that changes the drive power source from the main battery to the secondary battery and controls operation of the electronic device to reduce power consumption by the electronic device when removal of the main battery is detected by the battery detection unit. | 03-20-2014 |
| 20140082395 | INFORMATION PROCESSING APPARATUS, POWER CONTROL METHOD, AND COMPUTER-READABLE STORAGE MEDIUM - An information processing apparatus includes an application program; a power control unit configured to switch power modes so as to control ON/OFF of power supply to each piece of hardware; and a function execution unit configured to execute control of a specified function based on an instruction from the application program. The function execution unit is configured to inquire at the power control unit for the power modes in response to an instruction from the application program. The power control unit is configured to return a power mode to the function execution unit. The function execution unit is configured to notify the power control unit of a recovery request for powering ON the hardware that has been powered OFF in the power mode not supported. | 03-20-2014 |
| 20140089712 | Security Enclave Processor Power Control - An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory. | 03-27-2014 |
| 20140089713 | COMPUTER SYSTEM, POWER SUPPLY DEVICE AND METHOD THEREOF - A computer system includes a first electronic device configured to be operated by utilizing a regular voltage, a second electronic device configured to be operated by utilizing the regular voltage, and a power supply device for providing the regular voltage. The power supply device includes a voltage regulator coupled to the first electronic device for transforming a supply voltage to output the regular voltage to the first electronic device, a control logic circuit for generating an enable signal according to a control signal, and a load switch circuit coupled to the control logic circuit, the voltage regulator and the second electronic device for outputting the regular voltage to the second electronic device according to the enable signal. | 03-27-2014 |
| 20140089714 | CONFIGURING POWER DOMAINS OF A MICROCONTROLLER SYSTEM - A microcontroller system is organized into power domains. A power manager of the microcontroller system can change the power configuration of a power domain in response to event from an event generating module without activating a processor of the microcontroller system. | 03-27-2014 |
| 20140095916 | POWER SUPPLY CIRCUIT FOR PCI-E AND MOTHERBOARD HAVING SAME - An exemplary power supply circuit for a PCI-E on a motherboard includes a first power supply, a detection unit, a power control unit, and a discharge unit. The first power supply supplies power for the PCI-E via a power pin of the PCI-E. The detection unit detects whether the motherboard receives a soft shutdown command. The power control unit cuts off or maintains an electrical connection between the first power supply and the PCI-E under control of the detection unit. The discharge unit discharges residual electrical charges in the PCI-E when the motherboard receives the soft shutdown command. | 04-03-2014 |
| 20140101474 | System and Method for Extending System Uptime while Running on Backup Power - A server chassis includes an uninterruptible power supply, and a server including a controller. The uninterruptible power supply is configured to provide a reserve power when a primary power is lost, and to send a power loss signal when the primary power is lost. The controller is configured to receive a desired server uptime, to receive an indication that a power limit for the server is fixed or decreasing over the desired server, to receive the power loss signal from the uninterruptible power supply, to send a power capacity query to the uninterruptible power supply, to receive a reserve power capacity of the uninterruptible power supply in response to the power capacity query, to calculate the power limit for the server based on the reserve power capacity of the uninterruptible power supply and on the desired server uptime, and to enforce the power limit on the server. | 04-10-2014 |
| 20140108845 | METHOD AND APPARATUS TO REDUCE SERIAL BUS TRANSMISSION POWER - In some embodiments, a serial bus interface circuit includes at least two serial ports, a memory to store a relationship between serial bus addresses and the at least two serial ports, and a controller to control access to the at least two serial ports. The controller may be configured to receive an access request for a serial bus address, determine a first port of the at least two serial ports corresponding to the serial bus address using the relationships stored in the memory, and disable a second port of the at least two serial ports. Other embodiments are disclosed and claimed. | 04-17-2014 |
| 20140115370 | ELECTRONIC DEVICE AND METHOD FOR REDUCING ENERGY CONSUMPTION OF STORAGE DEVICES - In a method for reducing energy consumption of storage devices in an electronic device, a directory index of files stored in the storage devices is established, and the storage devices are turned off after establishing the directory index. In response to receiving a user request for processing a target file, the method determines a target storage device that stores the target file when the directory index includes information of the target file. The target storage device is turned on, and the user request is transmitted to the target storage device. The target file is processed in the target storage device according to the user request. | 04-24-2014 |
| 20140122912 | INFORMATION PROCESSING APPARATUS AND OPERATION CONTROL METHOD - According to one embodiment, an information processing apparatus detects whether or not a person is in front of a screen of a display arranged on a front surface of a second housing. When the second housing is set at a first position where the screen of the display and an upper surface of a first housing are exposed, the apparatus enables a control function for controlling a state of the display to transit from an ON state to an OFF state based on the detection result. When the second housing is set at a second position where the screen of the display is exposed and at least a part of the upper surface is covered with a back surface of the second housing, the apparatus disables the control function. | 05-01-2014 |
| 20140129863 | SERVER, POWER MANAGEMENT SYSTEM, POWER MANAGEMENT METHOD, AND PROGRAM - To increase the reliability of power supply control of a server group and reduce the power consumption of the server group. A server includes a power supply stop control unit which stops a power supply of a predetermined processing unit upon receiving a power supply stop instruction signal instructing to stop the power supply, a power supply start-up control unit which intermittently starts up the power supply of the predetermined processing unit when the power supply stop control unit stops the power supply of the predetermined processing unit, a power supply start-up determination unit which determines whether a processing load of other servers which are executing their processes among a plurality of other servers is higher than an upper limit load determined in advance as a load required to be processed by servers the number of which is greater than or equal to the number of the other servers which are executing their processes when the power supply start-up control unit starts up the power supply of the predetermined processing unit, and a process control unit which controls process execution for the predetermined processing unit when the processing load of the other servers which are executing their processes is determined to be higher than the upper limit load. | 05-08-2014 |
| 20140129864 | MULTIPROCESSOR SYSTEM AND METHOD OF SAVING ENERGY THEREIN - A multiprocessor system comprises: a plurality of processors; a counting, measuring and calculating (CMC) unit that determines a generating rate of sleep tasks and a time length of each of the sleep tasks based on an acceptable delay; a sleep task generator that generates the sleep tasks with the time length at the generating rate, and injects the generated sleep tasks into a traffic for original tasks; and a scheduler that assigns both the original tasks and the sleep tasks in the traffic to the plurality of processors, wherein each of the sleep tasks switches off one of the plurality of processors, on which the sleep task is assigned. | 05-08-2014 |
| 20140129865 | SYSTEM CONTROLLER, POWER CONTROL METHOD, AND ELECTRONIC SYSTEM - According to an aspect of an embodiment, a system controller included in a first electronic apparatus connected to a different electronic apparatus via a network, includes a monitoring unit and a power supply control unit. The monitoring unit mutually monitors a survival state with an operation system controller included in a second electronic apparatus. The power supply control unit, controls a power supply of a different system controller included in the first electronic apparatus to turn off when the monitoring unit starts monitoring a survival state of the operation system controller included in the second electronic apparatus. | 05-08-2014 |
| 20140136872 | Monitoring transaction requests using a policy engine within a storage drive driver to change power capability and latency settings for a storage drive - With embodiments of the invention, a more robust solution is provided using a storage driver that may already be used for the platforms operating system. This is efficient because the storage driver typically already monitors storage drive access requests, and thus knows when traffic is outstanding (performance may be critical) or when it's not outstanding (and power may be saved). | 05-15-2014 |
| 20140143576 | ENERGY SAVING NETWORK APPARATUS AND SYSTEM - An energy saving network apparatus comprises: a network apparatus including a plurality of beacons and a display unit; a portable identification apparatus including an identification code and token by a user; a access control apparatus used to control the user to approach the network apparatus, the access control apparatus including an identification reader used to read the identification code of the portable identification apparatus and transmit an identification signal including the identification code; and a server used to receive the identification signal and identify the identification code and send a signal to the access control apparatus and the network apparatus for controlling the access control apparatus, the beacons and the display unit to be powered on or off, whereby the beacons and the display unit are powered off so as to achieve power saving for the energy saving network system. | 05-22-2014 |
| 20140143577 | POWER CONSERVATION BY WAY OF MEMORY CHANNEL SHUTDOWN - A method is described that includes deciding to enter a lower power state, and, shutting down a memory channel in a computer system in response where thereafter other memory channels in the computer system remain active so that computer remains operative while the memory channel is shutdown. | 05-22-2014 |
| 20140149776 | IMAGE FORMING APPARATUS AND CONTROL METHOD THEREOF - An image forming apparatus and a control method thereof includes an image forming unit to form images, a main control unit to control operations of the image forming unit; a switching unit to selectively supply an operating voltage to the main control unit according to a level of the voltage control, a power mode selecting unit to convert an on state or an off state according to a user's operation, a first voltage determining unit to determine a level of the control voltage according to the state of the power mode selecting unit, and a second voltage determining unit to determine the level of the control voltage in parallel with the first voltage determining unit, according to the control signal output from the main control unit. | 05-29-2014 |
| 20140149777 | POWER SAVING SYSTEM AND METHOD - A computer obtains signals from interfaces of a graphics card in the computer. The computer turns off a switch that provides power to a graphics output unit corresponding to the interface, in response to a determination that the interface is not connected to a display device. The computer turns on the switch that provides power to the graphics output unit corresponding to the interface, in response to the determination that the interface is connected to the display device. | 05-29-2014 |
| 20140149778 | METHOD FOR TEMPORARY OPERATION OF AN AUTOMATED ANALYSIS DEVICE IN A STANDBY MODE - The present invention relates to an automated analysis device ( | 05-29-2014 |
| 20140164809 | METHODS AND DEVICES FOR REGULATING POWER IN WIRELESS RECEIVER CIRCUITS - Access terminals are adapted to regulate power in wireless receiver circuits. In one example, access terminals include a communications interface with at least one wireless receiver circuit. A processing circuit coupled with the communications interface can determine that data is not expected to be received by the access terminal for a period of time while operating in a connected mode. One or more components of the wireless receiver circuit, including a low noise amplifier (LNA) of the wireless receiver circuit, can subsequently be powered down (e.g., set to a passive state) in response to such a determination. Other aspects, embodiments, and features are also claimed and described. | 06-12-2014 |
| 20140164810 | SYSTEM AND METHODS FOR DIMM-TARGETED POWER SAVING FOR HYPERVISOR SYSTEMS - A method of saving power in a computing system having a plurality of dial in-line memory modules (DIMMs) and employing a suspend-to-RAM sleep mode includes, when entering suspend-to-RAM sleep mode, consolidating selected information into a subset of DIMMs, and turning off power to all other DIMMs. A DIMM power rail may be coupled to each of the DIMMs, the DIMM power rail being configured to selectively have power being supplied to respective DIMMs turned off in response to enable/disable logic signals. | 06-12-2014 |
| 20140181561 | POWER THROTTLING QUEUE - A power throttling queue includes a queue and a throttling circuit. The queue has multiple entries. Each entry has a data field and a valid field. The multiple entries include a first portion and a selectively disabled second portion. The throttling circuit is coupled to the queue, and selectively disables the second portion in response to a number of valid entries of the first portion. | 06-26-2014 |
| 20140181562 | METHOD FOR PREVENTING OVER-HEATING OF A DEVICE WITHIN A DATA PROCESSING SYSTEM - A method for providing over-heating protection of a target device within an information processing system is disclosed. A determination is made whether or not a power status of the information processing system is set to turn on a main power of a power supply device. If the power status of the information processing system is set to turn on a main power of a power supply device, a power switch of the target device is turned on; otherwise, another determining is made whether or not the target device is set to operate based on a user's setting. If the target device is set to operate based on the user's setting, the power switch of the target device is turned on; otherwise, the power switch of the target device is turned off. | 06-26-2014 |
| 20140189408 | SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION - Particular embodiments described herein can offer an apparatus that includes logic, the logic at least partially comprising hardware logic to receive a first notification indicating that at least one first user interaction device has become precluded; and cause, by a processor and absent intermediate operation of operating system software, disabling of at least one second user interaction device based, at least in part, on the first notification. | 07-03-2014 |
| 20140189409 | SYSTEM AND METHOD FOR PROVIDING UNIVERSAL SERIAL BUS LINK POWER MANAGEMENT POLICIES IN A PROCESSOR ENVIRONMENT - One particular example implementation may include an apparatus that includes logic, at least a portion of which is in hardware, the logic configured to: determine that a first device maintains a link to a platform in a selective suspend state; assign a first latency value to the first device; identify at least one user detectable artifact when a second device exits the selective suspend state; and assign, to the second device, a second latency value that is different from the first value. | 07-03-2014 |
| 20140189410 | SYSTEMS AND METHODS FOR PREDICTIVE POWER MANAGEMENT IN A COMPUTING CENTER - Aspects and implementations of the present disclosure are directed to systems and methods for predictive power management in a computing center. In general, in some implementations, a system for conserving resources in a multi-processor computing environment monitors usage of the processors in the environment and maintains a sorted list of usage changes that occur in each of a plurality of periodic intervals. The system uses the sorted list to predict, according to configurable parameters, how many processors will need to be available during a subsequent interval. In some implementations, the monitored intervals are consecutive and immediately prior to the subsequent interval. In some implementations, the usage changes during a periodic interval are determined as the difference between a maximum number of active-busy processors during the periodic interval and an initial number of active-busy processors for the periodic interval. | 07-03-2014 |
| 20140189411 | POWER CONTROL FOR CACHE STRUCTURES - Techniques are disclosed relating to reducing power consumption in integrated circuits. In one embodiment, an apparatus includes a cache having a set of tag structures and a power management unit. The power management unit is configured to power down a duplicate set of tag structures in responsive to the cache being powered down. In one embodiment, the cache is configured to provide, to the power management unit, an indication of whether the cache includes valid data. In such an embodiment, the power management unit is configured to power down the cache in response to the cache indicating that the cache does not include valid data. In some embodiments, the duplicate set of tag structures is located within a coherence point configured to maintain coherency between the cache and a memory. | 07-03-2014 |
| 20140195843 | METHOD AND SYSTEM FOR BATTERY POWER SAVING - The present disclosure provides a method and system for saving battery power. The method comprises: determining whether a new program has been initiated by a user and, when a new program has been initiated by the user, storing the new program initiated by the user in a history database; determining whether the user is connected to a network and, when the user is connected to a network, storing a network connection record of the user in the history database; determining whether a battery level triggers a dynamic power saving schedule and, when the battery level triggers the dynamic power saving schedule, performing the power saving schedule using a power saving scheduling engine; and determining whether a screen being turned off triggers a dynamic network schedule and, when the screen being turned off triggers the dynamic network schedule, performing the network schedule using a network scheduling engine. The method for saving battery power according to the present disclosure provides an improved intelligence in program control and/or network management | 07-10-2014 |
| 20140201553 | MULTI-ELEMENT MEMORY DEVICE WITH POWER CONTROL FOR INDIVIDUAL ELEMENTS - A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes side-band circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers. | 07-17-2014 |
| 20140201554 | POWER SOURCE MANAGEMENT DEVICE, POWER SOURCE MANAGEMENT METHOD, AND COMPUTER-READABLE RECORDING MEDIUM - A management server includes a storage unit that stores therein destination physical machine information capable of identifying a physical machine serving as a destination candidate of a certain virtual machine that operates on any one of a plurality of physical machines. The management server includes a control unit that performs the following control. To stop power supply to a first physical machine group performed by a first control unit, the control unit detects. The control unit changes the destination physical machine information such that the destination candidate of the certain virtual machine includes at least a physical machine belonging to a second physical machine group when information capable of identifying the physical machine serving as the destination candidate and stored in the storage unit includes no other physical machine than a physical machine belonging to the first physical machine group. | 07-17-2014 |
| 20140201555 | METHOD AND SYSTEM FOR GOVERNING AN ENTERPRISE LEVEL GREEN STORAGE SYSTEM DRIVE TECHNIQUE - A method and system for manipulating a spin state of each disk in a drive array is disclosed. In one embodiment, a method includes monitoring input/output (I/O) requests to each disk drive in a disk array and identifying any disk drive as an inactive disk drive based on a number of I/O requests directed to said any disk drive for a given time interval. The method further includes moving data from the inactive disk drive to an active disk drive having a free disk space to store the data and updating metadata associated with the data using a log-structured file system for the disk array. Further, the method includes manipulating a spin state of the inactive disk drive by spinning down the inactive disk drive to conserve power. Furthermore, the method includes redirecting subsequent I/O requests for the inactive disk drive to the active disk drive by accessing the metadata of the log-structured file system. | 07-17-2014 |
| 20140208144 | Method and Apparatus for Adaptive Power Management of Memory Subsystem - A method and apparatus are disclosed for performing adaptive memory power management in a system employing a CPU and a memory subsystem. A CPU throttle control (THR) module generates a CPU throttle control signal indicating when the CPU is idle. A memory controller (MC) module generates memory power management signals based on at least one of the CPU throttle control signal, memory read/write signals, memory access break events, and bus master access requests. Certain portions of the memory subsystem are powered down in response to the memory power management signals. Memory power management is performed on a time segment by time segment basis to achieve efficient power management of the memory subsystem during CPU run time. | 07-24-2014 |
| 20140208145 | METHODS AND APPARATUS FOR SAVING POWER - In one example embodiment, a device uses a camera and an eye detection service to determine whether a user is looking at a display of the device during periods when the user is not actively interacting with the device. In response to a determination that the user is not looking at the display, the display is automatically powered off. In response to the user's resumption of looking at the display, the display may be automatically powered back on. Other embodiments are described and claimed. | 07-24-2014 |
| 20140215252 | Low Power Control for Multiple Coherent Masters - Systems and methods are provided for efficiently managing power among system components. In an embodiment, a power manager receives information from subsystems and determines which subsystem components will require power to perform upcoming tasks. Based on this received information, the power manager can power on and power down individual subsystem components. Systems and methods according to embodiments of the present disclosure enable a cache of a subsystem to be powered on without requiring a power-up of every component of the subsystem. Thus, disclosed systems and methods enable a first subsystem to snoop into a cache of a second subsystem without requiring a full power-up of the second subsystem. | 07-31-2014 |
| 20140223213 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile memory, a controller configured to control an operation of the nonvolatile memory, a connector electrically connected to a host device, a power supply circuit configured to electrically connect the connector to the controller and the nonvolatile memory, and a power supply control circuit electrically connected to the connector and configured to control an operation of the power supply circuit in response to a first request sent from the host device. The power supply circuit cuts power supplies to the controller and the nonvolatile memory in response to the first request. | 08-07-2014 |
| 20140223214 | DYNAMIC POWER MODE SWITCHING PER RAIL - Aspects of dynamic power mode switching per rail based on power profiling are described. In one embodiment, an amount of current supplied by at least one of a plurality of power rails is sensed with a current sense circuit. The amount of current is profiled over a period of time and a profile of power consumed is generated and maintained. With reference to the power profile, one or more power-related decisions may be made in a system. One or more power rails may be powered off or placed into low power mode based on various factors, such as the amount of current being consumed per rail, the temperature of certain system components, or an unexpected ongoing consumption of power in the system. | 08-07-2014 |
| 20140223215 | SYSTEM AND METHOD FOR POWER MANAGEMENT OF STORAGE RESOURCES - A system and method for power management of storage resources are disclosed. A method may include detecting an occurrence of an event associated with a storage resource disposed in an array of storage resources. The method may further include transitioning the storage resource into a specified power state in response to the detection of the occurrence of the event. A system may include a storage resource and a power management module communicatively coupled to the storage resource. The storage resource may be disposed in an array of storage resources. The power management module may be operable to detect an occurrence of an event associated with the storage resource, and may be operable to transition the storage resource into a specified power state in response to the detection of the occurrence of the event. | 08-07-2014 |
| 20140223216 | POWER MANAGEMENT OF LOW POWER LINK STATES - A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described. | 08-07-2014 |
| 20140245050 | POWER MANAGEMENT FOR HOST WITH DEVICES ASSIGNED TO VIRTUAL MACHINES - A system and method of removing power from a device assigned to a virtual machine running on a host machine includes receiving a request, by a notification module, from the virtual machine to remove power from the device, and receiving, by the notification module, an indication from the virtual machine that a condition has been satisfied; managing an execution priority for requests, by a task module, where the task module schedules the request to be executed after the notification module receives the indication that the condition has been satisfied; and in response to execution of the request, by a power down module, sending a communication to the host machine to cause the host machine to remove power from the device. | 08-28-2014 |
| 20140245051 | DRIVER CIRCUIT POWERED BY TWO POWER SUPPLIES SEQUENTIALLY ACTIVATED - A driver circuit including front and rear amplifiers each powered by the primary and secondary power supplies, where the latter power supply is generated from the former power supply. The rear amplifier includes a cascade transistor whose base bias is provided from the bias source. The bias source provides the base bias to reduce the base current when the primary power supply is active but the secondary power supply is inactive, and to be equal to the primary power supply when two power supplies become active but the rear amplifier is inactive. | 08-28-2014 |
| 20140245052 | Method and device for storing an item of wake-up information in users of a can bus system - A device for connecting a user station to a CAN bus, the user station in the active state being able to exchange messages with other user stations via the CAN bus using the device, according to the standard ISO 11898; the user station in the at-rest state being able to be activated using the device, in response to the reception of a wake-up information; the wake-up information configured as a CAN message according to the standard ISO 11898; in the device, a suitable first arrangement selectively evaluating the wake-up information received, so that the wake-up process is initiated only in response to the presence of wake-up information that is specified or specifiable for the respective user station which is characterized in that a storage arrangement is provided in the device in order, in case the wake-up process is initiated, which store the wake-up information evaluated for this entirely or partially. | 08-28-2014 |
| 20140245053 | DISTRIBUTED COMPUTER SYSTEM - A local computer ( | 08-28-2014 |
| 20140250316 | Data Transfer Operation Completion Detection Circuit and Semiconductor Memory Device Provided Therewith - A data transfer operation completion detection circuit including a first counter for performing a shifting operation in response to the generation of a read initiation signal, a second counter for performing a shifting operation in response to the generation of a burst completion signal, and an SR latch circuit for generating a read enable signal in response to the burst completion signal being generated when the count value of the first counter matches the count value of the second counter. The completion of a read operation or another data transfer operation is thus detected based on a read initiation signal reception history; therefore, it is possible to detect whether all read operations are complete at a given time even if a new read command is received while a read operation or the like is in progress. | 09-04-2014 |
| 20140258758 | IMAGE FORMING APPARATUS AND CONTROL METHOD THEREOF - An image forming apparatus and a control method thereof includes an image forming unit to form images, a main control unit to control operations of the image forming unit; a switching unit to selectively supply an operating voltage to the main control unit according to a level of the voltage control, a power mode selecting unit to convert an on state or an off state according to a user's operation, a first voltage determining unit to determine a level of the control voltage according to the state of the power mode selecting unit, and a second voltage determining unit to determine the level of the control voltage in parallel with the first voltage determining unit, according to the control signal output from the main control unit. | 09-11-2014 |
| 20140258759 | SYSTEM AND METHOD FOR DE-QUEUING AN ACTIVE QUEUE - Aspects of the disclosure pertain to a system and method for de-queuing an active queue. The system promotes power efficiency by providing a mechanism for allowing some of its active queues to be de-queued and one or more of its processors associated with those active queues to be powered off during low traffic periods. Using fewer than all of its queues and processors, the system can handle incoming traffic during these low traffic periods without packet loss and without ordering issues. | 09-11-2014 |
| 20140281637 | MEMORY STATE MANAGEMENT FOR ELECTRONIC DEVICE - In one embodiment a controller comprises logic to determine whether an electronic device is operating in a low power state and in response to a determination that the electronic device is operating in a low power state, implement a memory state management routine which reduces power to at least a section of volatile memory in the memory system. Other embodiments may be described. | 09-18-2014 |
| 20140281638 | APPLICATION OF NORMALLY CLOSED POWER SEMICONDUCTOR DEVICES - A power source delivers power from a main power source using switching by a normally on transistor. A driver switches on and off the normally on transistor under a control signal by a controller during regular operation. A housekeeping power supply delivers auxiliary power to the driver. The driver switches off the normally on transistor during irregular operation. Irregular operation occurs at least when the control signal is absent or no auxiliary power is available or during transients such a power up or down. Bridge block pairs thereof can be arranged to form a half bridge power switch, an H bridge switch, a three phase bridge switch, a multi-phase switch, a buck converter, a buck-boost converter, or a boost converter. | 09-18-2014 |
| 20140281639 | DEVICE POWER MANAGEMENT STATE TRANSITION LATENCY ADVERTISEMENT FOR FASTER BOOT TIME - Methods and apparatus relating to device power management state transition latency advertisement for faster boot time are described. In some embodiments, a storage unit stores a value corresponding to a requisite transition delay period for a first agent to exit from a low power consumption state. The first agent writes the value to the storage unit and a second agent waits for the requisite transition delay period (after the first agent initiates its exit from the low power consumption state) before the second agent attempts to communicate with the first agent via a link. Other embodiments are also disclosed and claimed. | 09-18-2014 |
| 20140289549 | Methods and Apparatuses for Computer Power Down - The discussion makes reference to methods and apparatuses for network controlled computer power down. The link layer in computer networking can be used to save power in computers. | 09-25-2014 |
| 20140298067 | METHODS AND APPARATUS FOR REDUCING ENERGY CONSUMPTION OF NETWORK EQUIPMENT - In some embodiments, an equipment unit has a set of visual indicators, a power switch, and a set of compute components. The power switch receives a signal representing a status such that when the status is in a first mode, the power switch provides power to the set of visual indicators and when the status is in a second mode the power switch does not provide power to the set of visual indicators. The compute components are configured to receive power when the power switch does not provide power to the set of visual indicators. | 10-02-2014 |
| 20140298068 | DISTRIBUTION OF POWER GATING CONTROLS FOR HIERARCHICAL POWER DOMAINS - An integrated circuit device includes a first module disposed within a first power domain, a second module disposed in a second power domain that is a sub-domain of the first power domain, first power gating logic, and second power gating logic. The first power gating logic generates a first virtual power supply for the first module. The second power gating logic is powered by the first virtual power supply for generating a second virtual power supply for the second power domain. | 10-02-2014 |
| 20140304541 | Method for preventing over-heating of a device within a data processing system - A method for providing over-heating protection of a target device within an information processing system is disclosed. A determination is made whether or not a power status of the information processing system is set to turn on a main power of a power supply device. If the power status of the information processing system is set to turn on a main power of a power supply device, a power switch of the target device is turned on; otherwise, another determining is made whether or not the target device is set to operate based on a user's setting. If the target device is set to operate based on the user's setting, the power switch of the target device is turned on; otherwise, the power switch of the target device is turned off. | 10-09-2014 |
| 20140310552 | REDUCED-POWER SLEEP STATE S3 - Current computer systems support sleep states such as sleep state S | 10-16-2014 |
| 20140317431 | METHOD AND SYSTEM FOR REMOTELY CONTROLLING A STORAGE SHELF OF A STORAGE SYSTEM - System and method for remotely performing a power cycle operation for a storage shelf of a storage server using a control path independent of a data path used for processing I/O requests is provided. The storage server maintains a data structure for storing information regarding a state of a plurality of power latches that are used to control power for the storage shelf having an alternate control path module for receiving control commands via the control path. Depending on the state of the plurality of power latches, the storage server sends one or more commands to the alternate control path module to turn off power to the storage shelf during a power cycle operation. When the power shelf is powered off, the storage server waits for a certain duration and then sends one or more power on commands to the alternate control path module to power on the storage shelf. | 10-23-2014 |
| 20140344605 | CONTENT PRESENTATION SYSTEM AND METHOD - The present disclosure relates to a method and system for content presentation in a main processor shutoff mode. A method for content presentation includes transferring content to at least one of a co-processor and storage accessible by the co-processor and shutting off the main processor in response to the transferring of content such that the main processor is disabled while the co-processor presents the content stored in the storage. The content may include at least one of multimedia data, text data, and image data. A disclosed system includes a main processor in communication with a co-processor. The main processor includes data transfer logic operative to transfer the content and to shut off the main processor in response to the transferring of content such that the main processor is disabled while the co-processor presents the content stored in the storage. | 11-20-2014 |
| 20140344606 | Electronic System and Method for Starting Electronic System Through CEC - A method for starting an electronic system through CEC is disclosed, in which the electronic system includes a power management controller and a processing circuit controlled by the power management controller. In the method, a CEC bus which is electrically connected to the power management controller is detected, and a CEC data transmitted from the CEC bus is compared with a pre-determined logic value. After that, the processing circuit is powered on when the CEC data is equal to the pre-determined logic value. | 11-20-2014 |
| 20140344607 | FILE SHARING CIRCUIT AND COMPUTER USING THE SAME - File sharing circuit and computer using the same are provided. The computer includes a computer host and a file sharing circuit. The computer host includes a first storage device, a first system control chip, a control unit, and a power integrated circuit. The file sharing circuit includes a second system control chip and a first bus switch. When the second system control chip performs a file sharing procedure, the power integrated circuit powers the first storage device, the second system control chip, and the first bus switch, and the control unit switches the first bus switch to a first state so that the second system control chip accesses the first storage device. When the second system control chip does not perform the file sharing procedure, the control unit switches the first bus switch to a second state so that the first system control chip accesses the first storage device. | 11-20-2014 |
| 20140344608 | AUTOMATICALLY ADJUSTING DISPLAY AREAS TO REDUCE POWER CONSUMPTION - In an embodiment, a method includes receiving user interface information having event registrations for a user interface to be displayed on a display of a system, partitioning the display into an unused display area and an active display area based on the event registrations, and power managing the unused display area while maintaining the active display area fully powered. Other embodiments are described and claimed. | 11-20-2014 |
| 20140359334 | RECEIVING, AT LEAST IN PART, AND/OR ISSUING, AT LEAST IN PART, AT LEAST ONE PACKET TO REQUEST CHANGE IN POWER CONSUMPTION STATE - An embodiment may include circuitry to be included, at least in part, in at least one node to be used in a network. The circuitry may (a) receive, at least in part, via at least one power supply line of the at least one node, at least one packet, and/or (b) issue, at least in part, via the at least one power supply line, the at least one packet. The at least one packet may request at least one change, at least in part, in at least one power consumption state of at least one portion of the at least one node. Many modifications, variations, and alternatives are possible without departing from this embodiment. | 12-04-2014 |
| 20140359335 | MULTI-CORE APPARATUS AND JOB SCHEDULING METHOD THEREOF - A multi-core apparatus includes cores each including an active cycle counting unit configured to store an active cycle count, and a stall cycle counting unit configured to store a stall cycle count. The multi-core apparatus further includes a job scheduler configured to determine an optimal number of cores in an active state based on state information received from each of the cores, and adjust power to maintain the optimal number of cores. | 12-04-2014 |
| 20140365803 | Motion Fencing - In some implementations, a mobile device can be configured with virtual motion fences that delineate domains of motion detectable by the mobile device. In some implementations, the mobile device can be configured to invoke an application or function when the mobile device enters or exits a motion domain (by crossing a motion fence). In some implementations, entering or exiting a motion domain can cause components of the mobile device to power on or off (or awaken or sleep) in an incremental manner. | 12-11-2014 |
| 20140365804 | Non-Intrusive Power Management - A method and system for managing power consumption of a pool of computing devices are disclosed. One aspect of certain embodiments includes managing resource utilization for each computing device without installing customized software, firmware or hardware on the computing device and dynamically selecting, one or more candidate computing devices for altering their respective power states based on at least real-time information on the quantity of requests. | 12-11-2014 |
| 20140380078 | IMAGE FORMING APPARATUS AND POWER CONTROL METHOD THEREOF - An image forming apparatus and a power control method thereof are provided. The image forming apparatus includes: an image forming unit which forms an image; a power supply which supplies operating power for the image forming apparatus; a switching circuit unit which switches to selectively supply the operating power; a memory unit which stores information about power status of the switching circuit unit; and a controller which outputs a power control signal for controlling a switching operation of the switching circuit unit in accordance with the information about the power status stored in the memory unit if power is abnormally shut off and then supplied again from the power supply to the switching circuit unit. With this, the image forming apparatus operates in a last power status, so that power can be prevented from being wastefully consumed or data can be prevented from being lost. | 12-25-2014 |
| 20150012770 | METHOD AND APPARATUS FOR TRANSITIONING A DEVICE BETWEEN OPERATING STATES TO CONTROL POWER CONSUMED BY THE DEVICE - A method including: accounting for a transition time for a device to transition between two of first, second, and powered off states; generating a control signal based on the transition time; receiving, at the device and from a processor, an output signal and the control signal; and consuming power, via the device, while operating in the first state and the second state. The method further includes: in response to the control signal, transitioning the device to the second state based on a frequency of the output signal or the control signal; subsequent to transitioning to the second state, performing a function based on the first output signal; and subsequent to performing the function, generating an output via the device; generating a feedback signal based on the output; and based on the feedback signal, transitioning the device to either the first state or the powered off state. | 01-08-2015 |
| 20150012771 | POWER MANAGEMENT FOR INPUT/OUTPUT DEVICES - Methods and systems are provided for managing power consumption in network devices. In a network device that may comprise a plurality of ports, each of which being identified by a unique identifier and being adapted to handle separate network traffic, it may be determined whether a first port of the network device may need to be reactivated, where the first port may have been previously shut down by directing of traffic corresponding to the first port, through a virtual port generated on a second port. When the first port is to be reactivated, the virtual port may be turned off, and the first port may then be reactivated. Traffic being routed through the virtual port may be routed before shutting it down; and the paused traffic to and from the network device may be resumed through the first port after it is reactivated. | 01-08-2015 |
| 20150019896 | METHOD TO CONTROL THE NUMBER OF ACTIVE VECTOR LANES FOR POWER EFFICIENCY - The vector data path is divided into smaller vector lanes. The number of active vector lanes is controllable on the fly by the programmer to match the requirements of the executing program, and inactive vector lanes are powered down by the CPU to increase power efficiency of the vector processor. | 01-15-2015 |
| 20150019897 | COMMUNICATION SYSTEM, RELAY DEVICE, AND METHOD FOR CONTROLLING POWER SUPPLY - The present invention provides a communication system including a relay device that is capable of simplifying the configuration of a control device for controlling a device based on relay information and reducing cost of the whole system, the relay device and a method for controlling power supply. A GW device includes first to fourth communication parts respectively connected to communication buses, which are connected to ECUs respectively. The GW device receives a message transmitted from each of ECUs, extracts signal information S | 01-15-2015 |
| 20150026499 | CIRCUIT FOR CHANGING LOAD OPERATION USING TEMPORARY POWER-OFF MEANS - A circuit for changing load operation using temporary power-off means having a power-off detection circuit with input end connected to a power source and its output end is connected to a microprocessor (MCU) connected to at least one load driving circuit. A load appliance is mounted on each of the load driving circuits. The microprocessor (MCU) has a program controlling each load appliance. During operation, the power is restored immediately after the power source is temporarily powered off, such that the power-off detection circuit detects a temporary turned-off signal and sends the signal to the microprocessor (MCU). Accordingly, the program to control each of the load appliances in the microprocessor (MCU) manipulates each load appliance for performing another operation or function. | 01-22-2015 |
| 20150026500 | GENERAL PURPOSE PROCESSING UNIT WITH LOW POWER DIGITAL SIGNAL PROCESSING (DSP) MODE - A method and circuit arrangement utilize a general purpose processing unit having a low power DSP mode for reconfiguring the general purpose processing unit to efficiently execute DSP workloads with reduced power consumption. When in a DSP mode, one or more of a data cache, an execution unit, and simultaneous multithreading may be disabled to reduce power consumption and improve performance for DSP workloads. Furthermore, partitioning of a register file to support multithreading, and register renaming functionality, may be disabled to provide an expanded set of registers for use with DSP workloads. As a result, a general purpose processing unit may be provided with enhanced performance for DSP workloads with reduced power consumption, while also not sacrificing performance for other non-DSP/general purpose workloads. | 01-22-2015 |
| 20150033057 | POWER CONSERVATION BASED ON CACHING - The present invention relates to a method and device that conserves power. In some embodiments, the device is a battery powered storage device. The invention employs a large cache and aggressive caching algorithm to serve data from the storage media (hard disk or SSD) or write data to the storage media. The cache provides an efficient location from which to serve data, especially multi-media. In one embodiment, the algorithm determines when to place the drive into a lower power state, such as idle, or standby, based on the amount of anticipated idle time provided by the large cache. | 01-29-2015 |
| 20150033058 | SERVER CLUSTER AND CONTROL MECHANISM THEREOF - A server cluster including a network switch and multiple server nodes is provided. The network switch is connected to an external network. Each server node includes a network port, a network chip and a control unit. The network port is connected to the network switch via a cable. The network chip detects the cable to obtain a connection state with the external network at the server node after the network switch is started, and accordingly outputs a connection state signal. The control unit turns on or shuts down the server node according to the connection state signal and an on/off state of the server node. | 01-29-2015 |
| 20150046735 | PROCESSOR, NON-TRANSITORY COMPUTER READABLE MEDIUM, AND PROCESSING METHOD - A processor includes a communicating unit, a receiving unit, a processing unit, and a power-off controller. The receiving unit receives an operation from a user. The processing unit executes processing according to a processing request received by at least one of the communicating unit and the receiving unit. If a power-off request is received from a terminal by the communicating unit, the power-off controller stops the processing unit and disconnects a power supply when the operation received from the user by the receiving unit is not being processed and a condition determined in accordance with a processing mode of the power-off request is satisfied. | 02-12-2015 |
| 20150046736 | Uncore Thermal Management - A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value. | 02-12-2015 |
| 20150046737 | INERTIAL FORCE SENSOR AND ELECTRONIC DEVICE USING SAME - An inertial force sensor includes the following elements: a sensor element for converting an inertial force into an electrical signal; a sensor signal processor connected to the sensor element, for outputting an inertial force value; and a power controller for controlling electric power supply to the sensor signal processor, based on the inertial force value. When the inertial force value is maintained for a predetermined time period within a predetermined range in which a reference value is the middle value of the range, the power controller reduces the electric power supply to the sensor signal processor and updates the reference value to the inertial force value obtained after a lapse of the predetermined time period. | 02-12-2015 |
| 20150052377 | Method And Apparatus For A Zero Voltage Processor - Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory. | 02-19-2015 |
| 20150058650 | Forcing Core Low Power States In A Processor - In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed. | 02-26-2015 |
| 20150058651 | METHOD AND APPARATUS FOR SAVING BATTERY OF PORTABLE TERMINAL - A method for saving a battery power of a terminal includes receiving a touch input on a touch screen, detecting an input stop event where the touch input is stopped, switching the touch screen to a turned-off state or a dim state, in response to the input stop event, and detecting an input resume event where the touch input is resumed during the turned-off state or the dim state, and switching the touch screen to be a turned-on state in response to the input resume event. Other embodiments including an apparatus for saving a battery power are also disclosed. | 02-26-2015 |
| 20150067374 | ELECTRONIC DEVICE, CONTROL METHOD OF ELECTRONIC DEVICE, AND IMAGE FORMING APPARATUS - An electronic device, a control method of the electronic device, and an image forming apparatus to cut off unnecessary power after recognizing connection/disconnection statuses of Universal Serial Bus (USB) hosts/devices connected to a USB hub are provided. The electronic device includes a USB hub connected to a USB host/device, a first switch configured to switch power supply to the USB hub for reducing power consumption, a controller configured to turn the first switch off to cut off power supply to the USB hub when no USB host/device is connected to the USB hub or only a USB host/device not requiring constant power supply is connected to the USB hub. | 03-05-2015 |
| 20150067375 | INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING DEVICE, AND INFORMATION PROCESSING METHOD - An information processing system includes a receiving unit that receives user operation; a setting unit that holds association information in which pieces of necessity information each indicating necessity of a shutdown process indicating a process required for stopping power supply to a corresponding device are associated with a plurality of devices, respectively; a first instruction unit that instructs a target device for which the power supply is to be stopped to perform the shutdown process when the receiving unit receives operation to stop the power supply and the target device requires the shutdown process based on the association information; and a second instruction unit that instructs a power supply control device that controls execution or stop of the power supply to the target device to stop the power supply to the target device when the shutdown process of the target device is completed. | 03-05-2015 |
| 20150074440 | LINK POWER SAVINGS WITH STATE RETENTION - Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed. | 03-12-2015 |
| 20150082069 | ACCELERATING MICROPROCESSOR CORE WAKE UP VIA CHARGE FROM CAPACITANCE TANK WITHOUT INTRODUCING NOISE ON POWER GRID OF RUNNING MICROPROCESSOR CORES - A mechanism is provided for an integrated circuit with power gating. A power switch is configured to connect and disconnect circuits to a common voltage source. A capacitor tank is configured to supply wakeup charge to a given circuit. A controllable element is connected to the given circuit and to the capacitor tank. The controllable element is configured to controllably connect and disconnect the capacitor tank to the given circuit in order to supply the wakeup charge to the given circuit. The controllable element is configured to, responsive to the power switch disconnecting the given circuit from the common voltage source and to the given circuit being turned on to wakeup, supply the wakeup charge to the given circuit being turned on by transferring the wakeup charge from the capacitor tank to the given circuit. This reduces the electrical charge transferred from the circuits connected to the common voltage source. | 03-19-2015 |
| 20150082070 | ACCELERATING THE MICROPROCESSOR CORE WAKEUP BY PREDICTIVELY EXECUTING A SUBSET OF THE POWER-UP SEQUENCE - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any one of multiple circuits to a common voltage source, where a powered off circuit is disconnected from the common voltage source. A power-up sequencer includes an initial stages power-up component and a final stages power-up component. The final stages power-up component is configured to execute final stages of a power-up process for the powered off circuit, and the initial stages power-up component is configured to execute initial stages of the power-up process for the powered off circuit. The initial stages power-up component is activated in response to a predictive power-up request. | 03-19-2015 |
| 20150089266 | SWITCH CIRCUIT AND COMPUTING DEVICE HAVING SAME - A computing device includes a display, a universal serial bus (USB) power source having a voltage output port to output a voltage to power input/output (I/O) devices connected to USB interfaces of the computing device, and a switch circuit connected between the display and the USB power source. The switch circuit can synchronously turn off the display and control the USB power source to stop outputting the voltage, and can synchronously turn on the display and control the USB power source to output the voltage. | 03-26-2015 |
| 20150089267 | MEMORY CONTROL DEVICE THAT CONTROL SEMICONDUCTOR MEMORY, MEMORY CONTROL METHOD, INFORMATION DEVICE EQUIPPED WITH MEMORY CONTROL DEVICE, AND STORAGE MEDIUM STORING MEMORY CONTROL PROGRAM - A memory control device that is capable of making a nonvolatile memory of an information device exhibit the performance thereof certainly. A detection unit detects whether a data writable semiconductor memory is a nonvolatile memory or a volatile memory. A setting unit performs a setting to a volatile memory and performs a different setting to a nonvolatile memory that is detected with the detection unit. | 03-26-2015 |
| 20150089268 | APPARATUS AND METHOD FOR REDUCING POWER CONSUMPTION CAUSED BY COMMUNICATION BETWEEN PROCESSORS IN PORTABLE TERMINAL - An apparatus and method for reducing power consumption in a portable terminal are provided. The apparatus includes a display unit for displaying at least one indicator that indicates status information measured by a slave processor, a master processor for controlling one of ON and OFF of the display unit and for providing image data to the display unit, and the slave processor for transmitting to the master processor indicator update information for updating the at least one indicator, wherein transmission to the master processor of the indicator update information is discontinued if the status of the display unit is OFF. | 03-26-2015 |
| 20150095686 | POWER CONSUMPTION REDUCTION IN A COMPUTING DEVICE - Various techniques for reducing power consumption of a computing device are described herein. In one example, a method includes detecting that the computing device is to execute a first operation for a first hardware component. The method can also include determining that the computing device is not to execute a second operation for a second hardware component during a period of time. Furthermore, the method can include loading operation data corresponding to the first operation into a processor cache from a non-volatile storage device and detecting that the first operation is not to request memory data from a volatile storage device. The method can also include removing power from at least one storage device. | 04-02-2015 |
| 20150095687 | POWER CONTROL TECHNIQUES FOR INTEGRATED PCIE CONTROLLERS - Improved power control techniques for integrated peripheral component interconnect express (PCIe) controllers are described. In one embodiment, for example, a processor circuit may comprise an integrated PCIe controller and logic to detect a power reduction trigger, disable the integrated PCIe controller, and remove power from the integrated PCIe controller based on a power removal setting for the integrated PCIe controller. Other embodiments are described and claimed. | 04-02-2015 |
| 20150100810 | ADAPTIVE POWER-DOWN OF DISK DRIVES BASED ON PREDICTED IDLE TIME - Systems and methods presented herein provide a storage system that adaptively powers-down one or more disk drives based on the predicted idle time of each disk drive. One embodiment includes a storage controller that includes a processor operable to track idle durations of the disk drive. When an idle duration ends, the processor associates the idle duration with a time window that includes that idle duration. Each time window is associated with a number of previous idle durations of the disk drive. Upon detection of a current idle duration, the processor identifies a time window with the highest number of previous idle durations of the disk drive. Then, the processor determines whether a maximum time associated with the identified time window exceeds a predetermined threshold. When the maximum time exceeds the predetermined threshold, the processor powers-down the disk drive. | 04-09-2015 |
| 20150100811 | ELECTRONIC CONTROL UNIT - An electronic control unit of one embodiment includes first and second microcomputers for mutually monitoring operations, an output circuit for outputting a signal that is outputted from at least one of the first and second microcomputers, a power supply circuit for supplying electric power to the output circuit, and a stop unit for stopping supply of the electric power from the power supply circuit to the output circuit. The first microcomputer has operation modes including a normal mode and a low power mode. In the low power mode, the first microcomputer stops monitoring the operation of the second microcomputer and outputs a power supply stop signal that operates the stop unit to stop the supply of the electric power from the power supply circuit to the output circuit. | 04-09-2015 |
| 20150106640 | ACCELERATED THERMAL MITIGATION FOR MULTI-CORE PROCESSORS - A temperature sensor may sense the temperature of a multi-core processor. In response to the temperature of the multi-core processor exceeding a temperature threshold for the multi-core processor, one or more busy processor cores of the multi-core processor may be power collapsed without reducing clock speed of the multi-core processor. | 04-16-2015 |
| 20150121111 | SYSTEM AND METHOD FOR PROVIDING MULTI-USER POWER SAVING CODEBOOK OPTMIZATION - Systems and methods are disclosed for providing multi-user power saving codebook optimization. One such method comprises: generating a unique codebook for a plurality of computing devices, each unique codebook configured for encoding memory data in the corresponding computing device; providing the unique codebooks to the corresponding computing devices via a communications networks; receiving compression statistics from one or more of the computing devices via the communications network, the compression statistics related to the corresponding unique codebook; and generating an optimized codebook for at least one of the computing devices based on the received compression statistics. | 04-30-2015 |
| 20150121112 | METHOD FOR ADJUSTING SHUTDOWN THRESHOLD VOLTAGE, STARTUP METHOD, AND ELECTRONIC DEVICES THEREOF - The method for adjusting a shutdown threshold voltage includes: obtaining a current voltage of a battery of an electronic device; when the current voltage is greater than or equal to a lowest shutdown threshold of the electronic device and less than or equal to a general shutdown threshold of the electronic device, obtaining at least one piece of application information of at least one application program, where an application shutdown threshold of an application program corresponding to each piece of application information of the at least one piece of application information is greater than the lowest shutdown threshold and less than or equal to the current voltage; and setting a current shutdown threshold, which is corresponding to the current voltage, of the electronic device to a maximum application shutdown threshold of at least one application shutdown threshold corresponding to the at least one application program. | 04-30-2015 |
| 20150134994 | POWER MANAGEMENT FOR TOUCH CONTROLLER - Power management system or a touch controller can include a transmit section for transmitting stimulation signals to an associated touch sensor panel to drive the panel, where the touch controller can selectively adjust the transmit section to reduce power during the transmission. The touch controller can also include a receive section for receiving touch signals resulting from the driving of the panel, where the touch controller can selectively adjust the receive section to reduce power during the receipt of the touch signals. The touch controller can also include a demodulation section for demodulating the received touch signals to obtain touch event results, where the touch controller can selectively adjust the demodulation section to reduce power during the demodulation of the touch signals. The touch controller can also selectively reduce power below present low levels during idle periods. The touch controller can be incorporated into a touch sensitive device. | 05-14-2015 |
| 20150143153 | AUTOMATED INFRASTRUCTURE MANAGEMENT SYSTEMS AND METHODS FOR ENABLING REAL TIME ENERGY MANAGEMENT - Automated infrastructure management systems and methods document infrastructure elements within a facility, provide a comprehensive record of all network-connected equipment within a facility, and facilitate trouble shooting of network-connected equipment. An automated infrastructure management system includes a plurality of intelligent patch panels, each comprising a plurality of connector ports connected to individual communication channels of a network, a controller in communication with at least some of the intelligent patch panels that obtains connectivity information for the intelligent patch panel's ports, and management software in communication with the controller. The management software performs various functions including correlating the interconnection information for the intelligent patch panels with the physical location information for telecommunications in its database, applying energy management policies to a respective communication channel, providing real time physical location information for devices connected to communication channels to a network switch, and displaying real time physical location information of the devices. | 05-21-2015 |
| 20150149805 | Managing Graphics Power Consumption and Performance - The graphics pipeline produces real time utilization data for each of a plurality of functional units making up an overall graphics processor or graphics system on a chip. This information may be used for fine grain management of power consumption and performance at the functional unit level as opposed the overall device level. As a result, the graphics functional units may be managed dynamically based on real time hardware metrics to improve performance and reduce power consumption. The technique may be implemented in a software module in one embodiment. | 05-28-2015 |
| 20150293568 | Electronic Devices Having Integrated Reset Systems and Methods Thereof - Methods and devices for power cycling an electronic device are provided. Also provided are systems and kits. | 10-15-2015 |
| 20150293583 | POWER MANAGEMENT FOR TOUCH CONTROLLER - Power management for a touch controller is disclosed. The touch controller can include a transmit section for transmitting stimulation signals to an associated touch sensor panel to drive the panel, where the touch controller can selectively adjust the transmit section to reduce power during the transmission. The touch controller can also include a receive section for receiving touch signals resulting from the driving of the panel, where the touch controller can selectively adjust the receive section to reduce power during the receipt of the touch signals. The touch controller can also include a demodulation section for demodulating the received touch signals to obtain touch event results, where the touch controller can selectively adjust the demodulation section to reduce power during the demodulation of the touch signals. The touch controller can also selectively reduce power below present low levels during idle periods. The touch controller can be incorporated into a touch sensitive device. | 10-15-2015 |
| 20150324147 | LOW POWER DISTRIBUTED MEMORY NETWORK - A digital signal processing (DSP) system includes an analog to digital converter, program random access memory (PRAM), N switching devices, and a control module. The analog to digital converter is configured to convert samples of an analog signal into digital samples. The PRAM includes: N PRAM blocks, where N is an integer greater than one; and code for M digital signal processing functions stored in the N PRAM blocks, where M is an integer greater than one. The N switching devices are configured to connect and disconnect the N PRAM blocks, respectively, to and from a power source. The control module is configured to: control the N switching devices; and execute selected ones of the M digital signal processing functions on the digital samples to produce an output. | 11-12-2015 |
| 20150331476 | POWER SWITCHING TECHNIQUE FOR ARCHIVAL DATA STORAGE ENCLOSURE - A method of power management of a multiple-data-storage-devices enclosure is disclosed. In some embodiments, the method includes: receiving a network connection and power from a data connection port detachably coupled to a network cable; identifying a subset of data storage devices within the enclosure to activate; powering off components within the enclosure other than the subset of the data storage devices; for each data storage device in the subset that is not yet powered, activating the data storage device by: monitoring power consumption drawn from the data connection port; identifying a sequence of components associated with the data storage device, wherein the components within the sequence, when powered, together provide access to the data storage device; and powering on each component in the sequence when a previous component in the sequence has reached a steady state power consumption level, wherein when activating the data storage device, power supplied to power on the sequence of the components does not exceed a total power available from the data connection port. | 11-19-2015 |
| 20150331477 | LOW POWER ARCHIVAL DATA STORAGE ENCLOSURE - A method of controlling power within a multiple-data-storage-devices enclosure is disclosed. In at least one embodiment, the method comprises receiving a network connection and power from a data connection port to which a network cable is removably coupled; identifying one or more target data storage devices within the multiple-data-storage-devices enclosure to activate, wherein the one or more target data storage devices are a subset of all data storage devices within the multiple-data-storage-devices enclosure; powering off at least one of the data storage devices that draws power from the data connection port to make available additional power to supply from the data connection port; and powering the target data storage devices with the power received through the data connection port to activate the target data storage devices after all other data storage devices are powered off. | 11-19-2015 |
| 20150346795 | MULTI-HOST POWER CONTROLLER (MHPC) OF A FLASH-MEMORY-BASED STORAGE DEVICE - A multi-host power controller (MHPC) of a flash-memory-based storage device is disclosed. In one aspect, the MHPC receives power mode change requests from each of multiple input/output (I/O) clients. The MHPC extracts and stores a “vote,” or a requested power mode, from the power mode change requests, and then applies a voting logic to the stored votes to determine whether to transition the flash-memory-based storage device between power modes. If the flash-memory-based storage device is not currently operating in the power mode determined by the MHPC, the MHPC is configured to issue a power mode change command to the flash-memory-based storage device to transition to the determined power mode. In this manner, the MHPC is able to control the power mode of the flash-memory-based storage device while receiving direct power mode change requests from multiple I/O clients. | 12-03-2015 |
| 20150346801 | METHOD AND APPARTUS FOR DISTRIBUTED POWER ASSERTION - A method and an apparatus for a power assertion management are described. A power assertion indicator may be maintained for a device component having a power level. The power assertion indicator can indicate whether the power level of the device component is allowed to be lowered. A power assertion request may be sent from a first process to prevent lowering the power level of the device component before a data processing task is completed. A second process can receive a request from the first process to perform operations for the data processing task. The power level of the device component may not be allowed to be lowered before the second process completes the operations for the data processing task. The power level of the device component may be lowered after the data processing task is completed. | 12-03-2015 |
| 20150357865 | SYSTEMS AND METHODS FOR PROVIDING SCALABLE UNINTERRUPTABLE DC POWER TO A RACK-LEVEL POWER INFRASTRUCTURE - In accordance with the present disclosure, a battery back-up unit (BBU) element for providing uninterruptable direct current (DC) power in a rack-level power infrastructure is describe. The BBU element may include a rack-mountable chassis with a battery drawer. A battery may be disposed within the battery drawer, and at least one power module may be coupled to the battery. The BBU element may also include a power module controller that causes the battery to charge from or discharge to a busbar coupled to the BBU element. The power module controller may also communicate power management information to a power infrastructure controller. | 12-10-2015 |
| 20150362977 | ELECTRONIC DEVICE, METHOD, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, an electronic device is wearable by a user. The electronic device includes a first sensor, a second sensor, processing circuitry, and a power supply circuitry. The first sensor includes to measure a first physiological information of the user. The first physiological information is used to determine a wearing state of the electronic device. The second sensor includes to measure a second physiological information of the user. The processing circuitry includes to perform authentication of a user by using the second physiological information. The power supply circuitry includes to start, when a wearing state of the electronic device changes from an unworn state to a worn state, supplying power to the second sensor, and to stop, when the authentication of the user is completed, at least a portion of supplying power to the second sensor. | 12-17-2015 |
| 20150362980 | Always-On Processor as a Coprocessor - A system on a chip (SOC) may include a component that remains powered when the remainder of the SOC is powered off. The component may be configured to power up other components of the SOC while keeping the central processing unit (CPU) processors powered down, in order to perform a task assigned to such other component(s). The always-on component may further include a processor, in some embodiments, which may interact with the other components to perform the task. In an embodiment, the processor within the always-on component may execute operating system (OS) software to interact with the other components while the CPU processors are powered down. | 12-17-2015 |
| 20150362983 | SELECTIVE STORAGE RESOURCE POWERING FOR DATA TRANSFER MANAGEMENT - A mass data storage system includes a plurality of communicatively coupled storage resources arranged within a power grid. Responsive to receipt of a data transfer request, a compute node of the mass data storage system selectively powers from an off state one or more of the storage resources to receive incoming data or act as a data source for a read operation. | 12-17-2015 |
| 20150362984 | POWER-SAVING MODE FOR USB POWER DELIVERY SOURCING DEVICE - Methods of reducing power consumption in a USB power-delivery source device. In one such method, one or more source capabilities messages are sent by the USB power-delivery source device. If, after sending a source capabilities message, a response to said source capabilities message is not received within a predetermined time period, the device sends another source capabilities message. If, after sending a predetermined number of source capabilities messages, no response is received, the device waits an extended period of time before sending another source capabilities message. Receiving functionality of the USB power-delivery source device is turned off during some or all of said extended period of time. | 12-17-2015 |
| 20160011646 | SERVICE PROCESSOR (SP) INTIATEED DATA TRANSACTION WITH BIOS UTILIZING POWER OFF COMMANDS | 01-14-2016 |
| 20160018879 | POWER-SAVING METHOD AND ASSOCIATED ELECTRONIC DEVICE - A power-saving method and associated electronic device are provided. The electronic device is connected with a first external electronic device and a second external electronic device, and a first sensor and a second sensor are deployed on the first external electronic device and the second electronic device, respectively. The electronic device includes: a third sensor, and a processor, wherein the first, second, and third sensors have the same type. The processor gathers information from the first pedometer sensor, the second pedometer sensor, the first external electronic device, and the second external electronic device, and determines whether to turn off at least one of the first, second, and third pedometer sensors according to the information gathered. | 01-21-2016 |
| 20160041605 | IMAGE PROCESSING APPARATUS, CONTROL METHOD THEREFOR AND STORAGE MEDIUM - When the first time has elapsed after the operator operates a power switch to stop power supply, an image processing apparatus forcibly stops power supply. When stopping power supply, the image processing apparatus executes hibernation processing to retract, in a secondary storage device, the stored content of a main memory used as a work area by a CPU. When the hibernation processing will be completed within a target time necessary to complete the hibernation processing and end processing of the image processing apparatus before the first time elapses, the image processing apparatus executes the end processing of the image processing apparatus and stops power supply after completing the hibernation processing; otherwise, the image processing apparatus interrupts the hibernation processing, executes the end processing of the image processing apparatus, and stops power supply. | 02-11-2016 |
| 20160048193 | SUB-SYSTEM POWER MANAGEMENT CONTROL - An apparatus is disclosed that includes a processing sub-system having a plurality of processor circuits and an interrupt control circuit. The interrupt control circuit is configured to, in response to a peripheral interrupt, initiate performance of a task indicated by the peripheral interrupt by at least one of the plurality of processor circuits. The processing sub-system is configured to generate a power-down control signal in response to suspension of the plurality of processor circuits. A power management circuit disables power to the processing sub-system, including the interrupt control circuit, in response to the power-down control signal. The power management circuit enables power to the processing sub-system in response to a power-up control signal. The apparatus also includes a proxy interrupt control circuit configured to generate the power-up control signal in response to receiving a peripheral interrupt and power to the processing sub-system being disabled. | 02-18-2016 |
| 20160116962 | CONTROLLING METHOD FOR ELECTRONIC DEVICE - A method for controlling a central processor unit (CPU) of an electronic device includes establishing a corresponding relationship among operational parameters of the electronic device and a number of started cores of the CPU. Current operational parameters of the electronic device are acquired. The number of started cores of the CPU corresponding to the current operational parameters is adjusted based on the corresponding relationship. Then, the CPU is controlled to run with the adjusted number of started cores. | 04-28-2016 |
| 20160124490 | Dynamically Controlling Power Management Of An On-Die Memory Of A Processor - In one embodiment, a processor comprises: at least one core to execute instructions; a memory coupled to the at least one core, the memory including a plurality of pages to store information; and a page manager coupled to the memory, the page manager to access metadata of a page table entry associated with a page of the memory and update usage information of an entry of a database, the entry of the database associated with the page of the memory. The page manager may cause at least a portion of the memory to be dynamically powered down based at least in part on the usage information. Other embodiments are described and claimed. | 05-05-2016 |
| 20160139655 | Energy Efficiency Strategy for Interrupt Handling in a Multi-Cluster System - Energy efficiency is managed in a multi-cluster system. The system detects an event in which a current operating frequency of an active cluster enters or crosses any of one or more predetermined frequency spots of the active cluster, wherein the active cluster includes one or more first processor cores. When the event is detected, the system performs the following steps: (1) identifying a target cluster including one or more second processor cores, wherein the each first processor core in the first cluster and each second processor core in the second cluster have different energy efficiency characteristics; (2) activating at least one second processor core in the second cluster; (3) determining whether to migrate one or more interrupt requests from the first cluster to the second cluster; and (4) determining whether to deactivate at least one first processor core of the active cluster based on a performance and power requirement. | 05-19-2016 |
| 20160147285 | MANAGEMENT OF POWER CONSUMPTION IN LARGE COMPUTING CLUSTERS - Management of power consumption in large computing clusters is disclosed herein. According to an aspect, a computing device comprising a power manager may be configured to receive, via a communication interface, information associated with the cluster of computing nodes. The power manager of the computing device may also be configured to determine whether a switch is coupled to an inactive computing node of the cluster of computing nodes based on the received information. Further, the power manager of the computing device may be configured to communicate a command to the switch to remove power supplied to a switch port of the switch coupled to the inactive computing node in response to determining that the switch is coupled to an inactive computing node of the cluster of computing nodes. | 05-26-2016 |
| 20160147287 | MANAGEMENT OF POWER CONSUMPTION IN LARGE COMPUTING CLUSTERS - Management of power consumption in large computing clusters is disclosed herein. According to an aspect, a method includes using a power manager to receive, via a communication interface, information associated with the cluster of computing nodes. The method includes determining whether a switch is coupled to an inactive computing node of the cluster of computing nodes based on the received information. Further, the method includes communicating a command to the switch to remove power supplied to a switch port of the switch coupled to the inactive computing node in response to determining that the switch is coupled to an inactive computing node of the cluster of computing nodes. | 05-26-2016 |
| 20160147288 | Apparatus and Method for Activating and Shutting Down Enhanced Pipeline Stages and Enhanced Modules Based on Priority and Performance Requirements - A pipeline-based processor and method. The method includes partitioning a particular pipeline into one or more base pipeline stages and a plurality of enhanced pipeline stages, each enhanced pipeline stage configured to be either a shutdown enhanced pipeline stage or an activated enhanced pipeline stage. Each enhanced pipeline stage has an enhanced stage priority level. The method also includes configuring each enhanced pipeline stage to be activated or shut down based at least on the enhanced stage priority level. The method additionally includes partitioning a particular pipeline stage into at least one base module and a plurality of enhanced modules, each enhanced pipeline stage configured to be either a shutdown enhanced pipeline stage or an activated enhanced pipeline stage. Each enhanced module has a particular priority level. The method further includes configuring each enhanced module to be activated or shut down based at least on the particular priority level. | 05-26-2016 |
| 20160154702 | METHOD OF CONTROLLING SLED PLANAR OF BLADE SERVER | 06-02-2016 |
| 20160162017 | CENTRALIZED SYNCHRONIZATION MECHANISM FOR A MULTI-CORE PROCESSOR - A multi-core microprocessor supports a plurality of operating states that provide different levels of performance and power consumption to the microprocessor and its cores. A control unit puts selected cores into selected operating states at selected times. A core-specific synchronization register is provided for each core external to the core and readable by the control unit. Each core responds to an instruction to target an operating state by writing a value identifying the target operating state to the synchronization register. The control unit causes power saving actions that affect shared resources provided that the actions do not reduce performance of any core sharing the resources below the core's target operating state. | 06-09-2016 |
| 20160170470 | DYNAMIC CONTROL OF PROCESSORS TO REDUCE THERMAL AND POWER COSTS | 06-16-2016 |
| 20160170474 | POWER-SAVING CONTROL SYSTEM, CONTROL DEVICE, CONTROL METHOD, AND CONTROL PROGRAM FOR SERVER EQUIPPED WITH NON-VOLATILE MEMORY | 06-16-2016 |
| 20160187959 | POWER MANAGEMENT IN AN UNCORE FABRIC - In an example, a shared uncore memory fabric of a system-on-a-chip (SoC) is configured to provide real-time power management. The SoC may include a power management agent to inform the shared fabric that the processing cores and peripherals will be idle for a time, and to negotiate a power-saving state. The uncore fabric may also include a local power manager that detects when no access requests have been received for a time, such as when cores are operating from cache. The shared fabric may then unilaterally enter a power-saving state, and remain in that state until an access request is received. In the power-saving state, power and/or clocks are gated, and the fabric's state is stored in retention cells. When a new access request is received, an ungated controller may handle preliminary processing while the local power manager restores the state and powers up the shared fabric. | 06-30-2016 |
| 20160195918 | Method and Apparatus for Predictive and Adaptive Power Management of Memory Subsystem Based on memory access Information | 07-07-2016 |
| 20180024614 | AUTONOMOUS HARDWARE FOR APPLICATION POWER USAGE OPTIMIZATION | 01-25-2018 |
| 20190146572 | STORAGE SYSTEM WITH POWER SAVING FUNCTION | 05-16-2019 |
