| Entries |
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| 20080215862 | Program Creation Device, Program Test Device, Program Execution Device, Information Processing System - The present invention comprises a program generation apparatus for generating an obfuscated program difficult to analyze from outside and a program execution apparatus for executing the program. The program generation apparatus comprises: an acquisition unit operable to acquire a 1 | 09-04-2008 |
| 20080215863 | Method and Apparatus for Autonomically Initiating Measurement of Secondary Metrics Based on Hardware Counter Values for Primary Metrics - A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. Functionality may be provided in the performance monitoring application for initiating the measurement of secondary metrics with regard to identified instructions, data addresses, ranges of identified instructions, or ranges of identified data addresses, based on counter values for primary metrics. Thus, for example, when a primary metric counter, or a combination of primary metric counters, meets or exceeds a predetermined threshold value, an interrupt may be generated. In response to receiving the interrupt, counters associated with the measuring of secondary metrics of a range of instructions/data addresses may be initiated. | 09-04-2008 |
| 20080235498 | TEST APPARATUS AND ELECTRONIC DEVICE - There is provided a test apparatus for testing a device under test. The test apparatus includes an instruction storing section that stores thereon a test instruction sequence, a pattern generating section that sequentially reads and executes an instruction from the test instruction sequence, and outputs a test pattern associated with the executed instruction, a test signal output section that generates a test signal in accordance with the test pattern, and supplies the generated test signal to the device under test, and a result register that stores thereon a value having a predetermined number of bits. Here, the instruction storing section stores thereon the test instruction sequence including therein a result register update instruction to update a value of a designated bit position in the result register with a predetermined value, and when executing the result register update instruction, the pattern generating section updates, with the predetermined value, the value of the bit position in the result register which is designated by the result register update instruction. | 09-25-2008 |
| 20080244245 | OPTIMAL SELECTION OF COMPRESSION ENTRIES FOR COMPRESSING PROGRAM INSTRUCTIONS - A method of compressing instructions in a program may include extracting unique bit patterns from the instructions in the program and constructing a linear programming formulation or an integer programming formulation from the unique bit patterns, the instructions, and/or the size of a memory storage. The linear programming formulation or the integer programming formulation may be solved to produce a solution. The method may include compressing at least some of the instructions based on the solution by storing at least some of the unique bit patterns in a memory and placing corresponding indices to the memory in new compressed instructions. | 10-02-2008 |
| 20080263338 | EXCEPTION OPERATION APPARATUS, METHOD AND COMPUTER PROGRAM FOR CONTROLLING DEBUGGING APPARATUS, AND TELEVISION AND CELLULAR PHONE PROVIDING THE SAME - In order to automatically activate a debugger while maintaining the status of the machine as it was just before execution of the instruction which has raised an exception even in a case in which a break point is not set beforehand, a computer, which executes a program to be debugged, analyzes an exception raised on the computer, and replaces an instruction with another instruction for activating a debugger if the exception has been raised due to the instruction that conducts an abnormal operation and is stored in a memory space. After this, the computer selects and switches to a task to be processed based on the status of each of the tasks, or resumes an operation which has been suspended due to the exception. Then, when the computer executes the instruction for activating the debugger, the debugger detects this execution and is activated. | 10-23-2008 |
| 20080270770 | Method for Optimising the Logging and Replay of Mulit-Task Applications in a Mono-Processor or Multi-Processor Computer System - This invention relates to a system and method for the management, more particularly by external, transparent and non-intrusive control, of the running of one or more software tasks within a multi-task application executed on a computer or a network of computers. This management comprises in particular a recording of the running of these tasks in the form of logging data, as well as a replay of this running from such logging data in order to present a behaviour and a result corresponding to those obtained while logging. | 10-30-2008 |
| 20080294881 | METHOD AND APPARATUS FOR INSTRUCTION COMPLETION STALL IDENTIFICATION IN AN INFORMATION HANDLING SYSTEM - An information handling system includes a processor that executes multiple instructions or instruction threads within a software application program. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In one embodiment, the operating system manages instruction completion stall analysis software to determine the cause or causes of instruction stalls. In another embodiment, the stall analysis software cooperates with the operating system software to store instruction completion stall event data on a per instruction basis while the application program executes. The operating system software may cooperate with the stall analysis software to store instruction completion stall data in memory for later manipulation by system users or other software. | 11-27-2008 |
| 20080301417 | System and Method for Debugging of Computer - The present invention relates to debugging of computer programs, and in particular to bi-directional debugging. | 12-04-2008 |
| 20080301418 | TRACING COMMAND EXECUTION IN A PARALLEL PROCESSING SYSTEM - Tracing command execution in a data processing system having a host processor and a co-processor. The host processor maintains a record of a plurality of commands for the co-processor, storing each of the plurality of commands is stored in a command queue. Hardware trace logic is provided to store one or more events based, at least in part, on transfer of the plurality of commands to a small memory. Software is executed to store the one or more events to a main memory, wherein the one or more events are aggregated into a single memory trace within the main memory. | 12-04-2008 |
| 20080313442 | DEBUGGING TECHNIQUES FOR A PROGRAMMABLE INTEGRATED CIRCUIT - Techniques for debugging a programmable integrated circuit are described. Embodiments include steps of initiating instruction-cache-misses in the integrated circuit using a remote computer executing a test program; substituting, during an instruction-cache-miss event, instructions in the application program with test instructions provided by the test program; and debugging the integrated circuit based on analysis of its responses to the test instructions. In exemplary applications, such techniques are used for debugging graphics processors of wireless communication system-on-chip devices, among other programmable integrated circuit devices. | 12-18-2008 |
| 20090006825 | Method, Apparatus, and Computer Program Product in a Processor for Concurrently Sharing a Memory Controller Among a Tracing Process and Non-Tracing Processes Using a Programmable Variable Number of Shared Memory Write Buffers - A method, apparatus, and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data. | 01-01-2009 |
| 20090019270 | EMBEDDED DEVICE PROGRAM DEBUG CONTROL - An embedded processor system includes an integrated development environment and an embedded processor system operating system. The operating system is operable to run on the embedded processor system, and a command queue is operable to receive commands from a debugging module external to the embedded processor system. A command queue processing module is operable to change settings in the embedded processor in response to commands in the command queue. | 01-15-2009 |
| 20090019271 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM - An information processing apparatus having a storage unit configured to execute a workflow with a plurality of processes combined therein and hold history information of the workflow, the information processing apparatus comprising an instructing unit configured to instruct such that a test workflow regarding a workflow selected to be executed is executed; a generating unit configured to generate the test workflow for the workflow selected to be executed; and an executing unit configured to execute the test workflow; wherein the generating unit generates the test workflow at least by adding a process not held in history information to processes of the test workflow, without adding a process held in the history information to the processes of the test workflow. | 01-15-2009 |
| 20090037703 | CONDITIONAL DATA WATCHPOINT MANAGEMENT - A method, system and computer program product for managing a conditional data watchpoint in a set of instructions being traced is shown in accordance with illustrative embodiments. In one particular embodiment, the method comprises initializing a conditional data watchpoint and determining the watchpoint has been encountered. Upon that determination, examining a current instruction context associated with the encountered watchpoint prior to completion of the current instruction execution, further determining a first action responsive to a positive context examination; otherwise, determining a second action. | 02-05-2009 |
| 20090037704 | TRACE CONTROL FROM HARDWARE AND SOFTWARE - A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core. | 02-05-2009 |
| 20090055632 | Emulation Scheme for Programmable Pipeline Fabric - The present invention allows emulation of a programmable pipeline processor fabric or architecture. According to certain aspects, the invention permits real-time capture of state information for any given stage of a processing flow performed by the fabric or architecture. According to other aspects, the invention allows a particular stage and data set of a SIMD flow to be analyzed. According to other aspects, the invention utilizes an independent clocking domain for the capture of state information. | 02-26-2009 |
| 20090063829 | Method, System, computer program product and data processing program for verifying a processor Design - An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model comprises at least one execution unit for executing at least one instruction of a test file. The method comprises tracking each execution of each of the at least one instruction, monitoring relevant signals in each simulation cycle, maintaining information about the execution of the at least one instruction, wherein said maintained information comprises a determination of an execution length of a completely executed instruction, matching said maintained information about said completely executed instruction against a set of trap elements provided by the user through a trap file, and collecting the maintained information about the completely executed instruction in a monitor file in response to a match found between the maintained information and at least one of the trap elements. | 03-05-2009 |
| 20090063830 | DEBUGGING MECHANISM FOR A PROCESSOR, ARITHMETIC OPERATION UNIT AND PROCESSOR - A debugging mechanism equipped within a processor and receiving, as inputs, respective pieces of arithmetic operation data related to a plurality of arithmetic units comprised within the processor, and receiving, as inputs, respective control signals used for the respective arithmetic operations, comprising: an unit which comprises a counter performing a counting operation synchronously with the arithmetic operation and comprises a plurality of OR circuits each receiving, as inputs, any of the respective control signals and a signal that is output when the counter value of the counter is a specific counter value; and a debug storage unit which comprises a plurality of storage units each receiving any of the respective pieces of arithmetic operation data, any of the respective outputs of the individual OR circuits, and the counter value, and each storing the arithmetic operation data and counter value when the output of the input OR circuit is valid. | 03-05-2009 |
| 20090077357 | Method of Power Simulation and Power Simulator - Disclosed are a method of simulating power and a power simulator. The power simulator includes a static information extracting unit that extracts static information with respect to execution of the second instruction; a dynamic information extracting unit that extracts dynamic information with respect to the execution of the second instruction; and a calculation unit that calculates an estimated power of the processor based on the static information and the dynamic information. | 03-19-2009 |
| 20090077358 | MICROPROCESSOR CONTROL APPARATUS AS WELL AS METHOD AND PROGRAM FOR THE SAME - There is provided with a microprocessor control apparatus for controlling an operating speed of a microprocessor which executes a program including instruction codes, including: a state observing unit observing an execution state of the program at predetermined timings before execution of a deadline instruction code; prediction data of a remaining calculation amount required before execution of the deadline instruction code completes for each of predefined execution states; a predicted calculation amount acquiring unit acquiring a remaining calculation amount corresponding to an observed execution state as a remaining predicted calculation amount; a remaining time calculating unit calculating a remaining time until the deadline of the deadline instruction code; an operating speed calculating unit calculating a minimum operation speed of the microprocessor that is required to process the remaining predicted calculation amount within the remaining time; and
| 03-19-2009 |
| 20090100254 | DEBUG INSTRUCTION FOR USE IN A DATA PROCESSING SYSTEM - A method includes providing a debug instruction and providing a debug control register field, where if the debug control register field has a first value, the debug instruction executes a debug operation and where if the debug control register field has a second value, the debug instruction is to be executed as a no-operation (NOP) instruction. A data processing system includes instruction fetch circuitry for receiving a debug instruction, a debug control register field, and debug execution control circuitry for controlling execution of the debug instruction in a first manner if the debug control register field has a first value and in a second manner if the debug control register field has a second value, where in the first manner a debug operation is performed and in the second manner no debug operation is performed. | 04-16-2009 |
| 20090106539 | METHOD AND SYSTEM FOR ANALYZING A COMPLETION DELAY IN A PROCESSOR USING AN ADDITIVE STALL COUNTER - In a data processing system having a set of components for performing a set of operations, in which one or more of the set of operations has processing dependencies with respect to other of the set of operations, a method for using an additive stall counter to analyze a completion delay is disclosed. The method includes initiating execution of a group of instructions and a performance monitor unit resetting a value stored within the additive stall counter. The method further includes the performance monitor unit incrementing the value within the additive stall counter until all instructions within the group of instructions complete. In response to all instructions within the group of instructions completing a cause of the completion delay is determined. In response to determining that the delay was caused by the first stall cause, the value stored within the additive stall counter is added to a first performance monitor counter designated for the first stall cause, and, in response to determining that the delay was caused by a second stall cause, the value stored within the additive stall counter is added to a second performance monitor counter designated for the second stall cause. | 04-23-2009 |
| 20090113190 | GATHERING OPERATIONAL METRICS WITHIN A GRID ENVIRONMENT USING GHOST AGENTS - A method for gathering operational metrics can include the step of identifying a host within a grid environment, wherein the host can be a software object. A ghost agent can be associated with the host. The ghost agent can replicate actions of the host. Operational metrics for at least a portion of the replicated actions can be determined. The operational metrics can be recorded. The host can move within the grid environment. The ghost agent can responsively move in accordance with movement of the host. | 04-30-2009 |
| 20090164765 | Determining Thermal Characteristics Of Instruction Sets - Methods, apparatus, and products for determining thermal characteristics of instruction sets comprising one or more computer program instructions executed by a computer processor are disclosed that include tracking, in a performance counter, a number of classes of instructions run during execution of a plurality of instruction sets; identifying, for each instruction set, from the performance counter, a number of each class of instructions run during execution of the instruction set; and ranking the instruction sets in dependence upon the number of each class of instructions run during execution of each instruction set and a profile of thermal characteristics of classes of instructions. | 06-25-2009 |
| 20090172368 | Hardware Based Runtime Error Detection - A processor that includes a storage medium which includes microcode that performs runtime analysis. The storage medium can include instrumented microcode that monitors at least one execution of a machine instruction resulting in a memory access, instrumented microcode that accesses at least one memory state indicator to determine whether the memory access is improper, and instrumented microcode that outputs an exception when the memory access is improper. | 07-02-2009 |
| 20090187747 | SYSTEM AND METHOD FOR TRACING INSTRUCTION POINTERS AND DATA ACCESS - A system and method for tracing instruction pointers and data access is disclosed. In one embodiment the system includes a plurality of trace units including at least one first trace unit configured to perform an instruction pointer trace, and at least one second trace unit configured to perform a data trace. A multiplexer is connected between the plurality of processor cores and the plurality of trace units. | 07-23-2009 |
| 20090187748 | METHOD AND SYSTEM FOR DETECTING STACK ALTERATION - The disclosed systems and methods relate to employing one or more of machine instructions (i.e. assembler language instructions) to detect stack alterations. Aspects of the present invention also relate to employing CPU logic and one or more associated CPU registers to detect stack alterations. Aspects of the present invention may also relate to employing hidden content addressable memory (CAM) and registers that are only accessible by the CPU, and each cell in the CAM may be accessed using a PID unique to the running program, such as the process ID or thread ID assigned by the operating system scheduler. | 07-23-2009 |
| 20090193237 | PARSING-ENHANCEMENT FACILITY - An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general register, wherein a first general register stores an argument address, a second general register stores a function code, a third general register stores length of an argument-character buffer, and the fourth of which contains the address of the function-code data structure. | 07-30-2009 |
| 20090204795 | Method and System for Automatically Testing Performance of Applications run in a Distributed Processing Structure and Corresponding Computer Program Product - Performance of applications run on a distributed processing structure including a grid of processing units is automatically tested by: running at least one application on the distributed processing structure; loading the application with processing workload to thereby produce processing workload on the distributed processing structure; sensing the operating status of the processing units in the distributed processing structure under the processing workload and producing information signals indicative of such operating status; collecting these information signals; providing a rule engine and selectively modifying, as a function of the rules in the rule engine and the information signals collected, at least one of: the processing workload on the application, and the operating status of the processing units in the grid. | 08-13-2009 |
| 20090204796 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR VERIFYING ADDRESS GENERATION, INTERLOCKS AND BYPASSES - Method, system and computer program product for verifying the address generation, address generation, interlocks, and address generation bypassing controls in a CPU. An exemplary embodiment includes a verification method in a processor, the method including propagating a first set general purpose register values fern a first instruction to a second instruction, wherein the simulation monitor is coupled to a first stage of the instruction pipeline, and wherein the first set of general purpose register values are stored in a simulation instruction object, selecting a second set of general purpose register values, updating the first set of general purpose register values with the second set of general purpose register values and placing the second, set of general purpose register values on a bus. | 08-13-2009 |
| 20090210680 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR MILLICODE STORE ACCESS CHECKING INSTRUCTIONS - A system, method and computer program product for a millicode store access checking instruction are provided. The system includes an operand access control register (OACR) including a test modifier indicator. The system also includes an instruction unit subsystem for fetching and decoding instructions. The instructions include a millicode instruction with an operand defining an address to check for a store access exception. The system further includes an execution unit to execute the millicode instruction. The execution unit performs a method. The method includes receiving the millicode instruction from the instruction unit subsystem, testing for the store access exception at the address as if the test modifier is set absent an update to the OACR, and outputting a result of the testing for the store access exception. | 08-20-2009 |
| 20090210681 | Method and Apparatus of Handling Instruction Rejects, Partial Rejects, Stalls and Branch Wrong in a Simulation Model - A method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model provides pipeline states for various unit verification. It defines an instruction train to encounter many events of the hardware verifications. Drivers and monitors at a unit and a core simulation level can hook into the pipeline states and perform the verification easily without having to restructure the instructions in the pipeline due to rejects, partial rejects, stalls, branch wrongs. Different event counters have been placed in the instruction pipe during the events and expand the instruction train such that the instruction train provides an accurate and detailed state of each instruction so the hardware logic signals and data can be tracked and identified from each state. | 08-20-2009 |
| 20090217010 | DATA PROCESSOR DEVICE HAVING TRACE CAPABILITIES AND METHOD - In response to determining an event has occurred, information is stored at a trace buffer of an integrated circuit. When the trace buffer is full, execution of instructions at a CPU is halted to allow the trace buffer information to be accessed at an external interface to the integrated circuit device. The CPU is continually halted as the trace buffer is filled to facilitate retrieving all information written to the trace buffer. | 08-27-2009 |
| 20090217011 | DATA PROCESSING DEVICE AND METHOD THEREOF - A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to facilitate debugging. The exception event can be a reset exception event or an interrupt exception event. Normal exception processing by the data processor can be resumed after debugging, or exception processing by the data processor can be aborted to allow the normal execution of instructions by the data processor to resume. An exception event can be selectively treated as an interrupt or a reset. | 08-27-2009 |
| 20090217012 | MICROARCHITECTURE, METHOD AND COMPUTER PROGRAM PRODUCT FOR EFFICIENT DATA GATHERING FROM A SET OF TRACE ARRAYS - An architecture for collecting performance data in a processor, that includes: a trace read control unit and a trace data collect unit, each unit coupled to a plurality of trace array and multiplex units for providing performance data, the coupling accomplished by a trace read control bus, a data select bus, a trace row address bus and a data return bus; wherein each of the trace array and multiplex units receives a trace read signal and provides data including trace data and the trace read signal to the trace data collect unit. A method and a computer program product are provided. | 08-27-2009 |
| 20090222646 | METHOD AND APPARATUS FOR DETECTING PROCESSOR BEHAVIOR USING INSTRUCTION TRACE DATA - A method and apparatus for detecting processor behavior in real time using instruction trace data, in one aspect, identifies one or more call addresses from which a function to be observed is called and establishes one or more end addresses of the function. Said one or more call addresses and said one or more end addresses are stored, and compared with a branch address contained in the instruction trace data to detect start and end of the function dynamically in real time. | 09-03-2009 |
| 20090222647 | Method and Apparatus for Reducing Test Case Generation Time in Processor Testing - A method, apparatus and computer program product are provided for use in a system that includes one or more processors, and multiple threads that are respectively associated with the one or more processors. One embodiment of the invention is directed to a method that includes the steps of generating one or more test cases, wherein each test case comprises a specified set of instructions in a specified order, and defining a plurality of thread hardware allocations, each corresponding to a different one of the threads. The thread hardware allocation corresponding to a given thread comprises a set of processor hardware resources that are allocated to the given thread for use in executing test cases. The method further includes executing a particular one of the test cases on a first thread hardware allocation, in order to provide a first set of test data, and thereafter executing the particular test case using a second thread hardware allocation, in order to provide a second set of test data. | 09-03-2009 |
| 20090249044 | Apparatus for and Method for Life-Time Test Coverage for Executable Code - a novel and useful apparatus for and method of associating a dedicated coverage bit to each instruction in a software system. Coverage bits are set every time the software application runs, enabling a more comprehensive and on-going code coverage analysis. The code coverage bit mechanism enables code coverage analysis for all installations of a software application, not just software in development mode or at a specific installation. Code coverage bits are implemented in either the instruction set architecture (ISA) of the central processing unit, the executable file of a software application, a companion file to the executable file or a code coverage table residing in memory of the computer system. | 10-01-2009 |
| 20090249045 | APPARATUS AND METHOD FOR CONDENSING TRACE INFORMATION IN A MULTI-PROCESSOR SYSTEM - A computer readable storage medium includes executable instructions to characterize a coherency controller. The executable instructions define ports to receive processor trace information from a set of processors. The processor trace information from each processor includes a processor identity and a condensed coherence indicator. Circuitry produces a trace stream with trace metrics and condensed coherence indicators. | 10-01-2009 |
| 20090249046 | APPARATUS AND METHOD FOR LOW OVERHEAD CORRELATION OF MULTI-PROCESSOR TRACE INFORMATION - A method of coordinating trace information in a multiprocessor system includes receiving processor trace information from a set of processors. The processor trace information from each processor includes a processor identity and a coherence indicator that demarks selective shared memory transactions. Coherence manager trace information is generated for each of the processors. The coherence manager trace information for each processor includes trace metrics and a coherence indicator. | 10-01-2009 |
| 20090254739 | INFORMATION PROCESSING DEVICE - An information processing device having a function for efficiently debugging a parallel processing program by controlling snoop operation is provided. The information processing device is so configured that the following is implemented: the setting for receiving a snoop request from a central processing unit can be set at a snoop controller that controls snoop operation; and as the result of reception of a snoop request, a debug controller can stop multiple central processing units. | 10-08-2009 |
| 20090259830 | Quantifying Completion Stalls Using Instruction Sampling - A method, computer program product, and data processing system for collecting metrics regarding completion stalls in an out-of-order superscalar processor with branch prediction is disclosed. A preferred embodiment of the present invention selectively samples particular instructions (or classes of instructions). Each selected instruction, as it passes through the processor datapath, is marked (tagged) for monitoring by a performance monitoring unit. The progress of marked instructions is monitored by the performance monitoring unit, and various stall counters are triggered by the progress of the marked instructions and the instruction groups they form a part of. The stall counters count cycles to give an indication of when certain delays associated with particular instructions occur and how serious the delays are. | 10-15-2009 |
| 20090259831 | DEFINING MEMORY INDIFFERENT TRACE HANDLES - A handle for a trace is provided that is memory indifferent. The handle is created using contents of the trace rather than memory location of the trace. This enables the trace to be easily identified in subsequent runs of an application associated with the trace. | 10-15-2009 |
| 20090265530 | Latency hiding of traces using block coloring - An embodiment of the present invention is a technique to hide latency in program traces. Blocks of instructions between start and end of a critical section are associated with color information. The blocks correspond to a program trace and containing a wait instruction. The wait instruction is sunk down the blocks globally to the end of the critical section using the color information and a dependence constraint on the wait instruction. | 10-22-2009 |
| 20090265531 | Code Evaluation for In-Order Processing - Systems and methods of code evaluation for in-order processing are disclosed. In an embodiment, the method includes identifying a first instruction having multiple execution source paths. The method also includes generating a first execution path model identifying an execution order of multiple instructions based on a first condition and generating a second execution path model identifying an execution order of a second instruction based on a second condition. The method includes evaluating at least one of the execution path models to identify a hazard condition. | 10-22-2009 |
| 20090276610 | TEST CASE GENERATION WITH BACKWARD PROPAGATION OF PREDEFINED RESULTS AND OPERAND DEPENDENCIES - A method of generating a test case from a given test case structure, the method including generating instructions for the given test case structure, propagating predefined results in a backwards manner, randomly generating remaining operands of the test case structure in a forwards manner, and calculating a result for the test case by determining missing input operands and storing these input operands in both the temporary register file and the initial register file, and calculating missing results and storing all results in the temporary register file. | 11-05-2009 |
| 20090282227 | Monitoring Software Pipeline Performance On A Network On Chip - Software pipelining on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers. Embodiments of the present invention include implementing a software pipeline on the NOC, including segmenting a computer software application into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID; executing each stage of the software pipeline on a thread of execution on an IP block; monitoring software pipeline performance in real time; and reconfiguring the software pipeline, dynamically, in real time, and in dependence upon the monitored software pipeline performance. | 11-12-2009 |
| 20090307468 | Generating a Test Case Micro Generator During Processor Design Verification and Validation - A main generator generates a micro generator and initial test cases based upon a processor architecture specifications and user input, such as general purpose register availability, translation information, instruction sequences, base register available, target real memory pages, etc. In turn, the micro generator tests a processor using the initial test cases and subsequent test cases generated by the micro generator. The subsequent test cases may include modified test case properties such as changed machine state register bits, changed instruction sequence (shuffling), changed effective segment ID bits, and/or changed virtual segment ID bits. In addition to generating subsequent test cases, the micro generator performs functions such as test case dispatching, test case scheduling, test case execution, and interrupt handling. | 12-10-2009 |
| 20090313460 | TRACE COMPRESSION METHOD FOR DEBUG AND TRACE INTERFACE OF MICROPROCESSOR - The present invention proposed a trace compression method for a debug and trace interface of a microprocessor, in which the debug and trace interface is associated with a plurality of registers for storing data. The trace compression method comprises the steps of: (1) finding register content of each of the registers in a first cycle and register content of each of the registers in a second cycle, in which the second cycle is next to the first cycle; (2) calculating difference of the register content of each of the registers in the second cycle and the register content of each of the registers in the first cycle; and (3) packing the differences of the register contents into data trace packets, in which the differences of the register contents of adjacent registers are condensed into a single data trace packet when the differences of the register contents of the adjacent registers are zeroes. | 12-17-2009 |
| 20100017583 | Call Stack Sampling for a Multi-Processor System - A computer implemented method, apparatus, and computer usable program code for sampling call stack information. Responsive to identifying an interrupt, a determination is made as to whether all processors in a plurality of processors have generated the interrupt. A determination is made as whether to sample the call stack information based on a policy in response to a determination that all of the processors have generated the interrupt. The call stack information is sampled if a determination is made to sample the call stack information based on the policy | 01-21-2010 |
| 20100017584 | Call Stack Sampling for a Multi-Processor System - A computer implemented method for sampling call stack information. Responsive to identifying a set of interrupts, a determination is made as to whether all processors in a plurality of processors have generated the set of interrupts. A number of addresses are identified for a set of interrupted threads identified by the set of interrupts response to a determination that all of the processors have generated the set of interrupts. A determination is made as to whether the identified address falls within a set of address ranges. Responsive to a determination that the identified address falls within the set of address ranges, a sampler thread is notified to obtain call stack information. | 01-21-2010 |
| 20100017585 | Microcomputer and encoding system for instruction code and CPU - A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable as a timer counter, a peripheral function instruction is described in the specific task, the peripheral function instruction is set so as to indicate one or more general-purpose registers as an operand. The CPU executes the peripheral function instruction as one instruction and achieves information needed to execute the instruction by a general-purpose register and stores the execution result into the general-purpose registers. An instruction code encoding system includes an operation code and plural operands for indicating operation targets of an instruction in an instruction code and executing an instruction indicated by the operation code on the operation targets. When the operation targets indicated by the plural operands are set to a combination in which an execution result does not vary, the processing corresponding to an instruction different is executed. | 01-21-2010 |
| 20100023735 | DEBUG MESSAGE GENERATION USING A SELECTED ADDRESS TYPE - A method for generating a debug message includes receiving a translated address and an untranslated address associated with a same processor operation, determining a value of one or more control indicators, selecting the translated address or the untranslated address as a selected address based on the value of the one or more control indicators, and creating a debug message using at least a portion of the selected address. | 01-28-2010 |
| 20100023736 | RECONFIGURABLE CIRCUIT, RESET METHOD, AND CONFIGURATION INFORMATION GENERATION DEVICE - The present invention provides a reconfigurable circuit that comprises a plurality of reconfiguration cells and changes a configuration of a computation processing unit included in each of the reconfiguration cells. Here, each of the reconfiguration cells further includes: a computation storage unit operable to store a result of a computation performed by the computation processing unit; a flag holding unit operable to hold an initialization flag indicating whether an initialization of the computation storage unit is required; and an initialization control unit operable to, during the configuration change of the computation processing unit, control the initialization of the computation storage unit based on the initialization flag held by the flag holding unit. | 01-28-2010 |
| 20100049955 | DEBUG INSTRUCTION FOR USE IN A MULTI-THREADED DATA PROCESSING SYSTEM - For use in a data processing system comprising a processor configured to execute a first set of instructions corresponding to a first thread and a second set of instructions corresponding to a second thread, a method is provided. The method comprises in response to execution of a debug related instruction by the first thread while executing the first set of instructions, generating a debug event for processing by the second thread, wherein processing the debug event comprises causing a halting operation related to the processor. | 02-25-2010 |
| 20100049956 | DEBUG INSTRUCTION FOR USE IN A MULTI-THREADED DATA PROCESSING SYSTEM - For use in a data processing system comprising a processor configured to execute a first set of instructions corresponding to a first thread and a second set of instructions corresponding to a second thread, a method is provided. The method comprises in response to execution of a debug instruction by the first thread while executing the first set of instructions, generating a debug event for processing by the second thread. | 02-25-2010 |
| 20100082950 | Dynamically reconfiguring platform settings - In one embodiment, a system may receive a pattern from an analysis engine, where the pattern includes information regarding a corrective action to be taken on a configuration setting of a processor, configure a performance monitor based on the pattern, collect performance monitoring information during program operation, analyze the information during the program operation, and dynamically implement the corrective action during the program operation based on the analysis. Other embodiments are described and claimed. | 04-01-2010 |
| 20100100715 | HANDLING DEBUGGER BREAKPOINTS IN A SHARED INSTRUCTION SYSTEM - A debugger debugs processes that execute shared instructions so a breakpoint set for one process will not cause a breakpoint to occur in the other processes. A breakpoint is set by recording the original instruction at the desired location and writing a trap instruction to the shared instructions at that location. When a process encounters the breakpoint, the process passes control to the debugger for breakpoint processing if the breakpoint was set at that location for that process. If the trap was not set at that location for that process, the cacheline containing the trap is copied to a small scratchpad memory, and the virtual memory mappings are changed to translate the virtual address of the cacheline to the scratchpad. The original instruction is then written to replace the trap instruction in the scratchpad, so the process can execute the instructions in the scratchpad thereby avoiding the trap instruction. | 04-22-2010 |
| 20100122072 | Debugging system, debugging method, debugging control method, and debugging control program - A debugging system according to an exemplary embodiment of the present invention includes: a plurality of arithmetic processing units ( | 05-13-2010 |
| 20100131744 | METHOD AND SYSTEM OF A PROCESSOR-AGNOSTIC ENCODED DEBUG-ARCHITECTURE IN A PIPELINED ENVIRONMENT - A method and/or a system of a processor-agnostic encoded debug architecture in a pipelined environment is disclosed. In one embodiment, a method of a processor includes processing an event specified by a data processing system coupled to the processor to determine a boundary of the event, generating a matrix having combinations of the event and other events occurring simultaneously in the processor, capturing an output data of observed ones of the event and other events, and applying the matrix to generate an encoded debug data of the output data. The method may also include determining which of the combinations are valid based on an architecture of the processor. The event may be a trace-worthy event whose output value cannot be reliably predicted in an executable file in the data processing system and/or a sync event that is specified by a user of the data processing system. | 05-27-2010 |
| 20100138639 | SANDBOXED EXECUTION OF PLUG-INS - A sandbox architecture that isolates and identifies misbehaving plug-ins (intentional or unintentional) to prevent system interruptions and failure. Based on plug-in errors, the architecture automatically disables and blocks registration of the bad plug-in via a penalty point system. Publishers of bad plug-ins are controlled by disabling the bad plug-ins and registering the publisher in an unsafe list. Isolation can be provided in multiple levels, such as machine isolation, process isolation, secure accounts with limited access rights, and application domain isolation within processes using local security mechanisms. A combination of the multiple levels of isolation achieves a high level of security. Isolation provides separation from other plug-in executions and restriction to system resources such as file system and network IP. Moreover, the architecture is highly scalable, stateless, and low administration architecture for the execution of the plug-ins, which can be scaled by adding/removing additional sandbox servers on-the-fly without prior configuration. | 06-03-2010 |
| 20100169621 | PROCESSOR TEST APPARATUS, PROCESSOR TEST METHOD, AND PROCESSOR TEST PROGRAM - A processor test method of testing a processor includes executing each test instruction of a test instruction sequence to obtain a condition code set by a condition code setting instruction of the test instruction sequence for testing the processor; producing a condition branching instruction to add the produced condition branching instruction to the end of the condition code setting instruction of the test instruction sequence, the condition branching instruction branching to an error output instruction when a condition code that does not match the obtained condition code is supplied; and executing, by an advanced control scheme, a test instruction sequence in which the condition branching instruction is added to the test instruction sequence. | 07-01-2010 |
| 20100174892 | MULTIPROCESSOR SYSTEM AND METHOD FOR SYNCHRONIZING A DEBUGGING PROCESS OF A MULTIPROCESSOR SYSTEM - The invention relates to a method and a system for synchronizing a debugging process of a multiprocessor system ( | 07-08-2010 |
| 20100185838 | PROCESSOR ASSIGNING CONTROL SYSTEM AND METHOD - A processor assigning control system includes a first memory to store a plurality of control instructions and loading schedules, a second memory to temporarily store the plurality of control instructions and loading schedules, a real-time clock (RTC), and a main controller. The main controller includes a hardware detecting unit, a software obtaining unit, and a management unit. The RTC is configured for sending clock signal to make the hardware detecting unit detect whether a plurality of processors are in a normal state or an error state. The processor assigning control system is capable of detecting connection statues between the plurality of processor and a communication bus, and performance of the processors, to obtain and assign the control instructions to the corresponding processors to dynamically deploy the processors. | 07-22-2010 |
| 20100191941 | FAILURE ANALYSIS APPARATUS, METHOD - A debugger is operated in a host PC, and in response to operation of the debugger, first and second microprocessors execute an identical debug operation in parallel via first and second debug I/F devices. The host PC obtains internal information (dump results) from the first and second microprocessors via the first and second debug I/F devices and compares internal information (dump results) from the first and second microprocessors to perform failure analysis. | 07-29-2010 |
| 20100205414 | HIGH INTEGRITY PROCESSOR MONITOR - A method of ensuring high integrity of a processor is provided. The method includes executing sets of sequential instructions, each execution being based on a unique initial value, generating a computed final value responsive to each execution of a set of sequential instructions, and sending computed values to a monitoring portion of a high integrity processor monitor system responsive to the generating for each execution of the set of sequential instructions. The execution of the sets of sequential instructions tests pertinent addressing modes, operand sizes, and instruction side-effects for each instruction tested in a monitored central processing unit. | 08-12-2010 |
| 20100250904 | METHODS AND PROCESSOR-RELATED MEDIA TO PERFORM RAPID RETURNS FROM SUBROUTINES IN MICROPROCESSORS AND MICROCONTROLLERS - Various embodiments include methods and related media for performing operations including a return operation. One such method includes testing a content of a return value register and setting status flags. Testing the content of the return value register and setting the status flags are performed in response to a single instruction. | 09-30-2010 |
| 20100262811 | DEBUG SIGNALING IN A MULTIPLE PROCESSOR DATA PROCESSING SYSTEM - A system includes a first processor, a second processor, a first clock coupled to the first processor, and a third clock coupled to the first processor and to the second processor. The first processor includes debug circuitry coupled to receive the third clock, synchronization circuitry coupled to receive the first clock, wherein the synchronization circuitry receives a first request to enter a debug mode and provides a first synced debug entry request signal and wherein the first synced debug entry request signal is synchronized with respect to the first clock, and an input for receiving a second synced debug entry request signal from the second processor wherein the first processor waits to enter the debug mode until the first synced debug entry request signal and the second synced debug entry request signal are both asserted. | 10-14-2010 |
| 20100299507 | ON-LINE TESTING FOR DECODE LOGIC - Methods and apparatuses for on-line testing for decode logic are presented. In one embodiment, a processor comprises translation logic to decode an instruction to micro-operations and extraction logic to determine first information about numbers of occurrences of fields in the micro-operations. In one embodiment, the processor further comprises verification logic to indicate whether the decoding results of the instruction are accurate based at least on the first information. | 11-25-2010 |
| 20100325401 | Method of Translating N to N Instructions Employing an Enhanced Extended Translation Facility - A method, article, and system for providing an effective implementation of assembler language translate-n-to-n instructions implemented on 21, 31, and 64-bit architectures, while maintaining backward compatibility with existing systems. The enhanced Extended-Translation Facility 2 (ETF2) instruction set introduces a new operand in an unused field (M | 12-23-2010 |
| 20110010530 | MICROPROCESSOR WITH INTEROPERABILITY BETWEEN SERVICE PROCESSOR AND MICROCODE-BASED DEBUGGER - A microprocessor integrated circuit includes first and second processors, an internal memory accessible by the first and second processors, and a bus interface unit configured to interface to a bus external to the microprocessor for providing access to a memory external to the microprocessor. The bus interface unit, external bus, and external memory are accessible by the second processor but are inaccessible by the first processor. The first processor writes debug information to the internal memory. The first processor detects an event and provides a notification of the event to the second processor. The second processor, coupled to the bus interface unit, executes microcode in response to the event notification received from the first processor. The microcode reads the debug information from the internal memory and writes the debug information to the external memory via the bus interface unit and external bus for use in debugging the second processor. | 01-13-2011 |
| 20110010531 | DEBUGGABLE MICROPROCESSOR - A microprocessor integrated circuit includes first and second processors. The first processor is configured to detect that the second processor has not retired an instruction for a predetermined amount of clock cycles and to responsively reset the second processor. The microprocessor integrated circuit also includes microcode. The second processor is configured to execute the microcode in response to a reset of the second processor. The microcode is configured to read debug information within the microprocessor integrated circuit and to output the debug information external to the microprocessor integrated circuit in response to determining that the reset was performed by the first processor. | 01-13-2011 |
| 20110047363 | Microprogrammable Device Code Tracing - A microprogrammable electronic device has a first code memory storing instructions, and is configured to execute each instruction in the first code memory at a respective instruction cycle. The system comprises binary code generating means, and a tracing device. The binary code generating means form part of the device , and are configured to generate and output on a single pin of the device binary codes, each of which indicates a corresponding execution-related event, is generated and outputted at a corresponding instruction cycle, and has N bits, where N is an integer >=2. The tracing device is coupled with the single pin to receive the binary codes, and has a second code memory in which the instructions are stored. The tracing device is configured to trace instructions executed by the device, on the basis of the received binary codes and of the instructions stored in the second code memory. | 02-24-2011 |
| 20110078421 | ENHANCED MONITOR FACILITY - A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is generated. In another mode, in response to encountering a monitored event, one or more associated counters are incremented without causing an interrupt. | 03-31-2011 |
| 20110131396 | TIMING ANALYSIS - One aspect of the present invention provides processor comprising: an execution unit arranged to execute a sequence of instructions each comprising a respective opcode; and a counter coupled to the execution unit and arranged to generate a periodically updated counter value during execution. The execution unit comprises logic configured to identify an opcode representing a trap-if-late instruction in said sequence, and in response to execute the trap-if-late instruction by comparing a target value to the counter value and generating an exception on condition that the counter value represents a time that is late relative to said target value. Another aspect provides a compiler for inserting trap-if-late instructions based on timing constraints in higher-level code. | 06-02-2011 |
| 20110219216 | Mechanism for Performing Instruction Scheduling based on Register Pressure Sensitivity - A mechanism for performing instruction scheduling based on register pressure sensitivity is disclosed. A method of embodiments of the invention includes performing a preliminary register pressure minimization on program points during a compilation process of a software program running on a virtual machine of a computer system. The method further includes calculating a register pressure at each of the program points, detecting an instruction to be scheduled, and performing instruction scheduling of the instruction based on a current register pressure at a current scheduling point and potential register pressures at subsequent scheduling points. | 09-08-2011 |
| 20110219217 | System on Chip Breakpoint Methodology - A system-on-chip (SoC) with a debugging methodology. The system-on-chip (SoC) includes a central processing unit (CPU) and multiple computing elements connected to the CPU. The CPU is configured to program the computing elements with task descriptors and the computing elements are configured to receive the task descriptors and to perform a computation based on the task descriptors. The task descriptors include a field which specifies a breakpoint state of the computing element. A system level event status register (ESR) attaches to and is accessible by the CPU and the computing elements. Each of the computing elements has a comparator configured to compare the present state of the computing element to the breakpoint state. The computing element is configured to drive a breakpoint event to the event status register (ESR) if the present state of the computing element is the breakpoint state. Each of the computing elements has a halt logic unit operatively attached thereto, wherein the halt logic unit is configured to halt operation of the computing element. The ESR is configurable to drive a breakpoint event to the halt logic units to halt at least one of the computing elements other than the computing element driving the breakpoint event. | 09-08-2011 |
| 20110225400 | Device for Testing a Multitasking Computation Architecture and Corresponding Test Method - A device and method for testing a multitasking computation architecture is provided. Sequences of test instructions are generated corresponding to programming rules for the computation architecture. The execution of the instruction sequences is controlled so that the sequences are alternately executed within the computation architecture. | 09-15-2011 |
| 20110258421 | Architecture Support for Debugging Multithreaded Code - Mechanisms are provided for debugging application code using a content addressable memory. The mechanisms receive an instruction in a hardware unit of a processor of the data processing system, the instruction having a target memory address that the instruction is attempting to access. A content addressable memory (CAM) associated with the hardware unit is searched for an entry in the CAM corresponding to the target memory address. In response to an entry in the CAM corresponding to the target memory address being found, a determination is made as to whether information in the entry identifies the instruction as an instruction of interest. In response to the entry identifying the instruction as an instruction of interest, an exception is generated and sent to one of an exception handler or a debugger application. In this way, debugging of multithreaded applications may be performed in an efficient manner. | 10-20-2011 |
| 20110271085 | PARSING-ENHACEMENT FACILITY - An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general register, wherein a first general register stores an argument address, a second general register stores a function code, a third general register stores length of an argument-character buffer, and the fourth of which contains the address of the function-code data structure. | 11-03-2011 |
| 20110283094 | Semiconductor device controlling debug operation of processing unit in response to permission or prohibition from other processing unit - A semiconductor device is capable of being coupled to a first debugger and a second debugger, the first and second debuggers being capable of debugging a program in the semiconductor device. The semiconductor device includes a first chip, and a second chip that is coupled to the first chip. The first chip includes a first processing unit that executes a first instruction group, and a first debug control unit capable of being coupled to the first debugger to control a communication with the first debugger, and the second chip includes a memory that stores a first data and the program including the first instruction group and a second instruction group, the first data is generated based on a second data inputted from the second debugger, a second processing unit that executes the second instruction group, a second debug control unit capable of being coupled to the second debugger to control a communication with the second debugger, and the first debug control unit controls permission or prohibition of a connection configuration to the first debugger based on the second data and a third data inputted from the first debugger. | 11-17-2011 |
| 20110289301 | Tracing Flow of Data in a Distributed Computing Application - A method is provided for tracing dataflow in a distributed computing application. For example, the method includes incrementally advancing a dataflow in a dataflow path of one or more dataflow paths according to two or more directives encoded in two or more data messages. The method further includes performing the two or more directives. The dataflow path includes one or more operators including at least one merge operator operative to merge the two or more data messages and merge the two or more directives. One or more of the incrementally advancing of the dataflow and the performing of the two or more directives are implemented as instruction code performed on a processor device. | 11-24-2011 |
| 20110289302 | DATA PROCESSING DEVICE AND METHOD - Overhead is significant when a timestamp according to a reference time is inserted. In view of this, there is provided an LSI which includes: a first time information conversion unit which converts, into time information of a reference time, time information from a first trace data source; a second time information conversion unit which converts, into time information of a reference time, time information from a second trace data source; and a packet merging unit. | 11-24-2011 |
| 20110314264 | Key allocation when tracing data processing systems - A trace unit is provided which is configured to generate items of trace data indicative of processing activities, of a data processing unit. The trace unit comprises a trace indexing unit configured to associate an index value with at least a subset of the items of trace data generated by the trace unit. The trace indexing unit is configured to generate each index value as one of a predetermined sequence of index values, wherein an n+1 | 12-22-2011 |
| 20110320783 | VERIFICATION USING OPCODE COMPARE - A verification method is provided and includes randomly choosing a hardware executed instruction in a predefined program to force Opcode Compare on, determining an identity of a corresponding opcode from the chosen instruction and initializing Opcode Compare logic to trap the chosen instruction to firmware and creating firmware to initiate performance of hardware verification in the firmware and re-initiating performance of the hardware verification in hardware. | 12-29-2011 |
| 20110320784 | VERIFICATION OF PROCESSOR ARCHITECTURES ALLOWING FOR SELF MODIFYING CODE - A verification operation including generating a predefined instruction, initializing a relevant self modifying code (SMC) target memory location to form an SMC trap, binding the SMC trap to the predefined instruction to form an SMC trap source and propagating initialization of instruction code into the SMC trap source. | 12-29-2011 |
| 20120023315 | Generating Hardware Events Via the Instruction Stream for Microprocessor Verification - A processor receives an instruction operation (OP) code from a verification system. The instruction OP code includes instruction bits and forced event bits. The processor identifies a forced event based upon the forced event bits, which is unrelated to an instruction that corresponds to the instruction bits. In turn, the processor executes the forced event. | 01-26-2012 |
| 20120042153 | DATA PROCESSING SYSTEM HAVING TEMPORAL REDUNDANCY AND METHOD THEREFOR - In a data processing system having execution circuitry, a method includes providing a reference instruction to the execution circuitry, the reference instruction having an operand; providing a cross-check instruction to the execution circuitry; executing the reference instruction to obtain a first result, wherein, during the step of executing the reference instruction, residual information is derived from execution of the reference instruction; executing the cross-check instruction using the residual information to obtain a second result; and comparing the second result obtained from execution of the cross-check instruction to the operand of the reference instruction to determine whether an error occurred during execution of the reference instruction or the cross-check instruction. | 02-16-2012 |
| 20120079254 | Debugging of a data processing apparatus - A data processing apparatus is provided comprising data processing circuitry and debug circuitry. The debug circuitry controls operation of the processing circuitry when operating in a debug mode. The data processing circuitry determines upon entry into a debug mode a current operating state of the data processing apparatus. The data processing circuitry allocates one of a plurality of instruction sets to be used as a debug instruction set depending upon the determined current operating state. | 03-29-2012 |
| 20120084537 | SYSTEM AND METHOD FOR EXECUTION BASED FILTERING OF INSTRUCTIONS OF A PROCESSOR TO MANAGE DYNAMIC CODE OPTIMIZATION - A filter executing on a processor monitors instructions executing on the processor to identify instructions that will benefit from performance tuning. Filtering instructions before analysis for performance tuning reduces overhead by identifying candidates for performance tuning with low cost monitoring before expending resources on analysis so that only instructions that will have performance tuning are analyzed. Reducing overhead for performance tuning makes performance tuning practical in a dynamic optimization environment in which instructions and their effective addresses change over time. | 04-05-2012 |
| 20120084538 | Methodology and Framework for Run-Time Coverage Measurement of Architectural Events of a Microprocessor - A post-silicon testing apparatus, method, and computer program product provide for runtime coverage measurement methodology to measure the architectural events in hardware. Measurement of all architectural events discernable from the instructions and architectural state changes are tracked and recorded. A mechanism to ensure capturing of maskable events is also provided. A feedback driven test-generation approach is enabled by the runtime coverage measurement. The runtime coverage measurement system presents a live view of the comprehensive architectural event coverage to the user/tester. The methodology can be implemented on an operating system environment and also as a standalone/bare-metal tool. | 04-05-2012 |
| 20120089820 | HYBRID MECHANISM FOR MORE EFFICIENT EMULATION AND METHOD THEREFOR - In a host system, a method for using instruction scheduling to efficiently emulate the operation of a target computing syste includes preparing, on the host system, an instruction sequence to interpret an instruction written for execution on the target computing system. An instruction scheduling on the instruction sequence is performed, to achieve an efficient instruction level parallelism, for the host system. A separate and independent instruction sequence is inserted, which, when executed simultaneously with the instruction sequence, performs to copy to a separate location a minimum instruction sequence necessary to execute an intent of an interpreted target instruction, the interpreted target instruction being a translation; and modifies the interpreter code such that a next interpretation of the target instruction results in execution of the translated version, thereby removing execution of interpreter overhead. | 04-12-2012 |
| 20120110310 | MICROPROCESSOR WITH PIPELINE BUBBLE DETECTION DEVICE - A microprocessor includes a pipeline microarchitecture and a pipeline bubble detection device. The pipeline bubble detection device has a minimum execution clock cycle ascertainment unit for ascertaining a minimum or optimum number of execution clock cycles for one or more program commands which pass through the pipeline microarchitecture or are handled by the pipeline microarchitecture. | 05-03-2012 |
| 20120144171 | Mechanism for Detection and Measurement of Hardware-Based Processor Latency - A mechanism for detection and measurement of hardware-based processor latency is disclosed. A method of the invention includes issuing an instruction to stop all running instructions on one or more processors of a multi-core computing device, starting a latency measurement code loop on each of the one or more processors, wherein for each of the one or more processors the latency measurement code loop operates to sample a time stamp counter (TSC) for a first time reading and sample the TSC for a second time reading after a predetermined period of time, and determine whether a difference between the first and the second time readings represents a discontinuous time interval where an operating system (OS) of the computing device does not control the one or more processors. | 06-07-2012 |
| 20120159131 | System and method for performing deterministic processing - A system and method is provided for performing deterministic processing on a non-deterministic computer system. In one example, the system forces execution of one or more computer instructions to execute within a constant execution time. A deterministic engine, if necessary, waits a variable amount of time to ensure that the execution of the computer instructions is performed over the constant execution time. Because the execution time is constant, the execution is deterministic and therefore may be used in applications requiring deterministic behavior. For example, such a deterministic engine may be used in automated test equipment (ATE) applications. | 06-21-2012 |
| 20120166774 | COMPUTER-READABLE MEDIUM STORING PROCESSOR TESTING PROGRAM - A non-transitory computer-readable medium storing a processor testing program causing a computer to execute a testing process for a processor, the processor having a plurality of pipeline stages for processing an instruction and a controller for providing the pipeline stage with an inter-lock signal for aborting a transition of the instruction between the pipeline stages when a pipeline hazard is expected to occur. The testing process has a timing generating process including: referring to a pipeline-stage combination pattern indicating whether or not an instruction is under process at each pipeline stage and prescribes a processing status to be tested, and timing generating which provides the inter-lock signal, while an instruction included in a test instruction sequence is executed, so that a processing status of the instruction is matched with the processing status to be tested according to an status information. | 06-28-2012 |
| 20120179898 | SYSTEM AND METHOD FOR ENFORCING SOFTWARE SECURITY THROUGH CPU STATISTICS GATHERED USING HARDWARE FEATURES - This disclosure is directed to measuring hardware-based statistics, such as the number of instructions executed in a specific section of a program during execution, for enforcing software security. The counting can be accomplished through a specific set of instructions, which can either be implemented in hardware or included in the instruction set of a virtual machine. For example, the set of instructions can include atomic instructions of reset, start, stop, get instruction count, and get CPU cycle count. To obtain information on a specific section of code, a software developer can insert start and stop instructions around the desired code section. For each instruction in the identified code block, when the instruction is executed, a counter is incremented. The counter can be stored in a dedicated register. The gathered statistics can be used for a variety of purposes, such as detecting unauthorized code modifications or measuring code performance. | 07-12-2012 |
| 20120198216 | ENHANCED MONITOR FACILITY - A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is generated. In another mode, in response to encountering a monitored event, one or more associated counters are incremented without causing an interrupt. | 08-02-2012 |
| 20120210103 | SYSTEM AND METHOD FOR MULTI-CORE SYNCHRONOUS DEBUGGING OF A MULTI-CORE PLATFORM - A system and a corresponding method for multi-core synchronous debugging of a multi-core platform including a plurality of cores are provided. The method includes the following steps. Transmit a core debugging instruction to one of the cores selected by a system debugging instruction or store a group setting included in the system debugging instruction according to the type of the system debugging instruction. Control every core in a group to start executing program instructions simultaneously according to another system debugging instruction. The group is a subset of the cores and the group setting indicates which ones of the cores are included in the group. Use a handshaking mechanism to control all cores of the group to enter a debug mode simultaneously when a debug event happens in any core of the group. | 08-16-2012 |
| 20120216023 | PROCESSOR TESTING - Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may also include randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may additionally include generating a plurality of instructions to increment a counter when each branch instruction is encountered during execution. | 08-23-2012 |
| 20120221838 | SOFTWARE PROGRAMMABLE HARDWARE STATE MACHINES - The present invention provides software programmable hardware state machines to detect a cause of an error in a processor and prevent the error from occurring. A processor core is provided that includes an execution unit, a programmable mask register and a buffer that stores values representing instructions dispatched to the execution unit. The processor core also includes control logic to determine whether there is a match between a sequence in the mask register and a sequence in the buffer and, upon detecting a match, to generate control signals to perform a desired action. The desired action prevents an unwanted change from occurring to the architectural state of the processor. The processor core further comprises a programmable fix register. In an embodiment, the control logic generates the control signals based on control bits stored in the fix register. | 08-30-2012 |
| 20120239913 | DIAGNOSING CODE USING SINGLE STEP EXECUTION - A method and apparatus for controlling a processor to execute in a single step mode such that a single instruction from the instruction stream is executed, the processor determines if the single instruction is one of at least one predetermined type of instruction and stores a type indicator in a data storage location and a diagnostic exception is taken after the processor has processed the single instruction. Additionally, a diagnostic operation is performed including accessing the type indicator stored in the data storage location and, when the single instruction was not one of the predetermined type, controlling the processor to continue executing instructions in the single step mode, and, when the single instruction was one of the at least one predetermined type, controlling the processor to exit the single step mode and not execute the next instruction within the instruction stream as a single instruction followed by an exception. | 09-20-2012 |
| 20120284490 | WORKING SET PROFILER - A working set profiler can monitor an execution of a program or can monitor a user-specified portion of a program to identify methods executed within the monitored execution and associate memory page accesses with each of the identified methods. Memory page accesses are categorized as shared or exclusive, where a shared page is a page that is accessed by more than one method and where an exclusive page is a page that is accessed by only one method in the monitored portion of the program. A call tree can be constructed and augmented with the collected information regarding memory page accesses. Further, for shared pages, the name of the method with which a particular method shares the page access can be collected. The augmented call tree information can be analyzed and prioritized to identify methods whose elimination would reduce program latency. | 11-08-2012 |
| 20120297173 | DEBUGGER SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR DEBUGGING INSTRUCTIONS - Debugger system, method and computer program product for debugging instructions. The method for debugging instructions may include: receiving, by a debugger module, a group of instructions that are stored in a non-volatile memory module and is scheduled to be executed by a processor of a device; determining whether the group of instructions includes a conditional branch instruction; defining, by the debugger module, a hardware breakpoint address as an address of the conditional branch instruction if the group of instructions includes the conditional branch instruction; defining, by the debugger module, the hardware breakpoint as an address of a last instruction of the group of instructions to be executed if the group of instructions does not comprise the conditional branch instruction; instructing a hardware breakpoint detector of the device to detect the hardware breakpoint address; instructing the processor to execute instructions of the group of instructions in a continuous mode until the hardware breakpoint detector detects the hardware breakpoint address; instructing the processor to execute at least one instruction of the group of instructions in a single step mode after the hardware breakpoint detector detects the hardware breakpoint address; and receiving, from the device, debug information that is indicative of an execution of instructions by the processor. | 11-22-2012 |
| 20120324208 | Effective Validation of Execution Units Within a Processor - A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated. | 12-20-2012 |
| 20120331277 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, PROGRAM, AND NON-TRANSITORY INFORMATION STORAGE MEDIUM - An acquisition unit acquires a command that is executable by a processor of an other type being a processor of a different type from a processor of a processing execution subject apparatus. An identification unit identifies processing that is executable by the processor of the processing execution subject apparatus which is associated with the command acquired by the acquisition unit. An execution control unit controls execution of the processing performed by the processor of the processing execution subject apparatus based on a value of a parameter which is set in a specific command for the processor of the other type, the value of the parameter which is set in the specific command not affecting execution of processing performed by the processor of the other type. | 12-27-2012 |
| 20130024674 | RETURN ADDRESS OPTIMISATION FOR A DYNAMIC CODE TRANSLATOR - A dynamic code translator with isoblocking uses a return trampoline having branch instructions conditioned on different isostates to optimize return address translation, by allowing the hardware to predict that the address of a future return will be the address of trampoline. An IP relative call is inserted into translated code to write the trampoline address to a target link register and a target return address stack used by the native machine to predict return addresses. If a computed subject return address matches a subject return address register value, the current isostate of the isoblock is written to an isostate register. The isostate value in the isostate register is then used to select the branch instruction in the trampoline for the true subject return address. Sufficient code area in the trampoline instruction set can be reserved for a number of compare/branch pairs which is equal to the number of available isostates. | 01-24-2013 |
| 20130046962 | Operating a Pipeline Flattener in a Semiconductor Device - A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages. | 02-21-2013 |
| 20130080748 | MULTI-PROCESSOR DATA PROCESSING SYSTEM HAVING SYNCHRONIZED EXIT FROM DEBUG MODE AND METHOD THEREFOR - A data processing system includes a plurality of data processors, debug logic, and linking logic. The debug logic is coupled to each data processor of the plurality of data processors, and is for providing an instruction for exiting debug mode to the plurality of data processors. The linking logic is coupled to the debug logic and to each of the plurality of data processors. The linking logic is for linking selected ones of the plurality of data processors with each other and to the debug logic. The debug logic provides the instruction for exiting the debug mode when the selected ones of the plurality of data processors are linked in parallel by the linking logic. | 03-28-2013 |
| 20130091342 | TRACING SOFTWARE EXECUTION OF A BUSINESS PROCESS - Various embodiments of systems and methods to trace an execution of a business process are disclosed. Business rules and corresponding business objects required to execute the business process are identified and rendered to receive an input. Based upon detecting a trigger to execute the business process, the business rules and the corresponding business objects are processed to compute a process-resultant for the business process. A process-path of the computed process-resultant is traced by tracing key-strings corresponding to the business objects involved in computing the process-resultant, to generate a trace-resultant. The trace-resultant is parsed by determining versioned business objects and business information of the key-strings, to derive a business definition for the traced business objects involved in computing the process-resultant. Based upon the business definition, a comprehensive trace-map comprising a compilation of the process-resultant to execute the business process is generated. | 04-11-2013 |
| 20130124837 | ANALYSIS OF SHORT TERM CPU SPIKES IN AN OPERATING SYSTEM KERNEL - A profiler may analyze processes being run by a processor. The profiler may include logic to periodically sample a value of an instruction pointer that indicates an instruction in the first process that is currently being executed by the processor and logic to update profile data based on the sampled value. The profiler may additionally include logic to determine, in response to a context switch that includes the operating system switching the active process from the first process to another of the plurality of processes, whether the first process executes for greater than a first length of time; logic to stop operation of the profiler when the first process executes for greater than the first length of time; and logic to clear the profile data when the first process fails to execute for greater than the first length of time. | 05-16-2013 |
| 20130191620 | HARDWARE DEBUGGING APPARATUS AND METHOD FOR SOFTWARE PIPELINED PROGRAM - Provided is a hardware debugging apparatus and method for a software-pipelined program. The hardware debugging apparatus and method overcome a currency problem caused during hardware debugging in the software-pipelined program by guarding certain execution blocks and restarting the processing of the software-pipelined program. | 07-25-2013 |
| 20130205124 | BRANCH TARGET COMPUTATION - Embodiments related to conducting and constructing a secure start-up process are disclosed, One embodiment provides, on a computing device, a method of conducting a secure start-up process. The method comprises recognizing the branch instruction, and, in response, calculating an integrity datum of a data segment. The method further comprises obtaining an adjustment datum, and computing a branch target address based on the integrity datum and the adjustment datum. | 08-08-2013 |
| 20130246767 | INSTRUCTION TO COMPUTE THE DISTANCE TO A SPECIFIED MEMORY BOUNDARY - A Load Count to Block Boundary instruction is provided that provides a distance from a specified memory address to a specified memory boundary. The memory boundary is a boundary that is not to be crossed in loading data. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary; or it may be dynamically determined. | 09-19-2013 |
| 20130246768 | TRANSFORMING NON-CONTIGUOUS INSTRUCTION SPECIFIERS TO CONTIGUOUS INSTRUCTION SPECIFIERS - Emulation of instructions that include non-contiguous specifiers is facilitated. A non-contiguous specifier specifies a resource of an instruction, such as a register, using multiple fields of the instruction. For example, multiple fields of the instruction (e.g., two fields) include bits that together designate a particular register to be used by the instruction. Non-contiguous specifiers of instructions defined in one computer system architecture are transformed to contiguous specifiers usable by instructions defined in another computer system architecture. The instructions defined in the another computer system architecture emulate the instructions defined for the one computer system architecture. | 09-19-2013 |
| 20130246769 | RUN-TIME INSTRUMENTATION MONITORING FOR PROCESSOR CHARACTERISTIC CHANGES - Embodiments of the invention relate to monitoring processor characteristic information of a processor using run-time-instrumentation. An aspect of the invention includes executing an instruction stream on the processor and detecting a run-time instrumentation sample point of the executing instruction stream on the processor. A reporting group is stored in a run-time instrumentation program buffer based on the run-time instrumentation sample point. The reporting group includes processor characteristic information associated with the processor. | 09-19-2013 |
| 20130246770 | CONTROLLING OPERATION OF A RUN-TIME INSTRUMENTATION FACILITY FROM A LESSER-PRIVILEGED STATE - Embodiments of the invention relate to enabling and disabling execution of a run-time instrumentation facility. An instruction for execution by the processor in a lesser privileged state is fetched by the processor. It is determined, by the processor, that the run-time instrumentation facility permits execution of the instruction in the lesser-privileged state and that controls associated with the run-time instrumentation facility are valid. The run-time instrumentation facility is disabled based on the instruction being a run-time instrumentation facility off (RIOFF) instruction. The disabling includes updating a bit in a program status word (PSW) of the processor to indicate that run-time instrumentation data should not be captured by the processor. The run-time instrumentation facility is enabled based on the instruction being a run-time instrumentation facility on (RION) instruction. The enabling includes updating the bit in the PSW to indicate that run-time instrumentation data should be captured by the processor. | 09-19-2013 |
| 20130246771 | RUN-TIME INSTRUMENTATION MONITORING OF PROCESSOR CHARACTERISTICS - Embodiments of the invention relate to monitoring processor characteristic information of a processor using run-time-instrumentation. An aspect of the invention includes executing an instruction stream on the processor and detecting a run-time instrumentation sample point of the executing instruction stream on the processor. A reporting group is stored in a run-time instrumentation program buffer based on the run-time instrumentation sample point. The reporting group includes processor characteristic information associated with the processor. | 09-19-2013 |
| 20130246772 | RUN-TIME INSTRUMENTATION INDIRECT SAMPLING BY INSTRUCTION OPERATION CODE - Embodiments of the invention relate to implementing run-time instrumentation indirect sampling by instruction operation code. An aspect of the invention includes a method for implementing run-time instrumentation indirect sampling by instruction operation code. The method includes reading sample-point instruction operation codes from a sample-point instruction array, and comparing, by a processor, the sample-point instruction operation codes to an operation code of an instruction from an instruction stream executing on the processor. The method also includes recognizing a sample point upon execution of the instruction with the operation code matching one of the sample-point instruction operation codes. The run-time instrumentation information is obtained from the sample point. The method further includes storing the run-time instrumentation information in a run-time instrumentation program buffer as a reporting group. | 09-19-2013 |
| 20130246773 | HARDWARE BASED RUN-TIME INSTRUMENTATION FACILITY FOR MANAGED RUN-TIMES - Embodiments of the invention relate to performing run-time instrumentation. Run-time instrumentation is captured, by a processor, based on an instruction stream of instructions of an application program executing on the processor. The capturing includes storing the run-time instrumentation data in a collection buffer of the processor. A run-time instrumentation sample point trigger is detected by the processor. Contents of the collection buffer are copied into a program buffer as a reporting group based on detecting the run-time instrumentation sample point trigger. The program buffer is located in main storage in an address space that is accessible by the application program. | 09-19-2013 |
| 20130246774 | RUN-TIME INSTRUMENTATION SAMPLING IN TRANSACTIONAL-EXECUTION MODE - Embodiments of the invention relate to implementing run-time instrumentation indirect sampling by address. An aspect of the invention includes a method for implementing run-time instrumentation indirect sampling by address. The method includes reading sample-point addresses from a sample-point address array, and comparing, by a processor, the sample-point addresses to an address associated with an instruction from an instruction stream executing on the processor. The method further includes recognizing a sample point upon execution of the instruction associated with the address matching one of the sample-point addresses. Run-time instrumentation information is obtained from the sample point. The method also includes storing the run-time instrumentation information in a run-time instrumentation program buffer as a reporting group. | 09-19-2013 |
| 20130246775 | RUN-TIME INSTRUMENTATION SAMPLING IN TRANSACTIONAL-EXECUTION MODE - Embodiments of the invention relate to implementing run-time instrumentation sampling in transactional-execution mode. An aspect of the invention includes a method for implementing run-time instrumentation sampling in transactional-execution mode. The method includes determining, by a processor, that the processor is configured to execute instructions of an instruction stream in a transactional-execution mode, the instructions defining a transaction. The method also includes interlocking completion of storage operations of the instructions to prevent instruction-directed storage until completion of the transaction. The method further includes recognizing a sample point during execution of the instructions while in the transactional-execution mode. The method additionally includes run-time-instrumentation-directed storing, upon successful completion of the transaction, run-time instrumentation information obtained at the sample point. | 09-19-2013 |
| 20130246776 | RUN-TIME INSTRUMENTATION REPORTING - Embodiments of the invention relate to run-time instrumentation reporting. An instruction stream is executed by a processor. Run-time instrumentation information of the executing instruction stream is captured by the processor. Run-time instrumentation records are created based on the captured run-time instrumentation information. A run-time instrumentation sample point of the executing instruction stream on the processor is detected. A reporting group is stored in a run-time instrumentation program buffer. The storing is based on the detecting and the storing includes: determining a current address of the run-time instrumentation program buffer, the determining based on instruction accessible run-time instrumentation controls; and storing the reporting group into the run-time instrumentation program buffer based on an origin address and the current address of the run-time instrumentation program buffer, the reporting group including the created run-time instrumentation records. | 09-19-2013 |
| 20130262843 | FUNCTION-BASED SOFTWARE COMPARISON METHOD - A method for comparing a first subroutine and a second subroutine in functionality, includes: defining a plurality of instruction sets, each instruction set associated with a corresponding instruction set process; obtaining a first program section and a second program section from a first subroutine and a second subroutine, respectively, and categorizing the first subroutine and the second subroutine to one of the instruction sets, respectively; performing a program section comparison process to select and perform one of the instruction sets according to the instruction set to which the first program section is categorized and the instruction set to which the second program section is categorized, so as to compare whether the first program section and the second program section have identical functions, and to accordingly determine whether the first subroutine and the second subroutine are equivalent in functionality. | 10-03-2013 |
| 20130297917 | SYSTEM AND METHOD FOR REAL TIME INSTRUCTION TRACING - An apparatus and method are described for real time instruction tracing. For example, a method according to one embodiment comprises: recording user specified address ranges for which tracing is required; monitoring a next linear instruction pointer (NLIP) values and/or branch linear instruction pointer (BLIP) values to determine if address range has been entered; when the range is entered, compressing the NLIP and/or BLIP values and constructing fixed length packets containing the tracing data; and transferring the fixed length packets to a memory execution cluster. | 11-07-2013 |
| 20130311757 | EXTRACT CPU TIME FACILITY - An efficient facility for determining resource usage, such as a processor time used by tasks. The determination is performed on behalf of user applications that do not require a call to operating system services. The facility includes an instruction that determines elapsed time and reports it to the user as a single unit of operation. | 11-21-2013 |
| 20130326202 | LOAD TEST CAPACITY PLANNING - Disclosed herein are techniques for load test capacity planning. Resources consumed by instructions executing in a first computer apparatus are determined. A metric associated with a second computer apparatus is determined. A number of instances of the instructions that are able to execute concurrently in the second computer apparatus is determined. | 12-05-2013 |
| 20130326203 | MULTIPROCESSOR - A microprocessor has a plurality of debug modules, multiple sets of processor cores provided corresponding to the debug modules so that each set of the processor cores are debugged by the corresponding debug module, and a plurality of debug ring units provided corresponding to the debug modules, each debug ring unit generating a debug ring signal for instructing the corresponding processor cores to transit to a debug mode. The debug ring units are connected to generate a ring and sequentially transmit the debug ring signal, and when receiving the debug ring signal, each debug ring unit outputs, to the corresponding debug module, a debug transition signal for instructing the corresponding processor cores to transit to the debug mode. | 12-05-2013 |
| 20130332711 | SYSTEMS AND METHODS FOR EFFICIENT SCHEDULING OF CONCURRENT APPLICATIONS IN MULTITHREADED PROCESSORS - Systems and methods which provide a modular processor framework and instruction set architecture designed to efficiently execute applications whose memory access patterns are irregular or non-unit stride as disclosed. A hybrid multithreading framework (HMTF) of embodiments provides a framework for constructing tightly coupled, chip-multithreading (CMT) processors that contain specific features well-suited to hiding latency to main memory and executing highly concurrent applications. The HMTF of embodiments includes an instruction set designed specifically to exploit the high degree of parallelism and concurrency control mechanisms present in the HMTF hardware modules. The instruction format implemented by a HMTF of embodiments is designed to give the architecture, the runtime libraries, and/or the application ultimate control over how and when concurrency between thread cache units is initiated. For example, one or more bit of the instruction payload may be designated as a context switch bit (CTX) for expressly controlling context switching. | 12-12-2013 |
| 20130339683 | INSTRUCTION FILTERING - Embodiments relate to instruction filtering. An aspect includes a system for instruction filtering. The system includes memory configured to store instructions accessible by a processor, and the processor includes a tracking array and a tracked instruction logic block. The processor is configured to perform a method including detecting a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in the tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. Instruction text of the subsequently fetched instruction is marked to indicate previous execution based on the tracking array. An action of the tracked instruction logic block is prevented based on the marked instruction text. | 12-19-2013 |
| 20130339684 | RESTRICTING PROCESSING WITHIN A PROCESSOR TO FACILITATE TRANSACTION COMPLETION - Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors. | 12-19-2013 |
| 20130339685 | RESTRICTED INSTRUCTIONS IN TRANSACTIONAL EXECUTION - Restricted instructions are prohibited from execution within a transaction. There are classes of instructions that are restricted regardless of type of transaction: constrained or nonconstrained. There are instructions only restricted in constrained transactions, and there are instructions that are selectively restricted for given transactions based on controls specified on instructions used to initiate the transactions. | 12-19-2013 |
| 20130339686 | PROCESSING APPARATUS, TRACE UNIT AND DIAGNOSTIC APPARATUS - A processing circuit is responsive to at least one conditional instruction to perform a conditional operation in dependence on a current value of a subset of at least one condition flag. A trace circuit is provided for generating trace data elements indicative of operations performed by the processing circuit. When the processing circuit | 12-19-2013 |
| 20140019733 | REAL TIME INSTRUCTION TRACING COMPRESSION OF RET INSTRUCTIONS - In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing Real Time Instruction Tracing compression of RET instructions For example, in one embodiment, such means may include an integrated circuit having means for initiating instruction tracing for instructions of a traced application, mode, or code region, as the instructions are executed by the integrated circuit; means for generating a plurality of packets describing the instruction tracing; and means for compressing a multi-bit RET instruction (RETurn instruction) to a single bit RET instruction. | 01-16-2014 |
| 20140019734 | DATA PROCESSING APPARATUS AND METHOD USING CHECKPOINTING - A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency. If the execution circuitry does not complete execution of that instance of the predetermined type of instruction due to occurrence of a predetermined event, the data processing apparatus is arranged to reinstate the state of the data processing apparatus with reference to the checkpoint information, such that the execution circuitry is then configured to recommence execution of the sequence of program instructions at that instance of the predetermined type of instruction. | 01-16-2014 |
| 20140032883 | Lock Free Streaming of Executable Code Data - A disassembler receives instructions and disassembles them into a plurality of separate opcodes. The disassembler creates a table identifying boundaries between each opcode. Each opcode is written to memory in an opcode-by-opcode manner by atomically writing standard blocks of memory. Debug break point opcodes are appended to opcode to create a full block of memory when needed. The block of memory may be thirty-two or sixty-four bits long, for example. Long opcodes may overlap two or more memory blocks. Debug break point opcodes may be appended to a second portion of the long opcode to create a full block of memory. A stream fault interceptor identifies when a requested data page is not available and retrieving the data page. | 01-30-2014 |
| 20140052971 | NATIVE CODE INSTRUCTION SELECTION - Methods, systems, and apparatus, including computer programs encoded on computer storage media, for selecting native code instructions. One of the methods includes receiving an initial machine language instruction for execution by a processor in a first execution mode; determining that a portion of the initial machine language instruction, when executed by the processor in a second execution mode, satisfies one or more risk criteria; generating one or more alternative machine language instructions to replace the initial machine language instruction for execution by the processor in the first execution mode, wherein the one or more alternative machine language instructions, when executed by the processor in the second execution mode, mitigate the one or more risk criteria; and providing the one or more alternative machine language instructions. | 02-20-2014 |
| 20140059330 | PARSING-ENHANCEMENT FACILITY - An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general registers, wherein a first general register stores an argument address, a second general register stores a function code, a third general register stores length of an argument-character buffer, and the fourth of which contains the address of the function-code data structure. | 02-27-2014 |
| 20140068234 | INSTRUCTION INSERTION IN STATE MACHINE ENGINES - State machine engines are disclosed, including those having an instruction insertion register. One such instruction insertion register may provide an initialization instruction, such as to prepare a state machine engine for data analysis. An instruction insertion register may also provide an instruction in an attempt to resolve an error that occurs during operation of a state machine engine. An instruction insertion register may also be used to debug a state machine engine, such as after the state machine experiences a fatal error. | 03-06-2014 |
| 20140075164 | TEMPORAL LOCALITY AWARE INSTRUCTION SAMPLING - A method and system are disclosed for sampling instructions executing on a computer processor. A computer processor determines a number of times a specified event has occurred within a specified temporal window. The computer processor determines to mark an instruction to be executed for monitoring based on the number of times the specified event has occurred within the temporal window, and in response, the computer processor marks the instruction. | 03-13-2014 |
| 20140082335 | CHARACTERIZATION AND VALIDATION OF PROCESSOR LINKS - A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link. | 03-20-2014 |
| 20140095846 | TRACE BASED MEASUREMENT ARCHITECTURE - A method for performing trace based measurement for a plurality of CPUs in parallel includes receiving a signal to perform a CPU parallel trace mode and enabling a parallel trace mode multiplexer to output all trace data, representing all data writes to the local memory, to a single observation unit. In one embodiment, the single observation unit is a processor observation block (POB), and in another embodiment, a bus observation block (BOB). If the single observation unit is a BOB, then the parallel trace mode multiplexer first routes the local memory data trace through a BOB adaptation layer to convert the CPU trace output data to data which is understood by the BOB. | 04-03-2014 |
| 20140129810 | Known Good Code for On-Chip Device Management - In one embodiment, a processor comprises a programmable map and a circuit. The programmable map is configured to store data that identifies at least one instruction for which an architectural modification of an instruction set architecture implemented by the processor has been defined, wherein the processor does not implement the modification. The circuitry is configured to detect the instruction or its memory operands and cause a transition to Known Good Code (KGC), wherein the KGC is protected from unauthorized modification and is provided from an authenticated entity. The KGC comprises code that, when executed, emulates the modification. In another embodiment, an integrated circuit comprises at least one processor core; at least one other circuit; and a KGC source configured to supply KGC to the processor core for execution. The KGC comprises interface code for the other circuit whereby an application executing on the processor core interfaces to the other circuit through the KGC. | 05-08-2014 |
| 20140129811 | MULTI-CORE PROCESSOR SYSTEM AND CONTROL METHOD - A multi-core processor system includes a multi-core processor that has plural core groups; and a storage device that stores a constraint on execution time for each application. A first identified core of the multi-core processor is configured to identify a constraint on execution time of a given application that is among the applications and for which an invocation instruction is received; determine whether the identified constraint meets a performance drop condition; assign the given application to a predetermined core of the multi-core processor, upon determining that the identified constraint meets the performance drop condition; and notify a second identified core of a core group among the core groups, of an assignment instruction for the given application, upon determining that the identified constraint does not meet the performance drop condition. | 05-08-2014 |
| 20140136821 | MULTIPROCESSOR SYSTEM - To provide a multi-processor system that efficiently debugs operations of one processor and operations of another processor. The multiprocessor system has a first processor and a second processor that executes processing by receiving notification from the first processor. The first processor: sequentially specifies instructions to be executed from an instruction queue; sends a notification based on a processing request instruction to the second processor when an instruction that is specified is the processing request instruction; executes the instruction that is specified when the instruction that is specified is not the processing request instruction; and determines whether or not a debug mode is set. When the first processor determines that the debug mode is set, the first processor stops specifying instructions after specifying the processing request instruction, and, after sending the notification, resumes specifying instructions after detecting that the second processor has completed processing corresponding to the notification. | 05-15-2014 |
| 20140143525 | SYSTEMS AND METHODS FOR DATA GENERATION - The invention provides, in one aspect, a digital data processor-based test data generator, that includes a digital data processing system with one or more digital data processors that are coupled for communications. A scenario creator executes on the digital data processing system and accepts, for each of one or more entities (“domains”), a plurality of parameters, including a hierarchical relationship between that entity and one or more other entities, a priority-of-test-data-creation relationship between that entity and one or more entities, and one or more attributes of that entity. The scenario creator generates a parameter set that defines a test data set specifying the aforesaid entities, relationships and attributes. The test generator further includes an engine that enumerates values for the entities and their attributes in an order determined by the aforesaid relationships. | 05-22-2014 |
| 20140149725 | Method for the On-Line Testing of Pipeline Stages Temporarily Not In Use, and Associated Device - A method for online testing pipeline systems comprising a succession of stages separated by buffers each associated with an idle signal, or idle signal, and/or at least one status bit, comprising: detecting values of the idle signal and/or the corresponding status bits indicating the availability of a cycle or the abrupt interruption of the flow of operations in a pipeline, and indicating that a valid operation, executed by a stage in the pipeline, is followed by an unused cycle; maintaining the state of the buffer in order to allow said valid operation to be re-executed during the unused cycle indicated by said idle signal; re-executing, during the unused cycle, the valid operation, in order to obtain at least a first version and a second version of said valid operation; memorizing, at the output of the pipeline, the results that correspond to the first version of said repeated or re-executed operation, in order to compare with the results of said second version of the same repeated or re-executed operation; and comparing the results obtained at the output of the pipeline, which results correspond to the first version and the second version, and, if there is a difference, indicating an error. | 05-29-2014 |
| 20140156975 | Redundant Threading for Improved Reliability - In some embodiments, a method for improving reliability in a processor is provided. The method can include replicating input data for first and second lanes of a processor, the first and second lanes being located in a same cluster of the processor and the first and second lanes each generating a respective value associated with an instruction to be executed in the respective lane, and responsive to a determination that the generated values do not match, providing an indication that the generated values do not match. | 06-05-2014 |
| 20140173259 | COMPUTER PROCESSOR WITH INSTRUCTION FOR EXECUTION BASED ON AVAILABLE INSTRUCTION SETS - A system and method for testing whether a computer processor is capable of executing a requested instruction set. The system includes a computer processor configured to receive an encoded conditional branch instruction in a form of machine code executable directly by the computer processor, and implement the encoded conditional branch instruction unconditionally, based on underlying hardware architecture of the computer processor. The Method for testing whether a computer processor is capable of executing a requested instruction set, the method including, receiving an encoded conditional branch instruction in a form of machine code executable directly by the computer processor, and implementing the encoded conditional branch instruction unconditionally, based on underlying hardware architecture of the computer processor. | 06-19-2014 |
| 20140195785 | FORMAL VERIFICATION OF A LOGIC DESIGN - A method is provided for verification of a logic design for a processor execution unit which includes an instruction pipeline with one or more pipeline stages. The method includes: creating a design under test using at least a first and a second instance of the logic design; initializing the instruction pipeline using the first instance of the design under test with the same value in each instruction pipeline stage and the second instance with random values in its pipeline stages; selecting an instruction of the processor execution unit out of a plurality of instructions and simultaneously issuing the instruction to each instance of the design under test; providing a comparison between the outputs of the instruction pipeline executing the instruction for each instance; and if the instruction is verifiable by formal model checking, approving the correctness of the logic design if the comparison result is true. | 07-10-2014 |
| 20140195786 | TRACING SPECULATIVELY EXECUTED INSTRUCTIONS - A trace unit for generating items of trace data indicative of processing activities of a processor executing a stream of instructions, the unit includes trace circuitry for monitoring a behaviour of the processor; storage circuitry for storing current trace control data for controlling the trace circuitry; a data store for storing at least some of the trace control data; the trace circuitry being configured to store the trace control data in the data store in response to detection of execution of the group of instructions, wherein the trace circuitry is responsive to detecting the at least one processor cancelling at least one group of the speculatively executed instructions to retrieve at least some of the trace control data stored in the data store for the group of instructions executed before the cancelled speculatively executed instructions and to store the retrieved trace control data in the storage circuitry. | 07-10-2014 |
| 20140208081 | FLOWCHART COMPILER FOR A COMPOUND COMPLEX INSTRUCTION SET COMPUTER (CCISC) PROCESSOR ARCHITECTURE - Systems and methods herein provide for a compiler to create executable programs for a compound instruction based processor directly from flowcharts. In one embodiment, a system receives one or more flowchart diagram files that represent a computer program for a Compound CISC (CCISC) processor. The system identifies a flowchart symbol in the one or more flowchart diagram files, identifies a computing category for the flowchart symbol, and generates one or more CCISC instructions based on the computing category for execution by the CCISC processor. Further, the one or more CCISC instructions generated by the flowchart compiler direct the CCISC processor to access and operate on at least two data values in a multi-channel memory during the same clock cycle. | 07-24-2014 |
| 20140208082 | AUTOMATED TEST PLATFORM - A segmented subsystem, for use within an automated test platform, includes a first subsystem segment configured to execute one or more instructions within the first subsystem segment. A second subsystem segment is configured to execute one or more instructions within the second subsystem segment. The first subsystem segment includes: a first functionality, a second functionality, and a status polling engine. The status polling engine is configured to: determine a first status for the first functionality and a second status for the second functionality, and generate a consolidated status indicator for the first subsystem segment based, at least in part, upon the first status for the first functionality and the second status for the second functionality. | 07-24-2014 |
| 20140223150 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND STOP METHOD - An information processing apparatus includes a first preservation unit configured to preserve execution request information for information processing; an execution unit configured to execute one or more types of the information processing; an execution control unit configured to have the execution unit being capable of executing one of the types of the information processing execute the information processing of the execution request information preserved by the first preservation unit; and a second preservation unit configured to preserve a stop command of the execution unit. If the execution unit does not execute the information processing, the execution control unit checks the second preservation unit if the second preservation unit preserves the stop command to have the execution unit execute a stop procedure. | 08-07-2014 |
| 20140237219 | MICROSTACKSHOTS - A method and apparatus of a device that captures a stackshot of an executing process is described. In an exemplary embodiment, the device detects an interrupt of the process occurring during the execution of the process, where the process execution can be in a kernel space and user space, and the interrupt occurs during the user space. The device further determines whether to capture a stackshot during the interrupt using a penalty function. If the stackshot is to be captured, the device captures the stackshot and saves the stackshot. | 08-21-2014 |
| 20140281433 | APPARATUS AND METHOD FOR TRACING EXCEPTIONS - A data processing apparatus comprises processing circuitry for executing a stream of instructions, and exception handling circuitry for selecting, from one or more exceptions, an exception to be handled by the processing circuitry. The unselected exceptions are referred to as pending exceptions. The data processing apparatus further comprises trace generating circuitry that generates trace data packets in dependence on activity of the processing circuitry. The trace generating circuitry detects pending exceptions and, if an exception is detected to be pending, includes an indication of the pending exception in at least one trace data packet. By tracking when a particular exception is pended, rather than when it is selected for handling by the processing circuitry, it is possible to more precisely determine when the exception occurred, as opposed to when it is finally handled. | 09-18-2014 |
| 20140281434 | PATH PROFILING USING HARDWARE AND SOFTWARE COMBINATION - A mechanism for generating a path profile is disclosed. A profiling module may insert profiling instructions into instruction blocks. The profiling instructions may generate a path identifier as a processor executes an execution path executes a sequence or path of instruction blocks). A path identifier module may add path identifiers to path identifier data, such as a table, and may track the number of times an execution path associated with the path identifier is executed. The profiling module may periodically copy and/or modify the path identifier data and may generate a path profile based on the path identifier data | 09-18-2014 |
| 20140281435 | METHOD TO PARALLEIZE LOOPS IN THE PRESENCE OF POSSIBLE MEMORY ALIASES - In one particular example, this disclosure provides an efficient mechanism to determine the degree of parallelization possible for a loop in the presence of possible memory aliases that cannot be resolved at compile-time. Hardware instructions are provided that test memory addresses at run-time and set a mode or register that enables a single instance of a loop to run the maximum number of SIMD (Single Instruction, Multiple Data) lanes to run in parallel that obey the semantics of the original scalar loop. Other hardware features that extend applicability or performance of such instructions are enumerated. | 09-18-2014 |
| 20140281436 | METHOD FOR EMULATING A GUEST CENTRALIZED FLAG ARCHITECTURE BY USING A NATIVE DISTRIBUTED FLAG ARCHITECTURE - A method for emulating a guest centralized flag architecture by using a native distributed flag architecture. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks, wherein each of the instruction blocks comprise two half blocks; scheduling the instructions of the instruction block to execute in accordance with a scheduler; and using a distributed flag architecture to emulate a centralized flag architecture for the emulation of guest instruction execution. | 09-18-2014 |
| 20140325191 | SEMICONDUCTOR TEST APPARATUS FOR CONTROLLING TESTER - A tester instruction generation unit generates a tester instruction for terminals of a plurality of devices connected to a tester based on an instruction of a user program and causes an instruction storage unit to store the tester instruction. A transfer mode setting unit sets a transfer mode to either a successive transfer mode or a batch transfer mode, based on the number of tester instructions in the instruction storage unit or an instruction of the user program. A transfer control unit transmits the tester instruction in the instruction storage unit to the tester in accordance with the set transfer mode. | 10-30-2014 |
| 20140344556 | INTERLEAVED INSTRUCTION DEBUGGER - One or more embodiments of the invention are directed to a method including monitoring execution of a set of programs each including a set of instructions executing interleaved with other instructions of the set of instructions, where each of the set of instructions includes at least one operation operating on a set of threads; organizing a first set of instructions corresponding to a first program of the set of programs based on an execution order of the first set of instructions; generating a result set representing the first set of instructions organized based on the execution order; and displaying the result set. | 11-20-2014 |
| 20150019846 | SYSTEM LEVEL ARCHITECTURE VERIFICATION FOR TRANSACTION EXECUTION IN A MULTI-PROCESSING ENVIRONMENT - Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution. The computing device may cause the transaction execution to be tested in a multi-processing system based on the instruction stream. A status of the test may be output to one or more output devices. | 01-15-2015 |
| 20150039868 | INTRA-INSTRUCTIONAL TRANSACTION ABORT HANDLING - Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction. | 02-05-2015 |
| 20150046688 | METHOD OF GENERATING PROCESSOR TEST INSTRUCTION SEQUENCE AND GENERATING APPARATUS - A test instruction sequence generating method for a processor includes classifying registers used for executing test instructions into two register groups, generating a test instruction executed by the processor, amending a register specified in a result value register field of the test instruction to a register of a first register group when a first instruction is specified in an arithmetic type field of the test instruction and a register of a second register group is specified in the result value register field of the test instruction, and further amending a register specified in a input value register field of the test instruction to a register of the second register group when a second instruction is specified in the arithmetic type field of the test instruction and a register of the first register group is specified in the input value register field of the test instruction. | 02-12-2015 |
| 20150058604 | VERIFYING FORWARDING PATHS IN PIPELINES - A tool for formally verifying forwarding paths in an information pipeline. The tool creates two logic design copies of the pipeline to be verified. The tool retrieves a first and a second instruction, which have previously been proven to compute a mathematically correct result when executed separately. The tool defines driver input functions for issuing instructions to the two logic design copies. In accordance with the driver input functions, the tool issues instructions to the two logic design copies. The tool abstracts data flow of the two logic design copies to isolate forwarding paths for verification. The tool adjusts for latency differences between the first and second logic design copies. The tool checks a register for results, and when results from of two logic design copies become available in the register, the tool verifies the results to conclusively prove the correctness of all states of the information pipeline. | 02-26-2015 |
| 20150095626 | TRACE METHOD AND INFORMATION PROCESSING APPARATUS - An information processing apparatus includes a rewriting unit and an execution unit. The rewriting unit rewrites a first instruction described at a trace point in a function defined in a program to a second instruction which gives instructions to execute a trace code, and stores the first instruction in a storage unit. The execution unit executes the trace code on the basis of the second instruction at the time of execution at the trace point in the function. If a third instruction which calls the function is included in the trace code, the execution unit replaces, at the time of executing the third instruction, the second instruction at the trace point in the function with the first instruction stored in the storage unit, and performs the function. | 04-02-2015 |
| 20150355937 | INDICATING NEARING THE COMPLETION OF A TRANSACTION - In a multi-processor transaction execution environment, a transaction executes a hint instruction indicating proximity to completion of the transaction. Pending aborts of the transaction due to memory conflicts are suppressed based on the proximity of the transaction to completion. | 12-10-2015 |
| 20150378730 | SYSTEM ON A CHIP WITH MANAGING PROCESSOR AND METHOD THEREFOR - A system on a chip comprises a managing processor for controlling operations of the system on a chip. The managing processor comprises a core monitor control logic circuit operable to: receive at least one instruction; determine whether the instruction is an activation instruction; determine whether the managing processor is in or transitioning to an idle state; and transition the managing processor from a first mode of operation to a second mode of operation in response to the instruction being an activation instruction and the managing processor being in or transitioning to an idle state. | 12-31-2015 |
| 20160054996 | Computer Program Instruction Analysis - Disclosed is a method of analysis of a computer program instruction for use in a central processing unit having a decoding unit. The method includes receiving an address of an instruction to be analyzed, fetching said instruction stored at said address, decoding by a decoding unit associated with the central processing unit, the fetched instruction, and returning the results of said decoding of said fetched instruction. The decoded results may be returned as a data block stored in memory associated with the central processing unit or in one or more registers of the central processing unit. The decoded results may include the type of the instruction and/or the instruction length. The method may further include analyzing the decoded results to determine whether the instruction may be replaced with one of a trap or a break point. | 02-25-2016 |
| 20160077836 | PREDICTING LITERAL LOAD VALUES USING A LITERAL LOAD PREDICTION TABLE, AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA - Predicting literal load values using a literal load prediction table, and related circuits, methods, and computer-readable media are disclosed. In one aspect, an instruction processing circuit provides a literal load prediction table containing one or more entries, each comprising an address and a literal load value. Upon detecting a literal load instruction in an instruction stream, the instruction processing circuit determines whether the literal load prediction table contains an entry having an address of the literal load instruction. If so, the instruction processing circuit provides the predicted literal load value stored in the entry to at least one dependent instruction. The instruction processing circuit subsequently determines whether the predicted literal load value matches the actual literal load value loaded by the literal load instruction. If a mismatch exists, the instruction processing circuit initiates a misprediction recovery. The at least one dependent instruction is re-executed using the actual literal load value. | 03-17-2016 |
| 20160103686 | APPARATUS AND METHOD FOR DETERMINING A CUMULATIVE SIZE OF TRACE MESSAGES GENERATED BY A PLURALITY OF INSTRUCTIONS - An apparatus comprising: at least one processor; and at least one memory including computer program code; the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to perform static code analysis of a plurality of instructions comprising, for each instruction: determining whether a trace message is generated by the instruction; determining whether a size of the trace message generated by the instruction is dependent on a context; determining a size of the trace message generated by the instruction; and updating the context; and to perform determining a cumulative size of trace messages generated by the plurality of instructions. | 04-14-2016 |
| 20160124834 | HISTORICAL CONTROL FLOW VISUALIZATION IN PRODUCTION DIAGNOSTICS - A diagnostic tool can dynamically instrument an application to collect program control flow information using one or more non-stopping production breakpoints. Analyzed program control flow information can be displayed. Dynamic code rewriting techniques can be used to change the production software without deploying new source code. The information collected at the non-stopping breakpoint can include the actual control flow that an instance of the production application took to reach the breakpoint in addition to information about the data. The analyzed control flow information can be visualized in a diagnostic tool allowing a user to see the path an execution of the program took to arrive at a particular breakpoint. | 05-05-2016 |
