| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 712212000 | Decoding by plural parallel decoders | 8 |
| 20080263328 | ORTHOGONAL REGISTER ACCESS - Embodiments of the invention relate to a method and system for accessing a set of parallel registers orthogonally. A decoder may be used to select a particular row or column of the set of parallel registers to perform register operations in a parallel fashion corresponding to the selected row or in an orthogonal fashion corresponding to the selected column. Thus, when a particular row is selected, a register operation may be carried out for each bit of the selected row to produce a parallel register output, such as by reading/writing each bit of the selected row to a parallel register. On the other hand, when a particular column is selected, a register operation may be carried out for each bit of the selected column, such as by reading/writing each bit of the selected column to an orthogonal register. The orthogonal register access allows for fast and efficient access to a particular bit in the set of parallel registers. | 10-23-2008 |
| 20100169614 | PROCESSOR FOR EXECUTING HIGHLY EFFICIENT VLIW - A 32-bit instruction | 07-01-2010 |
| 20120005458 | Fast Static Rotator/Shifter with Non Two's Complemented Decode and Fast Mask Generation - In one embodiment, a rotator, a mask generator, and circuitry configured to mask the rotated operand output by the rotator with the output mask generated by the mask generator perform a shift operation. The rotator is configured to rotate the input operand by the shift count. The mask generator is configured to generate an output mask by decoding a most significant bit (MSB) field of the shift count to generate a first mask, decoding a least significant bit (LSB) field of the shift count to generate a second mask, logically ANDing the bits of the second mask with the corresponding bit of the first mask and logically ORing the result with an adjacent bit of the first mask that is selected responsive to the shift direction. | 01-05-2012 |
| 20120030449 | DATA TAG CONTROL FOR QUANTUM-DOT CELLULAR AUTOMATA - The present disclosure relates to methods and systems for data tag control for quantum dot cellular automata (QCA). An example method includes receiving data, associating a data tag with the data, communicating the data tag along a first wire-like element to a local tag decoder, reading instructions from the data tag using the local tag decoder, communicating the instructions to a processing element, communicating the data along a second wire-like element to the processing element, and processing the data with the processing element according to the instructions. A length of the first wire-like elements and a length of the second wire-like element are approximately the same such that communication of the instructions and the data to the processing element are synchronized. | 02-02-2012 |
| 20120079249 | Training Decode Unit for Previously-Detected Instruction Type - In an embodiment, a decode unit includes multiple decoders configured to decode different types of instructions. One or more of the decoders may be complex decoders, and the decode unit may disable the complex decoders if an instruction of the corresponding type is not being decoded. In an embodiment, the decode unit may disable the complex decoders by data-gating the instruction into the decoder. The decode unit may also include a control unit that is configured to detect instructions of the type decoded by the complex decoders, and to enable the complex decoders and redirect the fetching in response to the detection. The decode unit may also record an indication of the instruction (e.g. the program counter address (PC) of the instruction) to more rapidly detect the instruction and prevent a redirect in subsequent fetches. | 03-29-2012 |
| 20130145126 | REGISTER MAPPING WITH MULTIPLE INSTRUCTION SETS - A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file | 06-06-2013 |
| 20140052964 | Programmable Logic Unit and Method for Translating and Processing Instructions Using Interpretation Registers - An architecture for microprocessors and the like in which instructions include a type identifier, which selects one of several interpretation registers. The interpretation registers hold information for interpreting the opcode of each instruction, so that a stream of compressed instructions (with type identifiers) can be translated into a stream of expanded instructions. Preferably the type identifiers also distinguish sequencer instructions from processing-element instructions, and can even distinguish among different types of sequencer instructions (as well as among different types of processing-element instructions). | 02-20-2014 |
| 20160019063 | THREAD PAUSE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS - A processor of an aspect includes a decode unit to decode a thread pause instruction from a first thread. A back-end portion of the processor is coupled with the decode unit. The back-end portion of the processor, in response to the thread pause instruction, is to pause processing of subsequent instructions of the first thread for execution. The subsequent instructions occur after the thread pause instruction in program order. The back-end portion, in response to the thread pause instruction, is also to keep at least a majority of the back-end portion of the processor, empty of instructions of the first thread, except for the thread pause instruction, for a predetermined period of time. The majority may include a plurality of execution units and an instruction queue unit. | 01-21-2016 |
