| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 712209000 | Decoding instruction to accommodate plural instruction interpretations (e.g., different dialects, languages, emulation, etc.) | 13 |
| 20080263327 | Automatically selecting firmware instructions for an operating system - Embodiments of the present invention pertain to automatically selecting firmware instructions for an operating system. According to one embodiment, at least a part of a first subset of firmware instructions on a computer system is executed. An automatic determination of whether the first subset of firmware instructions supports an operating system the computer system will execute is made. If the first subset of firmware instructions does not support the operating system, a second subset of firmware instructions that does support the operating system is automatically caused to execute without requiring human intervention. A single firmware includes the first subset and the second subset of firmware instructions for different operating systems. | 10-23-2008 |
| 20080270761 | Techniques to generate event contexts for recurring events - Techniques to generate event contexts for recurring events are described. A computer system may comprise a context management module with an event detection module to detect a first occurrence of an event, a context recording module to record context information for the event, the event detection module to detect a second occurrence of the event, and a context generator module to create an event context for the event with the context information during the second occurrence of the event. Other embodiments are described and claimed. | 10-30-2008 |
| 20090276607 | VIRTUALIZATION PLATFORM WITH DEDICATED CACHE ACCESS - A computing system supports a virtualization platform with dedicated cache access. The computing system is configured for usage with a memory and a cache and comprises an instruction decoder configured to decode a cache-line allocation instruction and control logic. The control logic is coupled to the instruction decoder and controls the computing system to execute a cache-line allocation instruction that loads portions of data and code regions of the memory into dedicated cache-lines of the cache which are exempted from eviction according to a cache controller replacement policy. | 11-05-2009 |
| 20100011191 | DATA PROCESSING DEVICE WITH INSTRUCTION TRANSLATOR AND MEMORY INTERFACE DEVICE TO TRANSLATE NON-NATIVE INSTRUCTIONS INTO NATIVE INSTRUCTIONS FOR PROCESSOR - A data processing device includes a processor core, and a memory interface portion arranged between the processor core and an external memory mapped into a predetermined external memory space. The memory interface portion includes a fetch circuit for receiving an address value for access to the external memory space from the processor core, and fetching the data at the address in the external memory, a translator for translating the normative instruction fetched from the external memory into the native instruction, and a select circuit for selectively applying the data read from the external memory space and the instruction prepared by translating the instruction read from the external memory space by the translator to the processor core depending on whether the address value for the access to the external memory space is in a predetermined region or not. | 01-14-2010 |
| 20110029760 | NON-ATOMIC SCHEDULING OF MICRO-OPERATIONS TO PERFORM ROUND INSTRUCTION - A microprocessor executes an instruction specifying a floating-point input operand having a predetermined size and that instructs the microprocessor to round the floating-point input operand to an integer value using a rounding mode and to return a floating-point result having the same predetermined size. An instruction translator translates the instruction into first and second microinstructions. An execution unit executes the first and second microinstructions. The first microinstruction receives as an input operand the instruction floating-point input operand and generates an intermediate result from the input operand. The second microinstruction receives as an input operand the intermediate result of the first microinstruction and generates the floating-point result of the instruction from the intermediate result. The intermediate result is the same predetermined size as the instruction floating-point input operand. The microprocessor executes the first and second microinstructions such that the commencement of their executions may have indeterminate separation in time. | 02-03-2011 |
| 20120023313 | PROCESSOR MICRO-ARCHITECTURE FOR COMPUTE, SAVE OR RESTORE MULTIPLE REGISTERS, DEVICES, SYSTEMS, METHODS AND PROCESSES OF MANUFACTURE - An electronic circuit ( | 01-26-2012 |
| 20120089818 | Decoding instructions from multiple instructions sets - A data processing apparatus, method and computer program are described that are capable of decoding instructions from different instruction sets. The method comprising: receiving an instruction; if an operation code of said instruction is an operation code of an instruction from a base set of instructions decoding said instruction according to decode rules for said base set of instructions; and if said operation code of said instruction is an operation code of an instruction from at least one further set of instructions decoding said instruction according to a set of decode rules determined by an indicator value indicating which of said at least one further set of instructions is currently to be decoded. | 04-12-2012 |
| 20120331271 | COMPRESSED INSTRUCTION FORMAT - A technique for decoding an instruction in an a variable-length instruction set. In one embodiment, an instruction encoding is described, in which legacy, present, and future instruction set extensions are supported, and increased functionality is provided, without expanding the code size and, in some cases, reducing the code size. | 12-27-2012 |
| 20140189310 | FAULT DETECTION IN INSTRUCTION TRANSLATIONS - In one embodiment, a method for identifying and replacing code translations that generate spurious fault events includes detecting, while executing a first native translation of target instruction set architecture (ISA) instructions, occurrence of a fault event, executing the target ISA instructions or a functionally equivalent version thereof, determining whether occurrence of the fault event is replicated while executing the target ISA instructions or the functionally equivalent version thereof, and in response to determining that the fault event is not replicated, determining whether to allow future execution of the first native translation or to prevent such future execution in favor of forming and executing one or more alternate native translations. | 07-03-2014 |
| 20140281399 | INSTRUCTION EMULATION PROCESSORS, METHODS, AND SYSTEMS - A processor of an aspect includes decode logic to receive a first instruction and to determine that the first instruction is to be emulated. The processor also includes emulation mode aware post-decode instruction processor logic coupled with the decode logic. The emulation mode aware post-decode instruction processor logic is to process one or more control signals decoded from an instruction. The instruction is one of a set of one or more instructions used to emulate the first instruction. The one or more control signals are to be processed differently by the emulation mode aware post-decode instruction processor logic when in an emulation mode than when not in the emulation mode. Other apparatus are also disclosed as well as methods and systems. | 09-18-2014 |
| 20160077852 | VIRTUAL MACHINE COPROCESSOR FOR ACCELERATING SOFTWARE EXECUTION - In one general aspect, a system includes an abstract machine instruction stream, a virtual machine coprocessor configured to receive an instruction from the abstract machine instruction stream and to generate one or more native machine instructions in response to the received instruction, and a processor coupled to the virtual machine coprocessor and operable to execute the native machine instructions generated by the virtual machine coprocessor. The virtual machine coprocessor is operable to generate one or more native machine instructions to explicitly control the virtual machine coprocessor. | 03-17-2016 |
| 20160139919 | Machine Level Instructions to Compute a 3D Z-Curve Index from 3D Coordinates - In one embodiment, a processor includes 32-bit and 64-bit machine level instructions to compute a 3D Z-curve Index. A processor decode unit is configured to decode a z-curve ordering instruction having three source operands, each operand associated with one of a first, second, or third coordinate and a processor execution unit is configured to execute the decoded instruction before outputting the 3D Z-curve index to a location specified by a destination operand. | 05-19-2016 |
| 20190146798 | TEST SYSTEM AND METHOD FOR CARRYING OUT A TEST IN A COORDINATED MANNER | 05-16-2019 |
