| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 712037000 | Programmable (e.g., EPROM) | 18 |
| 20080263322 | MAC ARCHITECTURE FOR PIPELINED ACCUMULATIONS - A programmable accumulation module ( | 10-23-2008 |
| 20080307199 | Portable extended display identification data burning device - The present invention relates to a portable extended display identification data (EDID) burning device, which could perform an EDID burning operation via an input device without connecting to a computer. The portable EDID burning device comprises: at least one video connection interface connected to a to-be-burned display device, a memory unit used for storing EDID and system data, an input device interface used for connecting to the input device, and a microcontroller electronically connected to the at least one video connection interface, the memory unit and the input device interface. Therefore, the present invention could be departed from a computer structure and could directly burn in the EDID. That is, the present invention could burn in more than one connection interface at a time during an independent operation, thereby saving cost and time. | 12-11-2008 |
| 20080307200 | Method of burning in extended display identification data without using a computer - The present invention relates to a method of burning in extended display identification data (EDID) without using a computer, wherein an EDID burning device is connected to an input device via an input device interface, a product barcode labeled on a to-be-burned display device is inputted for obtaining product data which is then respectively merged into a plurality of EDID, and then an EDID burning operation is performed to the to-be-burned display device via a VGA video connection interface, a DVI video connection interface and a HDMI video connection interface at the same time. Therefore, the present invention could be departed from a computer structure and could directly burn in the EDID. That is, the present invention could burn in more than one connection interface at a time during an independent operation, thereby saving cost and time. | 12-11-2008 |
| 20090031109 | APPARATUS AND METHOD FOR FAST MICROCODE PATCH FROM MEMORY - A microcode patch apparatus including a patch array, a mux, and a RAM. The patch array receives a microcode ROM address and determines that the microcode ROM address matches one of a plurality of entries within the patch array. The patch array outputs a corresponding branch instruction and asserts a hit signal. The branch instruction prescribes a microcode branch target address. The mux receives the branch instruction from the patch array and a micro instruction corresponding to the microcode ROM address from a microcode ROM. The mux provides the micro instruction or the corresponding branch instruction to an instruction register based upon the state of the hit signal. The RAM stores a plurality of patch instructions that are to be executed in place of the micro instruction. The first one of the plurality of patch instructions is stored at a location in the RAM corresponding to the microcode branch target address. | 01-29-2009 |
| 20090031110 | MICROCODE PATCH EXPANSION MECHANISM - A microcode patch expansion mechanism includes a patch RAM, an expansion RAM, and a controller. The patch RAM stores a first plurality of patch instructions. The first plurality is to be executed by the microprocessor in place of one or more micro instructions which are stored in a microcode ROM. The expansion RAM stores a second plurality of patch instructions. The number of the second plurality is greater than the number of the first plurality. The second plurality is to be executed by the microprocessor in place of a second one or more micro instructions which are stored in the microcode ROM. The controller executes an EXPRAM micro instruction directing that one or more of the second plurality of patch instructions be loaded into the patch RAM, and loads the one or more of the second plurality of patch instructions into the patch RAM. | 01-29-2009 |
| 20090177865 | Extensible Microcomputer Architecture - Described is microprocessor architecture that includes at least one reconfigurable execution path (e.g., implemented via FPGAs or CPLDs). When an instruction is fetched, a mechanism determines whether the reconfigurable execution path (and/or which path) will handle that instruction. A content addressable memory may be used to determine the execution path when fed the instruction's operational code, or an arbiter and multiplexer may resolve conflicts if multiple instruction decode blocks recognize the same instruction. The execution path may be dynamically reconfigured, activated or deactivated as needed, such as to extend an instruction set, to optimize instructions for a particular application program, to implement a peripheral device, to provide parallel computing, and/or based on power consumption and/or processing power needs. Security may be provided by having the reconfigurable execution path loaded from an extension file that is associated with metadata, including security information. | 07-09-2009 |
| 20090292901 | MICROPROCESSOR APPARATUS AND METHOD FOR PERSISTENT ENABLEMENT OF A SECURE EXECUTION MODE - An apparatus providing for a secure execution environment including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program. The secure application program is executed exclusively within a secure execution mode within the microprocessor. The non-secure application programs are accessed from a system memory via a system bus. The microprocessor has a non-volatile enabled indicator register that is configured indicate whether the microprocessor is within the secure execution mode or a non-secure execution mode, where contents of the non-volatile enabled indicator register persist through power removal and reapplication to the microprocessor. The secure non-volatile memory is coupled to the microprocessor via a private bus and is configured to store the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor. | 11-26-2009 |
| 20100262805 | PROCESSOR WITH ASSIGNABLE GENERAL PURPOSE REGISTER SET - A processor has a central processing unit (CPU), a first CPU register set, a second CPU register set, a multiplexer logic for either coupling the first or the second CPU register set with the CPU, and control logic for controlling the multiplexer logic to switch from the first CPU register set to the second CPU register set upon receipt of at least one of a plurality of interrupt signals, wherein the at least one of a plurality of interrupt signals must meet a condition that is programmable within the control logic. | 10-14-2010 |
| 20110131393 | Programmable processor architecture - One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value wherein and smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations. | 06-02-2011 |
| 20110145547 | RECONFIGURABLE ELEMENTS - A cell element field for data processing having function cells for execution of algebraic and/or logic functions and memory cells for receiving, storing and/or outputting information is described. A control connection may lead from the function cells to the memory cells. | 06-16-2011 |
| 20110320770 | DATA PROCESSING DEVICE - An internal buffer is provided for a DRP core. A selector SEL switches input/output destination of the DRP core between external memory and an internal buffer. Control software executed by a CPU core receives information a pipeline of configurations for a sequence of target processing and generates combinations as to whether the processing result is transferred between the configurations via the external memory or via the internal buffer as transfer manners. Next, for each manner, bandwidth and performance of the external memory used by the DRP core in the manner are calculated. The manner of the best performance satisfying a previously specified bandwidth restriction is selected among the manners and the selector SEL is switched in accordance with the manner. | 12-29-2011 |
| 20120144160 | MULTIPLE-CYCLE PROGRAMMABLE PROCESSOR - The multi-cycle programmable processor emulates the features of a conventional microprocessor. Processor hardware functional units include a program counter (instruction pointer), an arithmetic and logic unit, an accumulator, an instruction register, a 2×1 multiplexer, 2×4 decoder, 1×2 decoder, an AND gate and an OR gate. Additionally, a controller modeled by a finite state machine (FSM) is operably connected to the microprocessor functional units and has a plurality of states that defines the operation of the microprocessor functional units. Each control state of the FSM implements the transfer of information between the registers of the datapath. The execution sequences through three states: an instruction fetch; an instruction decode; and instruction execute. The controller issues the required signals to the various hardware components to execute the instruction needed in three clock cycles. | 06-07-2012 |
| 20120159123 | CSTATE BOOST METHOD AND APPARATUS - A central processing unit (processor) having multiple cores and a method for controlling the performance of the processor. The processor includes a first storage location configured to store a first threshold associated with a first boost performance state (P-State). The processor also includes logic circuitry configured to increase performance of active processor cores when an inactive processor core count meets or exceeds the first threshold. The processor may also include a second storage location configured to store a second threshold associated with a second boost P-State. The logic circuitry may be configured to compare the inactive processor core count to the first and second thresholds, select one of the first and second boost P-States and increase performance of active processor cores based on the selected boost P-State. | 06-21-2012 |
| 20120185674 | EXTENDING A PROCESSOR SYSTEM WITHIN AN INTEGRATED CIRCUIT - A method of extending a processor system within an integrated circuit (IC) can include executing program code within the processor system implemented within the IC, wherein the IC includes a programmable fabric. The processor system further can be coupled to the programmable fabric. A process can be performed using a process-specific circuit implemented within the programmable fabric in lieu of using the processor system. A result of the process from the process-specific circuit can be made available to the processor system. | 07-19-2012 |
| 20120221832 | APPARATUS AND METHODS FOR IN-APPLICATION PROGRAMMING OF FLASH-BASED PROGRAMABLE LOGIC DEVICES - An architecture disposed in an integrated circuit for in-application programming of flash-based programmable logic devices includes a processor coupled to a processor system bus. An I/O peripheral is coupled to the processor over the system bus and is also coupled to an off-chip data source. A programmable logic device fabric includes flash-based programmable devices. A program controller is coupled to the flash-based programmable devices. An in-application programming controller is coupled to the program controller and is coupled to the processor over the system bus. | 08-30-2012 |
| 20120221833 | INTEGRATED CIRCUIT WITH PROGRAMMABLE CIRCUITRY AND AN EMBEDDED PROCESSOR SYSTEM - An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein. | 08-30-2012 |
| 20150052332 | MICROPROCESSOR INTEGRATED CONFIGURATION CONTROLLER FOR CONFIGURABLE MATH HARDWARE ACCELERATORS - A microprocessor circuit may include a software programmable microprocessor core and a data memory accessible via a data memory bus. The data memory may include sets of configuration data structured according to respective predetermined data structure specifications for configurable math hardware accelerators, and sets of input data for configurable math hardware accelerators, each configured to apply a predetermined signal processing function to the set of input data according to received configuration data. A configuration controller is coupled to the data memory via the data memory bus and to the configurable math hardware accelerators. The configuration controller may fetch the configuration data for each math hardware accelerator from the data memory and translate the configuration data. The configuration controller may transmit each set of configuration data to the corresponding configurable math hardware accelerator and write the configuration data to configuration registers of the math hardware accelerator. | 02-19-2015 |
| 20150134932 | STRUCTURE ACCESS PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS - A method of an aspect, which may be performed responsive to one or more structure access instructions, includes changing a state of a portion of a structure of a processor to a sequestered state. In the sequestered state, components of the processor are not able to access the portion of the structure but are able to access one or more other portions of the structure. Non-architecturally visible data in the portion of the structure is modified, while the portion of the structure is in the sequestered state. The state of the portion of the structure is then changed from the sequestered state to a non-sequestered state, after the non-architecturally visible data in the portion of the structure has been modified. Other methods, apparatus, systems, and instructions are also disclosed. | 05-14-2015 |
