| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 712036000 | Application specific | 40 |
| 20090083519 | Processing Element (PE) Structure Forming Floating Point-Reconfigurable Array (FP-RA) and FP-RA Control Circuit for Controlling the FP-RA - Techniques, systems and apparatus are described for providing a processing element (PE) structure forming a floating point unit (FPU)-processing element. Each processing element includes each of two multiplexers (MUXes) to receive data from one or more sources including another PE, and select one value from the received data. The processing element includes an arithmetic logic unit (ALU) in communication with the two multiplexers to receive the selected value from each multiplexer as two input values, and process the received two input values to generate results of the ALU. | 03-26-2009 |
| 20090089545 | MULTI PROCESSOR SYSTEM HAVING MULTIPORT SEMICONDUCTOR MEMORY WITH PROCESSOR WAKE-UP FUNCTION - A multiport semiconductor memory device having a processor wake-up function and multiprocessor system employing the same is provided. The multiprocessor system includes: a first processor configured to perform a first predetermined task; a second processor configured to perform a second predetermined task; and a multiport semiconductor memory device coupled to the first processor and the second processor, the multiport semiconductor memory device including: a memory cell array having at least one shared memory area; a first port coupled to the at least one shared memory area; a second port coupled to the at least one shared memory area; and a wake-up signal generator, the first processor being coupled to the at least one shared memory area via the first port, the second processor being coupled to the at least one shared memory area via the second port, the wake-up signal generator being coupled to the first processor and the second processor. | 04-02-2009 |
| 20090106532 | RAPID CREATION AND CONFIGURATION OF MICROCONTROLLER PRODUCTS WITH CONFIGURABLE LOGIC DEVICES - Methods and apparatus suitable for rapid creation and configuration of microcontroller products, which include a microcontroller or similar computational resource, and configurable logic devices are described. Various embodiments of the present invention allow development of new microcontroller-based products and product families in a rapid and cost-effective manner, thereby enabling early entry of such products into the marketplace. An existing microcontroller block and existing configurable logic devices are combined to form a unique product, wherein the microcontroller block is operable to configure the configurable logic devices to form the desired unique hardware characteristics of the microcontroller-based product. The microcontroller block configures the configurable logic devices when the product is reset, and/or when a power-up condition is recognized. | 04-23-2009 |
| 20090113175 | Processor architecture for concurrently fetching data and instructions - In one embodiment, a processor architecture for concurrently fetching data and patched instructions includes a microprocessor, an instruction patch, a dedicated instruction memory, a patch memory, and a dedicated data memory. The instruction patch is coupled to the microprocessor by an instruction bus, and is also coupled to the dedicated instruction memory and the patch memory. The patch memory and the dedicated data memory are coupled to the microprocessor by a data bus separate from the instruction bus. In one embodiment, the instruction patch has a number of comparators that can be individually enabled by respective enable signals. Each comparator that is enabled compares every bit on an instruction address with a corresponding bit of a patched instruction address to detect a patch condition. When a patch condition is detected, patched instructions are fetched from the patch memory, while the microprocessor can concurrently fetch data from the dedicated data memory. | 04-30-2009 |
| 20090119483 | SYSTEMS, METHODS, AND COMPUTER READABLE MEDIA FOR PREEMPTION IN ASYNCHRONOUS SYSTEMS USING ANTI-TOKENS - Systems, methods, and computer program products for preemption in asynchronous systems using anti-tokens are disclosed. According to one aspect, configurable system for constructing asynchronous application specific integrated data pipeline circuits with preemption includes a plurality of modular circuit stages that are connectable with each other and with other circuit elements to form multi-stage asynchronous application specific integrated data pipeline circuits for asynchronously sending data and tokens in a forward direction through the pipeline and for asynchronously sending anti-tokens in a backward direction through the pipeline. Each stage is configured to perform a handshaking protocol with other pipeline stages, the protocol including receiving either a token from the previous stage or an anti-token from the next stage, and in response, sending both a token forward to the next stage and an anti-token backward to the previous stage. | 05-07-2009 |
| 20090132789 | APPARATUS AND METHOD FOR CHANNEL-SPECIFIC CONFIGURATION IN A READOUT ASIC - An application-specific integrated circuit (ASIC) comprising a plurality of channels, each channel having circuitry for time and energy discrimination, a plurality of programmable registers, each programmable register configured to output at least one configuration parameter for the circuitry, and a channel-select register configured to identify a channel of the plurality of channels to be configured. The ASIC further includes a configuration-select register configured to identify the programmable register to be used for channel configuration, and a communications interface configured to transmit instructions received from a controller to one of the channel-select register, the configuration-select register, and the plurality of programmable registers. | 05-21-2009 |
| 20090164756 | Geological Response Data Imaging With Stream Processors - The invention describes a method to convert geological response data to graphical raw data by using at least one stream processor for this purpose. The geological response data is pre-processed by a CPU and the preprocessed geological response data is fed into one or more stream processors. The stream processor then does the calculation intensive work on the preprocessed geological response data and returns the processing results back to the CPU which does some post-processing on the results coming from the stream processor Stream processors comprise single or multiple programmable GPUs, clusters/networks of nodes with one or several GPU's; cell processors (or processors derived from it) or a cluster of cell processor nodes, game computers (in the spirit of Sony's PlayStation, Nintendo's GameCube, etc.) or clusters of game computers. | 06-25-2009 |
| 20090187736 | Computing Device, a System and a Method for Parallel Processing of Data Streams - A computing arrangement for identification of a current temporal input against one or more learned signals. The arrangement comprising a number of computational cores, each core comprises properties having at least some statistical independency from other of the computational, the properties being set independently of each other core, each core being able to independently produce an output indicating recognition of a previously learned signal, and at least one decision unit for receiving the produced outputs from the number of computational cores and making an identification of the current temporal input based the produced outputs. | 07-23-2009 |
| 20090187737 | IMAGE FORMING APPARATUS - A disclosed image processing apparatus includes a SIMD microprocessor in which multiple processor elements are arranged in one dimension, each of the processor elements including multiple access registers arranged in stages for storing image data; and multiple data processing devices corresponding one-to-one with the stages of the access registers, arranged in one dimension in the same direction as the processor elements, and configured to read and write image data from/to the access registers. The access registers of each of the stages, each of which access registers is included in a different one of the processor elements, are connected with a common line. Wiring outlets, each of which connects the common line of a different one of the stages to a corresponding data processing device, are individually disposed within the SIMD microprocessor in such a manner that each wiring outlet has a shortest possible distance to the corresponding data processing device. | 07-23-2009 |
| 20090216999 | Automated Execution Of Virtual Appliances - Methods and apparatus, including computer program products, are provided for selecting a processor, such as a hardware provider, for executing a virtual appliance. In one aspect, there is provided a computer-implemented method. The method may include receiving information representative of whether one or more processors are capable of executing at least one of a plurality of virtual appliances. The received information may further including one or more costs to execute the at least one virtual appliance at one of the processors. One of the processors may be selected based on the received information. The selection enables the processor to execute the at least one virtual appliance. Related apparatus, systems, methods, and articles are also described. | 08-27-2009 |
| 20090217000 | CLOCK SIGNALS IN DIGITAL SYSTEMS - A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first processor X and Y logic comprise first X and Y latches, respectively; and a first ASIC chip electrically coupled to the processor chip, wherein the first processor X and Y logics are configured to be simultaneously in a functional mode, wherein the first processor X logic is configured to switch from the functional mode to a scanning mode while the first processor Y logic remains in the functional mode, and wherein in response to the first processor Y logic being in the functional mode, the first processor Y logic is configured to generate a first reference ASIC clock signal to the first ASIC chip. | 08-27-2009 |
| 20090240917 | Method and apparatus for matrix decomposition in programmable logic devices - A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values. | 09-24-2009 |
| 20090282218 | Unsupervised Clustering of Multimedia Data Using a Large-Scale Matching System - A method and apparatus for clustering a plurality of data elements. The method comprises receiving a plurality of cluster elements, each cluster element containing at least a data element; generating a clustering score for each cluster element of the plurality of cluster elements versus all other cluster elements of the plurality of cluster elements using a computing device; determining a size of a diagonal matrix having a size corresponding to the number of the plurality of cluster elements; placing the clustering score in a diagonal matrix in storage one clustering score for each pair of cluster elements; creating a new cluster element for each two cluster elements in the diagonal matrix having a clustering score that exceeds a threshold; and storing generated new cluster elements in the storage. | 11-12-2009 |
| 20100023729 | IMPLEMENTING SIGNAL PROCESSING CORES AS APPLICATION SPECIFIC PROCESSORS - Methods and apparatus are provided for efficiently implementing signal processing cores as application specific processors. A signal processing core, such as a Fast Fourier Transform (FFT) core or a Finite Impulse Response (FIR) core includes a data path and a control path. A control path is implemented using processor components to increase resource efficiency. Both the data path and the control path can be implemented using function units that are selected, parameterized, and interconnected. A variety of signal processing algorithms can be implemented on the same application specific processor. | 01-28-2010 |
| 20100031004 | ARITHMETIC DEVICE - To reduce the size of a basic block composed of a plurality of arithmetic & logical processing unit blocks, and achieve high-speed operation. | 02-04-2010 |
| 20100049945 | Crypto-engine for cryptographic processing of data - A crypto-engine for cryptographic processing has an arithmetic unit and an interface controller for managing communications between the arithmetic unit and a host processor. The arithmetic unit has a memory unit for storing and loading data and arithmetic units for performing arithmetic operations on the data. The memory and arithmetic units are controlled by an arithmetic controller. | 02-25-2010 |
| 20100058030 | ARITHMETIC-LOGIC UNIT, PROCESSOR, AND PROCESSOR ARCHITECTURE - An arithmetic-logic unit for performing an operation of a prescribed bit length in an execution stage of a processor includes a plurality of sub-arithmetic-logic units which perform in respectively different pipeline stages sub-operations created by decomposing the operation of the prescribed bit length in a bit length direction, and a plurality of pipeline registers provided so as to separate the pipeline stages from each other, wherein each of the pipeline registers operates in such a manner as to be switchable between two operation modes, a flip-flop mode in which an output value is updated in synchronism with an input trigger and a transparent mode in which an input value is directly output. | 03-04-2010 |
| 20100064117 | APPARATUS AND METHOD FOR UPDATING SET OF LIMITED ACCESS MODEL SPECIFIC REGISTERS IN A MICROPROCESSOR - A microprocessor having model specific registers (MSRs) includes, for each of the MSRs, an associated default value that indicates whether the MSR is protected or non-protected and an associated fuse that, if blown, toggles the associated default value from protected to non-protected or non-protected to protected. In one embodiment, microcode that does the following in response to the microprocessor encountering an instruction that accesses a specified MSR: determines whether the fuse associated with the specified MSR is blown or unblown, uses the default value associated with the MSR as an indicator of whether the MSR is protected if the associated fuse is unblown; toggles the associated default value to generate the indicator if the associated fuse is blown; protects access to the MSR if the indicator indicates the MSR is protected; and refrains from protecting access to the MSR if the indicator indicates the MSR is non-protected. | 03-11-2010 |
| 20100153687 | STREAMING PROCESSOR, OPERATION METHOD OF STREAMING PROCESSOR AND PROCESSOR SYSTEM - There is provided a streaming processor which includes one general-purpose processor core and multiple operation processor cores and which performs parallel processing by assigning multiple processes of decoding processing of an encoded stream to the operation processor cores. The streaming processor performs stream analysis processing for estimating a processing load for each stream on the basis of stream information and assigning processes to be performed by the operation processor cores on the basis of the estimated processing load. | 06-17-2010 |
| 20100174887 | Buses for Pattern-Recognition Processors - Disclosed are methods and systems, among which is a system that includes a pattern-recognition processor, a central processing unit (CPU) coupled to the pattern-recognition processor via a pattern-recognition bus, and memory coupled to the CPU via a memory bus. In some embodiments, the pattern-recognition bus and the memory bus form about the same number of connections to the pattern-recognition processor and the memory, respectively. | 07-08-2010 |
| 20100205399 | PERFORMANCE COUNTER FOR MICROCODE INSTRUCTION EXECUTION - An apparatus for counting microcode instruction execution in a microprocessor includes a first register, a second register, a comparator, and a counter. The first register stores an address of a microcode instruction. The microcode instruction is stored in a microcode memory of the microprocessor. The second register stores an address of the next microcode instruction to be retired by a retire unit of the microprocessor. The comparator compares the addresses stored in the first and second registers to indicate a match between them. The counter counts the number of times the comparator indicates a match between the addresses stored in the first register and the second register. The first register is user-programmable and the counter is user-readable. A mask register may be included to create a range of microcode memory addresses so that executions of microcode instructions within the range are counted. | 08-12-2010 |
| 20100325393 | Technique for performing layer 2 processing using a distributed memory architecture - A distributed memory architecture for a layer 2 processing circuit chip ( | 12-23-2010 |
| 20100332798 | Digital Processor and Method - A processor subunit for a processor for processing data. The processor subunit includes registers, and at least one functional unit for executing instructions on data. One or more registers of the registers are connected to an input of the at least one functional unit, where each register connected to the input of the at least one functional unit which has an input multiplexer. One or more registers of the registers are connected to an output of the at least one functional unit, where each register connected to the output of the at least one functional unit which has an input multiplexer. At least one output bus is connected to at least one register. At least one input bus is connected to at least one register. The processor subunit may be used in a processor, which may be used in a data streaming accelerator. | 12-30-2010 |
| 20110022822 | Motion Controller Utilizing a Plurality of Processors - Controlling a motion system using a plurality of processors. First input data may be received which corresponds to a first portion of the motion system. Second input data may be received which corresponds to a second portion of the motion system. Execution of a first function of a plurality of sequential functions may be assigned to a first processor to determine output for the first portion based on the first input data. Execution of the first function may be assigned to a second processor to determine output for the second portion based on the second input data. The first processor executing the first function and the second processor executing the first function may be performed in parallel. The output for the first portion of the motion system may be provided to the first portion. The output for the second portion of the motion system may be provided to the second portion. | 01-27-2011 |
| 20120079239 | TIMING MODULE - A timing module and a microcontroller. An independent processing unit, which is provided as a component of at least one closed-loop control circuit, is integrated in the timing module. | 03-29-2012 |
| 20120144159 | QUANTUM PROCESSOR - One embodiment of the invention includes a quantum processor system. The quantum processor system includes a first resonator having a first characteristic frequency and a second resonator having a second characteristic frequency greater than the first characteristic frequency. A qubit cell is coupled to each of the first resonator and the second resonator. The qubit cell has a frequency tunable over a range of frequencies including the first characteristic frequency and the second characteristic frequency. A classical control mechanism is configured to tune the frequency of the qubit cell as to transfer quantum information between the first resonator and the second resonator. | 06-07-2012 |
| 20120151184 | HARD OBJECT: CONSTRAINING CONTROL FLOW AND PROVIDING LIGHTWEIGHT KERNEL CROSSINGS - A method providing simple fine-grain hardware primitives with which software engineers can efficiently implement enforceable separation of programs into modules and constraints on control flow, thereby providing fine-grain locality of causality to the world of software. Additionally, a mechanism is provided to mark some modules, or parts thereof, as having kernel privileges and thereby allows the provision of kernel services through normal function calls, obviating the expensive prior art mechanism of system calls. Together with software changes, Object Oriented encapsulation semantics and control flow integrity in hardware are enforced. | 06-14-2012 |
| 20120198207 | ASYMMETRIC PERFORMANCE MULTICORE ARCHITECTURE WITH SAME INSTRUCTION SET ARCHITECTURE - A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency. | 08-02-2012 |
| 20120216018 | PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA - A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data. | 08-23-2012 |
| 20120239907 | ACTIVE MEMORY COMMAND ENGINE AND METHOD - A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in an array control unit where processing array instructions are stored. | 09-20-2012 |
| 20130159670 | COUNTER OPERATION IN A STATE MACHINE LATTICE - Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers. | 06-20-2013 |
| 20130159671 | METHODS AND SYSTEMS FOR DETECTION IN A STATE MACHINE - A device including a data analysis element including a plurality of memory cells. The memory cells analyze at least a portion of a data stream and output a result of the analysis. The device also includes a detection cell. The detection cell includes an AND gate. The AND gate receives result of the analysis as a first input. The detection cell also includes a D-flip flop including an output coupled to a second input of the AND gate. | 06-20-2013 |
| 20130262819 | SINGLE CYCLE COMPARE AND SELECT OPERATIONS - An apparatus includes a processor to determine an extremum among a series of values that are successively provided to a first register and a second register. The processor is configured to execute a single cycle search instruction, including compare a value in the first register with a value in a first accumulator, and store an extremum of the two values in the first accumulator; and compare a value in the second register with a value in a second accumulator, and store an extremum of the two values in the second accumulator. The processor is configured to execute a single cycle select instruction, including compare the value in the first accumulator with the value in the second accumulator, and store an extremum of the two values in the first accumulator, the extremum stored in the first accumulator representing the extremum of the series of numbers. | 10-03-2013 |
| 20130318326 | Self-Similar Processing Network - Self-similar processing by unit processing cells may together solve a problem. A unit processing cell may include a processor, a memory and a plurality of Input/Output (IO) channels coupled to the processor. The memory may include a dictionary having one or more instructions that configure the processor to perform at least one function. The plurality of IO channels may be used to communicably couple the unit processing cell with a plurality of other unit processing cells each including their own respective dictionary. The processor may update the dictionary so that the unit processing cell builds a different dictionary from the plurality of other unit processing cells, thereby being self-similar to the plurality of other unit processing cells. | 11-28-2013 |
| 20130346726 | DISTRIBUTED MICRO INSTRUCTION SET PROCESSOR ARCHITECTURE FOR HIGH-EFFICIENCY SIGNAL PROCESSING - A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank. | 12-26-2013 |
| 20140115299 | COUNTER OPERATION IN A STATE MACHINE LATTICE - Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers. | 04-24-2014 |
| 20140201500 | Controlling Bandwidth Allocations In A System On A Chip (SoC) - In one embodiment, a fabric of a processor such as a system on a chip includes at least one data buffer including a plurality of entries each to store data to be transferred to and from a plurality of agents and to and from a memory, a request tracker to maintain track of pending requests to be output to an ordered domain of the fabric, and an output throttle logic to control allocation into the ordered domain between write transactions from a core agent and read completion transactions from the memory. Other embodiments are described and claimed. | 07-17-2014 |
| 20140258679 | Reconfigurable Protocol Tables Within An ASIC - A high performance computing system is provided with an ASIC that communicates with another device in the system according to a protocol defined by the other device. The ASIC is coupled to a reconfigurable protocol table, in the form of a high speed content-addressable memory (“CAM”). The CAM includes instructions to control the execution of the protocol by the ASIC. The CAM may include instructions to control the ASIC in the event that unanticipated signals or other errors are encountered while executing the protocol. Internal ASIC state data may be routed to the CAM to permit the ASIC to generate a reasonable response to errors either in the design or fabrication of the ASIC or the device with which it is communicating. | 09-11-2014 |
| 20150074375 | Reconfigurable Protocol Tables Within An ASIC - A high performance computing system is provided with an ASIC that communicates with another device in the system according to a protocol defined by the other device. The ASIC is coupled to a reconfigurable protocol table, in the form of a high speed content-addressable memory (“CAM”). The CAM includes instructions to control the execution of the protocol by the ASIC. The CAM may include instructions to control the ASIC in the event that unanticipated signals or other errors are encountered while executing the protocol. Internal ASIC state data may be routed to the CAM to permit the ASIC to generate a reasonable response to errors either in the design or fabrication of the ASIC or the device with which it is communicating. | 03-12-2015 |
| 20190147278 | BUSES FOR PATTERN-RECOGNITION PROCESSORS | 05-16-2019 |
