| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 712033000 | Having multiple internal buses | 7 |
| 20100146243 | Transaction Aware, Flexible Interface For A State Correlation And Transition Execution Engine - The subject matter disclosed herein provides methods and apparatus, including computer program products, for state alignment and transaction coupling to enable reliable communication between an application, such as a backend system, and a correlation engine (or rules engine). In one aspect there is provided a method. The method may provide a first interface to receive information from an adapter for an application separate from a state correlation engine and provide a second interface to receive information from the state correlation engine to the adapter. The first and second interfaces may provide state alignment between the application and the state correlation engine. Related systems, apparatus, methods, and/or articles are also described. | 06-10-2010 |
| 20100325392 | HYBRID MULTI FUNCTION COMPONENT SYSTEM - This invention describes an apparatus, architecture, method, operating system, data network, and application program products for a hybrid digital system with multiple heterogeneous components. This invention is applied to a multiple generic microprocessor architecture s with a set (e.g., one or more cores) of controlling components and a set of groups of sub-processing components. Under this arrangement, different technology cores and functional components, such as memory, are organized in a way that different technologies can collaborate as a system. | 12-23-2010 |
| 20110264890 | ELECTRONIC CHIP AND INTEGRATED CIRCUIT INCLUDING SUCH AN ELECTRONIC CHIP - This electronic chip includes functional modules each including a single processing unit and a single routing unit ( | 10-27-2011 |
| 20120072699 | LOGIC CELL ARRAY AND BUS SYSTEM - A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points. | 03-22-2012 |
| 20140052961 | PARALLEL MEMORY SYSTEMS - The invention relates to a multi-core processor memory system, wherein it is provided that the system comprises memory channels between the multi-core processor and the system memory, and that the system comprises at least as many memory channels as processor cores, each memory channel being dedicated to a processor core, and that the memory system relates at run-time dynamically memory blocks dedicatedly to the accessing core, the accessing core having dedicated access to the memory bank via the memory channel. | 02-20-2014 |
| 20140136818 | FETCH LESS INSTRUCTION PROCESSING (FLIP) COMPUTER ARCHITECTURE FOR CENTRAL PROCESSING UNITS (CPU) - Fetch Less Instruction Processing (FLIP) Computer Architecture for Central Processing Units (CPU). This embodiment relates to computing systems, and more particularly to central processing units in computing systems. The principal object of this embodiment is to provide a Fetch Less Instruction Processing (FLIP) computer architecture using FLIP elements as building blocks for computer program processing. Another object of the embodiment is to use a protocol to interconnect FLIP elements, which makes the current operating systems, program execution models, compilers, libraries and so on to be easily transitioned to the FLIP computer architecture with minimal changes. | 05-15-2014 |
| 20150058599 | EFFICIENT ARTHIMETIC LOGIC UNITS - A processor may include a conditional arithmetic logic unit and a main arithmetic logic unit. The conditional arithmetic logic unit may perform a first arithmetic logic operation to generate a first result, and output the result. The main arithmetic logic unit may select input buses among a plurality of data buses that carry the first result from the conditional arithmetic logic unit, perform a second arithmetic logic operation on data provided by the selected input buses to generate a second result, and write the second result in a storage component. | 02-26-2015 |
