| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 712031000 | Master/slave | 29 |
| 20080235493 | INSTRUCTION COMMUNICATION TECHNIQUES FOR MULTI-PROCESSOR SYSTEM - A method for communicating instructions to slave processors in a multi-processor system having a master processor and pipelined slave processors controlled by the master processor is described. The method uses a pass-through command having (i) a header block coded using a computer language understood by the slave processors and (ii) a payload block including instructions coded in a computer language understood by a destined slave processor. The pass-through command is transmitted to an outermost slave processor and then forwarded, without recoding, by intermediate downstream slave processors until the command reaches the destined slave processor. In one application, the method is used in a system adapted for processing video data or rendering graphics. | 09-25-2008 |
| 20080301407 | Resolving A Layer 3 Address In A Processor System With A Unified IP Presence - Resolving a Layer 3 address includes maintaining an address resolution table at each slave processor of a number of slave processors. The slave processors have a master processor, and the master processor and the slave processors are associated with a unified address. An address resolution table includes one or more Layer 2-Layer 3 address mappings. An address resolution request requesting a Layer 2 address corresponding to a Layer 3 address is sent from a slave processor. The address resolution request uses the unified address. An address resolution response comprising the Layer 2 address is received at the master processor. The master processor sends the response to the slaves. | 12-04-2008 |
| 20080301408 | SYSTEM COMPRISING A PLURALITY OF PROCESSORS AND METHOD OF OPERATING THE SAME - A system comprises a master processor and at least one slave processor. A state of the master processor comprises a first plurality of variables and a state of the slave processor comprises a second plurality of variables. The system comprises a parallel mode of operation wherein data are processed by the master processor and the slave processor and a serial mode of operation wherein data are processed by the master processor. In case of an interrupt or exception occurring in the parallel mode of operation, the system performs the steps of saving at least a portion of the first plurality of variables and the second plurality of variables to a buffer memory and switching the system to the serial mode of operation. If the interrupt or exception is occurring in the slave processor, at least one of the first plurality of variables is set to a value of at least one of the second plurality of variables. | 12-04-2008 |
| 20090043988 | Configuring Compute Nodes of a Parallel Computer in an Operational Group into a Plurality of Independent Non-Overlapping Collective Networks - Methods, apparatus, and products are disclosed for configuring compute nodes of a parallel computer in an operational group into a plurality of independent non-overlapping collective networks, the compute nodes in the operational group connected together for data communications through a global combining network, that include: partitioning the compute nodes in the operational group into a plurality of non-overlapping subgroups; designating one compute node from each of the non-overlapping subgroups as a master node; and assigning, to the compute nodes in each of the non-overlapping subgroups, class routing instructions that organize the compute nodes in that non-overlapping subgroup as a collective network such that the master node is a physical root. | 02-12-2009 |
| 20090132788 | CONTROL SYSTEM WITH MULTIPLE PROCESSORS AND CONTROL METHOD THEREOF - A control system comprises a master processor, a main memory and multiple slave processors. The main memory stores programs, and a signal-program table for storing relationships between the programs and input signals. The multiple slave processors are configured for sending input signals in response to external stimuli to the master processor, and executing programs corresponding to the input signals sent back by the master processor. The master processor is configured for interrogating the signal-program table to determine the corresponding programs according to one of the input signals, searching the main memory for acquiring the corresponding programs, determining which one or more of the multiple slave processors should execute the corresponding programs, and transmitting each of the corresponding programs to the one or more of the multiple slave processors. A related control method is also provided. | 05-21-2009 |
| 20090158009 | ELECTRONIC EQUIPMENT AND CONTROL METHOD - Plural CPUs are provided, and when a first CPU of the plural CPUs is a master, the other CPU operates as a slave. Also, plural memories are provided including a memory that operates and is used for first processing when the master CPU operates and a memory that operates and is used for second processing when the slave CPU operates. Every time an OS (Operating System) starts, the CPU to serve as a master is sequentially switched, then the remaining CPU is caused to serve as a slave, and the memories used for the first processing and the second processing are sequentially switched. | 06-18-2009 |
| 20090307464 | System and Method for Parallel Video Processing in Multicore Devices - Embodiments are disclosed for a system and method for parallel processing of video signals. A multi-core processor is used to establish a master-slave relationship between a first processing core and a plurality of individual processing cores. Shared memory is used to store data and control messages. A plurality of individual private memories are associated with each of the individual processing cores; and control logic is used to establish a master-slave protocol for using the plurality of individual cores to process video data. The master processing core is operable to balance the video data processing load among the individual slave processing cores. | 12-10-2009 |
| 20090313454 | Multiprocessor System and Display Device Using the Same - In a multiprocessor system ( | 12-17-2009 |
| 20100064116 | METHOD AND SYSTEM FOR PACKET ENCRYPTION - A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyse the packets and to provide a header including a list of processes to perform on the packet of data and an ordering thereof. The master controller is programmed with process related data relating to the overall processing function of the processor. The header is appended to the packet of data. The packet with the appended header information is stored within a buffer. A buffer controller acts to determine for each packet stored within the buffer based on the header within the packet a next processor to process the packet. The controller then provides the packet to the determined processor for processing. The processed packet is returned with some indication that the processing is done. For example, the process may be deleted from the list of processes. The buffer controller repeatedly makes a determination of a next process until there is no next process for a packet at which time it is provided to an output port. | 03-11-2010 |
| 20100205398 | Transmission device and swichover processing method - In an optical transmission device, firmware that operates within a CPU of a first LIU and firmware that operates within a CPU of a second LIU periodically measure a load status of a CPU via an OS, respectively. Switchover control of a master CPU is performed according to a load status of a CPU measured by the firmware of each LIU. For example, when a load status of the CPU of the second LIU is lower than that of the CPU of the first LIU, a master CPU that performs switchover control of a predetermined port is switched to a slave CPU in the first LIU, and a slave CPU related to the predetermined port is switched to a master CPU in the second LIU, thereby dynamically changing the setting. | 08-12-2010 |
| 20100306501 | Hybrid Computer Systems - A hybrid computer system is provided, including first and second computer devices. The first computer device is configured with the second computer device via a connection unit. Each of the first computer device and the second computer device is capable of operating independently when the first computer device and the second computer device are separated. The first computer device and the second computer device communicate with each other in a master-slave structure and combined with each other into a single system. The peripheral devices of the first and second computer devices are shared, wherein the first and second computer devices are master/slave systems or slave/master systems. | 12-02-2010 |
| 20100306502 | DIGITAL SIGNAL PROCESSOR HAVING A PLURALITY OF INDEPENDENT DEDICATED PROCESSORS - A digital signal processor uses a number of independent sub-processors that may be controlled by a master programmable controller. For example, a specialized input processor may process input signals while a specialized output processor may process output signals. Each of these processors may also accomplish math functions when input and output processing is not necessary. The various processors may communicate with one another through general purpose registers which receive data and provide data to any of the processors in the system. Math processors may be added as needed to accomplish desired mathematical functions. In addition, a RAM processor may be utilized to hold the results of intermediate calculations in one embodiment of the present invention. In this way, an adaptable and scaleable design may be implemented that accommodates a variety of different operations without requiring redesign of all the components. | 12-02-2010 |
| 20100325391 | SYSTEMS AND METHODS FOR INITIALIZATION AND LINK MANAGEMENT OF NICS IN A MULTI-CORE ENVIRONMENT - The present application is directed towards systems and methods for coordination and management of a shared resource in a multi-core system. In a multi-core system, multiple cores may be utilizing a shared resource. However, internal resources common to the shared resource may need to be initialized by only one core, and independent and uncoordinated initialization by multiple cores may cause errors. The present invention provides systems and methods for coordinating such initialization and use through a handshaking protocol. | 12-23-2010 |
| 20110208948 | READING TO AND WRITING FROM PERIPHERALS WITH TEMPORALLY SEPARATED REDUNDANT PROCESSOR EXECUTION - Embodiments relate to systems and methods for reading from and writing to interface peripherals or other shared resources during robust computation utilizing temporally separated redundant execution. Embodiments can be utilized in safety-relevant applications related to automotive, banking and finance, aerospace, defense, Internet payment, and others. | 08-25-2011 |
| 20110225393 | DEVICE ACTIVATING UNIT AND CPU - A register circuit having a plurality of registers enabling the writing and reading of data by the specification of an address; a register controlling circuit monitoring data of a plurality of registers of the register circuit through the specification of an address, and writing, to a register pre-established in the register circuit, for activating devices; and a signal transmitting circuit causing a device to execute a specific operation, based on a specified address and on data read from the register circuit are provided; and not only is a collection of first bits for controlling jointly the individual operations of the plurality of devices assigned in a first register that is established in advance in the plurality of registers, but also second bits for controlling individually the individual operations in the plurality of devices are assigned respectively in a plurality of respective second registers that differ from the first register. | 09-15-2011 |
| 20110258414 | APPARATUS AND METHOD FOR PROCESSING DATA STREAMS - A distributed architecture and method for maintaining the integrity of data streams within a multi-pipelined processing environment. The architecture comprising a communications network for carrying a plurality of data streams and a master processor adapted to process one or more messages in at least one of the data streams, the message processing including the creation of one or more data packets within the stream, each packet encapsulating at least a transaction summary of the data that has been processed. The architecture further comprising at least one slave processor per master processor adapted to emulate the transactional state of the master processor by regenerating the data stream as a result of processing the one or more data packets, whereupon in response to an error event on the master processor, the slave processor acts to avoid interrupting the data stream by generating one or more successive data packet(s). Hence, the architecture and method serve as a high availability, robust fault tolerant system, mitigating against the loss of data within data streams. | 10-20-2011 |
| 20110314257 | DISTRIBUTED MICRO INSTRUCTIONS SET PROCESSOR ARCHITECTURE FOR HIGH-EFFICIENCY SIGNAL PROCESSING - A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank. | 12-22-2011 |
| 20120089815 | DETERMINING PROCESSOR OFFSETS TO SYNCHRONIZE PROCESSOR TIME VALUES - Provided are a computer program product, system, and method for determining processor offsets to synchronize processor time values. A determination is made of a master processor offset from one of a plurality of time values of the master processor and a time value of one of the slave processors. A determination is made of slave processor offsets, wherein each slave processor offset is determined from the master processor offset, one of the time values of the master processor, and a time value of the slave processor. A current time value of the master processor is adjusted by the master processor offset. A current time value of each of the slave processors is adjusted by the slave processor offset for the slave processor whose time value is being adjusted. | 04-12-2012 |
| 20120159122 | SYSTEMS AND METHODS FOR LATTICE REDUCTION - Disclosed herein are lattice reduction systems and methods for a MIMO communication system. One such method includes providing a channel matrix corresponding to a channel in a MIMO communication system, preprocessing the channel matrix to form at least an upper triangular matrix, implementing a relaxed size reduction process, and implementing a basis update process. Implementing the relaxed size reduction process comprises choosing a first relaxed size reduction parameter for a first-off-diagonal element of the upper triangular matrix, choosing a second relaxed size reduction parameter, which is greater than the first relaxed size reduction parameter, for a second-off-diagonal element of the upper triangular matrix evaluating whether a first relaxed size reduction condition is satisfied for the first-off-diagonal element of the upper triangular matrix, and evaluating whether a second relaxed size reduction condition is satisfied for the second-off-diagonal element of the upper triangular matrix. | 06-21-2012 |
| 20120239906 | Launching A Secure Kernel In A Multiprocessor System - In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example. | 09-20-2012 |
| 20120272042 | DISTRIBUTED MICRO INSTRUCTIONS SET PROCESSOR ARCHITECTURE FOR HIGH-EFFICIENCY SIGNAL PROCESSING - A wireless communication base station comprising a plurality of application specific instruction set processors (ASISPs) configured to support one or more processes hosted by the base station, and to track process state information associated with each of the processes; and a memory configured to store the tracked process state information, and when an ASISP of the plurality of ASISPs is reallocated from a first process to a second process, the respective ASISP is configured to retrieve from the memory process state information for the second process. | 10-25-2012 |
| 20140095829 | Method and device for passing parameters between processors - The disclosure provides a method for passing a parameter between processors. The method comprises the following steps: in a source program of a slave processor, directly introducing a static configuration parameter to be passed; obtaining a relative address of the static configuration parameter when converting the source program of the slave processor into a target program of the slave processor; and configuring directly, by a master processor, a parameter value of the static configuration parameter in the target program of the slave processor according to the obtained relative address of the static configuration parameter. The disclosure also provides a system for passing a parameter between processors. The system has no need to use external hardware such as a dual-port Random Access Memory (RAM) and a register, thus, the requirement of parameter transmission on the external hardware is reduced, and further the area and static power consumption of a chip are reduced. The disclosure reduces the cycle delay of the slave processor in accessing the dual-port RAM and the register, thereby effectively reducing the dynamic power consumption of the chip, improving the processing capability of the slave processor and enhancing the effective performance of the slave processor. | 04-03-2014 |
| 20140189303 | MULTISTAGE MODULE EXPANSION SYSTEM AND MULTISTAGE MODULE COMMUNICATION METHOD - A multistage module expansion system and multistage module communication method, applicable to a set-top box, are introduced. The system includes a master module, at least a preceding expansion module, and at least a succeeding expansion module. The master module generates and sends a control instruction to the preceding expansion module and the succeeding expansion module. The preceding expansion module and the succeeding expansion module each determine whether the control instruction is of a type executable by the preceding expansion module and the succeeding expansion module, respectively. If the determination is affirmative, the preceding expansion module creates and sends a preceding data packet to the master module, and the succeeding expansion module creates and sends a succeeding data packet to the preceding expansion module, such that the preceding expansion module sends the succeeding data packet to the master module. | 07-03-2014 |
| 20140208070 | SYSTEMS AND METHODS FOR INTERFACING MASTER AND SLAVE PROCESSORS - System and methods are provided. In one embodiment, a system includes a first processor comprising a serial peripheral interface (SPI) port, and a second processor. The system further includes a galvanic isolation barrier. The system additionally includes a SPI bridge comprising a first output pin control configured to control a device. The SPI bridge additionally includes a first analog multiplexor control configured to route signals to a circuitry. The SPI bridge is configured to communicatively couple the first processor with the second processor through the galvanic isolation barrier, and to communicatively couple the first processor to the device through the first output pin control, and to route the signals between the first processor and the circuitry by using the first analog multiplexor control. | 07-24-2014 |
| 20140208071 | ADAPTIVE SERVICE CONTROLLER, SYSTEM ON CHIP AND METHOD OF CONTROLLING THE SAME - A system on chip (SOC) includes a slave device, a plurality of master devices, an interconnect device and a plurality of service controllers. The master devices generate requests to demand services from the slave device. The interconnect device is coupled to the slave device and the master devices through respective channels, and the interconnect device performs an arbitrating operation on the requests. The service controllers control request flows from the master devices adaptively depending on an operational environment change of the SOC. | 07-24-2014 |
| 20140208072 | USER-LEVEL MANAGER TO HANDLE MULTI-PROCESSING ON MANY-CORE COPROCESSOR-BASED SYSTEMS - A method is disclosed to manage a multi-processor system with one or more multiple-core coprocessors by intercepting coprocessor offload infrastructure application program interface (API) calls; scheduling user processes to run on one of the coprocessors; scheduling offloads within user processes to run on one of the coprocessors; and affinitizing offloads to predetermined cores within one of the coprocessors by selecting and allocating cores to an offload, and obtaining a thread-to-core mapping from a user. | 07-24-2014 |
| 20140250287 | INFORMATION PROCESSING DEVICE, JOB SCHEDULING METHOD, AND JOB SCHEDULING PROGRAM - An information processing device includes: a measurement unit | 09-04-2014 |
| 20140281381 | SYSTEM-ON-CHIP AND METHOD OF OPERATING THE SAME - A system-on-chip (SoC) includes a slave intellectual property (IP) block, a master IP block, and an update control unit. The slave IP block is configured to perform first processing on first data based on first control information stored in a first storage unit. The master IP block is configured to perform second processing on second data in response to receiving a first processing result obtained by performing the first processing on the first data. Performing the second processing is based on second control information stored in a second storage unit. The update control unit is configured to determine an update time of the first control information or an update time of the second control information in response to performing the first processing and performing the second processing. | 09-18-2014 |
| 20150019839 | DETERMINING PROCESSOR OFFSETS TO SYNCHRONIZE PROCESSOR TIME VALUES - Provided are a computer program product, system, and method for determining processor offsets to synchronize processor time values. A determination is made of a master processor offset from one of a plurality of time values of the master processor and a time value of one of the slave processors. A determination is made of slave processor offsets, wherein each slave processor offset is determined from the master processor offset, one of the time values of the master processor, and a time value of the slave processor. A current time value of the master processor is adjusted by the master processor offset. A current time value of each of the slave processors is adjusted by the slave processor offset for the slave processor whose time value is being adjusted. | 01-15-2015 |
